Ieee 2012 Vlsi

28,South Usman Road,, TNagar, Chennai-17. Ph : 044-43855940 Mobile : +91-9042085008 Web : www.temasolution.com email : temasolution@gmail.
com
S.NO 1.
PROJECT TITLE
Simulation Simulation Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E Spartan 3E
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time.
2.
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders.
3.
Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm. A novel all-digital multichannel multimode RF Transmitter using delta-sigma modulation
4.
5.
Highly scalable parallel arithmetic coding on Multi-core processors using LDPC codes
6.
Pipelined parallel FFT architectures via Folding transformation
7.
Robust secure scan design against scan-based Differential cryptanalysis
Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim &
Spartan 3E
8.
Synchronous FPGA-based high-resolution Implementations of digital pulse-width modulators
Spartan 3E
9.
The LUT-SR family of uniform random Number generators for FPGA architectures
Spartan 3E
Further more details visit : http://www.temasolution.com/downloads.html send your request to : info@temasolution.com
28,South Usman Road,, TNagar, Chennai-17. Ph : 044-43855940 Mobile : +91-9042085008 Web : www.temasolution.com email : temasolution@gmail.com
10.
VLSI architecture of arithmetic coder Used in SPIHT
Xilinx Modelsim &
Spartan 3E
11.
PAPR reduction by linear coding techniques for MIMOOFDM systems performance Improvement: simulation and hardware implementation Extending the effective throughput of NOCS with Distributed shared-buffer routers
Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim &
Spartan 3E
12.
Spartan 3E
13.
FPGA implementation of the multilayer neural Network for the speed estimation of the Two-mass drive system
Spartan 3E
14.
BIST using genetic algorithm for error detection and correction
Spartan 3E
15.
Low-Power and Area-Efficient Carry Select Adder
Spartan 3E
16.
Optimizing Floating Point Units in Hybrid FPGAs
Xilinx Modelsim &
Spartan 3E
17.
Optimizing Floating Point Units in Hybrid FPGAs
Xilinx Modelsim &
Spartan 3E
18.
Bayesian Equalization for LDPC Channel Decoding
Xilinx Modelsim & Xilinx
Spartan 3E
19.
Low-Complexity Soft Decoding of Huffman Codes and Iterative Joint Source Channel Decoding.
Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx
Spartan 3E
20.
Human Gait Modeling Using a Genetic Fuzzy Finite State Machine.
Spartan 3E
21.
Accurate Analysis of Double-Weight Optical CDMA With Power Control
Spartan 3E
22.
Optimal Channel and Relay Assignment in OFDM-Based Multi-Relay Multi-Pair Two-Way Communication Networks
Spartan 3E
23.
Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform
Spartan 3E
24.
Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems
Spartan 3E
25.
Nonlinear Trellis Codes for Binary-Input Binary-Output Multiple-Access Channels with Single-User Decoding
Spartan 3E
26.
Low-Complexity Iterative Channel Estimation for Turbo Receivers
Spartan 3E
27.
A Low Complexity MMSE for OFDM Systems over Frequency-Selective Fading Channels
Spartan 3E
28.
A Row-Parallel 88 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation
Modelsim & Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim &
Spartan 3E
29.
A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL
Spartan 3E
30.
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy
Spartan 3E
31.
Separable Reversible Data Hiding in Encrypted Image
Spartan 3E
32.
FPGA-Based Track Circuit for Railways Using Transmission Encoding
Xilinx Modelsim & Xilinx Modelsim &
Spartan 3E
33.
Sub W Noise Reduction for CIC Hearing Aids
Spartan 3E
34.
On Modulo 2n 1 Adder Design
Xilinx Modelsim &
Spartan 3E
35.
A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio Receivers.
Xilinx Modelsim & Xilinx Modelsim & Xilinx
Spartan 3E
36.
VLSI Friendly ECG QRS Complex Detector for Body Sensor Networks.
Spartan 3E
37.
Accumulator Based 3-Weight Pattern Generation.
Modelsim &
Spartan 3E
38.
High-Throughput Soft-Output MIMO Detector Based on PathPreserving Trellis-Search Algorithm.
Xilinx Modelsim & Xilinx Modelsim &
Spartan 3E
39.
Single Cycle Access Structure for Logic Test.
Spartan 3E
40.
Area and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-DDWT.
Xilinx Modelsim & Xilinx Modelsim & Xilinx
Spartan 3E
41.
VLSI design of memory efficient, high-speed baseline MQ coder for JPEG 2000.
Spartan 3E

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28,South Usman Road,, TNagar, Chennai-17. Ph : 044-43855940 Mobile : +91-9042085008 Web : www.temasolution.com email : temasolution@gmail.

High-Speed Low-Power Viterbi Decoder Design for TCM Decoders.

Pipelined parallel FFT architectures via Folding transformation

Robust secure scan design against scan-based Differential cryptanalysis

Xilinx Modelsim & Xilinx Modelsim & Xilinx Modelsim &

Synchronous FPGA-based high-resolution Implementations of digital pulse-width modulators

Further more details visit : http://www.temasolution.com/downloads.html send your request to : info@temasolution.com

VLSI architecture of arithmetic coder Used in SPIHT

Xilinx Modelsim &

BIST using genetic algorithm for error detection and correction

Low-Power and Area-Efficient Carry Select Adder

Optimizing Floating Point Units in Hybrid FPGAs

Xilinx Modelsim &

Optimizing Floating Point Units in Hybrid FPGAs

Xilinx Modelsim &

Bayesian Equalization for LDPC Channel Decoding

Xilinx Modelsim & Xilinx

Further more details visit : http://www.temasolution.com/downloads.html send your request to : info@temasolution.com

Human Gait Modeling Using a Genetic Fuzzy Finite State Machine.

Accurate Analysis of Double-Weight Optical CDMA With Power Control

Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform

Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems

Low-Complexity Iterative Channel Estimation for Turbo Receivers

Further more details visit : http://www.temasolution.com/downloads.html send your request to : info@temasolution.com

A Row-Parallel 88 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL

A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy

Separable Reversible Data Hiding in Encrypted Image

FPGA-Based Track Circuit for Railways Using Transmission Encoding

Xilinx Modelsim & Xilinx Modelsim &

Sub W Noise Reduction for CIC Hearing Aids

On Modulo 2n 1 Adder Design

Xilinx Modelsim &

Xilinx Modelsim & Xilinx Modelsim & Xilinx

Further more details visit : http://www.temasolution.com/downloads.html send your request to : info@temasolution.com

Accumulator Based 3-Weight Pattern Generation.

High-Throughput Soft-Output MIMO Detector Based on PathPreserving Trellis-Search Algorithm.

Xilinx Modelsim & Xilinx Modelsim &

Single Cycle Access Structure for Logic Test.

Area and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-DDWT.

Xilinx Modelsim & Xilinx Modelsim & Xilinx

Further more details visit : http://www.temasolution.com/downloads.html send your request to : info@temasolution.com

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