SoC Design Flow & Tools: Introduction

Jiun-Lang Huang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University

Contents
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Moving to SoC Design Design Methodologies Reuse

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Moving to SoC Design

Evolution of Silicon Technology

The gap between silicon capacity and design capability is growing. Integration of heterogeneoud device technologies is yet another challenge.
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The Consumer Demands

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Higher-level of integration and mobility are the keys. However, under the pressure of
shorter product lifespan, and shrinking design cycles.

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Technology + Demand = SoC

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What is SoC?
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Sysem-on-Chip An IC that integrates the major functional elements of a complete end-product into a single chip.

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An SoC
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usually contains
reusable IP embedded processor, memory real-world interface mixed-signal blocks programmable hardware

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has more than 500 K gates, use .25 mm technology or below, and is not an ASIC.

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SoC Challenges
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Chip complexity
Gate count, heterogeneous device technologies

DSM effects
Signal integrity, timing

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Design methodology Testing

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The Design Productivity Gap

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Design Methodology Transition

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SoC Testing Challenges

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Distributed design and test

Core provider does not know the target environment. System integrator is responsible for manufacturing testing.

Test access
Difficulties to access deeply embedded cores. Bandwidth, I/O pin count limitations.

Test optimization
Minimizing test cost while satisfying constraints such as

power, resources, coverage, etc.

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SoC Design Methodology

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Timing Driven Design Methodology

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Best for moderately sized and complex ASICs that

consists primarily of new logic on DSM processes, and doesnt have a significant utilization of hierarchical design.

Problems:
Looping between synthesis and placement. Long turnaround times for each loop. Unanticipated chip-size growth late in the

design process.
Repeated area, power, and timing

optimizations.
Late creations of adequate manufacturing

test vectors.
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Block-Based Design Methodology

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Ideally, BDD is behaviorally modeled at the system level, where HW/SW tradeoffs and co-verification is performed. New design components are partitioned and mapped onto specified functional RTL blocks. The RTL blocks are then designed to budgeted timing, power, and area constraints.

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BBD Characteristics
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Opportunistically reused functions are poorly characterized, subject to modification, and require pre-verification.

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Hard, firm, or soft programmable processor cores. Extracting testbench data from system-level simulation to support functional verification.
A shift from ASIC-out to system-in verification.

Processor-dominated or custom bus architecture.

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BBD Characteristics - contd

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A predominately flat manufacturing test architecture is used. Timing analysis in both a hierarchical and flat context.
Top-down planning to create block budgets for hierarchical

timing analysis. Flat detailed timing analysis for higher accuracy. Management of guard band becomes critical in DSM design to ensure design convergence.
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Handoff between the design team and an ASIC vendor often occurs at a lower level than in TDD.
A fully placed netlist is normal, not uncommon to go all the

way to GDS II. RTF is attractive, but impractical for all but the least aggressive designs.
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BBD Linchpin Technologies

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Application-specific, high-level system algorithmic analysis tools

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Block floor planning Integrated synthesis and physical design

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Platform-Based Design Methodology

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TDD + BDD + extensive and planned design reuse. PBD separates design into two areas of focus:
Block authoring System-chip integration

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Block Authoring
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Blocks are generated so that they interface easily with multiple target designs. Two new design concepts must be established:
Interface standardization:

Block authoring may be distributed among different design teams if under the same interface specifications and design methodology guidelines.
Virtual system design

To establish the system constraints necessary for block design. For example:
Power profile, Test options, Hard, firm, or soft,
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System-Chip Integration
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Focus on designing and verifying the system architecture, and the interfaces between blocks.

Starts with partitioning the system around the preexisting block-level functions and identifying the new or differentiating functions needed.
System-level partitioning along with performance analysis,

HW/SW design tradeoffs, and functional verification.

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PBD Characteristics
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A PBD design is either derivative design with added functionality, or a convergence design where previously separate functions are integrated. Hierarchical, heterogeneous test architecture
The manufacturing test design is incorporated into the

standard interfaces to support each blocks specific test methodology.

BIST, scan BIST, full/partial scan, JTAG,
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Hierarchical timing analysis

Based on pre-characterized block timing.

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PBD Characteristics - contd

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Hierarchical routing
Interblock routing is to and from area-based block connectors Constraint driven to meet SI and interface timing

requirements.

The physical design is a key stage in the design.

Usually 0.25 mm and smaller process technology. DSM interconnect-dominated delays.

Uses primarily firm or hard VCs.

Predictable, and pre-verified.

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PBD Linchpin Technologies

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High-level, system-level algorithmic and architectural design tools and HW/SW co-design technologies.

Physical layout tools focused on bus planning and block integration.

VC-authoring functional verification tools.

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Summary of Design Characteristics

TDD Design complexity (gate) Design level Design team Primary design Design reuse 500 to 250 K RTL Small, focused Custom logic None BBD 150 K to 1.5 M Behavior/RTL Multi-discplinary Blocks in context, custom interfaces Opportunistic soft, firm, and hard PBD 300 K or more Architecture and VC evaluation Multi-group, multi-disciplinary Interfacing to system and bus Planned firm and hard Silicon-compatible system architecture VCs

Primary optimization Synthesis, gate-level Floor planning, focus architecture block architecture Primary design granularity
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Gates and memory

Functional clusters, cores

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Summary of Design Characteristics contd

TDD Bus architecture Test architecture Mixed-signal Constraint/goal specification Verification level Partition focus None/custom None/scan None Logic sonstraints RTL/gate Synthesis limitations (hierarchical) Custom Scan/JTAG/BIST/ custom A/D, PLLs Blocked-budgeted constraints BBD PBD Standardized/multiple application-specific Hierarchical, parallel scan/JTAG/BIST/ custom Functions, interfaces Interface constraints

Bus function to cycle Mixed (ISS to RTL w/ HW and SW) accurate/RTL/gate Function/ Functions communications (hierarchical) (hierarchical)

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Summary of Design Characteristics contd

TDD Placement Routing Timing analysis Delay calculation Flat Flat Flat Flat BBD Hierarchical Flat Flat with limited hierarchy Flat Flat with limited hierarchy PBD Hierarchical Hierarchical Hierarchical Hierarchical Hierarchical

Physical verification Flat

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Reuse - The Key to SoC Design

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IP Reuse
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TTM will assume a dominant role in product planning. NTRS asserts that design reuse is paramount to realizing their projections.

Reusing IP has long been touted as the fastest way to increasing productivity.

However, we have only seen some small victories, and a lot of unfulfilled promise!!

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Models of Reuse
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Personal Source Core VC (Virtual component)

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Evolution of VC Reuse

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Personal Reuse Portfolio

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Human knowledge based Exercised through reapplying personal or team design experience to produce derivative projects.

Challenges
Does not scale. Dependent on retaining key personnel. Changes to technology or architecture significantly

undermine productivity benefits.

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Transitioning to Source Reuse

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Source Reuse Portfolio

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In BBD, the opportunity to reuse designs created elsewhere begins to open up. Source reuse provides a pre-existing RTL or netlistlevel design that can then be modified to meet the system constraints. Challenges
Eroded productivity if re-verification is required. Testbench development often limits productivity for many

blocks. Hard to evaluate and understand what is available. Poor predictability of performance, area, and power. Most existing IPs are not well documented for reuse, often lacking an adequate testbench.
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Transitioning to Core Reuse

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Core Reuse Portfolio

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Refined and improved in the following ways:

More information is available on the block realization in

silicon (area, timing, footprint, power). More blocks in firm or hard forms. Reusable, placed netlist is in a relevant library (firm). Qualification constraints exist for entering into the reuse VC database and pruning existing low-value entries. Documentation on the context where the block has been used and/or reused. Third-party VC blocks are integrated and specific details on the engagement process with the vendor exist. More participation and mechanisms supporting the block occur from the author for internal VCs.

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Core Reuse Portfolio - contd

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Challenges
The VC core must be modified to adapt to the bus, clock,

test, and power environment of the product design.

Verification of blocks in the system context after modification

is still a problem.
Architectures for dealing with mixed-signal design are ad hoc

in terms of block reuse across products.

The productivity benefits are not growing at the same rate as

the design size and DSM interconnect problems.

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Transitioning to VC Reuse

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VC Reuse Portfolio
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Separation of authoring and integration is most clearly observed. VCs are pre-characterized, pre-verified, and premodeled to target a specific virtual system environment. IPs are differentiated largely by the elegance of the design, the completeness of the models/documentation, and the options. The blocks are known entities, designed to fit together without change.

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VC Reuse Portfolio - contd

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Challenges
TTM forces trade-offs in flexibility and optimality. More high-performance analysis and modeling needed to

support HW/SW partitioning decisions.

Fundamental business models for VC control and protection

are a barrier to inter-company VC sharing.

Porting analog/mixed-signal cores is still manual.

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