DIGITAL SYSTEM DESIGN (EE-414) LAB MANUAL 01

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Introductory Tutorial For Xilinx ISE Foundation

Objectives:
Become familiar with the Xilinx ISE Foundation software package Create a New Project Creating a Verilog Source Verifying Functionality using Behavioral Simulation Simulating Design Functionality

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project: 1. Select File => New Project... The New Project Wizard appears. 2. Type lab1 in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A lab1 subdirectory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below: Product Category: All Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: Verilog (or VHDL) Verify that Enable Enhanced Design Summary is selected. Leave the default values in the remaining fields. When the table is complete, your project properties will look like the following:
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Create a New Project

Design Functionality

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7. Click Next to proceed to the Create New Source window in the New Project Wizard. Atthe end of the next section, your new project will be complete.

Creating a Verilog Source

Create the top-level Verilog source file for the project as follows: 1. Click New Source in the New Project dialog box. 2. Select Verilog Module as the source type in the New Source dialog box. 3. Type in the file name counter. 4. Verify that the Add to Project checkbox is selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port information as shown below:

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7. Click Next, then Finish in the New Source Information dialog box to complete the new source file template. 8. Click Next, then Next, then Finish.

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Design Simulation

Verifying Functionality using Behavioral Simulation

Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench. Create the test bench waveform as follows: 1. Select the fa HDL file in the Sources window. 2. Create a new test bench source by selecting Project New Source. 3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type fa_tbw in the File Name field. 4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next. 6. The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish. 7. You need to set the clock frequency, setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. Since the first module we are going to verify is combinational, so check Combinational (or internal) option in the Clock information tab on the top right corner
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8. Click Finish to complete the timing initialization. 9. You will see waveforms for output and input. Apply different possible combinations at the inputs

10. Save the waveform. 11. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project.

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Simulating Design Functionality

Verify that the counter design functions as you expect by performing behavior simulation as follows: 1. Verify that Behavioral Simulation and fa_tbw are selected in the Sources window. 2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process and doubleclick the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench. 3. To view your simulation results, select the Simulation tab and zoom in on the transitions. The simulation waveform results will look like the following:

Laboratory Rules

4. Verify that the full adder is producing sum and carry as expected. 5. Close the simulation view. If you are prompted with the following message, You have an active simulation open. Are you sure you want to close it?, click Yes to continue. You have now completed simulation of your design using the ISE Simulator. Every system will be used by not more than two students. Students must work on the system allocated to them. And will not be allowed to change their allocated systems Each group must save its projects in a specified folder.

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Assignments

In the next class, you are required to submit verilog code and test bench waveforms for the following circuits i. 4 x 1 Multiplexer ii. 4-bit Carry Look Ahead Adder

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DIGITAL SYSTEM DESIGN (EE-414) LAB MANUAL 02

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Verilog Coding of Simple Combinational Circuits

Objectives:
Practice verilog coding of simple combinational circuits Understanding basic concepts of design hierarchy Learn functional testing of the designed circuit through Test Benches Learn how to find the truth table of a unknown circuit through Test Bench

Example 1: Four Bit Adder Subtracter

In the first example you have to encode the following circuit of Four Bit Adder subtracter in verilog.

Where as

is a full adder module.

Note: You have to follow the proper design hierarchy.

Example 2: Gate Level Implementation of the given circuit.

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DIGITAL SYSTEM DESIGN (EE-414) LAB MANUAL 02

In the second example you have to encode the following circuit in verilog. After that you have to apply a stimulus covering all possible combinations inputs Draw a truth table from the simulation results. Analyze the truth table and give your comments about the functionality of the circuit.

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Assessment and Lab Report

1. Verilog coding of your experiment circuit. 2. Present simulation waveforms. 3. Review of the results to form a truth table to indicate that for each entry the logic simulator give the right results. Feel free to label the waveforms to indicate the proper operation. 1. 2. 3. 4. 5. 6. Name of the project must include your roll no. Code should be well documented. Indentation should be proper. Simulation waveforms should be clear showing all the results. Any plagiarism if found, will cause considerable reduction in grades. No submission will be accepted after the deadline.

Submission Rules

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DIGITAL SYSTEM DESIGN (EE-414) LAB MANUAL 03

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Verilog Coding of Simple Combinational Circuits

Objectives:
Practice verilog coding of simple combinational circuits Learn functional testing of the designed circuit through Test Benches

Problem 1: Implementation of 8 x 3 encoder

In the first example you have to encode the following circuit of Four Bit Adder subtracter in verilog.
8x3 Encoder

Problem 2: Implementation of 3 x 8 decoder

3x8 Decoder

Problem 3: Implementation of 8 x 3 priority encoder

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8x3 Priority Encoder

Assessment and Lab Report

1. In the this lab, you have to encode the above circuits in verilog. 2. After that you have to apply a stimulus and present simulation waveforms covering all possible combinations of inputs 3. Draw a truth table from the simulation results. 4. Review of the results to form a truth table to indicate that for each entry the logic simulator give the right results Name of the project must include your roll no. Code should be well documented. Indentation should be proper. Simulation waveforms should be clear showing all the results. Any plagiarism if found, will cause considerable reduction in grades. No submission will be accepted after the deadline.

Submission Rules
1. 2. 3. 4. 5. 6.

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DIGITAL SYSTEM DESIGN (EE-414) LAB MANUAL 03

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Name Roll No Section Marks

Verilog Coding of Simple Combinational Circuits

Objectives:
Practice verilog coding of simple combinational circuits Learn functional testing of the designed circuit through Test Benches

Problem 1: Implementation of 8 x 3 encoder

In this programming exercise, we want to display each hexadecimal digit (0,1,....9,A,b,C,d,E,F) on the 7-segment display.
D0 D1 D2 D3

Hex to Seven Segment Display Converter

a b c d ef

e f g d

b c

So in order to display, for example, the hexadecimal digit A (10 in decimal), the LEDs with labels a, b, c, e, f, g should be ON, and the other LED with label d should be OFF. This means that the corresponding pins of the converter should have logic-0. Since we can represent each hexadecimal digit by means of 4 bits, well implement a 47 decoder.

Problem 2: Implementation 4 bit Register

In this programming exercise, we are going to implement a simple 4 bit register. This four bit register should be implemented by instantiating a D flipflop 4 times. Clock should be positive edge triggered and reset should be negative edge triggered.

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din clk_p rst_n

4- bit Register

dout

Assessment and Lab Report

1. In the this lab, you have to encode the above circuits in verilog. 2. After that you have to apply a stimulus and present simulation waveforms covering all possible combinations of inputs 3. Review of the results to form a truth table to indicate that for each entry the logic simulator gives the right results Name of the project must include your roll no. Code should be well documented. Indentation should be proper. Simulation waveforms should be clear showing all the results. Any plagiarism if found, will cause considerable reduction in grades. No submission will be accepted after the deadline.

Submission Rules
1. 2. 3. 4. 5. 6.

DEPARTMENT OF ELECTRICAL ENGINEERING

UNIVERSITY OF GUJRAT