DesignandImplementationofa32bitRISCProcessoronXilinx FPGA

WaelMElMedany, KhalidA AlKooheji DepartmentofCommunicationsandElectricalEngineering,FacultyofEngineering,FayoumUniversity,Egypt, Computer EngineeringDepartment, InformationTechnologyCollege,UniversityOfBahrain,32038Bahrain, Email: wmelmedany@itc.uob.bh, waelelmedany@gmail.com,TelNo:+97339764964 Alba,Manama,BahrainPoBox570

Abstract
This paper concerned with the designandimplementationof a 32bit Reduced Instruction Set Computer (RISC) processor on a Field Programmable Gate Arrays (FPGAs). The processorhas been designed with VHDL, synthesizedusingXilinxISE9.1iWebpack,simulatedusingModelSimsimulator,andthenimplementedonXilinx Spartan2EFPGAthathas143availableInput/Outputpinsand50MHzclockoscillator.Thetestbenchwaveforms forthedifferentpartsoftheprocessorare presented andthesystemarchitectureisdemonstrated. Keywords:FPGA,CPU,VHDL,RISC,Processor.

1.Introduction
ComputerEngineeringandComputerDesignareverymuchconcernedwiththecostandperformanceof components in the implementation domain. Reduced Instruction Set Computer (RISC) focuses on reducing the numberandcomplexityofinstructionsinthemachine[1,2]. FieldProgrammableGateArrays(FPGAs)aregrowing fast with cost reduction compared to ASIC design [3]. In this paper a low cost 32bit RISC Processor has been designed and synthesized, the design has been described using VHDL, and some components have been implementedandtestedonXilinxFPGA[4,5,6,and7].Spartan2Edevelopmentboard,DIO1,andDIO2extension boardsfromDigilenthave beenusedforthehardwareimplementation.TheWebpack fromXilinxandModelSim havebeenusedforsynthesisandsimulation. ThetextinthisarticleisorganizedasfollowstheintroductionisgiveninsectionIsectionIIistalkingaboutthe systemarchitecturethedesignoftheControlUnitisgiveninsectionIIIinsectionIVwedefinethemainstructure oftheDataPaththedesignoftheROMisgiveninsectionVsectionVIwillpresentsthesimulationresultsforthe differentpartsoftheprocessortheconclusionand futurework willbegivenattheendinsectionVII.

2.SystemArchitecture
The RISC processor presented in this paper consists of three components as shown in Figure .1, these components are, the Control Unit (CU), the DataPath, andthe ROM. The Central Processing Unit (CPU) has 17 instructions. Inthe followingsectionswewilldescribethedesignofthethreemaincomponentsoftheprocessor.

ROM
Rom address, dataand readsignals RCL MCL

Control Unit

ALUCL BUCL

DATA PATH

Figure(1)SystemArchitecture

3.DesignoftheControlUnit
The control unit design is based on using FSM (Finite State Machine) and we designed it ina way that allowseachstatetorunatoneclockcycle,thefirststateistheresetwhichisinitializestheCPUinternalregisters and variables. The machine goes to the reset state by enabling the reset signal for a certain number of clocks. Following thereset state would be the instruction fetchingand decoding states which will enable the appropriate signalsforreadinginstructiondatafromtheROMthendecodingthepartsoftheinstruction.Thedecodingstatewill alsoselectthenextstatedependingontheinstruction,sinceeveryinstructionhasitsownsetofstates,thecontrol unitwilljumptothecorrectstatebasedontheinstructiongiven.Afterallstatesofarunninginstructionarefinished, thelastonewillreturntothefetchstatewhichwill allowustoprocessthenextinstructionintheprogram.Figure.2 showsthestatediagramforthecontrolunit.

4.DesignoftheDataPath
The Data Path consists of subunits that are necessary for performing all of arithmetic and logic operations. A Datapathisa hardwarethatperformsdataprocessingoperations[8,9,10,and11].Itisoneoftwotypesofmodules usedtorepresentadigitalsystem,theotherbeingacontrolunit.TheDatapathmodelwedesignedconsistsofthe units necessary to perform all the operations on the data selected by the control unit. The components include a RegisterFile,Arithmetic/LogicUnit,MemoryInterfaceandBranchingUnitasshowninfigure.3.The RegisterFile holdsthetableofthe32generalpurposeregistersavailabletotheCPU,ithastwooutputports(output1,outpu2)and one input port, also it has a 16 bit bus connected directly to the Control Unit to pass immediate data. The ALU designconsistsoftwoinputportsandoneoutputportwhichmainlyperformsoperationsontwooperands.Ithasa designsimilartothecontrolunitwhichselectsanoperationbasedonacodegivenbytheALUCL. TheMemory Interfacewasdesignedtoaccommodatesimpleload/storeoperationswiththe16x32memory.Theeffectiveaddress is calculated by adding the content of the address registerand the immediate data. TheBranch Unit calculates a givenconditionbythecontrolunitandraisesabranch flagwhethertheconditionismetornot,andiftheflagis raised,itsendsthebranchaddressbacktothecontrolunitinordertoreplacetheprogramcounter.Thecontrollines comingfromthecontrolunitoperatealltheunitsinthedatapath.Thepathstartsfromtheregisterfilethathastwo outputportswhichareconnectedtoalltheotherunits,afterthattheprocessingisdonebyoneoftheotherunitsthen finallyreturnedbacktotheregisterfilesinputportusingthemultiplexer. Thesignalsusedinthedatapathare forwardedfromthecontrolunittoeachsubcomponentasneeded.
MCL BUCL
S0/Fetch

Regfileoutput1and2

RCL

Register File

BranchUnit

S4/op S1/Decode

ALUCL

ALU

Memory

Mux selection 00
S3/op S2/op

Mux selection 01

MUX 4*1

Mux_selectection(CU)

Figure(2)StateDiagramfortheCUDesign

Figure(3)theSubcomponentsoftheDataPath

5.DesignoftheROM
TheCPUhasabuiltinROMwhichenablesustoprogramsimplecodeandexecuteit.Itisabasic16x32ROM anditis32bitaligned. TheListof signalsintheROM are: address:addresssentbythecontrolunit data_out:thedatathatiscontainedthegivenaddress read:thesignaltoenablereadingfromtheROM ready:thesignaltoindicatewhentheROMisreadyforreading clk:themainclocksignal reset:theinitialresetsignal

5.SimulationResults
Inthissectionwearegoingtoshowsometestbenchwaveformsthatwillverifytheworkingoperationof ourRISCProcessor.InFigure.4, thefollowingsimple programwashardcodedandsimulatedonthe CPU: LI SHW r2,#0000, SHWr2, r1, LI r2,#0030, LI r1,#0000, SHW r1,r1, LI r1,#0001, LIr3,#0000 r3,r3,LI r3,#0008, LI r4,#0000,SHW r4,r4, LI r4,#0004, ADD r4,r4,r1, BRAG r2,r3,r4

Thereare5mainsignalsthatareviewedinthroughoutthesimulation.Thesim_clocksignalistheclockgenerated forthesimulationandrunsat50Mhz,instruction_fetchsignalshows whenthecontrolunitrequestsdatafromthe ROM,theinstruction_address32bitbusistheaddressof theinstructionbeingfetched, theinstruction_data32bitbus isthedatasentoutfromtheROM,andtheresetstateisenabledfor3.5cycletogiveenoughtimeforallunitsto resetandinitialize,afterthatwecanseethefirstinstructionbeginningataddress0isexecutedfollowedbyallthe proceedinginstructionsuntiltheinstructionataddress40WhichistheshifthalfwordSHW.Figure.5showsthe simulationresultsoftheALU,inwhichweareattemptingtousetheadditionoperationtoaddthevalues(44+22), we send the opcode of the add operation (33) through the ALUCL signal and the result (66) will be in the alu_output_32bitbus.InFigure.6,thetestbenchwaveformfortheMemoryUnitisshown,inwhichwedemonstrate how the unit can be used to read some data from the RAM, our RAM is a 16 slot array of 32bit vectors, the following data are stored in the RAM for simulation purposes 0x12345678 is stored in location 00, and 0x11133344 is stored in location 04. Figure .7 shows the simulationresults of the Register File Unit. Inthis simulation,wedemonstrate howtosenddatatoaspecificregisterinthefileandstoreit,wetriedtostorethevalue 48intoregister2,the reg_testsignalshowsanydatawrittentothe inputportoftheregisterfile.

Figure(4)SimulationResultsofaSimpleProgramExecution

Figure(5)SimulationResultsfortheALU

Figure(6)SimulationResultsfortheMemoryUnit

Figure(7)SimulationResultsfortheRegisterFileUnit

4.ConclusionandFutureWork
32bit RISC Process has been design and implemented in hardware on Xilinx Spartan 2E FPGA. The designhasbeenachievedusingVHDLandsimulatedwithModelSim.DigilentSpartan2Edevelopmentboardhas been used for the hardware part. Most of the goals were achieved and simulation shows that the processor is working perfectly, but the Spartan 2E FPGA was not sufficient for implementing the whole design into a real hardware, since the total available logic gate in Spartan 2E is 200K Logic Gate, which was not enough for implementingthewholeprocessor,butpartsoftheprocessorhavebeenimplementedandtestinarealhardware. Future work will be added by increasingthe number of instructions and make a pipelined design with less clock cyclesperinstructionandmoreimprovementcanbeaddedinthefuturework.

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