1MRK502027-UEN A en Technical Reference Manual REG670 1.2

Relion® 670 series
Generator protection REG670

Technical reference manual
Document ID: 1MRK 502 027-UEN
Issued: September 2011
Revision: A
Product version: 1.2
© Copyright 2011 ABB. All rights reserved

Copyright
This document and parts thereof must not be reproduced or copied without written
permission from ABB, and the contents thereof must not be imparted to a third
party, nor used for any unauthorized purpose.
The software or hardware described in this document is furnished under a license

and may be used or disclosed only in accordance with the terms of such license.
Trademarks
ABB and Relion are registered trademarks of ABB Group. All other brand or
product names mentioned in this document may be trademarks or registered
trademarks of their respective holders.
Warranty
Please inquire about the terms of warranty from your nearest ABB representative.
ABB AB
Substation Automation Products
SE-721 59 Västerås
Sweden
Telephone: +46 (0) 21 32 50 00
Facsimile: +46 (0) 21 14 69 18
http://www.abb.com/substationautomation
Disclaimer
The data, examples and diagrams in this manual are included solely for the concept
or product description and are not to be deemed as a statement of guaranteed
properties. All persons responsible for applying the equipment addressed in this
manual must satisfy themselves that each intended application is suitable and
acceptable, including that any applicable safety or other operational requirements
are complied with. In particular, any risks in applications where a system failure and/
or product failure would create a risk for harm to property or persons (including but
not limited to personal injuries or death) shall be the sole responsibility of the
person or entity applying the equipment, and those so responsible are hereby
requested to ensure that all measures are taken to exclude or mitigate such risks.
This document has been carefully checked by ABB but deviations cannot be
completely ruled out. In case any errors are detected, the reader is kindly requested
to notify the manufacturer. Other than under explicit contractual commitments, in
no event shall ABB be responsible or liable for any loss or damage resulting from
the use of this manual or the application of the equipment.
Conformity
This product complies with the directive of the Council of the European
Communities on the approximation of the laws of the Member States relating to
electromagnetic compatibility (EMC Directive 2004/108/EC) and concerning
electrical equipment for use within specified voltage limits (Low-voltage directive
2006/95/EC). This conformity is the result of tests conducted by ABB in
accordance with the product standards EN 50263 and EN 60255-26 for the EMC
directive, and with the product standards EN 60255-1 and EN 60255-27 for the low
voltage directive. The IED is designed in accordance with the international
standards of the IEC 60255 series.
Table of contents
Table of contents
Section 1 Introduction.....................................................................25
Introduction to the technical reference manual.................................25
About the complete set of manuals for an IED............................25
About the technical reference manual.........................................26
This manual.................................................................................27
Introduction.............................................................................27
Principle of operation..............................................................27
Input and output signals.........................................................30
Function block........................................................................30
Setting parameters.................................................................30
Technical data........................................................................31
Intended audience.......................................................................31
Related documents......................................................................31
Revision notes.............................................................................32
Section 2 Analog inputs..................................................................33

Introduction.......................................................................................33
Operation principle...........................................................................33
Function block..................................................................................34
Setting parameters...........................................................................34
Section 3 Local HMI.......................................................................41

Human machine interface ................................................................41
Small size HMI..................................................................................43
Small............................................................................................43
Design.........................................................................................43
Medium size graphic HMI.................................................................45
Medium........................................................................................45
Design.........................................................................................45
Keypad.............................................................................................47
LED...................................................................................................48
Introduction..................................................................................48
Status indication LEDs................................................................48
Indication LEDs...........................................................................48
Local HMI related functions..............................................................49
Introduction..................................................................................49
General setting parameters.........................................................50
Status LEDs.................................................................................50
Design....................................................................................50
Function block........................................................................50
1
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Indication LEDs...........................................................................51
Introduction.............................................................................51
Design....................................................................................51
Function block........................................................................58
Setting parameters.................................................................58
Section 4 Basic IED functions........................................................61

Authorization.....................................................................................61
Principle of operation...................................................................61
Authorization handling in the IED...........................................62
Self supervision with internal event list.............................................63
Introduction..................................................................................63
Internal signals.......................................................................65
Run-time model......................................................................67
Function block.............................................................................68
Output signals..............................................................................68
Setting parameters......................................................................68
Technical data.............................................................................69
Time synchronization........................................................................69
Introduction..................................................................................69
General concepts...................................................................69
Real-time clock (RTC) operation............................................72
Synchronization alternatives..................................................73
Function block.............................................................................76
Output signals..............................................................................76
Technical data.............................................................................79
Parameter setting groups.................................................................79
Introduction..................................................................................79
Function block.............................................................................81
Input and output signals..............................................................81
ChangeLock function CHNGLCK.....................................................82
Introduction..................................................................................82
Function block.............................................................................83
Test mode functionality TEST..........................................................83
2
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Introduction..................................................................................83
Function block.............................................................................85
IED identifiers...................................................................................86
Introduction..................................................................................86
Product information..........................................................................87
Introduction..................................................................................87
Factory defined settings..............................................................87
Signal matrix for binary inputs SMBI................................................88
Introduction..................................................................................88
Function block.............................................................................89
Signal matrix for binary outputs SMBO ...........................................90
Introduction..................................................................................90
Function block.............................................................................90
Signal matrix for mA inputs SMMI....................................................91
Introduction..................................................................................91
Function block.............................................................................92
Signal matrix for analog inputs SMAI...............................................92
Introduction..................................................................................92
Frequency values........................................................................93
Function block.............................................................................94
Summation block 3 phase 3PHSUM................................................97
Introduction..................................................................................97
Function block.............................................................................98
Authority status ATHSTAT...............................................................99
Introduction..................................................................................99
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Function block.............................................................................99
Output signals..............................................................................99
Setting parameters....................................................................100
Denial of service DOS....................................................................100
Introduction................................................................................100
Principle of operation.................................................................100
Function blocks..........................................................................100
Signals.......................................................................................101
Settings......................................................................................101
Section 5 Differential protection...................................................103

Generator differential protection GENPDIF ...................................103
Introduction................................................................................103
Function calculation principles.............................................105
Fundamental frequency differential currents........................105
Supplementary criteria.........................................................109
Harmonic restrain.................................................................112
Cross-block logic scheme....................................................112
Function block...........................................................................116
Input and output signals............................................................116
Technical data...........................................................................118
Transformer differential protection T2WPDIF and T3WPDIF ........119
Introduction ...............................................................................119
Function calculation principles.............................................122
Logic diagram.......................................................................144
Function block...........................................................................150
Technical data...........................................................................159
Restricted earth fault protection, low impedance REFPDIF ..........160
Introduction................................................................................160
Fundamental principles of the restricted earthfault
protection..............................................................................161
Restricted earth-fault protection, low impedance as a
differential protection............................................................164
Calculation of differential current and bias current...............165
Detection of external earth faults..........................................167
Algorithm of the restricted earth fault protection...................168
Function block...........................................................................169
4
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Technical data...........................................................................171
1Ph High impedance differential protection HZPDIF .....................171
Identification..............................................................................171
Introduction................................................................................171
Logic diagram.......................................................................172
Function block...........................................................................172
Technical data...........................................................................173
Section 6 Impedance protection ..................................................175

Full-scheme distance measuring, Mho characteristic
ZMHPDIS ......................................................................................175
Introduction................................................................................175
Full scheme measurement...................................................175
Impedance characteristic.....................................................176
Basic operation characteristics.............................................177
Theory of operation..............................................................178
Simplified logic diagrams......................................................187
Function block...........................................................................190
Technical data...........................................................................193
Directional impedance element for mho characteristic
ZDMRDIR.......................................................................................193
Introduction................................................................................194
Directional impedance element for mho characteristic
ZDMRDIR.............................................................................194
Function block...........................................................................197
Pole slip protection PSPPPAM ......................................................198
Introduction................................................................................198
Function block...........................................................................203
Technical data...........................................................................204
Loss of excitation LEXPDIS............................................................205
Introduction................................................................................205
5
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Function block...........................................................................210
Technical data...........................................................................212
Sensitive rotor earth fault protection, injection based
ROTIPHIZ ......................................................................................212
Introduction................................................................................212
The injection unit REX060....................................................214
Rotor Earth Fault Protection function...................................215
General measurement of earth fault impedance..................216
Simplified logic diagram.......................................................218
Commissioning tool ICT.......................................................220
Description of input signals........................................................223
Description of output signals.....................................................223
Function block...........................................................................225
Technical data...........................................................................227
100% stator earth fault protection, injection based STTIPHIZ .......227
Introduction................................................................................228
Configuration principle..........................................................229
Generator system earthing methods....................................231
100% Stator earth fault protection function..........................235
General measurement of earth fault impedance..................239
Measuring reference impedance..........................................241
Simplified logic diagram.......................................................246
The commissioning tool ICT.................................................247
Description of input signals........................................................249
Description of output signals.....................................................250
Function block...........................................................................251
Input and Output signals............................................................252
Technical data...........................................................................254
Section 7 Current protection.........................................................255

Instantaneous phase overcurrent protection PHPIOC ..................255
Introduction................................................................................255
Function block...........................................................................256
6
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Technical data...........................................................................257
Four step phase overcurrent protection OC4PTOC ......................257
Introduction................................................................................257
Function block...........................................................................262
Technical data...........................................................................269
Instantaneous residual overcurrent protection EFPIOC ................270
Introduction................................................................................270
Function block...........................................................................271
Technical data...........................................................................272
Four step residual overcurrent protection EF4PTOC ....................272
Introduction................................................................................272
Operating quantity within the function..................................273
Internal polarizing.................................................................274
External polarizing for earth-fault function............................276
Base quantities within the protection....................................276
Internal earth-fault protection structure................................276
Four residual overcurrent steps............................................277
Directional supervision element with integrated
directional comparison function............................................278
Second harmonic blocking element.....................................280
Switch on to fault feature......................................................282
Function block...........................................................................284
Technical data...........................................................................291
Four step directional negative phase sequence overcurrent
protection NS4PTOC .....................................................................291
Introduction................................................................................292
Operating quantity within the function..................................292
Internal polarizing facility of the function..............................293
External polarizing for negative sequence function..............294
Base quantities within the function.......................................294
Internal negative sequence protection structure..................295
Four negative sequence overcurrent stages........................295
Directional supervision element with integrated
directional comparison function............................................296
7
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Function block...........................................................................299
Technical data...........................................................................305
Sensitive directional residual overcurrent and power protection
SDEPSDE .....................................................................................305
Introduction................................................................................305
Function inputs.....................................................................307
Function block...........................................................................313
Technical data...........................................................................317
Thermal overload protection, two time constants TRPTTR ...........318
Introduction................................................................................318
Function block...........................................................................322
Technical data...........................................................................324
Breaker failure protection CCRBRF ..............................................324
Introduction................................................................................324
Function block...........................................................................327
Technical data...........................................................................329
Pole discordance protection CCRPLD ..........................................330
Introduction................................................................................330
Pole discordance signaling from circuit breaker...................333
Unsymmetrical current detection..........................................333
Function block...........................................................................333
Technical data...........................................................................335
Directional underpower protection GUPPDUP...............................335
Introduction................................................................................335
Low pass filtering..................................................................338
Calibration of analog inputs..................................................338
Function block...........................................................................339
8
Table of contents
Technical data...........................................................................341
Directional overpower protection GOPPDOP ................................342
Introduction................................................................................342
Low pass filtering..................................................................345
Calibration of analog inputs..................................................345
Function block...........................................................................346
Technical data...........................................................................349
Negativ sequence time overcurrent protection for machines
NS2PTOC ......................................................................................349
Introduction................................................................................349
Start sensitivity.....................................................................352
Alarm function......................................................................352
Logic diagram.......................................................................352
Function block...........................................................................353
Technical data...........................................................................355
Accidental energizing protection for synchronous generator
AEGGAPC......................................................................................355
Introduction ...............................................................................355
Function block...........................................................................357
Technical data...........................................................................358
Section 8 Voltage protection........................................................359

Two step undervoltage protection UV2PTUV ................................359
Introduction................................................................................359
Measurement principle.........................................................360
Time delay............................................................................360
Blocking................................................................................365
Design..................................................................................366
Function block...........................................................................368
Technical data...........................................................................371
Two step overvoltage protection OV2PTOV ..................................372
9
Table of contents
Introduction................................................................................372
Time delay............................................................................373
Blocking................................................................................379
Design..................................................................................379
Function block...........................................................................381
Technical data...........................................................................384
Two step residual overvoltage protection ROV2PTOV .................384
Introduction................................................................................384
Time delay............................................................................385
Blocking................................................................................390
Design..................................................................................390
Function block...........................................................................391
Technical data...........................................................................394
Overexcitation protection OEXPVPH ............................................394
Introduction................................................................................394
Measured voltage.................................................................397
Operate time of the overexcitation protection.......................398
Cooling.................................................................................402
Overexcitation protection function measurands...................402
Overexcitation alarm............................................................403
Logic diagram.......................................................................403
Function block...........................................................................404
Technical data...........................................................................406
Voltage differential protection VDCPTOV ......................................406
Introduction................................................................................406
Function block...........................................................................408
Technical data...........................................................................409
100% Stator earth fault protection, 3rd harmonic based
STEFPHIZ......................................................................................409
10
Table of contents
Introduction................................................................................410
Function block...........................................................................416
Technical data...........................................................................418
Section 9 Frequency protection....................................................419

Underfrequency protection SAPTUF .............................................419
Introduction................................................................................419
Time delay............................................................................420
Voltage dependent time delay..............................................420
Blocking................................................................................422
Design..................................................................................422
Function block...........................................................................423
Technical data...........................................................................424
Overfrequency protection SAPTOF ...............................................424
Introduction................................................................................425
Time delay............................................................................425
Blocking................................................................................426
Design..................................................................................426
Function block...........................................................................427
Technical data...........................................................................428
Rate-of-change frequency protection SAPFRC .............................428
Introduction................................................................................428
Time delay............................................................................429
Blocking................................................................................429
Design..................................................................................430
Function block...........................................................................431
Technical data...........................................................................432
Section 10 Multipurpose protection................................................433
11
Table of contents
General current and voltage protection CVGAPC..........................433

Introduction................................................................................433
Inadvertent generator energization......................................434
Measured quantities within CVGAPC...................................434
Base quantities for CVGAPC function..................................436
Built-in overcurrent protection steps.....................................437
Built-in undercurrent protection steps...................................442
Built-in overvoltage protection steps....................................443
Built-in undervoltage protection steps..................................443
Inadvertent generator energizing.........................................443
Logic diagram.......................................................................445
Function block...........................................................................450
Technical data...........................................................................460
Rotor earth fault protection.............................................................461
Introduction................................................................................461
Rotor earth fault....................................................................462
Technical data...........................................................................465
Section 11 Secondary system supervision.....................................467

Current circuit supervision CCSRDIF ............................................467
Introduction................................................................................467
Function block...........................................................................469
Technical data...........................................................................470
Fuse failure supervision SDDRFUF...............................................470
Introduction................................................................................470
Zero and negative sequence detection................................471
Delta current and delta voltage detection.............................475
Dead line detection...............................................................477
Main logic.............................................................................477
Function block...........................................................................481
Technical data...........................................................................482
Section 12 Control..........................................................................485
12
Table of contents
Synchrocheck, energizing check, and synchronizing

SESRSYN......................................................................................485
Introduction................................................................................485
Basic functionality.................................................................486
Logic diagrams.....................................................................486
Function block...........................................................................495
Technical data...........................................................................501
Apparatus control APC...................................................................501
Introduction................................................................................501
Error handling............................................................................502
Bay control QCBAY...................................................................503
Introduction...........................................................................503
Function block......................................................................503
Input and output signals.......................................................504
Setting parameters...............................................................504
Local/Remote switch.................................................................504
Introduction...........................................................................504
Principle of operation............................................................504
Function block......................................................................506
Switch controller SCSWI...........................................................507
Introduction...........................................................................508
Function block......................................................................513
Circuit breaker SXCBR..............................................................514
Introduction...........................................................................515
Function block......................................................................519
Circuit switch SXSWI.................................................................520
Introduction...........................................................................520
Function block......................................................................524
Bay reserve QCRSV..................................................................525
13
Table of contents
Introduction...........................................................................526
Function block......................................................................528
Reservation input RESIN...........................................................530
Introduction...........................................................................530
Function block......................................................................532
Interlocking ....................................................................................534
Introduction................................................................................534
Logical node for interlocking SCILO .........................................537
Introduction...........................................................................537
Logic diagram.......................................................................537
Function block......................................................................538
Interlocking for busbar earthing switch BB_ES .........................538
Introduction...........................................................................539
Function block......................................................................539
Logic diagram.......................................................................539
Interlocking for bus-section breaker A1A2_BS..........................540
Introduction...........................................................................540
Function block......................................................................541
Logic diagram.......................................................................542
Interlocking for bus-section disconnector A1A2_DC ................544
Introduction...........................................................................545
Function block......................................................................545
Logic diagram.......................................................................546
Interlocking for bus-coupler bay ABC_BC ................................547
Introduction...........................................................................547
Function block......................................................................548
Logic diagram.......................................................................549
Interlocking for 1 1/2 CB BH .....................................................554
Introduction...........................................................................554
Function blocks....................................................................555
Logic diagrams.....................................................................557
14
Table of contents

Interlocking for double CB bay DB ...........................................566
Introduction...........................................................................566
Function block......................................................................567
Logic diagrams.....................................................................569
Input and output signals ......................................................572
Interlocking for line bay ABC_LINE ..........................................575
Introduction...........................................................................575
Function block......................................................................576
Logic diagram.......................................................................577
Interlocking for transformer bay AB_TRAFO ............................584
Introduction...........................................................................585
Function block......................................................................586
Logic diagram.......................................................................587
Position evaluation POS_EVAL.................................................590
Introduction...........................................................................590
Logic diagram.......................................................................590
Function block......................................................................591
Logic rotating switch for function selection and LHMI
presentation SLGGIO.....................................................................591
Introduction................................................................................591
Functionality and behaviour ................................................593
Graphical display..................................................................593
Function block...........................................................................595
Selector mini switch VSGGIO.........................................................597
Introduction................................................................................597
Function block...........................................................................598
Generic double point function block DPGGIO................................599
Introduction................................................................................599
Function block...........................................................................600
Settings......................................................................................600
Single point generic control 8 signals SPC8GGIO.........................600
15
Table of contents
Introduction................................................................................600
Function block...........................................................................601
AutomationBits, command function for DNP3.0 AUTOBITS..........602
Introduction................................................................................603
Function block...........................................................................604
Single command, 16 signals SINGLECMD....................................619
Introduction................................................................................619
Function block...........................................................................620
Section 13 Logic.............................................................................623
Tripping logic SMPPTRC ...............................................................623
Introduction................................................................................623
Logic diagram.......................................................................625
Function block...........................................................................628
Technical data...........................................................................630
Trip matrix logic TMAGGIO............................................................630
Introduction................................................................................630
Function block...........................................................................632
Configurable logic blocks................................................................634
Introduction................................................................................634
Inverter function block INV........................................................634
OR function block OR................................................................635
AND function block AND...........................................................636
Timer function block TIMER......................................................636
Pulse timer function block PULSETIMER..................................637
Exclusive OR function block XOR.............................................637
Loop delay function block LOOPDELAY...................................638
Set-reset with memory function block SRMEMORY.................638
Reset-set with memory function block RSMEMORY.................639
16
Table of contents
Controllable gate function block GATE......................................640

Settable timer function block TIMERSET..................................641
Technical data...........................................................................642
Fixed signal function block FXDSIGN............................................642
Function block...........................................................................643
Boolean 16 to Integer conversion B16I..........................................644
Introduction................................................................................644
Function block...........................................................................644
Boolean 16 to Integer conversion with logic node
representation B16IFCVI................................................................645
Introduction................................................................................645
Function block...........................................................................646
Integer to Boolean 16 conversion IB16..........................................647
Introduction................................................................................647
Function block...........................................................................648
Integer to Boolean 16 conversion with logic node
representation IB16FCVB...............................................................649
Introduction................................................................................649
Function block...........................................................................650
Section 14 Monitoring.....................................................................653
Measurements................................................................................653
Introduction................................................................................654
Measurement supervision....................................................655
Measurements CVMMXN.....................................................659
Phase current measurement CMMXU.................................664
Phase-phase and phase-neutral voltage measurements
VMMXU, VNMMXU..............................................................665
17
Table of contents
Voltage and current sequence measurements VMSQI,

CMSQI..................................................................................665
Function block...........................................................................665
Technical data...........................................................................683
Event counter CNTGGIO................................................................683
Identification..............................................................................683
Introduction................................................................................683
Reporting..............................................................................684
Design..................................................................................684
Function block...........................................................................685
Input signals..............................................................................685
Technical data...........................................................................686
Event function EVENT....................................................................686
Introduction................................................................................686
Function block...........................................................................688
Logical signal status report BINSTATREP.....................................691
Introduction................................................................................691
Function block...........................................................................692
Measured value expander block RANGE_XP................................693
Introduction................................................................................694
Function block...........................................................................694
Disturbance report DRPRDRE.......................................................695
Introduction................................................................................695
Function block...........................................................................703
Technical data...........................................................................716
Event list.........................................................................................716
Introduction................................................................................716
18
Table of contents
Function block...........................................................................717
Input signals..............................................................................717
Technical data...........................................................................717
Indications......................................................................................717
Introduction................................................................................717
Function block...........................................................................719
Input signals..............................................................................719
Technical data...........................................................................719
Event recorder ...............................................................................719
Introduction................................................................................719
Function block...........................................................................720
Input signals..............................................................................720
Technical data...........................................................................720
Trip value recorder.........................................................................720
Introduction................................................................................720
Function block...........................................................................721
Input signals..............................................................................721
Technical data...........................................................................722
Disturbance recorder......................................................................722
Introduction................................................................................722
Memory and storage............................................................723
IEC 60870-5-103..................................................................724
Function block...........................................................................725
Technical data...........................................................................725
Section 15 Metering.......................................................................727
Pulse-counter logic PCGGIO..........................................................727
Introduction................................................................................727
Function block...........................................................................729
Technical data...........................................................................731
Function for energy calculation and demand handling
ETPMMTR......................................................................................731
Introduction................................................................................731
Function block...........................................................................732
19
Table of contents

Section 16 Station communication.................................................735

Overview.........................................................................................735
IEC 61850-8-1 communication protocol.........................................735
Technical data...........................................................................736
IEC 61850 generic communication I/O functions SPGGIO,
SP16GGIO................................................................................736
Introduction...........................................................................736
Function block......................................................................736
IEC 61850 generic communication I/O functions MVGGIO.......738
Function block......................................................................738
IEC 61850-8-1 redundant station bus communication..............739
Introduction...........................................................................739
Function block......................................................................741
Output signals......................................................................741
LON communication protocol.........................................................741
Introduction................................................................................741
Technical data...........................................................................760
SPA communication protocol.........................................................760
Introduction................................................................................760
Communication ports...........................................................768
Design.......................................................................................768
Technical data...........................................................................769
IEC 60870-5-103 communication protocol.....................................769
Introduction................................................................................769
General.................................................................................769
Communication ports...........................................................779
Function block...........................................................................779
20
Table of contents

Technical data...........................................................................790
Horizontal communication via GOOSE for interlocking
GOOSEINTLKRCV.........................................................................790
Function block...........................................................................790
Goose binary receive GOOSEBINRCV..........................................793
Function block...........................................................................793
Multiple command and transmit MULTICMDRCV,
MULTICMDSND.............................................................................794
Introduction................................................................................795
Design.......................................................................................795
General.................................................................................795
Function block...........................................................................796
Section 17 Remote communication................................................799

Binary signal transfer......................................................................799
Introduction................................................................................799
Transmission of analog data from LDCM LDCMTransmit..............803
Function block...........................................................................803
Section 18 IED hardware...............................................................805

Overview.........................................................................................805
Variants of case and local HMI display size..............................805
Case from the rear side.............................................................808
Hardware modules.........................................................................812
Overview....................................................................................812
Combined backplane module (CBM).........................................813
Introduction...........................................................................813
Functionality.........................................................................813
Design..................................................................................814
Universal backplane module (UBM)..........................................816
Introduction...........................................................................816
Functionality.........................................................................816
21
Table of contents
Design..................................................................................816
Numeric processing module (NUM)..........................................818
Introduction...........................................................................818
Functionality.........................................................................818
Block diagram.......................................................................819
Power supply module (PSM).....................................................820
Introduction...........................................................................820
Design..................................................................................820
Technical data......................................................................820
Local human-machine interface (Local HMI).............................821
Transformer input module (TRM)..............................................821
Introduction...........................................................................821
Design..................................................................................821
Technical data......................................................................822
Analog digital conversion module, with time
synchronization (ADM) .............................................................823
Introduction...........................................................................823
Design..................................................................................823
Binary input module (BIM).........................................................825
Introduction...........................................................................825
Design..................................................................................825
Technical data......................................................................829
Binary output modules (BOM)...................................................829
Introduction...........................................................................829
Design..................................................................................829
Technical data......................................................................831
Binary input/output module (IOM)..............................................832
Introduction...........................................................................832
Design..................................................................................832
Technical data......................................................................834
mA input module (MIM).............................................................835
Introduction...........................................................................835
Design..................................................................................835
Technical data......................................................................837
Serial and LON communication module (SLM) ........................837
Introduction...........................................................................837
Design..................................................................................837
Technical data......................................................................839
Optical ethernet module (OEM).................................................839
Introduction...........................................................................839
Functionality.........................................................................839
Design..................................................................................840
Technical data......................................................................840
22
Table of contents
Line data communication module (LDCM)................................841

Introduction...........................................................................841
Design..................................................................................841
Technical data......................................................................842
GPS antenna.............................................................................843
Introduction...........................................................................843
Design..................................................................................843
Technical data......................................................................845
IRIG-B time synchronization module IRIG-B.............................846
Introduction...........................................................................846
Design..................................................................................846
Technical data......................................................................847
Dimensions.....................................................................................848
Case without rear cover.............................................................848
Case with rear cover..................................................................850
Flush mounting dimensions.......................................................852
Side-by-side flush mounting dimensions...................................853
Wall mounting dimensions.........................................................854
External resistor unit for high impedance differential
protection...................................................................................854
External current transformer unit...............................................855
Mounting alternatives.....................................................................856
Flush mounting..........................................................................856
Overview..............................................................................856
Mounting procedure for flush mounting................................857
19” panel rack mounting............................................................858
Overview..............................................................................858
Mounting procedure for 19” panel rack mounting.................859
Wall mounting............................................................................859
Overview..............................................................................859
Mounting procedure for wall mounting.................................860
How to reach the rear side of the IED..................................861
Side-by-side 19” rack mounting.................................................861
Overview..............................................................................861
Mounting procedure for side-by-side rack mounting............862
IED in the 670 series mounted with a RHGS6 case.............862
Side-by-side flush mounting......................................................863
Overview..............................................................................863
Mounting procedure for side-by-side flush mounting...........864
Technical data................................................................................864
Enclosure...................................................................................864
Connection system....................................................................865
Influencing factors.....................................................................865
23
Table of contents
Type tests according to standard..............................................866
Section 19 Injection equipment hardware......................................869

Overview.........................................................................................869
Front view of injection unit, coupling capacitor and shunt
resitor unit..................................................................................869
REX060 Injection unit...........................................................869
REX060 Front panel controls...............................................870
Coupling capacitor unit REX061..........................................871
Shunt resistor unit REX062..................................................872
Injection unit REX060 from rear side.........................................873
Injection unit REX060...........................................................873
Injection unit REX060.....................................................................874
Introduction................................................................................874
Design.......................................................................................874
Coupling capacitor unit REX061.....................................................877
Introduction................................................................................877
Design.......................................................................................877
Shunt resistor unit REX062............................................................878
Introduction................................................................................878
Design.......................................................................................878
Technical data................................................................................880
Hardware...................................................................................880
Type tests according to standards.............................................881
Influencing factors.....................................................................883
Section 20 Labels...........................................................................885
Labels on IED.................................................................................885
Labels on injection equipment........................................................888
Section 21 Connection diagrams...................................................893

Injection equipment........................................................................909
Section 22 Inverse time characteristics..........................................935

Application......................................................................................935
Principle of operation......................................................................938
Mode of operation......................................................................938
Inverse characteristics....................................................................943
Section 23 Glossary.......................................................................969
24
1MRK 502 027-UEN A Section 1
Introduction
Section 1 Introduction
About this chapter

This chapter explains concepts and conventions used in this manual and provides
information necessary to understand the contents of the manual.
1.1 Introduction to the technical reference manual
1.1.1 About the complete set of manuals for an IED

The user’s manual (UM) is a complete set of five different manuals:
deinstalling & disposal

Planning & purchase
Decommissioning
Commissioning
Maintenance
Engineering
Operation
Installing
Engineeringmanual
Installation and
Commissioning manual
Operator’s manual
Application manual
Technical reference
manual
IEC09000744-1-en.vsd
IEC09000744 V1 EN
The Application Manual (AM) contains application descriptions, setting

guidelines and setting parameters sorted per function. The application manual
should be used to find out when and for what purpose a typical protection function
could be used. The manual should also be used when calculating settings.
The Technical Reference Manual (TRM) contains application and functionality

descriptions and it lists function blocks, logic diagrams, input and output signals,
setting parameters and technical data sorted per function. The technical reference
25
Section 1 1MRK 502 027-UEN A
Introduction
manual should be used as a technical reference during the engineering phase,

installation and commissioning phase, and during normal service.
The Installation and Commissioning Manual (ICM) contains instructions on

how to install and commission the protection IED. The manual can also be used as
a reference during periodic testing. The manual covers procedures for mechanical
and electrical installation, energizing and checking of external circuitry, setting and
configuration as well as verifying settings and performing directional tests. The
chapters are organized in the chronological order (indicated by chapter/section
numbers) in which the protection IED should be installed and commissioned.
The Operator’s Manual (OM) contains instructions on how to operate the

protection IED during normal service once it has been commissioned. The
operator’s manual can be used to find out how to handle disturbances or how to
view calculated and measured network data in order to determine the cause of a fault.
The Engineering Manual (EM) contains instructions on how to engineer the IEDs
using the different tools in PCM600. The manual provides instructions on how to
set up a PCM600 project and insert IEDs to the project structure. The manual also
recommends a sequence for engineering of protection and control functions, LHMI
functions as well as communication engineering for IEC 61850 and DNP3.
1.1.2 About the technical reference manual

The following chapters are included in the technical reference manual.
• Local HMI describes the control panel on the IED and explains display
characteristics, control keys and various local HMI features.
• Basic IED functions presents functions for all protection types that are
included in all IEDs, for example, time synchronization, self supervision with
event list, test mode and other general functions.
• Current protection describes functions, for example, over current protection,
breaker failure protection and pole discordance.
• Voltage protection describes functions for under voltage and over voltage
protection and residual over voltage protection.
• Frequency protection describes functions for over frequency, under frequency
and rate of change of frequency protection.
• Multipurpose protection describes the general protection function for current
and voltage.
• Secondary system supervision describes current based functions for current
circuit supervision and fuse failure supervision.
• Control describes control functions, for example, synchronization and
energizing check and other product specific functions.
• Logic describes trip logic and related functions.
• Monitoring describes measurement related functions that are used to provide
data regarding relevant quantities, events and faults, for example.
• Station communication describes Ethernet based communication in general,
including the use of IEC 61850 and horizontal communication via GOOSE.
• Remote communication describes binary and analog signal transfer, and the
associated hardware.
26
Introduction
• Hardware describes the IED and its components.

• Connection diagrams provides terminal wiring diagrams and information
regarding connections to and from the IED.
• Inverse time characteristics describes and explains inverse time delay, inverse
time curves and their effects.
• Glossary is a list of terms, acronyms and abbreviations used in ABB technical
documentation.
1.1.3 This manual

The description of each IED related function follows the same structure (where
applicable). The different sections are outlined below.
1.1.3.1 Introduction
Outlines the implementation of a particular protection function.
1.1.3.2 Principle of operation
Describes how the function works, presents a general background to algorithms

and measurement techniques. Logic diagrams are used to illustrate functionality.
Logic diagrams
Logic diagrams describe the signal logic inside the function block and are bordered
by dashed lines.
Signal names
Input and output logic signals consist of two groups of letters separated by two
dashes. The first group consists of up to four letters and presents the abbreviated
name for the corresponding function. The second group presents the functionality
of the particular signal. According to this explanation, the meaning of the signal
BLKTR in figure 4 is as follows:
• BLKTR informs the user that the signal will BLOCK the TRIP command from
the under-voltage function, when its value is a logical one (1).
Input signals are always on the left hand side, and output signals on the right hand
side. Settings are not displayed.
Input and output signals

In a logic diagram, input and output signal paths are shown as a lines that touch the
outer border of the diagram.
Input and output signals can be configured using the ACT tool. They can be
connected to the inputs and outputs of other functions and to binary inputs and
outputs. Examples of input signals are BLKTR, BLOCK and VTSU. Examples
output signals are TRIP, START, STL1, STL2, STL3.
27
Introduction
Setting parameters
Signals in frames with a shaded area on their right hand side represent setting
parameter signals. These parameters can only be set via the PST or LHMI. Their
values are high (1) only when the corresponding setting parameter is set to the
symbolic value specified within the frame. Example is the signal Block TUV=Yes.
Their logical values correspond automatically to the selected setting value.
Internal signals
Internal signals are illustrated graphically and end approximately 2 mm from the
frame edge. If an internal signal path cannot be drawn with a continuous line, the
suffix -int is added to the signal name to indicate where the signal starts and
continues, see figure 1.
BLKTR
TEST
TEST
&
Block TUV=Yes BLOCK-int.
>1
BLOCK
VTSU
BLOCK-int.
&
STUL1N
BLOCK-int.
& >1 & TRIP
t
STUL2N
BLOCK-int.
START
&
STUL3N
STL1
STL2
STL3
xx04000375.vsd
IEC04000375 V1 EN
Figure 1: Logic diagram example with -int signals
External signals
Signal paths that extend beyond the logic diagram and continue in another diagram
have the suffix “-cont.”, see figure 2 and figure 3.
28
Introduction
STZMPP-cont.
>1
STCND
& STNDL1L2-cont.
1L1L2
STNDL2L3-cont.
&
1L2L3
& STNDL3L1-cont.
1L3L1
& STNDL1N-cont.
1L1N
& STNDL2N-cont.
1L2N
STNDL3N-cont.
&
1L3N
>1 STNDPE-cont.
>1
1--VTSZ 1--STND
>1 &
1--BLOCK
BLK-cont.
xx04000376.vsd
IEC04000376 V1 EN
Figure 2: Logic diagram example with an outgoing -cont signal
STNDL1N-cont.
>1
STNDL2N-cont. 15 ms
& t STL1
STNDL3N-cont.
STNDL1L2-cont. >1 15 ms
& t STL2
STNDL2L3-cont.
15 ms
STNDL3L1-cont. & t STL3
>1
15 ms
& t START
>1
BLK-cont.
xx04000377.vsd
IEC04000377 V1 EN
Figure 3: Logic diagram example with an incoming -cont signal
29
Introduction
1.1.3.3 Input and output signals
Input and output signals are presented in two separate tables. Each table consists of
two columns. The first column contains the name of the signal and the second
column contains the description of the signal.
1.1.3.4 Function block
Each function block is illustrated graphically.
Input signals are always on the left hand side and output signals on the right hand
side. Settings are not displayed. Special kinds of settings are sometimes available.
These are supposed to be connected to constants in the configuration scheme and
are therefore depicted as inputs. Such signals will be found in the signal list but
described in the settings table.
• The ^ character in front of an input or output signal name in the function block
symbol given for a function, indicates that the user can set a signal name of
their own in PCM600.
• The * character after an input or output signal name in the function block
symbol given for a function, indicates that the signal must be connected to
another function block in the application configuration to achieve a valid
application configuration.
IEC 61850 - 8 -1
Logical Node Mandatory
signal (*)
Inputs Outputs
PCGGIO
BLOCK INVALID
READ_VAL RESTART
BI_PULSE* BLOCKED
RS_CNT NEW_VAL
^SCAL_VAL
en05000511-1-en.vsd
User defined
name (^)
Diagram
Number
IEC05000511 V2 EN
Figure 4: Example of a function block
1.1.3.5 Setting parameters
These are presented in tables and include all parameters associated with the
function in question.
30
Introduction
1.1.3.6 Technical data
The technical data section provides specific technical information about the
function or hardware described.
1.1.4 Intended audience

General
This manual addresses system engineers, installation and commissioning
personnel, who use technical data during engineering, installation and
commissioning, and in normal service.
Requirements
The system engineer must have a thorough knowledge of protection systems,
protection equipment, protection functions and the configured functional logics in
the protective devices. The installation and commissioning personnel must have a
basic knowledge in the handling electronic equipment.
1.1.5 Related documents

Documents related to REG670 Identity number
Operator’s manual 1MRK 502 028-UEN
Installation and commissioning manual 1MRK 502 029-UEN
Technical reference manual 1MRK 502 027-UEN
Application manual 1MRK 502 030-UEN
Product guide customized 1MRK 502 031-BEN
Product guide pre-configured 1MRK 502 032-BEN
Rotor Earth Fault Protection with Injection Unit RXTTE4 and REG670 1MRG001910
Connection and Installation components 1MRK 513 003-BEN

Test system, COMBITEST 1MRK 512 001-BEN
Accessories for 670 series IEDs 1MRK 514 012-BEN
670 series SPA and signal list 1MRK 500 092-WEN
IEC 61850 Data objects list for 670 series 1MRK 500 091-WEN
Engineering manual 670 series 1MRK 511 240-UEN
Buyer’s guide REG 216 1MRB520004-BEN
Communication set-up for Relion 670 series 1MRK 505 260-UEN
More information can be found on www.abb.com/substationautomation.
31
Introduction
1.1.6 Revision notes

Revision Description
- First issue for 670 series version 1.2.
A Minor corrections made
32
Analog inputs
Section 2 Analog inputs
2.1 Introduction
Analog input channels must be configured and set properly to get correct
measurement results and correct protection operations. For power measuring and
all directional and differential functions the directions of the input currents must be
defined properly. Measuring and protection algorithms in the IED use primary
system quantities. Set values are done in primary quantities as well and it is
important to set the data about the connected current and voltage transformers
properly.
A reference PhaseAngleRef can be defined to facilitate service values reading. This

analog channels phase angle will always be fixed to zero degree and all other angle
information will be shown in relation to this analog input. During testing and
commissioning of the IED the reference channel can be changed to facilitate testing
and service values reading.
The availability of VT inputs depends on the ordered transformer

input module (TRM) type.
2.2 Operation principle
The direction of a current to the IED depends on the connection of the CT. The
main CTs are typically star connected and can be connected with the star point to
the object or from the object. This information must be set to the IED.
Directional conventions for current or power, for example
• Positive value of current or power means quantity direction into the object.
• Negative value of current or power means quantity direction out from the object.
Directional conventions for directional functions (see figure 5)
• Forward means direction into the object.

• Reverse means direction out from the object.
33
Analog inputs
Definition of direction Definition of direction

for directional functions for directional functions
Reverse Forward Forward Reverse
Protected Object
Line, transformer, etc
e.g. P, Q, I e.g. P, Q, I
Measured quantity is Measured quantity is
positive when flowing positive when flowing
towards the object towards the object
Set parameter Set parameter

CTStarPoint CTStarPoint
Correct Setting is Correct Setting is
"ToObject" "FromObject"
en05000456.vsd
IEC05000456 V1 EN
Figure 5: Internal convention of the directionality in the IED
The correct setting of the primary CT direction
• CTStarPoint is set to FromObject or ToObject.

• Positive quantities flow towards the object.
• Direction is defined as Forward and looks towards the object.
The ratios of the main CTs and VTs must be known to use primary system
quantities for settings and calculation in the IED, The user has to set the rated
secondary and primary currents and voltages of the CTs and VTs to provide the
IED with this information.
The CT and VT ratio and the name on respective channel is done under Main
menu/Hardware/Analog modules in the Parameter Settings tool.
2.3 Function block
The function blocks are not represented in the configuration tool.

The signals appear only in the SMT tool when a TRM is included in
the configuration with the function selector tool. In the SMT tool
they can be mapped to the desired virtual input (SMAI) of the IED
and used internally in the configuration.
2.4 Setting parameters
Dependent on ordered IED type.
34
Analog inputs
Table 1: AISVBAS Non group settings (basic)

Name Values (Range) Unit Step Default Description
PhaseAngleRef TRM40-Ch1 - - TRM40-Ch1 Reference channel for phase angle
TRM40-Ch2 presentation
TRM40-Ch3
TRM40-Ch4
TRM40-Ch5
TRM40-Ch6
TRM40-Ch7
TRM40-Ch8
TRM40-Ch9
TRM40-Ch10
TRM40-Ch11
TRM40-Ch12
TRM41-Ch1
TRM41-Ch2
TRM41-Ch3
TRM41-Ch4
TRM41-Ch5
TRM41-Ch6
TRM41-Ch7
TRM41-Ch8
TRM41-Ch9
TRM41-Ch10
TRM41-Ch11
TRM41-Ch12
MU1-L1I
MU1-L2I
MU1-L3I
MU1-L4I
MU1-L1U
MU1-L2U
MU1-L3U
MU1-L4U
MU2-L1I
MU2-L2I
MU2-L3I
MU2-L4I
MU2-L1U
MU2-L2U
MU2-L3U
MU2-L4U
MU3-L1I
MU3-L2I
MU3-L3I
MU3-L4I
MU3-L1U
MU3-L2U
MU3-L3U
MU3-L4U
Table 2: TRM_12I Non group settings (basic)

CTStarPoint1 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec1 1 - 10 A 1 1 Rated CT secondary current
CTprim1 1 - 99999 A 1 3000 Rated CT primary current
Table continues on next page
35
Analog inputs

36
Analog inputs
Table 3: TRM_6I_6U Non group settings (basic)

VTsec7 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim7 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
37
Analog inputs
Table 4: TRM_6I Non group settings (basic)


38
Analog inputs


39
Analog inputs

40
Local HMI
Section 3 Local HMI
About this chapter

This chapter describes the structure and use of local HMI, which is the control
panel at the IED.
3.1 Human machine interface
The local human machine interface is available in a small and a medium sized
model. The difference between the two models is the size of the LCD. The small
size LCD can display seven lines of text and the medium size LCD can display the
single line diagram with up to 15 objects on each page. Up to 12 single line
diagram pages can be defined, depending on the product capability.
The local HMI is divided into zones with different functionality.
• Status indication LEDs.

• Alarm indication LEDs, which consist of 15 LEDs (6 red and 9 yellow) with
user printable label. All LEDs are configurable from PCM600.
• Liquid crystal display (LCD).
• Keypad with push buttons for control and navigation purposes, switch for
selection between local and remote control and reset.
• Isolated RJ45 communication port.
41
Local HMI
IEC05000055-LITEN V1 EN
Figure 6: Small, alpha numeric HMI
IEC05000056-LITEN V1 EN
Figure 7: Example of medium graphic HMI
42
Local HMI
3.2 Small size HMI
3.2.1 Small
The small sized HMI is available for 1/2, 3/4 and 1/1 x 19” case. The LCD on the
small HMI measures 32 x 90 mm and displays 7 lines with up to 40 characters per
line. The first line displays the product name and the last line displays date and
time. The remaining 5 lines are dynamic. This LCD has no graphic display potential.
3.2.2 Design
The local HMI is identical for both the 1/2, 3/4 and 1/1 cases. The different parts of
the small local HMI are shown in figure 8
43
Local HMI
1 2 3
en05000055.eps
8 7
IEC05000055-CALLOUT V1 EN
Figure 8: Small graphic HMI
1 Status indication LEDs

2 LCD
3 Indication LEDs
4 Label
5 Local/Remote LEDs
6 RJ45 port
7 Communication indication LED
8 Keypad
44
Local HMI
3.3 Medium size graphic HMI
3.3.1 Medium
The following case sizes can be equipped with the medium size LCD:
• 1/2 x 19”
• 3/4 x 19”
• 1/1 x 19”
This is a fully graphical monochrome LCD which measures 120 x 90 mm. It has 28
lines with up to 40 characters per line. To display the single line diagram, this LCD
is required.
3.3.2 Design
The different parts of the medium size local HMI are shown in figure 9. The local
HMI exists in an IEC version and in an ANSI version. The difference is on the
keypad operation buttons and the yellow LED designation.
45
Local HMI
1 2 3
en05000056.eps
8 7
IEC05000056-CALLOUT V1 EN
Figure 9: Medium size graphic HMI
1 Status indication LEDs

2 LCD
3 Indication LEDs
4 Label
5 Local/Remote LEDs
6 RJ45 port
7 Communication indication LED
8 Keypad
46
Local HMI
3.4 Keypad
The keypad is used to monitor and operate the IED. The keypad has the same look
and feel in all IEDs. LCD screens and other details may differ but the way the keys
function is identical.
IEC05000153 V1 EN
Figure 10: The HMI keypad.
Table 7 describes the HMI keys that are used to operate the IED.
Table 7: HMI keys on the front of the IED

Key Function
Press to close or energize a breaker or disconnector.

IEC05000101 V1 EN
Press to open a breaker or disconnector.

IEC05000102 V1 EN
Press to open two sub menus: Key operation and IED information.
IEC05000103 V1 EN
Press to clear entries, cancel commands or edit.

IEC05000104 V1 EN
Press to open the main menu and to move to the default screen.
IEC05000105 V1 EN
Press to set the IED in local or remote control mode.

IEC05000106 V1 EN
Press to open the reset screen.

IEC05000107 V1 EN
Press to start the editing mode and confirm setting changes, when in editing mode.
IEC05000108 V1 EN
47
Local HMI
Key Function
Press to navigate forward between screens and move right in editing mode.
IEC05000109 V1 EN
Press to navigate backwards between screens and move left in editing mode.
IEC05000110 V1 EN
Press to move up in the single line diagram and in the menu tree.
IEC05000111 V1 EN
Press to move down in the single line diagram and in the menu tree.
IEC05000112 V1 EN
3.5 LED
3.5.1 Introduction
The LED module is a unidirectional means of communicating. This means that
events may occur that activate a LED in order to draw the operators attention to
something that has occurred and needs some sort of action.
3.5.2 Status indication LEDs

The three LEDs above the LCD provide information as shown in the table below.
LED Indication Information
Green:
Steady In service
Flashing Internal failure
Dark No power supply
Yellow:
Steady Dist. rep. triggered
Flashing Terminal in test mode
Red:
Steady Trip command issued
3.5.3 Indication LEDs

The LED indication module comprising 15 LEDs is standard in 670 series. Its main
purpose is to present an immediate visual information for protection indications or
alarm signals.
48
Local HMI
Alarm indication LEDs and hardware associated LEDs are located on the right
hand side of the front panel. Alarm LEDs are located on the right of the LCD
screen and show steady or flashing light.
• Steady light indicates normal operation.

• Flashing light indicates alarm.
Alarm LEDs can be configured in PCM600 and depend on the binary logic.
Therefore they can not be configured on the local HMI.
Typical examples of alarm LEDs
• Bay controller failure

• CB close blocked
• Interlocking bypassed
• Differential protection trip
• SF6 Gas refill
• Position error
• CB spring charge alarm
• Oil temperature alarm
• Thermal overload trip
• Bucholtz trip
The RJ45 port has a yellow LED indicating that communication has been
established between the IED and a computer.
The Local/Remote key on the front panel has two LEDs indicating whether local or
remote control of the IED is active.
3.6 Local HMI related functions
3.6.1 Introduction
The local HMI can be adapted to the application configuration and to user preferences.
• Function block LocalHMI

• Function block LEDGEN
• Setting parameters
49
Local HMI
3.6.2 General setting parameters

Table 8: SCREEN Non group settings (basic)
Language English - - English Local HMI language
OptionalLanguage
DisplayTimeout 10 - 120 Min 10 60 Local HMI display timeout
AutoRepeat Off - - On Activation of auto-repeat (On) or not (Off)
On
ContrastLevel -10 - 20 % 1 0 Contrast level for display
DefaultScreen 0-0 - 1 0 Default screen
EvListSrtOrder Latest on top - - Latest on top Sort order of event list
Oldest on top
SymbolFont IEC - - IEC Symbol font for Single Line Diagram
ANSI
3.6.3 Status LEDs
3.6.3.1 Design
The function block LocalHMI controls and supplies information about the status of
the status indication LEDs. The input and output signals of local HMI are
configured with PCM600.
The function block can be used if any of the signals are required in a configuration
logic.
See section "Status indication LEDs" for information about the LEDs.

LocalHMI
CLRLEDS HMI-ON
RED-S
YELLOW-S
YELLOW-F
CLRPULSE
LEDSCLRD
IEC05000773 V2 EN
Figure 11: LocalHMI function block

Table 9: LocalHMI Input signals
Name Type Default Description
CLRLEDS BOOLEAN 0 Input to clear the LCD-HMI LEDs
50
Local HMI
Table 10: LocalHMI Output signals

Name Type Description
HMI-ON BOOLEAN Backlight of the LCD display is active
RED-S BOOLEAN Red LED on the LCD-HMI is steady
YELLOW-S BOOLEAN Yellow LED on the LCD-HMI is steady
YELLOW-F BOOLEAN Yellow LED on the LCD-HMI is flashing
CLRPULSE BOOLEAN A pulse is provided when the LEDs on the LCD-
HMI are cleared
LEDSCLRD BOOLEAN Active when the LEDs on the LCD-HMI are not
active
3.6.4 Indication LEDs
The function block LEDGEN controls and supplies information about the status of
the indication LEDs. The input and output signals of LEDGEN are configured with
PCM600. The input signal for each LED is selected individually with the Signal
Matrix Tool in PCM600.
• LEDs (number 1–6) for trip indications are red.

• LEDs (number 7–15) for start indications are yellow.
Each indication LED on the local HMI can be set individually to operate in six
different sequences
• Two sequences operate as follow type.

• Four sequences operate as latch type.
• Two of the latching sequence types are intended to be used as a
protection indication system, either in collecting or restarting mode, with
reset functionality.
• Two of the latching sequence types are intended to be used as signaling
system in collecting (coll) mode with an acknowledgment functionality.
The light from the LEDs can be steady (-S) or flashing (-F). See the technical
reference manual for more information.
3.6.4.2 Design
The information on the LEDs is stored at loss of the auxiliary power to the IED in
some of the modes of LEDGEN. The latest LED picture appears immediately after
the IED is successfully restarted.
Operating modes
• Collecting mode
51
Local HMI
• LEDs which are used in collecting mode of operation are accumulated

continuously until the unit is acknowledged manually. This mode is
suitable when the LEDs are used as a simplified alarm system.
• Re-starting mode
• In the re-starting mode of operation each new start resets all previous
active LEDs and activates only those which appear during one
disturbance. Only LEDs defined for re-starting mode with the latched
sequence type 6 (LatchedReset-S) will initiate a reset and a restart at a
new disturbance. A disturbance is defined to end a settable time after the
reset of the activated input signals or when the maximum time limit has
elapsed.
Acknowledgment/reset
• From local HMI
• Active indications can be acknowledged or reset manually. Manual
acknowledgment and manual reset have the same meaning and is a
common signal for all the operating sequences and LEDs. The function
is positive edge triggered, not level triggered. The acknowledged or reset
is performed via the reset button and menus on the local HMI. See the
operator's manual for more information.
• From function input

• Active indications can also be acknowledged or reset from an input,
RESET, to the function. This input can, for example, be configured to a
binary input operated from an external push button. The function is
positive edge triggered, not level triggered. This means that even if the
button is continuously pressed, the acknowledgment or reset only affects
indications active at the moment when the button is first pressed.
• Automatic reset
• Automatic reset can only be performed for indications defined for re-
starting mode with the latched sequence type 6 (LatchedReset-S). When
automatic reset of the LEDs has been performed, still persisting
indications will be indicated with a steady light.
Operating sequences
The operating sequences can be of type Follow or Latched.
• For the Follow type the LED follows the input signal completely.
• For the Latched type each LED latches to the corresponding input signal until
it is reset.
52
Local HMI
Figure 12 show the function of available sequences that are selectable for each
LED separately.
• The acknowledgment or reset function is not applicable for sequence 1 and 2

(Follow type).
• Sequence 3 and 4 (Latched type with acknowledgement) are only working in
collecting mode.
• Sequence 5 is working according to Latched type and collecting mode.
• Sequence 6 is working according to Latched type and re-starting mode.
The letters S and F in the sequence names have the meaning S = Steady and F =
Flashing.
At the activation of the input signal, the indication operates according to the
selected sequence diagrams.
In the sequence diagrams the LEDs have the characteristics as shown in figure 12.
= No indication = Steady light = Flash
en05000506.vsd
IEC05000506 V1 EN
Figure 12: Symbols used in the sequence diagrams
Sequence 1 (Follow-S)
This sequence follows all the time, with a steady light, the corresponding input
signals. It does not react on acknowledgment or reset. Every LED is independent of
the other LEDs in its operation.
Activating
signal
LED
IEC01000228_2_en.vsd
IEC01000228 V2 EN
Figure 13: Operating sequence 1 (Follow-S)
Sequence 2 (Follow-F)
This sequence is the same as sequence 1, Follow-S, but the LEDs are flashing
instead of showing steady light.
Sequence 3 (LatchedAck-F-S)
This sequence has a latched function and works in collecting mode. Every LED is
independent of the other LEDs in its operation. At the activation of the input signal,
the indication starts flashing. After acknowledgment the indication disappears if
53
Local HMI
the signal is not present any more. If the signal is still present after
acknowledgment it gets a steady light.
Activating
signal
LED
Acknow.
en01000231.vsd
IEC01000231 V1 EN
Figure 14: Operating sequence 3 (LatchedAck-F-S)
Sequence 4 (LatchedAck-S-F)
This sequence has the same functionality as sequence 3, but steady and flashing
light have been alternated.
Sequence 5 (LatchedColl-S)
This sequence has a latched function and works in collecting mode. At the
activation of the input signal, the indication will light up with a steady light. The
difference to sequence 3 and 4 is that indications that are still activated will not be
affected by the reset that is, immediately after the positive edge of the reset has
been executed a new reading and storing of active signals is performed. Every LED
is independent of the other LEDs in its operation.
Activating
signal
LED
Reset
IEC01000235 V2 EN
Figure 15: Operating sequence 5 (LatchedColl-S)
Sequence 6 (LatchedReset-S)
In this mode all activated LEDs, which are set to sequence 6 (LatchedReset-S), are
automatically reset at a new disturbance when activating any input signal for other
LEDs set to sequence 6 (LatchedReset-S). Also in this case indications that are still
activated will not be affected by manual reset, that is, immediately after the
positive edge of that the manual reset has been executed a new reading and storing
54
Local HMI
of active signals is performed. LEDs set for sequence 6 are completely independent
in its operation of LEDs set for other sequences.
Definition of a disturbance
A disturbance is defined to last from the first LED set as LatchedReset-S is
activated until a settable time, tRestart, has elapsed after that all activating signals
for the LEDs set as LatchedReset-S have reset. However if all activating signals
have reset and some signal again becomes active before tRestart has elapsed, the
tRestart timer does not restart the timing sequence. A new disturbance start will be
issued first when all signals have reset after tRestart has elapsed. A diagram of this
functionality is shown in figure 16.
From
disturbance
length control ³1 New
per LED ³1 disturbance
set to
sequence 6
tRestart
& t
&
³1
³1
&
en01000237.vsd
IEC01000237 V1 EN
Figure 16: Activation of new disturbance
In order not to have a lock-up of the indications in the case of a persisting signal
each LED is provided with a timer, tMax, after which time the influence on the
definition of a disturbance of that specific LED is inhibited. This functionality is
shown i diagram in figure 17.
Activating signal
To LED
To disturbance
AND
tMax length control
t
en05000507.vsd
IEC05000507 V1 EN
Figure 17: Length control of activating signals
Timing diagram for sequence 6

Figure 18 shows the timing diagram for two indications within one disturbance.
55
Local HMI
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000239_2-en.vsd
IEC01000239 V2 EN
Figure 18: Operating sequence 6 (LatchedReset-S), two indications within

same disturbance
Figure 19 shows the timing diagram for a new indication after tRestart time has
elapsed.
Disturbance Disturbance
tRestart tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000240 V2 EN
Figure 19: Operating sequence 6 (LatchedReset-S), two different disturbances
56
Local HMI
Figure 20 shows the timing diagram when a new indication appears after the first
one has reset but before tRestart has elapsed.
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000241 V2 EN
Figure 20: Operating sequence 6 (LatchedReset-S), two indications within

same disturbance but with reset of activating signal between
Figure 21 shows the timing diagram for manual reset.
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000242 V2 EN
Figure 21: Operating sequence 6 (LatchedReset-S), manual reset
57
Local HMI

LEDGEN
BLOCK NEWIND
RESET ACK
LEDTEST
IEC05000508 V2 EN
Figure 22: LEDGEN function block

Table 11: LEDGEN Input signals
BLOCK BOOLEAN 0 Input to block the operation of the LED-unit
RESET BOOLEAN 0 Input to acknowledge/reset the indications of the
LED-unit
LEDTEST BOOLEAN 0 Input for external LED test
Table 12: LEDGEN Output signals

NEWIND BOOLEAN A new signal on any of the indication inputs occurs
ACK BOOLEAN A pulse is provided when the LEDs are
acknowledged

Table 13: LEDGEN Non group settings (basic)
Operation Off - - Off Operation mode for the LED function
On
tRestart 0.0 - 100.0 s 0.1 0.0 Defines the disturbance length
tMax 0.0 - 100.0 s 0.1 0.0 Maximum time for the definition of a
disturbance
SeqTypeLED1 Follow-S - - Follow-S Sequence type for LED 1
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
58
Local HMI

Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED8 Follow-S - - Follow-S sequence type for LED 8
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
59
Local HMI

Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
60
Basic IED functions
Section 4 Basic IED functions
About this chapter

This chapter presents functions that are basic to all 670 series IEDs. Typical
functions in this category are time synchronization, self supervision and test mode.
4.1 Authorization
To safeguard the interests of our customers, both the IED and the tools that are
accessing the IED are protected, by means of authorization handling. The
authorization handling of the IED and the PCM600 is implemented at both access
points to the IED:
• local, through the local HMI

• remote, through the communication ports
4.1.1 Principle of operation

There are different levels (or types) of users that can access or operate different
areas of the IED and tools functionality. The pre-defined user types are given in
Table 14.
Be sure that the user logged on to the IED has the access required
when writing particular data to the IED from PCM600.
The meaning of the legends used in the table:

• R= Read
• W= Write
• - = No access rights
Table 14: Pre-defined user types

Access rights System Protection Design User
Guest Super User SPA Guest
Operator Engineer Engineer Administrator
Basic setting possibilities (change R R/W R R/W R/W R/W R
setting group, control settings,
limit supervision)
Advanced setting possibilities (for R R/W R R R/W R/W R
example protection settings)
Basic control possibilities (process R R/W R/W R/W R/W R/W R
control, no bypass)
61
Basic IED functions
Access rights System Protection Design User

Guest Super User SPA Guest
Operator Engineer Engineer Administrator
Advanced control possibilities R R/W R/W R/W R/W R/W R
(process control including interlock
trigg)
Basic command handling (for R R/W R R/W R/W R/W R
example clear LEDs, manual trigg)
Advanced command handling (for R R/W R R R/W R/W R/W
example clear disturbance record)
Basic configuration possibilities (I/ R R/W R R R R/W R/W
O-configuration in SMT)
Advanced configuration R R/W R R R R/W R/W
possibilities (application
configuration including SMT, GDE
and CMT)
File loading (database loading - R/W - - - R/W R/W
from XML-file)
File dumping (database dumping - R/W - - - R/W R/W
to XML-file)
File transfer (FTP file transfer) - R/W - R/W R/W R/W R/W
File transfer (limited) (FTP file R R/W R R/W R/W R/W R/W
transfer)
File Transfer (SPA File Transfer) - R/W - - - R/W -
Database access for normal user R R/W R R/W R/W R/W R/W
User administration (user R R/W R R R R R/W
management – FTP File Transfer)
User administration (user - R/W - - - - -
management – SPA File Transfer)
The IED users can be created, deleted and edited only with the User Management
Tool (UMT) within PCM600. The user can only LogOn or LogOff on the local
HMI on the IED, there are no users, groups or functions that can be defined on
local HMI.
Only characters A - Z, a - z and 0 - 9 should be used in user names

and passwords.
At least one user must be included in the UserAdministrator group

to be able to write users, created in PCM600, to IED.
4.1.1.1 Authorization handling in the IED
At delivery the default user is the SuperUser. No Log on is required to operate the
IED until a user has been created with the User Management Tool.
62
Basic IED functions
Once a user is created and downloaded to the IED, that user can perform a Log on,
introducing the password assigned in the tool.
If there is no user created, an attempt to log on will display a message box: “No
user defined!”
If one user leaves the IED without logging off, then after the timeout (set in Main
menu/Settings/General Settings/HMI/Screen/Display Timeout) elapses, the IED
returns to Guest state, when only reading is possible. The display time out is set to
60 minutes at delivery.
If there are one or more users created with the User Management Tool and
downloaded into the IED, then, when a user intentionally attempts a Log on or
when the user attempts to perform an operation that is password protected, the Log
on window will appear.
The cursor is focused on the User identity field, so upon pressing the “E” key, the
user can change the user name, by browsing the list of users, with the “up” and
“down” arrows. After choosing the right user name, the user must press the “E”
key again. When it comes to password, upon pressing the “E” key, the following
character will show up: “$”. The user must scroll for every letter in the password.
After all the letters are introduced (passwords are case sensitive) choose OK and
press the “E” key again.
If everything is alright at a voluntary Log on, the local HMI returns to the
Authorization screen. If the Log on is OK, when required to change for example a
password protected setting, the local HMI returns to the actual setting folder. If the
Log on has failed, then the Log on window opens again, until either the user makes
it right or presses “Cancel”.
4.2 Self supervision with internal event list
4.2.1 Introduction
Self supervision with internal event list function listens and reacts to internal
system events, generated by the different built-in self-supervision elements. The
internal events are saved in an internal event list.

The self-supervision operates continuously and includes:
• Normal micro-processor watchdog function.

• Checking of digitized measuring signals.
• Other alarms, for example hardware and time synchronization.
63
Basic IED functions
The self-supervision function status can be monitored from the local HMI, from the
Event Viewer in PCM600 or from a SMS/SCS system.
Under the Diagnostics menu in the local HMI the present information from the self-
supervision function can be reviewed. The information can be found under Main
menu/Diagnostics/Internal events or Main menu/Diagnostics/IED status/
General. The information from the self-supervision function is also available in the
Event Viewer in PCM600.
A self-supervision summary can be obtained by means of the potential free alarm

contact (INTERNAL FAIL) located on the power supply module. The function of
this output relay is an OR-function between the INT-FAIL signal see figure 24 and
a couple of more severe faults that can occur in the IED, see figure 23
IEC04000520 V1 EN
Figure 23: Hardware self-supervision, potential-free alarm contact
64
Basic IED functions
IO fail
OR Set e.g. BIM 1 Error
IO stopped
Reset
IO started
e.g. IOM2 Error OR
e.g. IO (n) Error Internal
OR FAIL
LON ERROR
FTF fatal error

OR
Watchdog NUMFAIL
RTE fatal error
Internal
Set WARN
RTE Appl-fail
OR
RTE OK Reset
IEC61850 not ready NUMWARNING

OR
RTCERROR Set RTCERROR
RTC OK Reset
TIMESYNCHERROR
OR TIMESYNCHERROR
Time reset Set
SYNCH OK Reset
SETCHGD
Settings changed
1 second pulse
en04000519-1.vsd
IEC04000519 V2 EN
Figure 24: Software self-supervision, IES (IntErrorSign) function block
Some signals are available from the INTERRSIG function block. The signals from
this function block are sent as events to the station level of the control system. The
signals from the INTERRSIG function block can also be connected to binary
outputs for signalization via output relays or they can be used as conditions for
other functions if required/desired.
Individual error signals from I/O modules can be obtained from respective module
in the Signal Matrix tool. Error signals from time synchronization can be obtained
from the time synchronization block TIME.
4.2.2.1 Internal signals
Self supervision provides several status signals, that tells about the condition of the
IED. As they provide information about the internal status of the IED, they are also
called internal signals. The internal signals can be divided into two groups.
• Standard signals are always presented in the IED, see Table 15.
• Hardware dependent internal signals are collected depending on the hardware
configuration, see Table 16.
Explanations of internal signals are listed in Table 17.
65
Basic IED functions
Table 15: Self-supervision's standard internal signals

Name of signal Description
FAIL Internal Fail status
WARNING Internal Warning status
NUMFAIL CPU module Fail status
NUMWARNING CPU module Warning status
RTCERROR Real Time Clock status
TIMESYNCHERROR Time Synchronization status
RTEERROR Runtime Execution Error status
IEC61850ERROR IEC 61850 Error status
WATCHDOG SW Watchdog Error status
LMDERROR LON/Mip Device Error status
APPERROR Runtime Application Error status
SETCHGD Settings changed
SETGRPCHGD Setting groups changed
FTFERROR Fault Tolerant Filesystem status
Table 16: Self-supervision's hardware dependent internal signals

Card Name of signal Description
PSM PSM-Error Power Supply Module Error status
ADOne ADOne-Error Analog In Module Error status
BIM BIM-Error Binary In Module Error status
BOM BOM-Error Binary Out Module Error status
IOM IOM-Error In/Out Module Error status
MIM MIM-Error Millampere Input Module Error status
LDCM LDCM-Error Line Differential Communication Error status
Table 17: Explanations of internal signals

Name of signal Reasons for activation
FAIL This signal will be active if one or more of the following internal
signals are active; NUMFAIL, LMDERROR, WATCHDOG,
APPERROR, RTEERROR, FTFERROR, or any of the HW
dependent signals
WARNING This signal will be active if one or more of the following internal
signals are active; RTCERROR, IEC61850ERROR,
TIMESYNCHERROR
NUMFAIL This signal will be active if one or more of the following internal
signals are active; WATCHDOG, APPERROR, RTEERROR,
FTFERROR
NUMWARNING This signal will be active if one or more of the following internal
signals are active; RTCERROR, IEC61850ERROR
RTCERROR This signal will be active when there is a hardware error with the
real time clock.
66
Basic IED functions
Name of signal Reasons for activation

TIMESYNCHERROR This signal will be active when the source of the time
synchronization is lost, or when the time system has to make a
time reset.
RTEERROR This signal will be active if the Runtime Engine failed to do some
actions with the application threads. The actions can be loading
of settings or parameters for components, changing of setting
groups, loading or unloading of application threads.
IEC61850ERROR This signal will be active if the IEC 61850 stack did not succeed
in some actions like reading IEC 61850 configuration, startup,
for example
WATCHDOG This signal will be activated when the terminal has been under
too heavy load for at least 5 minutes. The operating systems
background task is used for the measurements.
LMDERROR LON network interface, MIP/DPS, is in an unrecoverable error
state.
APPERROR This signal will be active if one or more of the application threads
are not in the state that Runtime Engine expects. The states can
be CREATED, INITIALIZED, RUNNING, for example
SETCHGD This signal will generate an Internal Event to the Internal Event
list if any settings are changed.
SETGRPCHGD This signal will generate an Internal Event to the Internal Event
list if any setting groups are changed.
FTFERROR This signal will be active if both the working file and the backup
file are corrupted and can not be recovered.
4.2.2.2 Run-time model
The analog signals to the A/D converter is internally distributed into two different
converters, one with low amplification and one with high amplification, see Figure
25.
ADx
Adx_Low
x1
u1
x2
Adx
Adx_High Controller
x1
u1
x2
en05000296-2-en.vsd
IEC05000296 V2 EN
Figure 25: Simplified drawing of A/D converter for the IED.
67
Basic IED functions
The technique to split the analog input signal into two A/D converters with
different amplification makes it possible to supervise the incoming signals under
normal conditions where the signals from the two converters should be identical.
An alarm is given if the signals are out of the boundaries. Another benefit is that it
improves the dynamic performance of the A/D conversion.
The self-supervision of the A/D conversion is controlled by the ADx_Controller

function. One of the tasks for the controller is to perform a validation of the input
signals. This is done in a validation filter which has mainly two objects: First is the
validation part that checks that the A/D conversion seems to work as expected.
Secondly, the filter chooses which of the two signals that shall be sent to the CPU,
that is the signal that has the most suitable level, the ADx_LO or the 16 times
higherADx_HI.
When the signal is within measurable limits on both channels, a direct comparison
of the two channels can be performed. If the validation fails, the CPU will be
informed and an alarm will be given.
The ADx_Controller also supervise other parts of the A/D converter.
4.2.3 Function block
IEC09000787 V1 EN
Figure 26: INTERRSIG function block
4.2.4 Output signals

Table 18: INTERRSIG Output signals
FAIL BOOLEAN Internal fail
WARNING BOOLEAN Internal warning
CPUFAIL BOOLEAN CPU fail
CPUWARN BOOLEAN CPU warning
4.2.5 Setting parameters

The function does not have any parameters available in the local HMI or PCM600.
68
Basic IED functions
4.2.6 Technical data

Table 19: Self supervision with internal event list
Data Value
Recording manner Continuous, event controlled
List size 1000 events, first in-first out
4.3 Time synchronization
4.3.1 Introduction
The time synchronization source selector is used to select a common source of
absolute time for the IED when it is a part of a protection system. This makes it
possible to compare event- and disturbance data between all IEDs in a station
automation system possible.
Micro SCADA OPC server should not be used as a time

synchronization source.
4.3.2.1 General concepts
Time definitions
The error of a clock is the difference between the actual time of the clock, and the
time the clock is intended to have. The rate accuracy of a clock is normally called
the clock accuracy and means how much the error increases, that is how much the
clock gains or loses time. A disciplined (trained) clock knows its own faults and
tries to compensate for them.
Design of the time system (clock synchronization)

The time system is based on a software clock, which can be adjusted from external
time sources and a hardware clock. The protection and control modules will be
timed from a hardware clock, which runs independently from the software clock.
See figure 27.
69
Basic IED functions
External
Synchronization
sources Time tagging and general synchronisation
Off
Comm- Protection
LON Events
Time- unication and control
SPA Regulator functions
Min. pulse
(Setting,
GPS see
SW-time
technical
SNTP
reference
DNP manual) Connected when GPS-time is
IRIG-B used for differential protection
PPS
Synchronization for differential protection

(ECHO-mode or GPS)
Off Time-
GPS Regulator HW-time
(fast or slow)
IRIG-B
PPS Diff.-
A/D Trans-
converter comm- ducers*
unication
*IEC 61850-9-2
IEC08000287 V2 EN
Figure 27: Design of time system (clock synchronization)
All time tagging is performed by the software clock. When for example a status
signal is changed in the protection system with the function based on free running
hardware clock, the event is time tagged by the software clock when it reaches the
event recorder. Thus the hardware clock can run independently.
The echo mode for the differential protection is based on the hardware clock. Thus,
there is no need to synchronize the hardware clock and the software clock.
The synchronization of the hardware clock and the software clock is necessary only
when GPS or IRIG B 00X with optical fibre, IEEE 1344 is used for differential
protection. The two clock systems are synchronized by a special clock
synchronization unit with two modes, fast and slow. A special feature, an
automatic fast clock time regulator is used. The automatic fast mode makes the
synchronization time as short as possible during start-up or at interruptions/
disturbances in the GPS timing. The setting fast or slow is also available on the
local HMI.
If a GPS clock is used for other 670 series IEDs than line differential RED670, the
hardware and software clocks are not synchronized
70
Basic IED functions
Fast clock synchronization mode

At startup and after interruptions in the GPS or IRIG B time signal, the clock
deviation between the GPS time and the internal differential time system can be
substantial. A new startup is also required after for example maintenance of the
auxiliary voltage system.
When the time difference is >16us, the differential function is blocked and the time
regulator for the hardware clock is automatically using a fast mode to synchronize
the clock systems. The time adjustment is made with an exponential function, i.e.
big time adjustment steps in the beginning, then smaller steps until a time deviation
between the GPS time and the differential time system of >16us has been reached.
Then the differential function is enabled and the synchronization remains in fast
mode or switches to slow mode, depending on the setting.
Slow clock synchronization mode

During normal service, a setting with slow synchronization mode is normally used,
which prevents the hardware clock to make too big time steps, >16µs, emanating
from the differential protection requirement of correct timing.
Synchronization principle
From a general point of view synchronization can be seen as a hierarchical
structure. A function is synchronized from a higher level and provides
synchronization to lower levels.
Synchronization from
a higher level
Function
Optional synchronization of
modules at a lower level
IEC09000342 V1 EN
Figure 28: Synchronization principle
A function is said to be synchronized when it periodically receives synchronization

messages from a higher level. As the level decreases, the accuracy of the
synchronization decreases as well. A function can have several potential sources of
synchronization, with different maximum errors, which give the function the
possibility to choose the source with the best quality, and to adjust its internal clock
after this source. The maximum error of a clock can be defined as:
71
Basic IED functions
• The maximum error of the last used synchronization message

• The time since the last used synchronization message
• The rate accuracy of the internal clock in the function.
4.3.2.2 Real-time clock (RTC) operation
The IED has a built-in real-time clock (RTC) with a resolution of one second. The
clock has a built-in calendar that handles leap years through 2038.
Real-time clock at power off

During power off, the system time in the IED is kept by a capacitor-backed real-
time clock that will provide 35 ppm accuracy for 5 days. This means that if the
power is off, the time in the IED may drift with 3 seconds per day, during 5 days,
and after this time the time will be lost completely.
Real-time clock at startup
Time synchronization startup procedure

The first message that contains the full time (as for instance LON, SNTP and GPS)
gives an accurate time to the IED. After the initial setting of the clock, one of three
things happens with each of the coming synchronization messages configured as
“fine”:
• If the synchronization message, which is similar to the other messages, has an

offset compared to the internal time in the IED, the message is used directly
for synchronization, that is, for adjusting the internal clock to obtain zero
offset at the next coming time message.
• If the synchronization message has an offset that is large compared to the other
messages, a spike-filter in the IED removes this time-message.
• If the synchronization message has an offset that is large, and the following
message also has a large offset, the spike filter does not act and the offset in
the synchronization message is compared to a threshold that defaults to 100
milliseconds. If the offset is more than the threshold, the IED is brought into a
safe state and the clock is set to the correct time. If the offset is lower than the
threshold, the clock is adjusted with 1000 ppm until the offset is removed.
With an adjustment of 1000 ppm, it takes 100 seconds or 1.7 minutes to
remove an offset of 100 milliseconds.
Synchronization messages configured as coarse are only used for initial setting of
the time. After this has been done, the messages are checked against the internal
time and only an offset of more than 10 seconds resets the time.
Rate accuracy
In the IED, the rate accuracy at cold start is 100 ppm but if the IED is synchronized
for a while, the rate accuracy is approximately 1 ppm if the surrounding
temperature is constant. Normally, it takes 20 minutes to reach full accuracy.
72
Basic IED functions
Time-out on synchronization sources

All synchronization interfaces has a time-out and a configured interface must
receive time-messages regularly in order not to give an error signal (TSYNCERR).
Normally, the time-out is set so that one message can be lost without getting a
TSYNCERR, but if more than one message is lost, a TSYNCERR is given.
4.3.2.3 Synchronization alternatives
Three main alternatives of external time synchronization are available. Either the
synchronization message is applied via any of the communication ports of the IED
as a telegram message including date and time or as a minute pulse, connected to a
binary input, or via GPS. The minute pulse is used to fine tune already existing
time in the IEDs.
Synchronization via SNTP

SNTP provides a ping-pong method of synchronization. A message is sent from an
IED to an SNTP server, and the SNTP server returns the message after filling in a
reception time and a transmission time. SNTP operates via the normal Ethernet
network that connects IEDs together in an IEC 61850 network. For SNTP to
operate properly, there must be an SNTP-server present, preferably in the same
station. The SNTP synchronization provides an accuracy that gives 1 ms accuracy
for binary inputs. The IED itself can be set as an SNTP-time server.
SNTP server requirements

The SNTP server to be used is connected to the local network, that is not more than
4-5 switches or routers away from the IED. The SNTP server is dedicated for its
task, or at least equipped with a real-time operating system, that is not a PC with
SNTP server software. The SNTP server should be stable, that is, either
synchronized from a stable source like GPS, or local without synchronization.
Using a local SNTP server without synchronization as primary or secondary server
in a redundant configuration is not recommended.
Synchronization via Serial Communication Module (SLM)

On the serial buses (both LON and SPA) two types of synchronization messages
are sent.
• Coarse message is sent every minute and comprises complete date and time,
that is, year, month, day, hours, minutes, seconds and milliseconds.
• Fine message is sent every second and comprises only seconds and milliseconds.
IEC60870-5-103 is not used to synchronize the IED, but instead the offset between
the local time in the IED and the time received from 103 is added to all times (in
events and so on) sent via 103. In this way the IED acts as it is synchronized from
various 103 sessions at the same time. Actually, there is a “local” time for each 103
session.
The SLM module is located on the AD conversion Module (ADM).
73
Basic IED functions
Synchronization via binary input

The IED accepts minute pulses to a binary input. These minute pulses can be
generated from, for example station master clock. If the station master clock is not
synchronized from a world wide source, time will be a relative time valid for the
substation. Both positive and negative edge on the signal can be accepted. This
signal is also considered as a fine time synchronization signal.
The minute pulse is connected to any channel on any Binary Input Module in the
IED. The electrical characteristic is thereby the same as for any other binary input.
If the objective of synchronization is to achieve a relative time within the

substation and if no station master clock with minute pulse output is available, a
simple minute pulse generator can be designed and used for synchronization of the
IEDs. The minute pulse generator can be created using the logical elements and
timers available in the IED.
The definition of a minute pulse is that it occurs one minute after the last pulse. As
only the flanks are detected, the flank of the minute pulse shall occur one minute
after the last flank.
Binary minute pulses are checked with reference to frequency.
Pulse data:
• Period time (a) should be 60 seconds.

• Pulse length (b):
• Minimum pulse length should be >50 ms.
• Maximum pulse length is optional.
• Amplitude (c) - please refer to section "Binary input module (BIM)".
Deviations in the period time larger than 50 ms will cause TSYNCERR.
en05000251.vsd
IEC05000251 V1 EN
Figure 29: Binary minute pulses
The default time-out-time for a minute pulse is two minutes, and if no valid minute
pulse is received within two minutes a SYNCERR will be given.
74
Basic IED functions
If contact bounces occurs, only the first pulse will be detected as a minute pulse.
The next minute pulse will be registered first 60 s - 50 ms after the last contact bounce.
If the minute pulses are perfect, for example, it is exactly 60 seconds between the
pulses, contact bounces might occur 49 ms after the actual minute pulse without
effecting the system. If contact bounces occurs more than 50 ms, for example, it is
less than 59950 ms between the two most adjacent positive (or negative) flanks, the
minute pulse will not be accepted.
Binary synchronization example

An IED is configured to use only binary input, and a valid binary input is applied
to a binary input card. The HMI is used to tell the IED the approximate time and
the minute pulse is used to synchronize the IED thereafter. The definition of a
minute pulse is that it occurs one minute after the previous minute pulse, so the
first minute pulse is not used at all. The second minute pulse will probably be
rejected due to the spike filter. The third pulse will give the IED a good time and
will reset the time so that the fourth minute pulse will occur on a minute border.
After the first three minutes, the time in the IED will be good if the coarse time is
set properly via the HMI or the RTC backup still keeps the time since last up-time.
If the minute pulse is removed for instance for an hour, the internal time will drift
by maximum the error rate in the internal clock. If the minute pulse is returned, the
first pulse automatically is rejected. The second pulse will possibly be rejected due
to the spike filter. The third pulse will either synchronize the time, if the time offset
is more than 100 ms, or adjust the time, if the time offset is small enough. If the
time is set, the application will be brought to a safe state before the time is set. If
the time is adjusted, the time will reach its destination within 1.7 minutes.
Synchronization via IRIG-B

IRIG-B is a protocol used only for time synchronization. A clock can provide local
time of the year in this format. The “B” in IRIG-B states that 100 bits per second
are transmitted, and the message is sent every second. After IRIG-B there numbers
stating if and how the signal is modulated and the information transmitted.
To receive IRIG-B there are two connectors in the IRIG-B module, one galvanic
BNC connector and one optical ST connector. IRIG-B 12x messages can be
supplied via the galvanic interface, and IRIG-B 00x messages can be supplied via
either the galvanic interface or the optical interface, where x (in 00x or 12x) means
a number in the range of 1-7.
“00” means that a base band is used, and the information can be fed into the IRIG-
B module via the BNC contact or an optical fiber. “12” means that a 1 kHz
modulation is used. In this case the information must go into the module via the
BNC connector.
If the x in 00x or 12x is 4, 5, 6 or 7, the time message from IRIG-B contains

information of the year. If x is 0, 1, 2 or 3, the information contains only the time
within the year, and year information has to come from PCM600 or local HMI.
The IRIG-B module also takes care of IEEE1344 messages that are sent by IRIG-B
clocks, as IRIG-B previously did not have any year information. IEEE1344 is
75
Basic IED functions
compatible with IRIG-B and contains year information and information of the time-
zone.
It is recommended to use IEEE 1344 for supplying time information to the IRIG-B
module. In this case, send also the local time in the messages, as this local time
plus the TZ Offset supplied in the message equals UTC at all times.

TIMEERR
TSYNCERR
RTCERR
IEC05000425 V2 EN
Figure 30: TIMEERR function block

Table 20: TIMEERR Output signals
TSYNCERR BOOLEAN Time synchronization error
RTCERR BOOLEAN Real time clock error

Path in the local HMI is located under Main menu/Setting/Time
Path in PCM600 is located under Main menu/Settings/Time/Synchronization
76
Basic IED functions
Table 21: TIMESYNCHGEN Non group settings (basic)

CoarseSyncSrc Off - - Off Coarse time synchronization source
SPA
LON
SNTP
DNP
FineSyncSource Off - - Off Fine time synchronization source
SPA
LON
BIN
GPS
GPS+SPA
GPS+LON
GPS+BIN
SNTP
GPS+SNTP
IRIG-B
GPS+IRIG-B
PPS
SyncMaster Off - - Off Activate IED as synchronization master
SNTP-Server
TimeAdjustRate Slow - - Fast Adjust rate for time synchronization
Fast
HWSyncSrc Off - - Off Hardware time synchronization source
GPS
IRIG-B
PPS
AppSynch NoSynch - - NoSynch Time synchronization mode for
Synch application
SyncAccLevel Class T5 (1us) - - Unspecified Wanted time synchronization accuracy
Class T4 (4us)
Unspecified
Table 22: SYNCHBIN Non group settings (basic)

ModulePosition 3 - 16 - 1 3 Hardware position of IO module for time
synchronization
BinaryInput 1 - 16 - 1 1 Binary input number for time
synchronization
BinDetection PositiveEdge - - PositiveEdge Positive or negative edge detection
NegativeEdge
Table 23: SYNCHSNTP Non group settings (basic)

ServerIP-Add 0 - 18 IP 1 0.0.0.0 Server IP-address
Address
RedServIP-Add 0 - 18 IP 1 0.0.0.0 Redundant server IP-address
Address
77
Basic IED functions
Table 24: DSTBEGIN Non group settings (basic)

MonthInYear January - - March Month in year when daylight time starts
February
March
April
May
June
July
August
September
October
November
December
DayInWeek Sunday - - Sunday Day in week when daylight time starts
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
WeekInMonth Last - - Last Week in month when daylight time starts
First
Second
Third
Fourth
UTCTimeOfDay 0 - 172800 s 1 3600 UTC Time of day in seconds when
daylight time starts
Table 25: DSTEND Non group settings (basic)

MonthInYear January - - October Month in year when daylight time ends
February
March
April
May
June
July
August
September
October
November
December
DayInWeek Sunday - - Sunday Day in week when daylight time ends
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
WeekInMonth Last - - Last Week in month when daylight time ends
First
Second
Third
Fourth
UTCTimeOfDay 0 - 172800 s 1 3600 UTC Time of day in seconds when
daylight time ends
78
Basic IED functions
Table 26: TIMEZONE Non group settings (basic)

NoHalfHourUTC -24 - 24 - 1 0 Number of half-hours from UTC
Table 27: SYNCHIRIG-B Non group settings (basic)

SynchType BNC - - Opto Type of synchronization
Opto
TimeDomain LocalTime - - LocalTime Time domain
UTC
Encoding IRIG-B - - IRIG-B Type of encoding
1344
1344TZ
TimeZoneAs1344 MinusTZ - - PlusTZ Time zone as in 1344 standard
PlusTZ

Table 28: Time synchronization, time tagging
Function Value
Time tagging resolution, events and sampled measurement values 1 ms
Time tagging error with synchronization once/min (minute pulse ± 1.0 ms typically
synchronization), events and sampled measurement values
Time tagging error with SNTP synchronization, sampled ± 1.0 ms typically
measurement values
4.4 Parameter setting groups
4.4.1 Introduction
Use the six sets of settings to optimize the IED operation for different system
conditions. Creating and switching between fine-tuned setting sets, either from the
local HMI or configurable binary inputs, results in a highly adaptable IED that can
cope with a variety of system scenarios.

Parameter setting groups ActiveGroup function has six functional inputs, each
corresponding to one of the setting groups stored in the IED. Activation of any of
these inputs changes the active setting group. Seven functional output signals are
available for configuration purposes, so that up to date information on the active
setting group is always available.
79
Basic IED functions
A setting group is selected by using the local HMI, from a front connected personal
computer, remotely from the station control or station monitoring system or by
activating the corresponding input to the ActiveGroup function block.
Each input of the function block can be configured to connect to any of the binary
inputs in the IED. To do this PCM600 must be used.
The external control signals are used for activating a suitable setting group when
adaptive functionality is necessary. Input signals that should activate setting groups
must be either permanent or a pulse exceeding 400 ms.
More than one input may be activated at the same time. In such cases the lower
order setting group has priority. This means that if for example both group four and
group two are set to activate, group two will be the one activated.
Every time the active group is changed, the output signal SETCHGD is sending a
pulse.
The parameter MAXSETGR defines the maximum number of setting groups in use
to switch between.
ACTIVATE GROUP 6
ACTIVATE GROUP 5
ACTIVATE GROUP 4
ACTIVATE GROUP 3
ACTIVATE GROUP 2
+RL2 ACTIVATE GROUP 1
IOx-Bly1 ActiveGroup
Æ ACTGRP1 GRP1
IOx-Bly2
Æ ACTGRP2 GRP2
IOx-Bly3
Æ ACTGRP3 GRP3
IOx-Bly4
Æ ACTGRP4 GRP4
IOx-Bly5
Æ ACTGRP5 GRP5
IOx-Bly6 ACTGRP6
Æ GRP6
SETCHGD
en05000119.vsd
IEC05000119 V2 EN
Figure 31: Connection of the function to external circuits
The above example also includes seven output signals, for confirmation of which
group that is active.
SETGRPS function block has an input where the number of setting groups used is
defined. Switching can only be done within that number of groups. The number of
setting groups selected to be used will be filtered so only the setting groups used
will be shown on the Parameter Setting Tool.
80
Basic IED functions

ActiveGroup
ACTGRP1 GRP1
ACTGRP2 GRP2
ACTGRP3 GRP3
ACTGRP4 GRP4
ACTGRP5 GRP5
ACTGRP6 GRP6
SETCHGD
IEC05000433 V2 EN
Figure 32: ActiveGroup function block
SETGRPS
MAXSETGR
IEC05000716 V2 EN
Figure 33: SETGRPS function block
4.4.4 Input and output signals

Table 29: ActiveGroup Input signals
ACTGRP1 BOOLEAN 0 Selects setting group 1 as active
Table 30: ActiveGroup Output signals

GRP1 BOOLEAN Setting group 1 is active
SETCHGD BOOLEAN Pulse when setting changed
81
Basic IED functions

Table 31: ActiveGroup Non group settings (basic)
t 0.0 - 10.0 s 0.1 1.0 Pulse length of pulse when setting
changed
Table 32: SETGRPS Non group settings (basic)

ActiveSetGrp SettingGroup1 - - SettingGroup1 ActiveSettingGroup
SettingGroup2
SettingGroup3
SettingGroup4
SettingGroup5
SettingGroup6
MAXSETGR 1-6 No 1 1 Max number of setting groups 1-6
4.5 ChangeLock function CHNGLCK
4.5.1 Introduction
Change lock function (CHNGLCK) is used to block further changes to the IED
configuration and settings once the commissioning is complete. The purpose is to
block inadvertent IED configuration changes beyond a certain point in time.

The Change lock function (CHNGLCK) is configured using ACT.
The function, when activated, will still allow the following changes of the IED
state that does not involve reconfiguring of the IED:
• Monitoring
• Reading events
• Resetting events
• Reading disturbance data
• Clear disturbances
• Reset LEDs
• Reset counters and other runtime component states
• Control operations
• Set system time
• Enter and exit from test mode
• Change of active setting group
82
Basic IED functions
The binary input signal LOCK controlling the function is defined in ACT or SMT:
Binary input Function
1 Activated
0 Deactivated

CHNGLCK
LOCK
IEC09000946 V1 EN
Figure 34: CHNGLCK function block

Table 33: CHNGLCK Input signals
LOCK BOOLEAN 0 Parameter change lock

Table 34: CHNGLCK Non group settings (basic)
Operation LockHMI and Com - - LockHMI and Com Operation mode of change lock
LockHMI,
EnableCom
EnableHMI,
LockCom
4.6 Test mode functionality TEST
4.6.1 Introduction
When the Test mode functionality TESTMODE function is activated, protection
functions in the IED are automatically blocked. It is then possible to unblock the
protection functions individually from the local HMI or the Parameter Setting tool
to perform required tests.
When leaving TESTMODE, all blockings are removed and the IED resumes
normal operation. However, if during TESTMODE operation, power is removed
and later restored, the IED will remain in TESTMODE with the same protection
83
Basic IED functions
functions blocked or unblocked as before the power was removed. All testing will
be done with actually set and configured values within the IED. No settings will be
changed, thus mistakes are avoided.

Put the IED into test mode to test functions in the IED. Set the IED in test mode by
• configuration, activating the input signal of the function block TESTMODE.

• setting TestMode to On in the local HMI, under Main menu/TEST/IED test
mode.
While the IED is in test mode, the ACTIVE output of the function block
TESTMODE is activated. The other outputs of the function block TESTMODE
shows the generator of the “Test mode: On” state — input from configuration
(OUTPUT output is activated) or setting from local HMI (SETTING output is
activated).
While the IED is in test mode, the yellow START LED will flash and all functions
are blocked. Any function can be unblocked individually regarding functionality
and event signalling.
Most of the functions in the IED can individually be blocked by means of settings
from the local HMI. To enable these blockings the IED must be set in test mode
(output ACTIVE is activated), see example in figure 35. When leaving the test
mode, that is entering normal mode, these blockings are disabled and everything is
set to normal operation. All testing will be done with actually set and configured
values within the IED. No settings will be changed, thus no mistakes are possible.
The blocked functions will still be blocked next time entering the test mode, if the
blockings were not reset.
The blocking of a function concerns all output signals from the actual function, so
no outputs will be activated.
When a binary input is used to set the IED in test mode and a
parameter, that requires restart of the application, is changed, the
IED will re-enter test mode and all functions will be blocked, also
functions that were unblocked before the change. During the re-
entering to test mode, all functions will be temporarily unblocked
for a short time, which might lead to unwanted operations. This is
only valid if the IED is put in TEST mode by a binary input, not by
local HMI.
The TESTMODE function block might be used to automatically block functions

when a test handle is inserted in a test switch. A contact in the test switch (RTXP24
contact 29-30) can supply a binary input which in turn is configured to the
TESTMODE function block.
84
Basic IED functions
Each of the protection functions includes the blocking from the TESTMODE
function block. A typical example from the undervoltage function is shown in
figure 35.
The functions can also be blocked from sending events over IEC 61850 station bus
to prevent filling station and SCADA databases with test events, for example
during a maintenance test.
U Disconnection
Normal voltage
U1<
U2<
tBlkUV1 <
t1,t1Min
IntBlkStVal1
tBlkUV2 <
t2,t2Min
IntBlkStVal2
Time
Block step 1
Block step 2
en05000466.vsd
IEC05000466 V1 EN
Figure 35: Example of blocking the time delayed undervoltage protection

function.

TESTMODE
INPUT ACTIVE
OUTPUT
SETTING
NOEVENT
IEC09000219-1.vsd
IEC09000219 V1 EN
Figure 36: TESTMODE function block
85
Basic IED functions

Table 35: TESTMODE Input signals
INPUT BOOLEAN 0 Sets terminal in test mode when active
Table 36: TESTMODE Output signals

ACTIVE BOOLEAN Terminal in test mode when active
OUTPUT BOOLEAN Test input is active
SETTING BOOLEAN Test mode setting is (On) or not (Off)
NOEVENT BOOLEAN Event disabled during testmode

Table 37: TESTMODE Non group settings (basic)
TestMode Off - - Off Test mode in operation (On) or not (Off)
On
EventDisable Off - - Off Event disable during testmode
On
CmdTestBit Off - - Off Command bit for test required or not
On during testmode
4.7 IED identifiers
4.7.1 Introduction
IED identifiers (TERMINALID) function allows the user to identify the individual
IED in the system, not only in the substation, but in a whole region or a country.
Use only characters A-Z, a-z and 0-9 in station, object and unit names.
86
Basic IED functions

Table 38: TERMINALID Non group settings (basic)
StationName 0 - 18 - 1 Station name Station name
StationNumber 0 - 99999 - 1 0 Station number
ObjectName 0 - 18 - 1 Object name Object name
ObjectNumber 0 - 99999 - 1 0 Object number
UnitName 0 - 18 - 1 Unit name Unit name
UnitNumber 0 - 99999 - 1 0 Unit number
4.8 Product information
4.8.1 Introduction
The Product identifiers function identifies the IED. The function has seven pre-set,
settings that are unchangeable but nevertheless very important:
• IEDProdType
• ProductDef
• FirmwareVer
• SerialNo
• OrderingNo
• ProductionDate
The settings are visible on the local HMI , under Main menu/Diagnostics/IED
status/Product identifiers
They are very helpful in case of support process (such as repair or maintenance).

4.8.3 Factory defined settings

The factory defined settings are very useful for identifying a specific version and
very helpful in the case of maintenance, repair, interchanging IEDs between
different Substation Automation Systems and upgrading. The factory made settings
can not be changed by the customer. They can only be viewed. The settings are
found in the local HMI under Main menu/Diagnostics/IED status/Product
identifiers
The following identifiers are available:
87
Basic IED functions
• IEDProdType
• Describes the type of the IED (like REL, REC or RET). Example: REL670
• ProductDef
• Describes the release number, from the production. Example: 1.2.2.0
• FirmwareVer
• Describes the firmware version. Example: 1.4.51
• Firmware versions numbers are “running” independently from the
release production numbers. For every release numbers (like 1.5.0.17)
there can be one or more firmware versions, depending on the small
issues corrected in between releases.
• IEDMainFunType
• Main function type code according to IEC 60870-5-103. Example: 128
(meaning line protection).
• SerialNo
• OrderingNo
• ProductionDate
4.9 Signal matrix for binary inputs SMBI
4.9.1 Introduction
The Signal matrix for binary inputs (SMBI) function is used within the Application
Configuration Tool (ACT) in direct relation with the Signal Matrix Tool (SMT),
see the application manual to get information about how binary inputs are brought
in for one IED configuration.

The Signal matrix for binary inputs (SMBI) function , see figure 37, receives its
inputs from the real (hardware) binary inputs via the Signal Matrix Tool (SMT),
and makes them available to the rest of the configuration via its outputs, BI1 to
BI10. The inputs and outputs, as well as the whole block, can be given a user
defined name. These names will be represented in SMT as information which
signals shall be connected between physical IO and SMBI function. The input/
output user defined name will also appear on the respective output/input signal.
88
Basic IED functions

SMBI
^VIN1 ^BI1
^VIN2 ^BI2
^VIN3 ^BI3
^VIN4 ^BI4
^VIN5 ^BI5
^VIN6 ^BI6
^VIN7 ^BI7
^VIN8 ^BI8
^VIN9 ^BI9
^VIN10 ^BI10
IEC05000434 V2 EN
Figure 37: SMBI function block

Table 39: SMBI Input signals
VIn1 BOOLEAN 0 SMT Connect input
Table 40: SMBI Output signals

BI1 BOOLEAN Binary input 1
89
Basic IED functions
4.10 Signal matrix for binary outputs SMBO
4.10.1 Introduction
The Signal matrix for binary outputs (SMBO) function is used within the
Application Configuration Tool (ACT) in direct relation with the Signal Matrix
Tool (SMT), see the application manual to get information about how binary inputs
are sent from one IED configuration.

The Signal matrix for binary outputs (SMBO) function , see figure 38, receives
logical signal from the IED configuration, which is transferring to the real
(hardware) outputs, via the Signal Matrix Tool (SMT). The inputs in SMBO are
BO1 to BO10 and they, as well as the whole function block, can be tag-named. The
name tags will appear in SMT as information which signals shall be connected
between physical IO and the SMBO.
It is important that SMBO inputs are connected when SMBOs

are connected to physical outputs through the Signal Matrix
Tool. If SMBOs are connected (in SMT) but their inputs not, all
the physical outputs will be set by default. This might cause
malfunction of primary equipment and/or injury to personnel.

SMBO
BO1 ^BO1
BO2 ^BO2
BO3 ^BO3
BO4 ^BO4
BO5 ^BO5
BO6 ^BO6
BO7 ^BO7
BO8 ^BO8
BO9 ^BO9
BO10 ^BO10
IEC05000439 V2 EN
Figure 38: SMBO function block
90
Basic IED functions

Table 41: SMBO Input signals
BO1 BOOLEAN 1 Signal name for BO1 in Signal Matrix Tool
4.11 Signal matrix for mA inputs SMMI
4.11.1 Introduction
The Signal matrix for mA inputs (SMMI) function is used within the Application
Configuration Tool (ACT) in direct relation with the Signal Matrix Tool (SMT),
see the application manual to get information about how milliamp (mA) inputs are
brought in for one IED configuration.

The Signal matrix for mA inputs (SMMI) function, see figure 39, receives its
inputs from the real (hardware) mA inputs via the Signal Matrix Tool (SMT), and
makes them available to the rest of the configuration via its analog outputs, named
AI1 to AI6. The inputs, as well as the whole block, can be tag-named. These tags
will be represented in SMT.
The outputs on SMMI are normally connected to the IEC61850 generic

communication I/O functions (MVGGIO) function for further use of the mA signals.
91
Basic IED functions

SMMI
^VIN1 AI1
^VIN2 AI2
^VIN3 AI3
^VIN4 AI4
^VIN5 AI5
^VIN6 AI6
IEC05000440 V2 EN
Figure 39: SMMI function block

Table 42: SMMI Input signals
VIn1 REAL 0 SMT connected milliampere input
Table 43: SMMI Output signals

AI1 REAL Analog milliampere input 1
4.12 Signal matrix for analog inputs SMAI
4.12.1 Introduction
Signal matrix for analog inputs function SMAI (or the pre-processing function) is
used within PCM600 in direct relation with the Signal Matrix tool or the
Application Configuration tool. Signal Matrix tool represents the way analog
inputs are brought in for one IED configuration.
92
Basic IED functions

Every Signal matrix for analog inputs function (SMAI) can receive four analog
signals (three phases and one neutral value), either voltage or current, see figure 41
and figure 42. SMAI outputs give information about every aspect of the 3ph analog
signals acquired (phase angle, RMS value, frequency and frequency derivates etc. –
244 values in total). The BLOCK input will reset all outputs to 0.
The output signal AI1 to AI4 are direct output of the, in SMT, connected input to
GRPxL1, GRPxL2, GRPxL3 and GRPxN, x=1-12. AIN is always the neutral
current, calculated residual sum or the signal connected to GRPxN. Note that
function block will always calculate the residual sum of current/voltage if the input
is not connected in SMT. Applications with a few exceptions shall always be
connected to AI3P.
4.12.3 Frequency values

The frequency functions includes a functionality based on level of positive
sequence voltage, IntBlockLevel, to validate if the frequency measurement is valid
or not. If positive sequence voltage is lower than IntBlockLevel the function is
blocked. IntBlockLevel, is set in % of UBase/√3
If SMAI setting ConnectionType is Ph-Ph at least two of the inputs GRPxL1,

GRPxL2 and GRPxL3 must be connected in order to calculate positive sequence
voltage. If SMAI setting ConnectionType is Ph-N, all three inputs GRPxL1,
GRPxL2 and GRPxL3 must be connected in order to calculate positive sequence
voltage.
If only one phase-phase voltage is available and SMAI setting ConnectionType is

Ph-Ph the user is advised to connect two (not three) of the inputs GRPxL1,
GRPxL2 and GRPxL3 to the same voltage input as shown in figure 40 to make
SMAI calculating a positive sequence voltage (that is input voltage/√3).
IEC10000060 V1 EN
Figure 40: Connection example
The above described scenario does not work if SMAI setting

ConnectionType is Ph-N. If only one phase-earth voltage is
available, the same type of connection can be used but the SMAI
ConnectionType setting must still be Ph-Ph and this has to be
accounted for when setting IntBlockLevel. If SMAI setting
93
Basic IED functions
ConnectionType is Ph-N and the same voltage is connected to all

three SMAI inputs, the positive sequence voltage will be zero and
the frequency functions will not work properly.
The outputs from the above configured SMAI block shall only be
used for Overfrequency protection (SAPTOF), Underfrequency
protection (SAPTUF) and Rate-of-change frequency protection
(SAPFRC) due to that all other information except frequency and
positive sequence voltage might be wrongly calculated.
The same phase-phase voltage connection principle shall be used for frequency
tracking master SMAI block in pump-storage power plant applications when
swapping of positive and negative sequence voltages happens during generator/
motor mode of operation.

SMAI1
BLOCK SPFCOUT
DFTSPFC AI3P
^GRP1L1 AI1
^GRP1L2 AI2
^GRP1L3 AI3
^GRP1N AI4
TYPE AIN
IEC05000705 V2 EN
Figure 41: SMAI1 function block
SMAI2
BLOCK AI3P
^GRP2L1 AI1
^GRP2L2 AI2
^GRP2L3 AI3
^GRP2N AI4
TYPE AIN
IEC07000130 V2 EN
Figure 42: SMAI2 function block

Table 44: SMAI1 Input signals
BLOCK BOOLEAN 0 Block group 1
DFTSPFC REAL 20.0 Number of samples per fundamental cycle used
for DFT calculation
GRP1L1 STRING - Sample input to be used for group 1 phase L1
calculations
94
Basic IED functions

calculations
calculations
GRP1N STRING - Sample input to be used for group 1 residual
calculations
Table 45: SMAI1 Output signals

SPFCOUT REAL Number of samples per fundamental cycle from
internal DFT reference function
AI3P GROUP SIGNAL Group 1 analog input 3-phase group
AI1 GROUP SIGNAL Group 1 analog input 1
AIN GROUP SIGNAL Group 1 analog input residual for disturbance
recorder
Table 46: SMAI2 Input signals

BLOCK BOOLEAN 0 Block group 2
calculations
calculations
calculations
GRP2N STRING - Sample input to be used for group 2 residual
calculations
Table 47: SMAI2 Output signals

AI3P GROUP SIGNAL Group 2 analog input 3-phase group
AIN GROUP SIGNAL Group 2 analog input residual for disturbance
recorder
95
Basic IED functions
Settings DFTRefExtOut and DFTReference shall be set to default

value InternalDFTRef if no VT inputs are available. Internal
nominal frequency DFT reference is then the reference.
Table 48: SMAI1 Non group settings (basic)

DFTRefExtOut InternalDFTRef - - InternalDFTRef DFT reference for external output
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
DFTReference InternalDFTRef - - InternalDFTRef DFT reference
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
ConnectionType Ph-N - - Ph-N Input connection type
Ph-Ph
TYPE 1-2 Ch 1 1 1=Voltage, 2=Current
Table 49: SMAI1 Non group settings (advanced)

Negation Off - - Off Negation
NegateN
Negate3Ph
Negate3Ph+N
MinValFreqMeas 5 - 200 % 1 10 Limit for frequency calculation in % of
UBase
UBase 0.05 - 2000.00 kV 0.05 400.00 Base voltage
96
Basic IED functions
Table 50: SMAI2 Non group settings (basic)

AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
ConnectionType Ph-N - - Ph-N Input connection type
Ph-Ph
TYPE 1-2 Ch 1 1 1=Voltage, 2=Current
Table 51: SMAI2 Non group settings (advanced)

Negation Off - - Off Negation
NegateN
Negate3Ph
Negate3Ph+N
MinValFreqMeas 5 - 200 % 1 10 Limit for frequency calculation in % of
UBase
4.13 Summation block 3 phase 3PHSUM
4.13.1 Introduction
Summation block 3 phase function 3PHSUM is used to get the sum of two sets of
three-phase analog signals (of the same type) for those IED functions that might
need it.

Summation block 3 phase 3PHSUM receives the three-phase signals from Signal
matrix for analog inputs function (SMAI). In the same way, the BLOCK input will
reset all the outputs of the function to 0.
97
Basic IED functions

3PHSUM
BLOCK AI3P
DFTSPFC AI1
G1AI3P* AI2
G2AI3P* AI3
AI4
IEC05000441 V2 EN
Figure 43: 3PHSUM function block

Table 52: 3PHSUM Input signals
BLOCK BOOLEAN 0 Block
DFTSPFC REAL 0 Number of samples per fundamental cycle used
for DFT calculation
G1AI3P GROUP - Group 1 analog input 3-phase group
SIGNAL
G2AI3P GROUP - Group 2 analog input 3-phase group
SIGNAL
Table 53: 3PHSUM Output signals

AI3P GROUP SIGNAL Group analog input 3-phase group
AI1 GROUP SIGNAL Group 1 analog input
Settings DFTRefExtOut and DFTReference shall be set to default

value InternalDFTRef if no VT inputs are available.
Table 54: 3PHSUM Non group settings (basic)

SummationType Group1+Group2 - - Group1+Group2 Summation type
Group1-Group2
Group2-Group1
-(Group1+Group2)
AdDFTRefCh1
External DFT ref
98
Basic IED functions
Table 55: 3PHSUM Non group settings (advanced)

FreqMeasMinVal 5 - 200 % 1 10 Amplitude limit for frequency calculation
in % of Ubase
4.14 Authority status ATHSTAT
4.14.1 Introduction
Authority status (ATHSTAT) function is an indication function block for user log-
on activity.

Authority status (ATHSTAT) function informs about two events related to the IED
and the user authorization:
• the fact that at least one user has tried to log on wrongly into the IED and it
was blocked (the output USRBLKED)
• the fact that at least one user is logged on (the output LOGGEDON)
Whenever one of the two events occurs, the corresponding output (USRBLKED or
LOGGEDON) is activated. The output can for example, be connected on Event
(EVENT) function block for LON/SPA.The signals are also available on IEC
61850 station bus.

ATHSTAT
USRBLKED
LOGGEDON
IEC06000503 V2 EN
Figure 44: ATHSTAT function block

Table 56: ATHSTAT Output signals
USRBLKED BOOLEAN At least one user is blocked by invalid password
LOGGEDON BOOLEAN At least one user is logged on
99
Basic IED functions

4.15 Denial of service DOS
4.15.1 Introduction
The Denial of service functions (DOSFRNT, DOSOEMAB and DOSOEMCD) are
designed to limit overload on the IED produced by heavy Ethernet network traffic.
The communication facilities must not be allowed to compromise the primary
functionality of the device. All inbound network traffic will be quota controlled so
that too heavy network loads can be controlled. Heavy network load might for
instance be the result of malfunctioning equipment connected to the network.

The Denial of service functions (DOSFRNT, DOSOEMAB and DOSOEMCD)
measures the IED load from communication and, if necessary, limit it for not
jeopardizing the IEDs control and protection functionality due to high CPU load.
The function has the following outputs:
• LINKUP indicates the Ethernet link status
• WARNING indicates that communication (frame rate) is higher than normal
• ALARM indicates that the IED limits communication
4.15.3 Function blocks

DOSFRNT
LINKUP
WARNING
ALARM
IEC09000749 V1 EN
Figure 45: DOSFRNT function block
DOSOEMAB
LINKUP
WARNING
ALARM
IEC09000750 V1 EN
Figure 46: DOSOEMAB function block
100
Basic IED functions
DOSOEMCD
LINKUP
WARNING
ALARM
IEC09000751 V1 EN
Figure 47: DOSOEMCD function block
4.15.4 Signals
Table 57: DOSFRNT Output signals
LINKUP BOOLEAN Ethernet link status
WARNING BOOLEAN Frame rate is higher than normal state
ALARM BOOLEAN Frame rate is higher than throttle state
Table 58: DOSOEMAB Output signals

Table 59: DOSOEMCD Output signals

4.15.5 Settings
101
102
Differential protection
Section 5 Differential protection
About this chapter

This chapter describes the measuring principles, functions and parameters used in
differential protection.
5.1 Generator differential protection GENPDIF
Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2

identification identification device number
Generator differential protection GENPDIF 87G
Id>
SYMBOL-NN V1 EN
5.1.1 Introduction
Short circuit between the phases of the stator windings causes normally very large
fault currents. The short circuit gives risk of damages on insulation, windings and
stator iron core. The large short circuit currents cause large forces, which can cause
damage even to other components in the power plant, such as turbine and generator-
turbine shaft.
To limit the damage due to stator winding short circuits, the fault clearance must be
as fast as possible (instantaneous). If the generator block is connected to the power
system close to other generating blocks, the fast fault clearance is essential to
maintain the transient stability of the non-faulted generators.
Normally, the short circuit fault current is very large, that is, significantly larger
than the generator rated current. There is a risk that a short circuit can occur
between phases close to the neutral point of the generator, thus causing a relatively
small fault current. The fault current can also be limited due to low excitation of
the generator. Therefore, it is desired that the detection of generator phase-to-phase
short circuits shall be relatively sensitive, detecting small fault currents.
It is also of great importance that the generator differential protection does not trip
for external faults, with large fault currents flowing from the generator.
To combine fast fault clearance, as well as sensitivity and selectivity, the generator
differential protection is normally the best choice for phase-to-phase generator
short circuits.
103
Generator differential protection GENPDIF is also well suited to generate fast,

sensitive and selective fault clearance, if used to protect shunt reactors or small
busbars.

The task of Generator differential protection GENPDIF is to determine whether a
fault is within the protected zone, or outside the protected zone. The protected zone
is delimited by the position of current transformers, as shown in figure 48.
IEC06000430 V2 EN
Figure 48: Position of current transformers; the recommended (default)

orientation
If the fault is internal, the faulty generator must be quickly tripped, that is,
disconnected from the network, the field breaker tripped and the power to the
prime mover interrupted.
GENPDIF function always uses reference (default) directions of CTs towards the
protected generator as shown in figure 48. Thus, it always measures the currents on
the two sides of the generator with the same reference direction towards the
generator windings. With the orientation of CTs as in figure 48, the difference of
currents flowing in, and out, of a separate stator winding phase is simply obtained
by summation of the two currents fed to the differential protection function.
Numerical IEDs have brought a large number of advantages and new functionality
to the protective relaying. One of the benefits is the simplicity and accuracy of
calculating symmetrical components from individual phase quantities. Within the
firmware of a numerical IED, it is no more difficult to calculate negative-sequence
components than it is to calculate zero-sequence components. Diversity of
operation principles integrated in the same protection function enhances the overall
performance without a significant increase in cost.
A novelty in GENPDIF, namely the negative-sequence-current-based internal-

external fault discriminator, is used with advantage in order to determine whether a
fault is internal or external. Indeed, the internal-external fault discriminator not
only positively discriminates between internal and external faults, but can
independently detect minor faults which may not be felt (until they develop into
more serious faults) by the "usual" differential protection based on operate-restrain
characteristic.
GENPDIF is using fundamental frequency phase current phasors and negative

sequence current phasors. These quantities are derived outside the differential
protection function block, in the general pre-processing blocks. GENPDIF is also
using with advantage the DC component of the instantaneous differential current
104
and the 2nd and 5th harmonic components of the instantaneous differential currents.
The instantaneous differential currents are calculated from the input samples of the
instantaneous values of the currents measured at both ends of the stator winding.
The DC and the 2nd and 5th harmonic components of each separate instantaneous
differential current are extracted inside the differential protection.
5.1.2.1 Function calculation principles
To make a differential protection as sensitive and stable as possible, the restrained

differential characteristic is used. The protection must be provided with a
proportional bias, which makes the protection operate for a certain percentage
differential current related to the current through the generator stator winding. This
stabilizes the protection under through fault conditions while still permitting the
system to have good basic sensitivity. The following chapters explain how these
quantities are calculated.
The fundamental frequency phasors of the phase currents from both sides of the
generator (the neutral side and the terminal side) are delivered to the differential
protection function by the pre-processing module of the IED.
5.1.2.2 Fundamental frequency differential currents
The fundamental frequency RMS differential current is a vectorial sum (that is,
sum of fundamental frequency phasors) of the individual phase currents from the
two sides of the protected generator. The magnitude of the fundamental frequency
RMS differential current, in phase L1, is as calculated in equation 1:
Idiff _ L1 = [(Re( IL1n + IL1t ))2 + (Im( IL1n + IL1t )) 2 ]

EQUATION2316 V2 EN (Equation 1)
One common fundamental frequency bias current is used. The bias current is the
magnitude of the highest measured current in the protected circuit. The bias current
is not allowed to drop instantaneously, instead, it decays exponentially with a
predefined time constant. These principles make the differential IED more secure,
with less risk to operate for external faults. The “maximum” principle brings as
well more meaning to the breakpoint settings of the operate-restrain characteristic.
Ibias = max( IL1n, IL 2 n, IL3n, IL1t , IL 2t , IL 3t )

105
IL1n IL1t
IL1t Idiff
IL1n
IEC07000018 V3 EN
Figure 49: Internal fault
IL1n IL1t
External fault: IL1n = - IL1t
IL1t IL1n
Idiff = 0 en07000019-2.vsd
IEC07000019 V2 EN
Figure 50: External fault
Generator differential protection GENPDIF function uses two mutually

independent characteristics to which magnitudes of the three fundamental
frequency RMS differential currents are compared at each execution of the
differential protection function. These two characteristics divide, each of them
independently, the operate current – restrain current plane into two regions: the
operate (trip) region and the restrain (block) region, as shown in figure 52. Two
kinds of protection are obtained:
• the non-stabilized (instantaneous unrestrained) differential protection

• the stabilized differential protection
106
The non-stabilized (instantaneous) differential protection is used for very high

differential currents, where it must be beyond any doubt, that the fault is internal.
This limit, (defined by the setting UnrestrainedLimit), is a constant, not
proportional the bias (restrain) current. No harmonic or any other restrain is applied
to this limit, which is, therefore, called the unrestrained limit. The reset ratio of the
unrestrained characteristic is equal to 0.95.
The stabilized differential protection applies a differential (operate) current, and the
common bias (restrain) current, on the operate-restrain characteristic, as shown in
figure 52. Here, the actual limit, where the protection can operate, is dependent on
the bias (restrain) current. The operate value, is stabilized by the bias current. This
operate – restrain characteristic is represented by a double-slope, double-breakpoint
characteristic. The restrained characteristic is determined by the following 5 settings:
• IdMin (Sensitivity in section 1, set as multiple of generator rated current)

• EndSection1 (End of section 1, set as multiple of generator rated current)
• EndSection2 (End of section 2, set as multiple of generator rated current)
• SlopeSection2 (Slope in section 2 of the characteristic, set in percent)
• SlopeSection3 (Slope in section 3 of the characteristic, set in percent)
slope = D Ioperate × 100%

D Irestrain
Note that both slopes are calculated from the characteristics break
points.
The operate-restrain characteristic is tailor-made, in other words, it can be

constructed by the user. A default operate-restrain characteristic is suggested which
gives acceptably good results in a majority of applications. The operate-restrain
characteristic has in principle three sections with a section-wise proportionality of
the operate value to the common restrain (bias) current. The reset ratio is in all
parts of the characteristic equal to 0.95.
Section 1 is the most sensitive part on the characteristic. In section 1, normal

currents flow through the protected circuit and its current transformers, and risk for
higher false differential currents is low. With generators the only cause of small
false differential currents in this section can be tolerances of the current
transformers used on both sides of the protected generator. Slope in section 1 is
always zero percent. Normally, with the protected machine at rated load, the
restrain, bias current will be around 1 p.u., that is, equal to the machine rated current.
In section 2, a certain minor slope is introduced which is supposed to cope with

false differential currents proportional to higher than normal currents through the
current transformers.
107
The more pronounced slope in section 3 is designed to result in a higher tolerance

to substantial current transformer saturation at high through-fault currents, which
can be expected in this section.
Note that both slopes are calculated from the characteristics break
points.
Temporarily decreased sensitivity of differential protection is activated if the

binary input DESENSIT is (temporarily) set to 1 (TRUE). In this case, a new,
separate limit is superposed the otherwise unchanged operate-bias characteristic.
This limit is called TempIdMin and is a setting. The value of the setting TempIdMin
must be given as a multiple of the setting IdMin. In this case no trip command can
be issued if all fundamental frequency differential currents are below the value of
the setting TempIdMin.
AddTripDelay: If the input DESENSIT is activated also the operation time of the
protection function can be increased by using the setting AddTripDelay.
operate current
[ times IBase ]
Operate
5
unconditionally
UnrestrainedLimit
4
Operate
3
conditionally
2
Section 1 Section 2 Section 3
SlopeSection3
1
TempIdMin
IdMin
SlopeSection2 Restrain
0
0 1 2 3 4 5
EndSection1 restrain current

EndSection2 [ times IBase ]
en06000637.vsd
IEC06000637 V2 EN
Figure 52: Operate-restrain characteristic
GENPDIF can also be temporarily ‘desensitized’ if the Boolean setting

OperDCBiasing is set to 1 (TRUE). In this case, the DC component is extracted on-
line from the instantaneous differential currents. The highest DC component is
108
taken as a kind of bias in the sense that the highest sensitivity of the differential
protection is inversely proportional to the ratio of this DC component to the
maximum fundamental frequency differential current. Similar to the
‘desensitization’ described above, a separate (temporary) additional limit is
activated. The value of this limit is limited to either the generator rated current, or 3
times IdMin, whichever is smaller. This temporary extra limit decays exponentially
from its maximum value with a time constant equal to T = 1 second. This feature
must be used when unmatched CTs are used on the generator or shut reactor,
especially where a long DC time constant can be expected. The new limit is
superposed the otherwise unchanged operate-bias characteristic, and temporarily
determines the highest sensitivity of the differential protection. This temporary
sensitivity must be lower than the sensitivity in section 1 of the operate-bias
characteristic.
This DC desensitization is not active, if a disturbance has been

detected and characterized as internal fault.
5.1.2.3 Supplementary criteria
To relieve the burden of constructing an exact optimal operate-restrain

characteristic, two special features supplement the basic stabilized differential
protection function, making Generator differential protection GENPDIF a very
reliable one.
The supplementary criteria are:
• Internal/external fault discriminator (enhances, or blocks, the trip command)

• Harmonic restrain (blocks only)
The internal/external fault discriminator is a very reliable supplementary criterion.

It discriminates with a high speed between internal and external faults. The
discriminator is the main part of what is here called the negative-sequence-current-
based differential protections. It is recommended that this feature is always used
(that is, enabled, OpNegSeqDiff = On).
If a fault is classified as internal, then any eventual block signals by the harmonic
criterion are ignored, and the differential protection can operate very quickly
without any further delay.
If a fault (disturbance) is classified as external, then generally, but not

unconditionally, a trip command is prevented. If a fault is classified as external,
harmonic analysis of the fault conditions is initiated.
If all the differential currents which caused their respective start signals to be set,
are free of harmonic pollution, that is, if no harmonic block signal has been set,
then a (minor) internal fault, simultaneous with a predominant external fault, can
be suspected. This conclusion can be drawn because at external faults, major false
109
differential currents can only exist when one or more current transformers saturate
transiently. In this case, the false instantaneous differential currents are highly
polluted by higher harmonic components, the 2nd, and the 5th.
The existence of relatively high negative-sequence currents is in itself an indication

of a disturbance, as the negative-sequence currents are superimposed, pure-fault
quantities. The negative-sequence currents are measurable indications of abnormal
conditions. The negative sequence currents are particularly suitable for directional
tests. The negative sequence internal or external fault discriminator works
satisfactorily even in case of three-phase faults. Because of the fundamental
frequency components (50/60 Hz) of the decaying DC offset of the fault currents,
the system is not fully symmetrical immediately after the fault. Due to the transient
existence of the negative sequence system, faults can be distinguished as internal or
external, even for three-phase faults.
The internal or external fault discriminator responds to the relative phase angles of
the negative sequence fault currents at both ends of the stator winding. Observe
that the source of the negative sequence currents at unsymmetrical faults is at the
fault point.
• If the two negative sequence currents, as seen by the differential relay, flow in
the same direction (that is with the CTs oriented as in figure 48), the fault is
internal. If the two negative sequence currents flow in opposite directions, the
fault is external.
• Under external fault condition, the relative angle is theoretically equal to 180°.
Under internal fault condition, the angle is ideally 0°, but due to possible
different negative-sequence impedance angles on both sides of the internal
fault, it may differ somewhat from 0°.
The setting NegSeqROA, as shown in figure 53, represents the so called Relay
Operate Angle, which determines the boundary between the internal and external
fault regions. It can be selected in the range ±30° to ±90°, with a step of 1°. The
default value is ±60°. The default setting, ±60°, favors somewhat security in
comparison to dependability.
Magnitudes of both negative-sequence currents which are to be compared as to

their phase positions in the complex plane must be high enough so that one can be
sure that they are due to a fault. The limit value IMinNegSeq is settable in the range
[0.02 – 0.20] of the protected generator rated current. Adaptability is introduced if
the bias current is higher than 150 % rated current. Adaptability is introduced 10
ms after this limit of 150 % rated current has been crossed so that the internal/
external discriminator is given the time to detect correctly a fault before an
eventual CT saturation sets in. The threshold IMinNegSeq is dynamically increased
by 4 % of the bias current, in case of internal faults, and by 8 % of the bias current
in case of external faults. Only if magnitudes of both currents are above the limit
IMinNegSeq, the angle between the two currents is calculated. If any of the two
currents is too small, no decision is taken regarding the relative position of the
fault, and this feature then remains inactive rather than to produce a wrong
decision. The relative angle is then assigned the value of 120° (2.094 radians). If
110
this value persists, then this is an indication that no directional comparison has
been made. Neither internal, nor external fault (disturbance) is declared in this case.
90 deg
120 deg
NegSeqROA
Angle could not be (Relay Operate Angle)
measured. One or both
currents too small
Internal fault
region
180 deg 0 deg
IminNegSeq
External fault
region
Internal /
external fault
boundary.
Default ± 60 deg
The characteristic is defined by the
settings:
IMinNegSeq and NegSeqROA
270 deg
en06000433-2.vsd
IEC06000433 V2 EN
Figure 53: NegSeqROA determines the boundary between the internal and
external fault regions
Unrestrained negative sequence differential protection

If one or more start signals have been set by the restrained differential protection
algorithm, because one or more of the fundamental frequency differential currents
entered the “operate” region of the restrained differential protection, then the internal/
external fault discriminator can enhance the final, common, trip command by the
differential protection. If a fault is classified as internal, then any eventual block
signals by the harmonic criterion are ignored, and the differential protection
operates immediately without any further delay. This makes the overall generator
differential protection very fast. Operation of this protection is signaled on the
output of GENPDIF as TRNSUNRE.
Sensitive negative sequence differential protection

The difference from the unrestrained negative sequence differential protection,
described above, is that the sensitive one does not require any start signal to be set.
It is enough that both of the negative sequence currents, contributions to the total
negative sequence differential current, which should be compared, are above the
setting IMinNegSeq. Thus, this protection can be made very sensitive. Further, an
intentional delay of one cycle is added in order not to inadvertently operate for
some eventual transients. Further, the sensitive negative sequence differential
protection is automatically disabled when the bias current exceeds 1.5 times the
111
rated current of the protected generator. Operation of this protection is signaled on

the output of the function as TRNSENS.
5.1.2.4 Harmonic restrain
Harmonic restrain is the classical restrain method traditionally used with power
transformer differential protections. The goal there was to prevent an unwanted trip
command due to magnetizing inrush currents at switching operations, due to
magnetizing currents at over-voltages, or external faults. Harmonic restrain is just
as useful with Generator differential protection GENPDIF. The harmonic analysis
is only executed in those phases, where start signals have been set.
There is no magnetizing inrush to a generator, but there may be some in case of

shunt reactors. The false initial differential currents of a shunt reactor have an
appreciable amount of higher harmonic currents.
At external faults dangerous false differential currents can arise for different
reasons, mainly due to saturation of one or more current transformers. The false
differential currents display in this case a considerable amount of higher
harmonics, which can, therefore, be used to prevent an unwanted trip of a healthy
generator or shunt reactor.
If a fault is recognized as external by the internal/external fault discriminator, but

nevertheless one or more start signals have been set, the harmonic analysis is
initiated in the phases with start signal, as previously described. If all of the
instantaneous differential currents, where trip signals have been set, are free of
higher harmonics (that is the cross-block principle is imposed temporarily), a
(minor) internal fault is assumed to have happened simultaneously with a
predominant external one. A trip command is then allowed.
5.1.2.5 Cross-block logic scheme
The cross-block logic says that in order to issue a common trip command, the
harmonic contents in all phases with a start signal set (start = TRUE) must be
below the limit defined with the setting HarmDistLimit. In the opposite case, no
trip command will be issued.
The cross-block logic is active if the setting OpCrossBlock = Yes. By always using
the cross-block logic, the false trips can be prevented for external faults in cases
where the internal or external fault discriminator should for some reason fail to
declare an external fault. For internal faults, the higher frequency components of an
instantaneous differential current are most often relatively low, compared to the
fundamental frequency component. While for an external (heavy) fault, they can be
relatively high. For external faults with moderate fault currents, there can be little
or no current transformer saturation and only small false differential currents.
The principle design of the Generator differential protection GENPDIF is shown in

figure 54.
112
TRIP
Signals
Start
Phasors IL1N, IL2N,IL3N Magnitude phase
Calculation Idiff and Ibias Diff.prot. selective
Idiff and Ibias characteristic
Phasors IL1T, IL2T,IL3T
START
Signals
BLOCK
Signals
Samples IL1N, IL2N,IL3N Harm.

Calculation Samples Idiff Hamonic Block Start and INTFAULT
instantaneous analysis: DC, trip logic EXTFAULT
Samples IAT, IBT,ICT Idiff 2nd and 5th OPENCT
OPENCTAL
The sensitive protection is deactivated

above bias current > 150 % rated
current.
Internal/ Intern/ Analog

Phasor IL1N (neg.seq.) External Fault extern Outputs
Calculation
Discriminator Fault
negative
sequence and Sensitive
Phasor IL1T (neg.seq.) Idiff differential
protection
en06000434-2.vsd
IEC06000434 V3 EN
Figure 54: Simplified principle design of the Generator differential protection GENPDIF
Simplified logic diagrams of the function are shown in figures 55, 56, 57 and 58.
113
BLKUNRES
IdUnre a TRIPUNREL1
b>a AND
b
IDL1MAG
IBIAS STL1
AND
BLOCK
BLKRES
INTFAULT TRIPRESL1
AND
OR 1
IDL1 2nd and BLKHL1

5th
Harmonic
Cross Block
Cross Block to L2 or L3
from L2 or L3 AND
AND
OpCrossBlock=On
en07000020.vsd
IEC07000020 V2 EN
Figure 55: Generator differential logic diagram 1
Internal/ EXTFAULT
Neg.Seq. Diff External INTFAULT
Current Fault
Contributions discrimin
ator TRNSSENS
AND
OpNegSeqDiff=On
IBIAS
a
b>a
b
Constant
BLKNSSEN
BLKNSUNR
BLOCK
TRNSUNR
STL1 AND
STL2
OR
STL3
en07000021.vsd
IEC07000021 V2 EN
114
STL1
STL2 START
OR
STL3
BLKHL1
BLKHL2 BLKH
OR
BLKHL3
en07000022.vsd
IEC07000022 V1 EN
TRIPRESL1
TRIPRESL2 TRIPRES
OR
TRIPRESL3
TRIPUNREL1
TRIPUNREL2 TRIPUNRE
OR
TRIPUNREL3
TRIP
TRNSSENS OR
TRNSUNR
en07000023.vsd
IEC07000023 V1 EN
115

GENPDIF
I3PNCT1* TRIP
I3PNCT2* TRIPRES
I3PTCT1* TRIPUNRE
I3PTCT2* TRNSUNR
BLOCK TRNSSENS
BLKRES START
BLKUNRES STL1
BLKNSUNR STL2
BLKNSSEN STL3
DESENSIT BLKH
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDNSMAG
IBIAS
IEC11000212 V1 EN
Figure 59: GENPDIF function block

Table 60: GENPDIF Input signals
I3PNCT1 GROUP - Neutral side input1
SIGNAL
I3PNCT2 GROUP - Neutral side input2
SIGNAL
I3PTCT1 GROUP - Terminal side input1
SIGNAL
I3PTCT2 GROUP - Terminal side input2
SIGNAL
BLOCK BOOLEAN 0 Block of function
BLKRES BOOLEAN 0 Block of trip command by the restrained diff.
protection
BLKUNRES BOOLEAN 0 Block of trip by unrestrained "instantaneous" diff.
prot.
BLKNSUNR BOOLEAN 0 Block of trip for unrestr. neg. seq. differential
feature
BLKNSSEN BOOLEAN 0 Block of trip for sensitive neg. seq. differential
feature
DESENSIT BOOLEAN 0 Raise pick up: function temporarily desensitized
116
Table 61: GENPDIF Output signals

TRIP BOOLEAN General, common trip signal
TRIPRES BOOLEAN Trip signal from restrained differential protection
TRIPUNRE BOOLEAN Trip signal from unrestrained differential protection
TRNSUNR BOOLEAN Trip signal from unrestr. neg. seq. diff. protection
TRNSSENS BOOLEAN Trip signal from sensitive neg. seq. diff. protection
START BOOLEAN Common start signal from any phase
STL1 BOOLEAN Start signal from phase L1
BLKH BOOLEAN Common harmonic block signal
OPENCT BOOLEAN An open CT was detected
OPENCTAL BOOLEAN Open CT Alarm output signal. Issued after a
delay ...
IDL1 REAL Instantaneous differential current L1; in primary
Amperes
Amperes
Amperes
IDNSMAG REAL Negative Sequence Differential current; in
primary Amperes
IBIAS REAL Magnitude of the common Bias current; in
primary Amperes

Table 62: GENPDIF Group settings (basic)
Operation Off - - Off Operation Off / On
On
IdMin 0.05 - 1.00 IB 0.01 0.25 Section 1 sensitivity, multiple of
generator rated current
IdUnre 1.00 - 50.00 IB 0.01 10.00 Unrestr. prot. limit, multiple of generator
rated current
OpNegSeqDiff No - - Yes Negative Sequence Differential Enable
Yes Off/On
IMinNegSeq 0.02 - 0.20 IB 0.01 0.04 Neg. sequence curr. limit, as multiple of
gen. rated curr.
117
Table 63: GENPDIF Group settings (advanced)

EndSection1 0.20 - 1.50 IB 0.01 1.25 End of section 1, multiple of generator
rated current
EndSection2 1.00 - 10.00 IB 0.01 3.00 End of section 2, multiple of generator
rated current
SlopeSection2 10.0 - 50.0 % 0.1 40.0 Slope in section 2 of operate-restrain
characteristic, in %
OpCrossBlock No - - Yes Operation On / Off for cross-block logic
Yes between phases
NegSeqROA 30.0 - 120.0 Deg 0.1 60.0 Operate Angle of int/ext neg. seq. fault
discriminator, deg
HarmDistLimit 5.0 - 100.0 % 0.1 10.0 (Total) relative harmonic distorsion limit,
percent
TempIdMin 1.0 - 5.0 IdMin 0.1 2.0 Temp. Id pickup when input
raisePickUp=1, multiple of IdMin
AddTripDelay 0.000 - 60.000 s 0.001 0.100 Additional trip delay, when input
raisePickUp=1
OperDCBiasing Off - - Off Operation DC biasing On / Off
On
OpenCTEnable Off - - Off Open CT detection feature Off/On
On
tOCTAlarmDelay 0.100 - 10.000 s 0.001 1.000 Open CT: time to alarm if an open CT is
detected, in sec
tOCTResetDelay 0.100 - 10.000 s 0.001 0.250 Reset delay in s. After delay, diff.
function is activated
tOCTUnrstDelay 0.100 - 100.000 s 0.001 10.000 Unrestrained diff. protection blocked
after this delay, in s
Table 64: GENPDIF Non group settings (basic)

IBase 100.0 - 100000.0 A 0.1 5000.0 Rated current of protected generator,
Amperes
InvertCT2Curr No - - No Invert CT 2 curr., yes (1) or no (0).
Yes Default is no (0).

Table 65: GENPDIF technical data
Function Range or value Accuracy
Reset ratio > 95% -
Unrestrained differential current limit (1-50)p.u. of IBase ± 2.0% of set value
Base sensitivity function (0.05–1.00)p.u. of ± 2.0% of Ir
IBase
118

Negative sequence current level (0.02–0.2)p.u. of IBase ± 1.0% of Ir
Operate time, restrained function 25 ms typically at 0 to -

2 x set level
Reset time, restrained function 20 ms typically at 2 to -
0 x set level
Operate time, unrestrained function 12 ms typically at 0 to -
5 x set level
Reset time, unrestrained function 25 ms typically at 5 to -
0 x set level
Operate time, negative sequence 15 ms typically at 0 to -
unrestrained function 5 x set level
Critical impulse time, unrestrained function 2 ms typically at 0 to 5 -
x set level
5.2 Transformer differential protection T2WPDIF and

T3WPDIF

Transformer differential protection, two- T2WPDIF 87T
winding
3Id/I
SYMBOL-BB V1 EN
Transformer differential protection, T3WPDIF 87T

three-winding
3Id/I
SYMBOL-BB V1 EN
5.2.1 Introduction
The Transformer differential protection, two-winding (T2WPDIF) and Transformer
differential protection, three-winding (T3WPDIF) are provided with internal CT
ratio matching and vector group compensation and settable zero sequence current
elimination.
The function can be provided with up to three-phase sets of current inputs. All
current inputs are provided with percentage bias restraint features, making the IED
suitable for two- or three-winding transformer in multi-breaker station arrangements.
119
Two-winding applications
two-winding power
transformer
xx05000048.vsd
IEC05000048 V1 EN
two-winding power
transformer with
unconnected delta
xx05000049.vsd tertiary winding
IEC05000049 V1 EN
two-winding power
transformer with two
circuit breakers on
xx05000050.vsd one side
IEC05000050 V1 EN
two-winding power
circuit breakers and
two CT-sets on both
sides
xx05000051.vsd
IEC05000051 V1 EN
Three-winding applications
three-winding power
transformer with all
three windings
connected
xx05000052.vsd
IEC05000052 V1 EN
three-winding power
circuit breakers and
two CT-sets on one
side
xx05000053.vsd
IEC05000053 V1 EN
Autotransformer with
two circuit breakers
and two CT-sets on
two out of three sides
xx05000057.vsd
IEC05000057 V1 EN
Figure 60: CT group

arrangement for
differential protection
and other protections
120
The setting facilities cover the applications of the differential protection to all types
of power transformers and auto-transformers with or without load tap changer as
well as for shunt reactors or and local feeders within the station. An adaptive
stabilizing feature is included for heavy through-faults.By introducing the load tap
changer position, the differential protection pick-up can be set to optimum
sensitivity thus covering internal faults with low fault level.
Stabilization is included for inrush currents as well as for overexcitation conditions.

Adaptive stabilization is also included for system recovery inrush and CT
saturation for external faults. A high set unrestrained differential current protection
is included for a very high speed tripping at a high internal fault currents.
An innovative sensitive differential protection feature, based on the theory of

symmetrical components, offers the best possible coverage for power transformer
winding turn-to-turn faults.

The task of the power transformer differential protection is to determine whether a
fault is within the protected zone, or outside the protected zone. The protected zone
is delimited by the position of current transformers (see figure 61), and in principle
can include more objects than just transformer. If the fault is found to be internal,
the faulty power transformer must be quickly disconnected.
The main CTs are normally supposed to be star connected. The main CTs can be
earthed in anyway (that is, either "ToObject" or "FromObject"). However
internally the differential function will always use reference directions towards the
protected transformer as shown in figure 61. Thus the IED will always internally
measure the currents on all sides of the power transformer with the same reference
direction towards the power transformer windings as shown in figure 61.For more
information see the Application manual
IW1 IW2
Z1S1 Z1S2
E1S1 E1S2
IW1 IW2
IED
en05000186.vsd
IEC05000186 V1 EN
Figure 61: Typical CT location and definition of positive current direction
Even in a healthy power transformer, the currents are generally not equal when
they flow through the power transformer, due to the ratio of the number of turns of
the windings and the connection group of the protected transformer. Therefore the
121
differential protection must first correlate all currents to each other before any
calculation can be performed.
In numerical differential protections this correlation and comparison is performed

mathematically. First, compensation for the protected transformer transformation
ratio and connection group is made, and only then the currents are compared phase-
wise. This makes the external auxiliary (that is, interposing) current transformers
unnecessary. Conversion of all currents to the common reference side of the power
transformer is performed by pre-programmed coefficient matrices, which depends
on the protected power transformer transformation ratio and connection group.
Once the power transformer vector group, rated currents and voltages has been
entered by the user, the differential protection is capable to calculate off-line matrix
coefficients required in order to perform the on-line current comparison by means
of a fixed equation.
Numerical IEDs have brought a large number of well-known advantages and new
functionality to the protective relaying. One of the benefits is the simplicity and
accuracy of calculating symmetrical components from individual phase quantities.
Within the firmware of a numerical IED, it is no more difficult to calculate negative-
sequence components than it is to calculate zero-sequence components. Diversity
of operation principles integrated in the same protection function enhances the
overall performance without a significant increase in cost.
A novelty in power transformer differential protection, namely the negative-

sequence-current-based internal-external fault discriminator, is used with
advantage in order to determine whether a fault is internal or external. Indeed, the
internal-external fault discriminator not only positively discriminates between
internal and external faults, but can as well independently detect minor faults
which may not be felt by the "usual" differential protection based on operate-
restrain characteristic.
5.2.2.1 Function calculation principles
To make a differential IED as sensitive and stable as possible, restrained

differential characteristic have been developed and are now adopted as the general
practice in the protection of power transformers. The protection should be provided
with a proportional bias, which makes the protection operate for a certain
percentage differential current related to the current through the transformer. This
stabilizes the protection under through fault conditions while still permitting the
system to have good basic sensitivity. The following chapters explain how these
quantities are calculated.
Fundamental frequency differential currents

The fundamental frequency differential current is a vectorial sum (sum of
fundamental frequency phasors) of the individual phase currents from different side
of the protected power transformer.
122
Before any differential current can be calculated, the power transformer phase
shift, and its transformation ratio, must be allowed for. Conversion of all currents
to a common reference is performed in two steps:
• all current phasors are phase-shifted to (referred to) the phase-reference side,
(whenever possible a first winding with star connection)
• all currents magnitudes are always referred to the first winding of the power
transformer (typically transformer high-voltage side)
The two steps of conversion are made simultaneously on-line by the pre-
programmed coefficient matrices, as shown in equation 5 for a two-winding power
transformer, and in equation 6 for a three-winding power transformer.
These are internal compensation within the differential function.

The protected power transformer data are always entered as they
are given on the nameplate. Differential function will by it self
correlate nameplate data and select proper reference windings.
é IDL1 ù é IL1_ W 1 ù é IL1_ W 2 ù

ê IDL 2 ú = A × ê IL 2 _ W 1ú + Un _ W 2 × B × ê IL 2 _ W 2 ú
ê ú ê ú Un _ W 1 ê ú
êë IDL3 úû êë IL3 _ W 1úû êë IL3 _ W 2 úû
1 2 3
where:
1. is Differential Currents
2. is Differential current contribution from W1 side
123
é IDL1 ù é IL1_ W 1 ù é IL1_ W 2 ù é IL1_ W 3 ù

ê IDL 2 ú = A × ê IL 2 _ W 1ú + Un _ W 2 × B × ê IL 2 _ W 2 ú + Un _ W 3 × C × ê IL 2 _ W 3ú
ê ú ê ú Un _ W 1 ê ú Un _ W 1 ê ú
êë IDL3 úû êë IL3 _ W 1úû êë IL3 _ W 2 úû êë IL3 _ W 3 úû
1 2 3 4
where:
1. is Differential Currents
and where, for equation 5 and equation 6:

IDL1 is the fundamental frequency differential current in phase L1 (in W1 side primary amperes)
IDL3 is the fundamental frequency differential current in phase L3C (in W1 side primary
amperes)
IL1_W1 is the fundamental frequency phase current in phase L1 on W1 side
IL3_W2 is the fundamental frequency phase current in phase L3
Ur_W1 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
A, B & C are three by three matrices with numerical coefficients
Values of the matrix A, B & C coefficients depend on:
1. Power transformer winding connection type, such as star (Y/y) or delta (D/d)
2. Transformer vector group such as Yd1, Dy11, YNautod5, Yy0d5 and so on,
which introduce phase displacement between individual windings currents in
multiples of 30°.
3. Settings for elimination of zero sequence currents for individual windings.
124
When the end user enters all these parameters, transformer differential function
automatically calculates off-line the matrix coefficients. During this calculations
the following rules are used:
For the phase reference, the first winding with set star (Y) connection is always
used. For example, if the power transformer is a Yd1 power transformer, the HV
winding (Y) is taken as the phase reference winding. If the power transformer is a
Dy1, then the LV winding (y) is taken for the phase reference. If there is no star
connected winding, such as in Dd0 type of power transformers, then the HV delta
winding (D) is automatically chosen as the phase reference winding.
The fundamental frequency differential currents are in general composed of

currents of all sequences, that is, the positive-, the negative-, and the zero-sequence
currents. If the zero-sequence currents are eliminated (see section "Optional
Elimination of zero sequence currents"), then the differential currents can consist
only of the positive-, and the negative-sequence currents. When the zero-sequence
current is subtracted on one power transformer side, then it is subtracted from each
individual phase current.
As it can be seen from equation 5 and equation 6 the first entered winding (W1) is
always taken for ampere level reference (current magnitudes from all other sides
are always transferred to W1 side). In other words, within the differential
protection function, all differential currents and bias current are always expressed
in HV side primary Amperes.
It can be shown that the values of the matrix A, B & C coefficients (see equation 5
and equation 6) can be in advanced pre-calculated depending on the relative phase
shift between the reference winding and other power transformer windings.
Table 66 summarizes the values of the matrices for all standard phase shifts
between windings.
125
Table 66: Matrices for differential current calculation

Matrix with Zero Sequence Matrix with Zero Sequence
Reduction set to On Reduction set to Off
Matrix for Reference Winding
é 2 -1 -1ù é1 0 0 ù
1 ê
× -1 2 -1ú ê0 1 0 ú
3 ê ú ê ú
ëê -1 -1 2 ûú ëê0 0 1 úû
EQUATION1227 V1 EN (Equation 7) EQUATION1228 V1 EN (Equation 8)
Matrix for winding with 30° Not applicable. Matrix on the
lagging é 1 -1 0 ù left used.
1
× ê 0 1 -1ú
3 ê ú
ëê -1 0 1 úû
Matrix for winding with 60°
é1 -2 1ù é 0 -1 0 ù
lagging 1 ê
× 1 1 -2 ú ê 0 0 -1ú
3 ê ú ê ú
êë -2 1 1 úû ëê -1 0 0 úû
lagging é 0 -1 1 ù left used.
1
× ê 1 0 -1ú
3 ê ú
êë -1 1 0 úû
lagging é -1 -1 2 ù é0 0 1 ù
1 ê
× 2 -1 -1ú ê1 0 0 ú
3 ê ú ê ú
êë -1 2 -1úû êë0 1 0 úû
lagging é-1 0 1 ù left used.
1
× ê 1 -1 0 ú
3 ê ú
êë 0 1 -1úû
Matrix for winding which is in
opposite phase é -2 1 1ù é -1 0 0 ù
1 ê
× 1 -2 1 ú ê 0 -1 0 ú
3 ê ú ê ú
ëê 1 1 -2 ûú êë 0 0 -1úû
leading é-1 1 0 ù left used.
1
× ê 0 -1 1 ú
3 ê ú
ëê 1 0 -1ûú
126
Matrix with Zero Sequence Matrix with Zero Sequence

Reduction set to On Reduction set to Off
leading é -1 2 -1ù é0 1 0 ù
1 ê
× -1 -1 2 ú ê0 0 1 ú
3 ê ú ê ú
êë 2 -1 -1úû êë1 0 0 úû

leading é 0 1 -1ù left used.
1
× ê -1 0 1 ú
3 ê ú
êë 1 -1 0 úû
é1 1 -2 ù é 0 0 -1ù
leading 1 ê
× -2 1 1ú ê -1 0 0 ú
3 ê ú ê ú
êë 1 -2 1 úû êë 0 -1 0 úû
leading é 1 0 -1ù left used.
1 ê
× -1 1 0 ú
3 ê ú
êë 0 -1 1 úû
By using this table complete equation for calculation of fundamental frequency

differential currents for two winding power transformer with YNd5 vector group
and enabled zero sequence current reduction on HV side will be derived. From the
given power transformer vector group the following is possible to be concluded:
1. HV winding will be used as reference winding and zero sequence currents

shall be subtracted on that side
2. LV winding is lagging for 150°
With help of table 66, the following matrix equation can be written for this power
transformer:
é IDL1ù é 2 -1 -1ù é IL1_ W1ù é-1 0 1 ù é IL1_ W 2 ù

ê IDL2ú = 1 × ê-1 2 -1ú × ê IL2 _ W1ú + Ur _ W 2 × 1 × ê 1 -1 0 ú × ê IL2 _ W 2ú
ê ú 3 ê ú ê ú Ur _ W1 3 ê ú ê ú
êë IDL3úû êë-1 -1 2 úû êë IL3_ W1úû êë 0 1 -1úû êë IL3_ W 2 úû
where:
127

As marked in equation 5 and equation 6, the first term on the right hand side of the
equation, represents the total contribution from the individual phase currents from
W1 side to the fundamental frequency differential currents compensated for
eventual power transformer phase shift. The second term on the right hand side of
the equation, represents the total contribution from the individual phase currents
from W2 side to the fundamental frequency differential currents compensated for
eventual power transformer phase shift and transferred to the power transformer
W1 side. The third term on the right hand side of the equation, represents the total
contribution from the individual phase currents from W3 side to the fundamental
frequency differential currents compensated for eventual power transformer phase
shift and transferred to the power transformer W1 side. These current contributions
are important, because they are used for calculation of common bias current.
The fundamental frequency differential currents are the "usual" differential

currents, the magnitudes of which are applied in a phase-wise manner to the
operate - restrain characteristic of the differential protection. The magnitudes of the
differential currents can be read as service values from the function and they are
available as outputs IDL1MAG, IDL2MAG, IDL3MAG from the differential
protection function block. Thus they can be connected to the disturbance recorder
and automatically recorded during any external or internal fault condition.
On-line compensation for load tap changer movement

A load tap changer is a mechanical device, which is used to step-wise change
number of turns within one power transformer winding. Consequently the power
transformer overall turns ratio is changed. Typically the load tap changer is located
within the HV winding (that is, winding 1, W1) of the power transformer. By
operating load tap changer, it is possible to step-wise regulate voltage on the LV
side of the power transformer. However at the same time the differential protection
for power transformer becomes unbalanced. Differential function in the IED has built-
in feature to continuously monitor the load tap changer position and dynamically
compensate on-line for changes in power transformer turns ratio.
Differential currents are calculated as shown in equation 5and equation 6. If by

setting parameters is defined on which winding load tap changer is located and
what is the no-load voltage change for each step the differential function will make
no load voltage on that power transformer side dependent on actual load tap
changer position. Thus, if for example the load tap changer is located within
winding 1 the no-load voltage Vn_W1 will be treated as function of actual load tap
changer position in equation 5and equation 6. Thus for every load tap changer
128
position corresponding value for Ur_W1 will be calculated and used in above-
mentioned equations. By doing this complete on-line compensation for load tap
changer movement is achieved. Differential protection will be ideally balanced for
every load tap changer position and no false differential current will appear
irrespective on actual load tap changer position.
Typically the minimum differential protection pickup for power transformer with
load tap changer is set between 30% to 40%. However with this load tap changer
compensation feature it is possible to set differential protection in the IED more
sensitive pickup value of 15% to 20%.
Load tap changer position is measured within the IED by Tap changer control and
supervision, (TCLYLTC). Within this function block the load tap changer position
value is continuously monitored to insure its integrity.
When any error with load tap changer position is detected the alarm is given which
shall be connected to the OLTCxAL input into the differential function block.
While OLTCxAL input has logical value one the differential protection minimum
pickup, originally defined by setting parameter IdMin, will be increased by the set
range of the load tap changer. Alternatively the differential current alarm feature
can be used to alarm for any problems in the whole load tap changer compensation
chain.
It shall be noted that:
• two-winding differential protection in the IED can on-line compensate for one
load tap changer within protected power transformer
• three-winding differential protection in the IED can on-line compensate for up
to two load tap changers within protected power transformer
Differential current alarm

Fundamental frequency differential current level is monitored all the time within
the differential function. As soon as all three fundamental frequency differential
currents are set, a threshold defined by setting parameter IDiffAlarm a delay on
pickup timer is started. When the pre-set time, defined by setting parameter
tAlarmDelay, has expired the differential current alarm is generated and output
signal IDALARM is set to logical value one. This feature can be effectively used to
provide alarm when load tap changer position compensation is used and something
in the whole compensation chain goes wrong. This alarm can be as well used with
some additional IED configuration logic to desensitize the differential function.
Bias current
The bias current is calculated as the highest current amongst individual winding
current contributions to the total fundamental frequency differential currents, as
shown in equation 5 and equation 6. All individual winding current contributions
are already referred to the power transformer winding one side (power transformer
HV winding) and therefore they can be compared regarding their magnitudes.
There are six (or nine in case of three-winding transformer) contributions to the
total fundamental differential currents, which are the candidates for the common
129
bias current. The highest individual current contribution is taken as a common bias
(restrain) current for all three phases. This "maximum principle" makes the
differential protection more secure, with less risk to operate for external faults and
in the same time brings more meaning to the breakpoint settings of the operate -
restrain characteristic.
It shall be noted that if the zero-sequence currents are subtracted from the separate
contributions to the total differential current, then the zero-sequence component is
automatically eliminated from the bias current as well. This ensures that for
secondary injection from just one power transformer side the bias current is always
equal to the highest differential current regardless of the fault type. During normal
through-load operation of the power transformer, the bias current is equal to the
maximum load current from two (three) -power transformer windings.
The magnitudes of the common bias (restrain) current expressed in the HV side
Amperes can be read as service values from the function. At the same time it is
available as outputs IBIAS from the differential protection function block. Thus, it
can be connected to the disturbance recorder and automatically recorded during
any external or internal fault condition.
For application with so called "T" configuration, that is, two restraint CT inputs
from one side of the protected power transformer, such as in the case of breaker-and-
a-half scheme the primary CT ratings can be much higher then the rating of the
protected power transformer. In order to determine the bias current for such T
configuration, the two separate currents flowing on the T-side are scaled down to
the protected power transform level by means of additional setting. This is done in
order to prevent unwanted de-sensitizing of the overall differential protection. In
addition to that, the resultant currents (the sum of two currents) into the protected
power transformer winding, which is not directly measured is calculated, and
included as well in the common bias calculation. The rest of the bias calculation
procedure is the same as in protection schemes without breaker-and-a-half scheme.
Optional Elimination of zero sequence currents

To avoid unwanted trips for external earth-faults, the zero sequence currents should
be subtracted on the side of the protected power transformer, where the zero
sequence currents can flow at external earth-faults.
The zero sequence currents can be explicitly eliminated from the differential
currents and common bias current calculation by special, dedicated parameter
settings, which are available for every individual winding.
Elimination of the zero sequence component of current is necessary whenever:
• the protected power transformer cannot transform the zero sequence currents
to the other side, for any reason.
• the zero sequence currents can only flow on one side of the protected power
transformer.
In most cases, power transformers do not properly transform the zero sequence
current to the other side. A typical example is a power transformer of the star-delta
130
type, for example YNd1. Transformers of this type do not transform the zero
sequence quantities, but zero sequence currents can flow in the earthed star-
connected winding. In such cases, an external earth-fault on the star-side causes the
zero sequence currents to flow on the star-side of the power transformer, but not on
the other side. This results in false differential currents - consisting exclusively of
the zero sequence currents. If high enough, these false differential currents can
cause an unwanted disconnection of the healthy power transformer. They must
therefore be subtracted from the fundamental frequency differential currents if an
unwanted trip is to be avoided.
For delta windings this feature shall be enabled only if an earthing transformer
exist within differential zone on the delta side of the protected power transformer.
Removing the zero sequence current from the differential currents decreases to
some extent sensitivity of the differential protection for internal earth-faults. In
order to counteract this effect to some degree, the zero sequence currents are
subtracted not only from the three fundamental frequency differential currents, but
automatically from the bias current as well.
Restrained, and unrestrained limits of the differential protection

Power transformer differential protection function uses two limits, to which actual
magnitudes of the three fundamental frequency differential currents are compared
at each execution of the function.
The unrestrained (that is, non-stabilized, "instantaneous") part of the differential

protection is used for very high differential currents, where it should be beyond any
doubt, that the fault is internal. This settable limit is constant (that is, not
proportional to the bias current). Neither harmonic, nor any other restrain is applied
to this limit, which is therefore allowed to trip power transformer instantaneously.
The restrained (that is, stabilized) part of the differential protection compares the
calculated fundamental differential (that is, operating) currents, and the bias (that
is, restrain) current, by applying them to the operate - restrain characteristic.
Practically, the magnitudes of the individual fundamental frequency differential
currents are compared with an adaptive limit. This limit is adaptive because it is
dependent on the bias (that is, restrain) current magnitude. This limit is called the
operate - restrain characteristic. It is represented by a double-slope, double-
breakpoint characteristic, as shown in figure 62. The restrained characteristic is
determined by the following 5 settings:
1. IdMin (Sensitivity in section 1, multiple of trans. HV side rated current set

under the parameter RatedCurrentW1)
2. EndSection1 (End of section 1, as multiple of transformer HV side rated
current set under the parameter RatedCurrentW1)
3. EndSection2 (End of section 2, as multiple of transformer HV side rated
4. SlopeSection2 (Slope in section 2, as multiple of transformer HV side rated
5. SlopeSection3 (Slope in section 2, as multiple of transformer HV side rated
131
The restrained characteristic in figure 62 is defined by the settings:
1. IdMin
2. EndSection1
3. EndSection2
4. SlopeSection2
5. SlopeSection3
operate current
[ times IBase ]
Operate
5
unconditionally
UnrestrainedLimit
4
Operate
3
conditionally
2
Section 1 Section 2 Section 3
SlopeSection3
1
IdMin
SlopeSection2 Restrain
0
0 1 2 3 4 5
EndSection1 restrain current

EndSection2 [ times IBase ]
en05000187-2.vsd
IEC05000187 V2 EN
Figure 62: Description of the restrained, and the unrestrained operate

characteristics
where:
slope = D Ioperate × 100%

D Irestrain
EQUATION1246 V1 EN
The operate - restrain characteristic is tailor-made and can be designed freely by

the user after his needs. The default characteristic is recommended to be used. It
gives good results in a majority of applications. The operate - restrain characteristic
has in principle three sections with a section-wise proportionality of the operate
132
value to the bias (restrain) current. The reset ratio is in all parts of the characteristic
is equal to 0.95.
Section 1: This is the most sensitive part on the characteristic. In section 1, normal
currents flow through the protected circuit and its current transformers, and risk for
higher false differential currents is relatively low. Un-compensated on-load tap-
changer is a typical reason for existence of the false differential currents in this
section. Slope in section 1 is always zero percent.
Section 2: In section 2, a certain minor slope is introduced which is supposed to

cope with false differential currents proportional to higher than normal currents
through the current transformers.
Section 3: The more pronounced slope in section 3 is designed to result in a higher

tolerance to substantial current transformer saturation at high through-fault
currents, which may be expected in this section.
The operate - restrain characteristic should be designed so that it can be expected that:
• for internal faults, the operate (differential) currents are always safely, that is,
with a good margin, above the operate - restrain characteristic
• for external faults, the false (spurious) operate currents are safely, that is, with
a good margin, below the operate - restrain characteristic
Fundamental frequency negative sequence differential currents

Existence of relatively high negative sequence currents is in itself a proof of a
disturbance on the power system, possibly a fault in the protected power
transformer. The negative-sequence currents are measurable indications of
abnormal conditions, similar to the zero sequence currents. One of the several
advantages of the negative sequence currents compared to the zero sequence
currents is however that they provide coverage for phase-to-phase and power
transformer turn-to-turn faults as well, not only for earth-faults. Theoretically the
negative sequence currents do not exist during symmetrical three-phase faults,
however they do appear during initial stage of such faults for long enough time (in
most cases) for the IED to make proper decision. Further, the negative sequence
currents are not stopped at a power transformer of the Yd, or Dy connection. The
negative sequence currents are always properly transformed to the other side of any
power transformer for any external disturbance. Finally, the negative sequence
currents are not affected by symmetrical through-load currents.
For power transformer differential protection application, the negative sequence

based differential currents are calculated by using exactly the same matrix
equations, which are used to calculate the traditional phase-wise fundamental
frequency differential currents. However, the same equation shall be fed by the
negative sequence currents from the two power transformer sides instead of
individual phase currents, as shown in matrix equation 27 for a case of two-
winding, YNd5 power transformer.
133
é IDL1 _ NS ù é2 -1 -1ù é INS _ W 1 ù é -1 0 1 ù é INS _ W 2 ù

ê IDL 2 _ NS ú = 1 × ê -1 2 -1 × ê a × INS _ W 1 ú +
ú Ur _ W 2
×
1
×ê1 -1 0 ú × ê a × INS _ W 2 ú
ê ú 3 ê ú ê 2 ú Ur _ W 1 3 ê ú ê 2 ú
ëê IDL3 _ NS ûú ëê -1 -1 2ûú ëê a × INS _ W 1ûú ëê 0 1 ú ëê a × INS _ W 2 ûú
-1û
1 2 3
where:
1. is Negative Sequence Differential Currents
2. is Negative Sequence current contribution from W1 side
3. is Negative Sequence current contribution from W2 side
and where:
IDL1_NS is the negative sequence differential current in phase L1 (in
W1 side primary amperes)
INS_W1 is negative sequence current on W1 side in primary
amperes (phase L1 reference)
INS_W2 is negative sequence current on W1 side in primary
amperes (phase L1 reference)
Ur_W1 is transformer rated phase-to-phase voltage on W1 side
(setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W2 side
(setting parameter)
a is the complex operator for sequence quantities, for example,
j ×120
o 1 3
a=e =- + j×
2 2
Because the negative sequence currents always form the symmetrical three phase
current system on each transformer side (that is, negative sequence currents in
every phase will always have the same magnitude and be phase displaced for 120
electrical degrees from each other), it is only necessary to calculate the first
negative sequence differential current that is, IDL1_NS.
As marked in equation 27, the first term on the right hand side of the equation,
represents the total contribution of the negative sequence current from W1 side
compensated for eventual power transformer phase shift. The second term on the
right hand side of the equation, represents the total contribution of the negative
sequence current from W2 side compensated for eventual power transformer phase
134
shift and transferred to the power transformer W1 side. These negative sequence
current contributions are phasors, which are further used in directional
comparisons, made in order to characterize a fault as internal or external. See
section "Internal/external fault discriminator" for more information.
The magnitudes of the negative sequence differential current expressed in the HV

side A can be read as service values from the function. In the same time it is
available as outputs IDNSMAG from the differential protection function block.
Thus, it can be connected to the disturbance recorder and automatically recorded
during any external or internal fault condition.
Internal/external fault discriminator

The internal/external fault discriminator is a very powerful and reliable
supplementary criterion to the traditional differential protection. It is recommended
that this feature shall be always used (that is, On) when protecting three-phase
power transformers. The internal/external fault discriminator detects even minor
faults, with a high sensitivity and at high speed, and at the same time discriminates
with a high degree of dependability between internal and external faults.
The algorithm of the internal/external fault discriminator is based on the theory of

symmetrical components. Already in 1933, Wagner and Evans in their famous
book "Symmetrical Components" have stated that:
Source of the negative-sequence currents is at the point of fault,

1.
E NS = - I NS × Z NS

2. Negative-sequence currents distribute through the negative-sequence
network
3. Negative-sequence currents obey the first Kirchhoff"s law
The internal/external fault discriminator responds to magnitudes and the relative

phase angles of the negative-sequence fault currents at different windings (that is,
sides) of the protected power transformer. The negative sequence fault currents
must of course first be referred to the same phase reference side, and put to the
same magnitude reference. This is done by the matrix expression (see equation 27).
Operation of the internal/external fault discriminator is based on the relative

position of the two phasors representing winding one (W1) and winding two (W2)
negative sequence current contributions, respectively, defined by expression shown
in equation 27. It performs a directional comparison between these two phasors.
First, the LV side phasor is referred to the HV side (W1 side): both the magnitude,
and the phase position are referred to the HV (W1 side). Then the relative phase
displacement between the two negative sequence current phasors is calculated. In
case of three-winding power transformers, a little more complex algorithm is
applied, with two directional tests. The overall directional characteristic of the
internal/external fault discriminator is shown in figure 63, where the directional
characteristic is defined by two setting parameters:
135
1. IMinNegSeq
2. NegSeqROA
90 deg
120 deg
If one or the Internal/external
other of fault boundary
currents is too
low, then no
measurement
NegSeqROA
is done, and (Relay
120 degrees
Operate
is mapped Angle)
180 deg 0 deg
IMinNegSeq
External Internal
fault fault
region region
270 deg
en05000188-2-en.vsd
IEC05000188 V2 EN
Figure 63: Operating characteristic of the internal/external fault discriminator
In order to perform directional comparison of the two phasors their magnitudes

must be high enough so that one can be sure that they are due to a fault. On the
other hand, in order to guarantee a good sensitivity of the internal/external fault
discriminator, the value of this minimum limit must not be too high. Therefore this
limit value, called IminNegSeq, is settable in the range of 0.02 to 0.20 times the
IBase of the power transformer winding one. The default value is 0.04. Note that,
in order to enhance stability at higher fault currents, the relatively very low
threshold value IminNegSeq is dynamically increased at currents higher than
normal currents: if the bias current is higher than 110% IBase current, than 10% of
the bias current is added to the IminNegSeq.Only if magnitudes of both negative
sequence current contributions are above the actual limit, the relative position
between these two phasors is checked. If either of the negative sequence current
contributions, which should be compared, is too small (less than the set value for
IminNegSeq), no directional comparison is made in order to avoid the possibility to
produce a wrong decision. This magnitude check, as well guarantee stability of the
algorithm, when power transformer is energized. The setting NegSeqROA
represents the Relay Operate Angle, which determines the boundary between the
internal and external fault regions. It can be selected in the range from ±30 degrees
to ±90 degrees, with a step of 0.1 degree. The default value is ±60 degrees. The
default setting ±60 degree favours somewhat security in comparison to dependability.
136
If the above condition concerning magnitudes is fulfilled, the internal/external fault

discriminator compares the relative phase angle between the negative sequence
current contributions from the W1 and W2 sides of the power transformer using the
following two rules:
• If the negative sequence currents contributions from W1 and W2 sides are in

phase, the fault is internal (that is, both phasors are within protected zone)
• If the negative sequence currents contributions from W1 and W2 sides are 180
degrees out of phase, the fault is external (that is, W1 phasors is outside
protected zone)
For example, for any unsymmetrical external fault, ideally the respective negative
sequence current contributions from the W1 and W2 power transformer sides will
be exactly 180 degrees apart and equal in magnitude, regardless the power
transformer turns ratio and phase displacement. One such example is shown in
figure 64, which shows trajectories of the two separate phasors representing the
negative sequence current contributions from HV and LV sides of an Yd5 power
transformer (for example, after the compensation of the transformer turns ratio and
phase displacement by using equation 27) for an unsymmetrical external fault.
Observe that the relative phase angle between these two phasors is 180 electrical
degrees at any point in time. No current transformer saturation was assumed for
this case.
137
"steady state"
for HV side 90
neg. seq. phasor
60
150 30
10
ms
180 0
0.1 kA
0.2 kA
0.3 kA
10 0.4 kA
ms
210 330
"steady state"
240 for LV side
270 neg. seq. phasor
Contribution to neg. seq. differential current from HV side

Contribution to neg. seq. differential current from LV side
en05000189.vsd
IEC05000189 V1 EN
Figure 64: Trajectories of Negative Sequence Current Contributions from HV

and LV sides of Yd5 power transformer during external fault
Therefore, under all external fault condition, the relative angle is theoretically
equal to 180 degrees. During internal fault, the angle shall ideally be 0 degrees, but
due to possible different negative sequence source impedance angles on W1 and
W2 sides of the protected power transformer, it may differ somewhat from the
ideal zero value. However, during heavy faults, CT saturation might cause the
measured phase angle to differ from 180 degrees for external, and from about 0
degrees for internal fault. See figure 65 for an example of a heavy internal fault
with transient CT saturation.
138
Dire ctiona l Compa ris on Crite rion: Inte rna l fa ult a s s e e n from the HV s ide
90
e xcurs ion
120 60
from 0 de gre e s
35 ms due to CT
s a tura tion
150 30
de finite ly
a n inte rna l
fa ult
180 0
trip c o mmand
in 12 ms
e xte rna l
fa ult Inte rna l fa ult
0.5 kA de cla re d 7 ms
re gion
210 330 a fte r inte rna l
fa ult occure d
1.0 kA
240 300
1.5 kA
270
HV s ide contribution to the tota l ne ga tive s e que nce diffe re ntia l curre nt in kA
Dire ctiona l limit (within the re gion de limite d by ± 60 de gre e s is inte rna l fa ult)
en05000190.vsd
IEC05000190 V1 EN
Figure 65: Operation of the internal/external fault discriminator for internal

fault with CT saturation
However, it shall be noted that additional security measures are implemented in the
internal/external fault discriminator algorithm in order to guaranty proper operation
with heavily saturated current transformers. The trustworthy information on
whether a fault is internal or external is typically obtained in about 10ms after the
fault inception, depending on the setting IminNegSeq, and the magnitudes of the
fault currents. At heavy faults, approximately 5ms time to full saturation of the
main CT is sufficient in order to produce a correct discrimination between internal
and external faults.
Unrestrained, and sensitive negative sequence protections

Two sub functions, which are based on the internal/external fault discriminator
with the ability to trip a faulty power transformer, are parts to the traditional power
transformer differential protection.
The unrestrained negative sequence differential protection

If one or more start signals have been set by the traditional differential protection
algorithm, because one or more of the fundamental frequency differential currents
entered the operate region on the operate - restrain characteristic then the
unrestrained negative sequence protection is activated. So, this protection is not
independent of the traditional restrained differential protection - it is activated after
the first start signal has been placed.
139
If the same fault has been positively recognized as internal, then the unrestrained
negative sequence differential protection places its own trip request.
Any block signals by the harmonic and/or waveform criteria, which can block the
traditional differential protection are overridden, and the differential protection
operates quickly without any further delay.
This logic guarantees a fast disconnection of a faulty power transformer for any
heavier internal faults.
If the same fault has been classified as external, then generally, but not
unconditionally, a trip command is prevented. If a fault is classified as external, the
further analysis of the fault conditions is initiated. If all the instantaneous
differential currents in phases where start signals have been issued are free of
harmonic pollution, then a (minor) internal fault, simultaneous with a predominant
external fault can be suspected. This conclusion can be drawn because at external
faults, major false differential currents can only exist when one or more current
transformers saturate. In this case, the false instantaneous differential currents are
polluted by higher harmonic components, the 2nd, the 5th etc.
Sensitive negative sequence based turn-to-turn fault protection

The sensitive, negative sequence current based turn-to-turn fault protection detects
the low level faults, which are not detected by the traditional differential protection
until they develop into more severe faults, including power transformer iron core.
The sensitive protection is independent from the traditional differential protection
and is a very good complement to it. The essential part of this sensitive protection
is the internal/external fault discriminator. In order to be activated, the sensitive
protection requires no start signal from the traditional power transformer biased
differential protection. If magnitudes of HV and LV negative sequence current
contributions are above the set limit for IminNegSeq, then their relative positions
are determined. If the disturbance is characterized as an internal fault, then a
separate trip request will be placed. Any decision on the way to the final trip
request must be confirmed several times in succession in order to cope with
eventual CT transients. This causes a short additional operating time delay due to
this security count. For very low level turn-to-turn faults the overall response time
of this protection is about 30ms.
Instantaneous differential currents

The instantaneous differential currents are calculated from the instantaneous values
of the input currents in order to perform the harmonic analysis and waveform
analysis upon each one of them (see section "Harmonic and waveform block
criteria" for more information).
The instantaneous differential currents are calculated using the same matrix
expression as shown in equation 5 and equation 6. The same matrices A, B and C
are used for these calculations as well. The only difference is that the matrix
algorithm is fed by instantaneous values of currents, that is, samples.
140
Harmonic and waveform block criteria

The two block criteria are the harmonic restrain and the waveform restrain. These
two criteria have the power to block (that is, to prevent) a trip command by the
traditional differential protection, which produces start signals by applying the
differential currents, and the bias current, to the operate - restrain characteristic.
Harmonic restrain
The harmonic restrain is the classical restrain method traditionally used with power
transformer differential protections. The goal is to prevent an unwanted trip
command due to magnetizing inrush currents at switching operations, or due to
magnetizing currents at over-voltages.
The magnetizing currents of a power transformer flow only on one side of the
power transformer (one or the other) and are therefore always the cause of false
differential currents. The harmonic analysis (the 2nd and the 5th harmonic) is
applied to instantaneous differential currents. Typically instantaneous differential
currents during power transformer energizing are shown in figure 66. The
harmonic analysis is only applied in those phases, where start signals have been
set. For example, if the content of the 2nd harmonic in the instantaneous differential
current of phase L1 is above the setting I2/I1Ratio, then a block signal is set for
that phase, which can be read as BLK2HL1 output of the differential protection.
Waveform restrain
The waveform restrain criterion is a good complement to the harmonic analysis.
The waveform restrain is a pattern recognition algorithm, which looks for intervals
within each fundamental power system cycle with low instantaneous differential
current. This interval is often called current gap in protection literature. However,
within differential function this criterion actually searches for long-lasting intervals
with low rate-of-change in instantaneous differential current, which are typical for
the power transformer inrush currents. Block signals BLKWAVLx are set in those
phases where such behavior is detected. The algorithm do not requires any end user
settings. The waveform algorithm is automatically adapted dependent only on the
power transformer rated data.
141
IEC05000343 V1 EN
Figure 66: Inrush currents to a transformer as seen by a protective IED.

Typical is a high amount of the 2nd harmonic, and intervals of low
current, and low rate-of-change of current within each period.
Cross-blocking between phases

Basic definition of the cross-blocking is that one of the three phases can block
operation (that is,tripping) of the other two phases due to the harmonic pollution of
the differential current in that phase (that is, waveform, 2nd or 5th harmonic
content). In differential algorithm the user can control the cross-blocking between
the phases via the setting parameter CrossBlockEn=On.
When parameter CrossBlockEn=On cross blocking between phases is introduced.

There is no time settings involved, but the phase with the operating point above the
set bias characteristic (in the operate region) will be able to cross-block other two
phases if it is itself blocked by any of the previously explained restrained criteria.
As soon as the operating point for this phase is below the set bias characteristic
(that is, in the restrain region) cross blocking from that phase will be inhibited. In
this way cross-blocking of the temporary nature is achieved. It should be noted that
this is the default (recommended) setting value for this parameter.
When parameter CrossBlockEn=Off, any cross blocking between phases will be

disabled. It is recommended to use the value Off with caution in order to avoid the
unwanted tripping during initial energizing of the power transformer.
Switch onto fault feature

Transformer differential function in the IED has a built-in, advanced switch onto
fault feature. This feature can be enabled or disabled by a setting parameter
SOTFMode. When enabled this feature ensures quick differential protection
tripping in cases where a transformer is energized with an internal fault (for
example, forgotten earthing on transformer LV side). Operation of this feature is
based on the fact that a current gap (term current gap is explained under waveblock
feature above) will exist within the first power system cycle when healthy power
transformer is energized. If this is not the case the waveblock criterion will reset
142
quickly. A quick reset of the waveblock criterion will temporarily disable the
second harmonic blocking feature within the differential function. This
consequently ensures fast operation of the transformer differential function for a
switch onto a fault condition. It shall be noted that this feature is only active during
initial power transformer energizing, more exactly, under the first 50 ms. When the
switch onto fault feature is disabled by the setting parameter SOTFMode, the
waveblock and second harmonic blocking features work in parallel and are
completely independent from each other.
Open CT detection feature

differential protection has a built-in, advanced open CT detection feature.
The open CT circuit condition creates unexpected operations for differential

protection under the normal load conditions. It is also possible to damage
secondary equipment due to high voltage produced from open CT circuit outputs.
Therefore, it is always a requirement from security and reliability points of view to
have open CT detection function to block differential protection function in case of
open CT conditions and at the same time, produce the alarm signal to the
operational personal to make quick remedy actions to correct the open CT condition.
The built-in open CT feature can be enabled or disabled by a setting parameter

OpenCTEnable (Off/On). When enabled, this feature prevents mal-operation when
a loaded main CT connected to differential protection is by mistake open circuited
on the secondary side. Note that this feature can only detect interruption of one CT
phase current at the time. If two or even all three-phase currents of one set of CT
are accidentally interrupted at the same time this feature cannot operate and
differential protection generates trip signal, if the false differential current is
sufficiently high. To ensure blocking of the differential protection for open CT
condition this algorithm must operate within 10 ms in order to be able to prevent
unwanted operation of differential protection under all loading conditions.
The principle applied to detect an open CT is a simple pattern recognition method,

similar to the waveform check which has been with advantage used by the Power
Transformer Differential Protection in order to detect the magnetizing inrush
condition. The open CT detection principle is based on the fact, that for an open
CT, the current in the phase with the open CT suddenly drops (at least
theoretically) to zero (that is, as seen by the protection), while the currents of the
other two phases continue as before.
The open CT function is supposed to detect an open CT under normal conditions,

that is, with the protected multi-terminal circuit under normal load. If the load
currents are very low or zero, the open CT condition cannot be detected. The open
CT algorithm only detects an open CT if the load on the power transformer is from
10% to 110% of the rated load. Outside this range an open CT condition is not
even looked for. The search for an open CT starts after 60 seconds (50 seconds in
60 Hz systems) since the bias current enters the 10–110% range. The Open CT
detection feature can also be explicitly deactivated by setting: OpenCTEnable = 0
(Off).
143
If an open CT is detected and the output OPENCT set to 1, then all the differential
functions are blocked, except of the unrestrained (instantaneous) differential. An
alarm signal is also produced after a settable delay (tOCTAlarmDelay) to report to
operational personal for quick remedy actions once the open CT is detected. When
the open CT condition is removed (that is, the previously open CT reconnected),
the functions remain blocked for a specified interval of time, which is also a setting
(tOCTResetDelay). The task of this measure is to prevent an eventual mal-
operation after the reconnection of the previously open CT secondary circuit.
The open CT feature works only during normal loading condition. Thus, the open
CT feature must be automatically disabled for all external faults, big overloads and
inrush conditions.
The open CT algorithm provides detailed information about the location of the
defective CT secondary circuit. The algorithm clearly indicates IED side, CT input
and phase in which open CT condition has been detected. These indications are
provided via the following outputs from Line differential protection function:
1. Output OPENCT provides instant information to indicate that open CT circuit

has been detected
2. Output OPENCTAL provides time delayed alarm that the open CT circuit has
been detected. Time delay is defined by setting parameter tOCTAlarmDelay.
3. Integer output OPENCTIN provides information on the local HMI regarding
which open CT circuit has been detected (1=CT input No 1; 2=CT input No 2)
4. Integer output OPENCTPH provides information on the local HMI regarding
in which phase open CT circuit has been detected (1=Phase L1; 2= Phase L2;
3= Phase L3)
Once the open CT condition is declared, the algorithm stops to search for further
open CT circuits. It waits until the first open CT circuit has been corrected. Note
that once the open CT condition has been detected, it can be automatically reset
within the differential function. It is not possible to externally reset open CT
condition. To reset the open CT circuit alarm automatically, the following
conditions must be fulfilled:
• Bias current is for at least one minute smaller than 110%

• Open CT condition in defective CT circuit has been rectified (for example,
current asymmetry disappears)
• Above two conditions are fulfilled for longer time than defined by the setting
parameter tOCTResetDelay
After the reset, the open CT detection algorithm starts again to search for any other
open CT circuit within the protected zone.
5.2.2.2 Logic diagram
The simplified internal logics, for transformer differential protection are shown in
the following figures.
144
ADM Differential function

Trafo
Data
A/D conversion scaling with CT
Phasor calculation of individual
Open CT logic on W1 side

Instantaneous (sample based) IDL1
Phasors & samples

phase current
Differential current, phase L1
ratio
IDL2
Derive equation to calculate differential currents

Instantaneous (sample based)
Instantaneous (sample based) IDL3

Negative sequence diff current IDNSMAG

& NS current contribution from
A/D conversion scaling with CT
Phasor calculation of individual
individual windings
Open CT logic on W2 side
phase current
IDL1MAG
Fundamental frequency (phasor
based) Diff current, phase L1 &
ratio
phase current contributions from

individual windings
Phasors & samples
IDL2MAG
individual windings
IDL3MAG
individual windings
MAX IBIAS
Settings for Zer. Seq.

Current Reduction
en06000554-3-en.vsd
IEC06000544 V3 EN
Figure 67: Treatment of measured currents within IED for transformer differential function
Figure 67 shows how internal treatment of measured currents is done in case of two-
winding transformer.
The following currents are inputs to the power transformer differential protection
function. They must all be expressed in true power system (primary) A, that is, as
measured.
145
1. Instantaneous values of currents (samples) from HV, and LV sides for two-
winding power transformers, and from the HV, the first LV, and the second
LV sides for three-winding power transformers.
2. Currents from all power transformer sides expressed as fundamental frequency
phasors, with their real, and imaginary parts. These currents are calculated
within the protection function by the fundamental frequency Fourier filters.
3. Negative sequence currents from all power transformer sides expressed as
phasors. These currents are calculated within the protection function by the
symmetrical components module.
The power transformer differential protection:
1. Calculates three fundamental frequency differential currents, and one common

bias current. The zero-sequence component can optionally be eliminated from
each of the three fundamental frequency differential currents, and at the same
time from the common bias current.
2. Calculates three instantaneous differential currents. They are used for
harmonic, and waveform analysis. Instantaneous differential currents are
useful for post-fault analysis using disturbance recording
3. Calculates negative-sequence differential current. Contributions to it from both
(all three) power transformer sides are used by the internal/external fault
discriminator to detect and classify a fault as internal or external.
BLKUNRES
IdUnre a TRIPUNREL1
b>a AND
b
IDL1MAG
IBIAS STL1
AND
BLOCK
BLKRES
TRIPRESL1
AND
OR 1
IDL1
to fault logic
2nd BLK2HL1
Switch on
Harmonic
Wave BLKWAVL1
block
5th BLK5HL1
Harmonic
Cross Block
Cross Block to L2 or L3
from L2 or L3 AND
OR
AND
OpCrossBlock=On
en06000545.vsd
IEC06000545 V1 EN
Figure 68: Transformer differential protection simplified logic diagram for

Phase L1
146
IEC05000167-TIFF V1 EN
Figure 69: Transformer differential protection simplified logic diagram for

external/internal fault discriminator
TRIPRESL1
TRIPRESL2 TRIPRES
OR
TRIPRESL3
TRIPUNREL1
TRIPUNREL2 TRIPUNRE
OR
TRIPUNREL3
TRIP
TRNSSENS OR
TRNSUNR
en05000278.vsd
IEC05000278 V1 EN
Figure 70: Transformer differential protection internal grouping of tripping

signals
147
IEC05000279-TIFF V1 EN
Figure 71: Transformer differential protection internal grouping of logical signals
Logic in figures 68, 69, 70 and 71 can be summarized as follows:
1. The three fundamental frequency differential currents are applied in a phase-

wise manner to two limits. The first limit is the operate-restrain characteristic,
while the other is the high-set unrestrained limit. If the first limit is exceeded, a
start signal START is set. If the unrestrained limit is exceeded, an immediate
unrestrained trip TRIPUNRE and common trip TRIP are issued.
2. If a start signal is issued in a phase, then the harmonic-, and the waveform
block signals are checked. Only a start signal, which is free of all of its
respective block signals, can result in a trip command. If the cross-block logic
scheme is applied, then only if all phases with set start signal are free of their
respective block signals, a restrained trip TRIPRES and common trip TRIP are
issued
3. If a start signal is issued in a phase, and the fault has been classified as
internal, then any eventual block signals are overridden and a unrestrained
negative-sequence trip TRNSUNR and common trip TRIP are issued without
any further delay. This feature is called the unrestrained negative-sequence
protection.
4. The sensitive negative sequence differential protection is independent of any
start signals. It is meant to detect smaller internal faults, such as turn-to-turn
faults, which are often not detected by the traditional differential protection.
The sensitive negative sequence differential protection starts whenever both
contributions to the total negative sequence differential current (that must be
compared by the internal/external fault discriminator) are higher than the value
of the setting IMinNegSeq. If a fault is positively recognized as internal, and
the condition is stable with no interruption for at least one fundamental
frequency cycle the sensitive negative sequence differential protection
TRNSSENS and common trip TRIP are issued. This feature is called the
sensitive negative sequence differential protection.
5. If a start signal is issued in a phase (see signal STL1), even if the fault has
been classified as an external fault, then the instantaneous differential current
148
of that phase (see signal IDL1) is analyzed for the 2nd and the 5th harmonic
contents (see the blocks with the text inside: 2nd Harmonic; Wave block and
5th Harmonic). If there is less harmonic pollution, than allowed by the settings
I2/I1Ratio, and I5/I1Ratio, (then the outputs from the blocks 2nd harmonic and
5th harmonic is 0) then it is assumed that a minor simultaneous internal fault
must have occurred. Only under these conditions a trip command is allowed
(the signal TRIPRESL1 is = 1). The cross-block logic scheme is automatically
applied under such circumstances. (This means that the cross block signals
from the other two phases L2 and L3 is not activated to obtain a trip on the
TRIPRESL1 output signal in figure 68)
6. All start and blocking conditions are available as phase segregated as well as
common (that is three-phase) signals.
IDL1 MAG
a
a>b
I Diff Alarm b
IDL2 MAG tAlarm Delay

a
& IDALARM
a>b t
I Diff Alarm b
IDL3 MAG
a
a>b
I Diff Alarm b
en06000546.vsd
IEC06000546 V1 EN
Figure 72: Differential current alarm logic
149

T2WPDIF
I3PW1CT1* TRIP
I3PW1CT2* TRIPRES
I3PW2CT1* TRIPUNRE
I3PW2CT2* TRNSUNR
TAPOLTC1 TRNSSENS
OLTC1AL START
BLOCK STL1
BLKRES STL2
BLKUNRES STL3
BLKNSUNR BLK2H
BLKNSSEN BLK2HL1
BLK2HL2
BLK2HL3
BLK5H
BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
IDALARM
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
IDNSMAG
IEC06000249 V2 EN
Figure 73: T2WPDIF function block
150
T3WPDIF
I3PW1CT1* TRIP
I3PW1CT2* TRIPRES
I3PW2CT1* TRIPUNRE
I3PW2CT2* TRNSUNR
I3PW3CT1* TRNSSENS
I3PW3CT2* START
TAPOLTC1 STL1
TAPOLTC2 STL2
OLTC1AL STL3
OLTC2AL BLK2H
BLOCK BLK2HL1
BLKRES BLK2HL2
BLKUNRES BLK2HL3
BLKNSUNR BLK5H
BLKNSSEN BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
IDALARM
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
IDNSMAG
IEC06000250 V2 EN
Figure 74: T3WPDIF function block

Table 67: T2WPDIF Input signals
I3PW1CT1 GROUP - Three phase winding primary CT1
SIGNAL
SIGNAL
I3PW2CT1 GROUP - Three phase winding secondary CT1
SIGNAL
SIGNAL
TAPOLTC1 INTEGER 1 Most recent tap position reading on OLTC 1
OLTC1AL BOOLEAN 0 OLTC1 alarm
BLKRES BOOLEAN 0 Block of trip for restrained differential feature
BLKUNRES BOOLEAN 0 Block of trip for unrestrained differential feature
feature
feature
151
Table 68: T2WPDIF Output signals

BLK2H BOOLEAN Common second harmonic block signal from any
phase
BLK2HL1 BOOLEAN Second harmonic block signal, phase L1
BLK5H BOOLEAN Common fifth harmonic block signal from any
phase
BLK5HL1 BOOLEAN Fifth harmonic block signal, phase L1
BLKWAV BOOLEAN Common block signal, waveform criterion, from
any phase
BLKWAVL1 BOOLEAN Block signal, waveform criterion, phase L1
IDALARM BOOLEAN Alarm for sustained diff currents in all three phases
delay ...
IDL1 REAL Value of the instantaneous differential current,
phase L1
phase L2
phase L3
IDL1MAG REAL Magnitude of fundamental freq. diff. current,
phase L1
phase L2
phase L3
IBIAS REAL Magnitude of the bias current, which is common
to all phases
IDNSMAG REAL Magnitude of the negative sequence differential
current
152
Table 69: T3WPDIF Input signals

SIGNAL
SIGNAL
SIGNAL
SIGNAL
I3PW3CT1 GROUP - Three phase winding tertiary CT1
SIGNAL
I3PW3CT2 GROUP - Three phase winding tertiary CT2
SIGNAL
BLKRES BOOLEAN 0 Block of trip for restrained differential feature
BLKUNRES BOOLEAN 0 Block of trip for unrestrained differential feature
feature
feature
Table 70: T3WPDIF Output signals

BLK2H BOOLEAN Common second harmonic block signal from any
phase
BLK5H BOOLEAN Common fifth harmonic block signal from any
phase
153

BLKWAV BOOLEAN Common block signal, waveform criterion, from
any phase
IDALARM BOOLEAN Alarm for sustained diff currents in all three phases
delay ...
phase L1
phase L2
phase L3
phase L1
phase L2
phase L3
IBIAS REAL Magnitude of the bias current, which is common
to all phases
IDNSMAG REAL Magnitude of the negative sequence differential
current

Table 71: T2WPDIF Group settings (basic)
On
SOTFMode Off - - On Operation mode for switch onto fault
On
tAlarmDelay 0.000 - 60.000 s 0.001 10.000 Time delay for diff currents alarm level
IDiffAlarm 0.05 - 1.00 IB 0.01 0.20 Dif. cur. alarm, multiple of base curr,
usually W1 curr.
IdMin 0.05 - 0.60 IB 0.01 0.30 Section1 sensitivity, multi. of base curr,
usually W1 curr.
IdUnre 1.00 - 50.00 IB 0.01 10.00 Unrestr. prot. limit, multiple of Winding 1
rated current
154

CrossBlockEn Off - - On Operation Off/On for cross-block logic
On between phases
NegSeqDiffEn Off - - On Operation Off/On for neg. seq.
On differential protections
IMinNegSeq 0.02 - 0.20 IB 0.01 0.04 Neg. seq. curr. must be higher than this
level to be used
NegSeqROA 30.0 - 120.0 Deg 0.1 60.0 Operate Angle for int. / ext. neg. seq.
fault discriminator
Table 72: T2WPDIF Group settings (advanced)

EndSection1 0.20 - 1.50 IB 0.01 1.25 End of section 1, multiple of Winding 1
rated current
EndSection2 1.00 - 10.00 IB 0.01 3.00 End of section 2, multiple of Winding 1
rated current
I2/I1Ratio 5.0 - 100.0 % 0.1 15.0 Max. ratio of 2nd harm. to fundamental
harm dif. curr. in %
I5/I1Ratio 5.0 - 100.0 % 0.1 25.0 Max. ratio of 5th harm. to fundamental
OpenCTEnable Off - - Off Open CT detection feature. Open
On CTEnable Off/On
tOCTAlarmDelay 0.100 - 10.000 s 0.001 3.000 Open CT: time in s to alarm after an
open CT is detected
Table 73: T2WPDIF Non group settings (basic)

RatedVoltageW1 0.05 - 2000.00 kV 0.05 400.00 Rated voltage of transformer winding 1
(HV winding) in kV
in kV
RatedCurrentW1 1 - 99999 A 1 577 Rated current of transformer winding 1
(HV winding) in A
RatedCurrentW2 1 - 99999 A 1 1000 Rated current of transformer winding 2 in
A
ConnectTypeW1 WYE (Y) - - WYE (Y) Connection type of winding 1: Y-wye or D-
Delta (D) delta
Delta (D) delta
155

ClockNumberW2 0 [0 deg] - - 0 [0 deg] Phase displacement between W2 &
1 [30 deg lag] W1=HV winding, hour notation
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
ZSCurrSubtrW1 Off - - On Enable zer. seq. current subtraction for
On W1 side, On / Off
TconfigForW1 No - - No Two CT inputs (T-config.) for winding 1,
Yes YES / NO
CT1RatingW1 1 - 99999 A 1 3000 CT primary rating in A, T-branch 1, on
transf. W1 side
CT2RatingW1 1 - 99999 A 1 3000 CT primary in A, T-branch 2, on transf.
W1 side
Yes YES / NO
transf. W2 side
transf. W2 side
LocationOLTC1 Not Used - - Not Used Transformer winding where OLTC1 is
Winding 1 (W1) located
Winding 2 (W2)
LowTapPosOLTC1 0 - 10 - 1 1 OLTC1 lowest tap position designation
(e.g. 1)
RatedTapOLTC1 1 - 100 - 1 6 OLTC1 rated tap/mid-tap position
designation (e.g. 6)
HighTapPsOLTC1 1 - 100 - 1 11 OLTC1 highest tap position designation
(e.g. 11)
TapHighVoltTC1 1 - 100 - 1 1 OLTC1 end-tap position with winding
highest no-load voltage
StepSizeOLTC1 0.01 - 30.00 % 0.01 1.00 Voltage change per OLTC1 step in
percent of rated voltage
Table 74: T3WPDIF Group settings (basic)

On
SOTFMode Off - - On Operation mode for switch onto fault
On feature
tAlarmDelay 0.000 - 60.000 s 0.001 10.000 Time delay for diff currents alarm level
156

IDiffAlarm 0.05 - 1.00 IB 0.01 0.20 Dif. cur. alarm, multiple of base curr,
usually W1 curr.
IdMin 0.05 - 0.60 IB 0.01 0.30 Section1 sensitivity, multi. of base curr,
usually W1 curr.
IdUnre 1.00 - 50.00 IB 0.01 10.00 Unrestr. prot. limit, multi. of base curr.
usually W1 curr.
CrossBlockEn Off - - On Operation Off/On for cross-block logic
On between phases
NegSeqDiffEn Off - - On Operation Off/On for neg. seq.
On differential protections
IMinNegSeq 0.02 - 0.20 IB 0.01 0.04 Neg. seq. curr. limit, mult. of base curr,
usually W1 curr.
NegSeqROA 30.0 - 120.0 Deg 0.1 60.0 Operate Angle for int. / ext. neg. seq.
fault discriminator
Table 75: T3WPDIF Group settings (advanced)

EndSection1 0.20 - 1.50 IB 0.01 1.25 End of section 1, multi. of base current,
usually W1 curr.
EndSection2 1.00 - 10.00 IB 0.01 3.00 End of section 2, multi. of base current,
usually W1 curr.
I2/I1Ratio 5.0 - 100.0 % 0.1 15.0 Max. ratio of 2nd harm. to fundamental
I5/I1Ratio 5.0 - 100.0 % 0.1 25.0 Max. ratio of 5th harm. to fundamental
OpenCTEnable Off - - Off Open CT detection feature. Open
On CTEnable Off/On
tOCTAlarmDelay 0.100 - 10.000 s 0.001 3.000 Open CT: time in s to alarm after an
open CT is detected
Table 76: T3WPDIF Non group settings (basic)

(HV winding) in kV
in kV
in kV
157

RatedCurrentW1 1 - 99999 A 1 577 Rated current of transformer winding 1
(HV winding) in A
A
A
Delta (D) delta
Delta (D) delta
ConnectTypeW3 WYE (Y) - - Delta (D) Connection type of winding 3: Y-wye or D-
Delta (D) delta
ClockNumberW2 0 [0 deg] - - 0 [0 deg] Phase displacement between W2 &
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
ClockNumberW3 0 [0 deg] - - 5 [150 deg lag] Phase displacement between W3 &
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
Yes YES / NO
transf. W1 side
CT2RatingW1 1 - 99999 A 1 3000 CT primary in A, T-branch 2, on transf.
W1 side
Yes YES / NO
transf. W2 side
transf. W2 side
158

Yes YES / NO
transf. W3 side
transf. W3 side
Winding 2 (W2)
Winding 3 (W3)
(e.g. 1)
(e.g. 11)
Winding 2 (W2)
Winding 3 (W3)
(e.g. 1)
(e.g. 11)

Table 77: T2WPDIF, T3WPDIF technical data
Operating characteristic Adaptable ± 1.0% of Ir for I < Ir
± 1.0% of Ir for I > Ir
Reset ratio >95% -
Unrestrained differential current limit (100-5000)% ofIBase ± 1.0% of set value
on high voltage winding
Base sensitivity function (10-60)% of IBase ± 1.0% of Ir
Second harmonic blocking (5.0-100.0)% of ± 2.0% of Ir
fundamental differential
current
159

Fifth harmonic blocking (5.0-100.0)% of ± 5.0% of Ir
fundamental differential
current
Connection type for each of the windings Y or D -
Phase displacement between high voltage 0–11 -
winding, W1 and each of the windings, W2
and W3. Hour notation
Operate time, restrained function 25 ms typically at 0 to -
2 x Ib
Reset time, restrained function 20 ms typically at 2 to -
0 x Ib
Operate time, unrestrained function 12 ms typically at 0 to -
5 x Ib
Reset time, unrestrained function 25 ms typically at 5 to -
0 x Ib
Critical impulse time 2 ms typically at 0 to 5 -
x Ib
5.3 Restricted earth fault protection, low impedance

REFPDIF

Restricted earth fault protection, low REFPDIF 87N
impedance
IdN/I
SYMBOL-AA V1 EN
5.3.1 Introduction
Restricted earth-fault protection, low-impedance function (REFPDIF) can be used
on all directly or low-impedance earthed windings. The REFPDIF function
provides high sensitivity (down to 5%) and high speed tripping as it measures each
winding individually and thus does not need inrush stabilization.
The low-impedance function is a percentage biased function with an additional

zero sequence current directional comparison criterion. This gives excellent
sensitivity and stability during through faults. The function allows the use of
different CT ratios and magnetizing characteristics on the phase and neutral CT
cores and mixing with other functions and protection IEDs on the same cores.
160
5.3.2.1 Fundamental principles of the restricted earthfault protection
Restricted earth-fault protection, low impedance function (REFPDIF) must detect

earth faults on earthed power transformer windings. REFPDIF is a unit protection
of differential type. Since REFPDIF is based on the zero sequence currents, which
theoretically only exist in case of an earth-fault, the REFPDIF can be made very
sensitive; regardless of normal load currents. It is the fastest protection a power
transformer winding can have. It must be borne in mind, however, that the high
sensitivity, and the high speed, tend to make such a protection instable, and special
measures must be taken to make it insensitive to conditions, for which it should not
operate, for example heavy through faults of phase-to-phase type, or heavy external
earth faults.
REFPDIF is of “low impedance” type. All three phase power transformer terminal
currents, and the power transformer neutral point current, must be fed separately to
REFPDIF . These input currents are then conditioned within REFPDIF by
mathematical tools.
Fundamental frequency components of all currents are extracted from all input
currents, while other eventual zero sequence components (for example, the 3rd
harmonic currents) are fully suppressed. Then the residual current phasor is
constructed from the three line current phasors. This zero sequence current phasor
is then vectorially added to the neutral current, in order to obtain differential current.
The following facts may be observed from the figure 75 and the figure 76 (where
the three-phase line CTs are lumped into a single 3Io current, for the sake of
simplicity).
161
zone of protection
s Izs1 Ia = 0
o L1 L1
u Izs1 Ib = 0
L2 L2
r
c Izs1 Ic = 0
L3 L3
e
Uzs Current in the neutral (IN)
3Io=3I zs1 IN = -3Izs1 IN serves as a directional
reference because it has
the same direction for both
internal and external faults.
Uzs voltage is max. REFPDIF is a current polarized

at the earth-fault For external fault function
ROA RCA (Relay Characteristic Angle)
RCA = 0 deg.
3I0
REFPDIF is permanently set to
MTA
IN operate for internal earth-faults.
Reference is
ROA REFPDIF should never operate
neutral current
for any faults external to
the protected zone.
Restrain for Operate for Currents 3Io and IN are theoretically
external fault internal fault 180o out of phase for any external
earth-fault.
IEC09000107 V1 EN
Figure 75: Currents at an external earth-fault
162
power system
contribution to
fault current zone of protection
s Izs2 Izs1 Ia = 0
o L1 L1
u Izs2 Izs1
L2 Ib = 0 L2
r
c Izs2 Izs1 Ic = 0
e L3 L3
Ifault Current in the neutral (IN)

Uz serves as a directional
3Io = -3Izs2 IN
s reference because it has
the same direction for both
IN = - 3Izs1 internal and external faults.
Return path for 3Izs2 Return path for 3Izs1
currents 3Io and IN are approximately

For internal fault in phase for an internal earth-fault.
ROA 3I0
MTA
IN
Reference is
ROA
neutral current
Restrain for Operate for

external fault internal fault
IEC09000108 V1 EN
Figure 76: Currents at an internal earth fault
1. For an external earth fault, (figure 75) the residual current 3Io and the neutral
conductor current IN have equal magnitude, but they are 180 degree out-of-
phase due to internal CT reference directions used in the IED. This is easy to
understand, as both CTs ideally measure exactly the same component of the
earth fault current.
2. For an internal fault, the total earth-fault current is composed generally of two
zero sequence components. One zero sequence component (that is, 3IZS1)
flows towards the power transformer neutral point and into the earth, while the
other zero sequence component (that is, 3IZS2) flows out into the connected
power system. These two primary currents can be expected to be of
approximately opposite directions (about the same zero sequence impedance
angle is assumed on both sides of the earth-fault). However, on the secondary
CT sides they will be approximately in phase due to internal CT reference
directions used in the IED. The magnitudes of the two components may be
different, dependent on the magnitudes of zero sequence impedances of both
sides. No current can flow towards the power system, if the only point where
the system is earthed, is at the protected power transformer. Likewise, no
current can flow into the power system, if the winding is not connected to the
163
power system (circuit breaker open and power transformer energized from the
other side).
3. For both internal and external earth faults, the current in the neutral connection
IN has always the same direction, that is, towards the earth.
4. The two measured zero sequence current are 3Io and IN. The vectorial sum
between them is the REFPDIF differential current, which is equal to Idiff = IN
+3Io.
Since REFPDIF is a differential protection where the line zero sequence (residual)
current is constructed from 3 line (terminal) currents, a bias quantity must give
stability against false operations due to high through fault currents. An operate -
bias characteristic (only one) has been devised to the purpose.
It is not only external earth faults that REFPDIF should be stable against, but also
heavy phase-to-phase faults, not including earth. These faults may also give rise to
false zero sequence currents due to saturated line CTs. Such faults, however,
produce no neutral current, and can thus be eliminated as a source of danger, at
least during the fault.
As an additional measure against unwanted operation, a directional check is made

in agreement with the above points 1, and 2. An operation is only allowed if
currents 3Io and IN (as shown in figure 75 and the figure 76) are both within the
operating region. By taking a smaller ROA, REFPDIF can be made more stable
under heavy external fault conditions, as well as under the complex conditions,
when external faults are cleared by other protections.
5.3.2.2 Restricted earth-fault protection, low impedance as a differential

protection
Restricted earth-fault protection, low impedance (REFPDIF) is a protection of

differential type, a unit protection, whose settings are independent of any other
protection. Compared to the transformer differential protection it has some
advantages. It is simpler, as no current phase correction and magnitude correction
are needed, not even in the case of an eventual On-Load Tap-Changer (OLTC).
REFPDIF is not sensitive to inrush and overexcitation currents. The only danger
left is an eventual current transformer saturation.
REFPDIF has only one operate-bias characteristic, which is described in the table
78, and shown in the figure 77.
Table 78: Data of the operate - bias characteristic of REFPDIF

Default sensitivity Max. base Min. base sensitivity End of zone First slope Second
Idmin (zone 1) sensitivity Idmin Idmin (zone 1) 1 slope
(zone 1)
% IBase % IBase % IBase % IBase % %
30 4 100 125 70 100
164
As a differential protection, REFPDIF calculates a differential current and a bias

current. In case of internal earth-faults, the differential current is theoretically equal
to the total earth-fault current. The bias current is supposed to give stability to
REFPDIF . The bias current is a measure of how high the currents are, or better, a
measure of how difficult the conditions are under which the CTs operate. The
higher the bias, the more difficult conditions can be suspected, and the more likely
that the calculated differential current has a component of a false current, primarily
due to CT saturation. This “law” is formulated by the operate-bias characteristic.
This characteristic divides the Idiff - Ibias plane into two parts. The part above the
operate - bias characteristic is the so called operate area, while that below is the
block area, see the figure 77.
operate current in pu
4 operate
Base Sensitivity Idmin

3
*************************************
Range : 5 % to 50 % rated current
Step : 1 % transformer rated current
2
zone 1 zone 2 second slope
1
minimum base sensitivity 50 %
default base sensitivity 30 % first slope block
maximum base sensitivity 5 %
0 1 2 3 4 5 6
1.25 pu bias current in per unit
IEC98000017 V3 EN
Figure 77: Operate - bias characteristic of the Restricted earth-fault

protection, low impedance REFPDIF
5.3.2.3 Calculation of differential current and bias current
The differential current, (= operate current), as a fundamental frequency phasor, is

calculated as (with designations as in the figure 75 and the figure 76)
Idiff = IN + 3 Io
where:
IN current in the power transformer neutral as a fundamental frequency phasor,
3Io residual current of the power transformer line (terminal) currents as a phasor.
165
If there are two three-phase CT inputs on the HV winding side for REFPDIF (such
as in breaker-and-a-half configurations), then their respective residual currents are
added within REFPDIF function so that:
I3PW1 = I3PW1CT1 + I3PW1CT2
where the signals are defined in the input and output signal tables for REFPDIF.
The bias current is a measure (expressed as a current in Amperes) of how difficult

the conditions are under which the instrument current transformers operate.
Dependent on the magnitude of the bias current, the corresponding zone (section)
of the operate - bias characteristic is applied, when deciding whether “to trip, or
“not to trip”. In general, the higher the bias current, the higher the differential
current required to produce a trip.
As the bias current the highest current of all separate input currents to REFPDIF,
that is, of current in phase L1, phase L2, phase L3, and the current in the neutral
point (designated as IN in the figure 75 and in the figure 76).
If there are 2 feeders included in the zone of protection of REFPDIF, then the
respective bias current is found as the relatively highest of the following currents:
1
current[1] = max (I3PW1CT1) ×
CTFactorPri1
1
CTFactorPri2
1
CTFactorSec1
1
CTFactorSec2
current[5] = IN
The bias current is thus generally equal to none of the input currents. If all primary
ratings of the CTs were equal to IBase, then the bias current would be equal to the
highest current in Amperes. IBase shall be set equal to the rated current of the
protected winding where REFPDIF function is applied.
166
5.3.2.4 Detection of external earth faults
External faults are more common than internal earth faults for which the restricted
earth fault protection should operate. It is important that the restricted earth fault
protection remains stable during heavy external earth and phase-to-phase faults,
and also when such a heavy external fault is cleared by some other protection such
as overcurrent, or earth-fault protection, and so on. The conditions during a heavy
external fault, and particularly immediately after the clearing of such a fault may be
complex. The circuit breaker’s poles may not open exactly at the same moment,
some of the CTs may still be highly saturated, and so on.
The detection of external earth faults is based on the fact that for such a fault a high
neutral current appears first, while a false differential current only appears if and
when one, or more, current transformers saturate.
An external earth fault is thus assumed to have occurred when a high neutral
current suddenly appears, while at the same time the differential current Idiff
remains low, at least for a while. This condition must be detected before a trip
request is placed within REFPDIF. Any search for external fault is aborted if a trip
request has been placed. A condition for a successful detection is that it takes not
less than 4ms for the first CT to saturate.
For an internal earth fault, a true differential current develops immediately, while
for an external fault it only develops if a CT saturates. If a trip request comes first,
before an external fault could be positively established, then it must be an internal
fault.
If an external earth fault has been detected, then the REFPDIF is temporarily
desensitized.
Directional criterion
The directional criterion is applied in order to positively distinguish between
internal- and external earth faults. This check is an additional criterion, which
should prevent malfunctions at heavy external earth faults, and during the
disconnection of such faults by other protections. Earth faults on lines connecting
the power transformer occur much more often than earth faults on a power
transformer winding. It is important therefore that the Restricted earth faults
protection, low impedance (REFPDIF,) must remain secure during an external
fault, and immediately after the fault has been cleared by some other protection.
For an external earth faults with no CT saturation, the residual current in the lines
(3Io) and the neutral current (IN in the figure 75) are theoretically equal in
magnitude and are 180 degree out-of-phase. It is the current in the neutral (IN)
which serves as a directional reference because it flows for all earth faults, and it
has the same direction for all earth faults, both external and internal. The
directional criterion in REFPDIF protection makes it a current-polarized IED.
If one or more CTs saturate, then the measured currents 3Io and IN may no more be
equal, nor will their positions in the complex plane be exactly 180 degree apart.
There is a risk that the resulting false differential current Idiff enters the operate
167
area when clearing the external fault. If this happens, a directional test may prevent
a malfunction.
A directional check is only executed if:
1. a trip request signal has been issued, REFPDIF function START signal set to 1)
2. if the residual current in lines (3Io) is at least 3% of the IBase current.
If a directional check is either unreliable or not possible to do, due to too small
currents, then the direction is cancelled as a condition for an eventual trip.
If a directional check is executed, the REFPDIF protection operation is only

allowed if currents 3Io and IN (as seen in figure 75 and figure 76) are both within
the operating region.
RCA = 0 degrees = constant; where RCA stands for Relay Characteristic Angle
ROA = 60 to 90 degrees; where ROA stands for Relay Operate Angle.
RCA determines a direction MTA (“Maximum Torque Angle”) where the line
residual current 3Io must lie for an internal earth fault, while ROA sets a tolerance
margin.
Second harmonic analysis

At energizing of a reactor a false differential current may appear in Restricted earth-
fault protection, low impedance function (REFPDIF,) even though it does not exist
in the primary net. The phase CT’s may saturate due to a high dc-component with
long duration where as the current through the neutral CT does not have either the
same dc-component or the same amplitude and the risk for saturation in this CT is
not as high. The appearing differential current as a result of the saturation may be
so high that it reaches the operate characteristic. A calculation of the content of 2nd
harmonic in the neutral current is made when neutral current, residual current and
bias current are within some windows and some timing criteria are fulfilled. If the
ratio between second and fundamental harmonic exceeds 60%, REFPDIF must be
blocked.
5.3.2.5 Algorithm of the restricted earth fault protection
1. Check if current in the neutral Ineutral (IN) is less than 50% of the base
sensitivity Idmin. If yes, only service values are calculated, then REFPDIF
algorithm is exited.
2. If current in the Ineutral (IN) is more than 50% of Idmin, then determine the
bias current Ibias.
3. Determine the differential (operate) current Idiff as a phasor, and calculate its
magnitude.
4. Check if the point P(Ibias, Idiff) is above the operate - bias characteristic. If
yes, increment the trip request counter by 1. If the point P(Ibias, Idiff) is found
to be below the operate - bias characteristic, then the trip request counter is
reset to 0.
168
5. If the trip request counter is still 0, search for an eventual heavy external earth
fault. The search is only made if the neutral current is at least 50% of the IBase
current. If an external earth fault has been detected, a flag is set which remains
set until the external fault has been cleared. The external fault flag is reset to 0
when Ineutral falls below 50% of the base sensitivity Idmin. Any search for
external fault is aborted if trip request counter is more than 0.
6. For as long as the external fault persists an additional temporary trip condition
is introduced. That means that REFPDIF is temporarily desensitized.
7. If point P(Ibias, Idiff) is found to be above the operate - bias characteristic), so
that trip request counter is becomes more than 0, a directional check can be
made. The directional check is made only if Iresidual (3Io) is more than 3% of
the IBase current. If the result of the check means “external fault”, then the
internal trip request is reset. If the directional check cannot be executed, then
direction is no longer a condition for a trip.
8. When neutral current, residual current and bias current are within some
windows and some timing criteria are fulfilled, the ratio of 2nd to fundamental
tone is calculated. If it is found to be above 60% the trip request counter is
reset and TRIP remains zero.
9. Finally, a check is made if the trip request counter is equal to, or higher than 2.
If it is, and that at the same instance of time tREFtrip, the actual bias current at
this instance of time tREFtrip is at least 50% of the highest bias current Ibiasmax
(Ibiasmax is the highest recording of any of the three phase currents measured
during the disturbance) then REFPDIF sets output TRIP to 1. If the counter is
less than 2, TRIP signal remains 0.

REFPDIF
I3P* TRIP
I3PW1CT1* START
I3PW1CT2* DIROK
I3PW2CT1* BLK2H
I3PW2CT2* IRES
BLOCK IN
IBIAS
IDIFF
ANGLE
I2RATIO
IEC06000251 V2 EN
Figure 78: REFPDIF function block
169

Table 79: REFPDIF Input signals
I3P GROUP - Group signal for neutral current input
SIGNAL
I3PW1CT1 GROUP - Group signal for primary CT1 current input
SIGNAL
I3PW1CT2 GROUP - Group signal for primary CT2 current input
SIGNAL
I3PW2CT1 GROUP - Group signal for secondary CT1 current input
SIGNAL
I3PW2CT2 GROUP - Group signal for secondary CT2 current input
SIGNAL
Table 80: REFPDIF Output signals

TRIP BOOLEAN Trip by restricted earth fault protection function
START BOOLEAN Start by restricted earth fault protection function
DIROK BOOLEAN Directional Criteria has operated for internal fault
BLK2H BOOLEAN Block due to 2-nd harmonic
IRES REAL Magnitude of fund. freq. residual current
IN REAL Magnitude of fund. freq. neutral current
IBIAS REAL Magnitude of the bias current
IDIFF REAL Magnitude of fund. freq. differential current
ANGLE REAL Direction angle from zerosequence feature
I2RATIO REAL Second harmonic ratio

Table 81: REFPDIF Group settings (basic)
On
IBase 1 - 99999 A 1 3000 Base current
IdMin 4.0 - 100.0 %IB 0.1 10.0 Maximum sensitivity in % of Ibase
CTFactorPri1 1.0 - 10.0 - 0.1 1.0 CT factor for HV side CT1 (CT1rated/
HVrated current)
CTFactorPri2 1.0 - 10.0 - 0.1 1.0 CT factor for HV side CT2 (CT2rated/
HVrated current)
CTFactorSec1 1.0 - 10.0 - 0.1 1.0 CT factor for MV side CT1 (CT1rated/
MVrated current)
CTFactorSec2 1.0 - 10.0 - 0.1 1.0 CT factor for MV side CT2 (CT2rated/
MVrated current)
170
Table 82: REFPDIF Group settings (advanced)

ROA 60 - 90 Deg 1 60 Relay operate angle for zero sequence
directional feature

Table 83: REFPDIF technical data
Operate characteristic Adaptable ± 1.0% of Ir for I < IBase
± 1.0% of I for I > IBase
Reset ratio >95% -
Base sensitivity function (4.0-100.0)% of IBase ± 1.0% of Ir
Directional characteristic Fixed 180 degrees or ± 60 to ± ± 2.0 degree

90 degrees
Operate time, trip function 20 ms typically at 0 to 10 x IdMin -
Reset time, trip function 25 ms typically at 10 to 0 x IdMin -
Second harmonic blocking (5.0-100.0)% of fundamental ± 2.0% of IrBase
5.4 1Ph High impedance differential protection HZPDIF
5.4.1 Identification
IEC 61850 IEC 60617 ANSI/IEEE C37.2
Function description
1Ph High impedance differential Id

HZPDIF 87
protection
SYMBOL-CC V2 EN
5.4.2 Introduction
The 1Ph High impedance differential protection (HZPDIF) function can be used
when the involved CT cores have the same turns ratio and similar magnetizing
characteristics. It utilizes an external CT current summation by wiring, a series
resistor, and a voltage dependent resistor which are mounted externally connected
to the IED.
HZPDIF can be used to protect generator stator windings, tee-feeders or busbars.

Six single phase function blocks are available to allow application for two three-
phase zones busbar protection.
171

The 1Ph High impedance differential protection (HZPDIF) function is based on
one current input with external stabilizing resistors and voltage dependent resistors.
Three functions can be used to provide a three phase differential protection
function. The stabilizing resistor value is calculated from the IED function
operating value UR calculated to achieve through fault stability. The supplied
stabilizing resistor has a link to allow setting of the correct resistance value .
See the application manual for operating voltage and sensitivity calculation.
The logic diagram shows the operation principles for the 1Ph High impedance
differential protection function HZPDIF, see figure 79. It is a simple one step IED
function with an additional lower alarm level. By activating inputs, the HZPDIF
function can either be blocked completely, or only the trip output.
IEC05000301 V1 EN
Figure 79: Logic diagram for 1Ph High impedance differential protection
HZPDIF

HZPDIF
ISI* TRIP
BLOCK ALARM
BLKTR MEASVOLT
IEC05000363 V2 EN
Figure 80: HZPDIF function block
172

Table 84: HZPDIF Input signals
ISI GROUP - Group signal for current input
SIGNAL
BLKTR BOOLEAN 0 Block of trip
Table 85: HZPDIF Output signals

TRIP BOOLEAN Trip signal
ALARM BOOLEAN Alarm signal
MEASVOLT REAL Measured RMS voltage on CT secondary side

Table 86: HZPDIF Group settings (basic)
On
U>Alarm 2 - 500 V 1 10 Alarm voltage level in volts on CT
secondary side
tAlarm 0.000 - 60.000 s 0.001 5.000 Time delay to activate alarm
U>Trip 5 - 900 V 1 100 Operate voltage level in volts on CT
secondary side
SeriesResistor 10 - 20000 ohm 1 250 Value of series resistor in Ohms

Table 87: HZPDIF technical data
Operate voltage (20-400) V ± 1.0% of Ir
I=U/R
Reset ratio >95% -
Maximum U>Trip2/series resistor ≤200 W -
continuous voltage
Operate time 10 ms typically at 0 to 10 x Ud -
Reset time 90 ms typically at 10 to 0 x Ud -
Critical impulse time 2 ms typically at 0 to 10 x Ud -
173
174
Impedance protection
Section 6 Impedance protection
About this chapter

This chapter describes distance protection and associated functions. It includes
function blocks, logic diagrams and data tables with information about distance
protection, automatic switch onto fault, weak end in-feed and other associated
functions.
6.1 Full-scheme distance measuring, Mho

characteristic ZMHPDIS
Function description IEC 61850 IEC 60617 identification ANSI/IEEE

identification C37.2 device
number
Full-scheme distance protection, mho ZMHPDIS 21
characteristic
S00346 V1 EN
6.1.1 Introduction
The numerical mho line distance protection is a, up to four zone full scheme
protection for back-up detection of short circuit and earth faults. The four zones
have fully independent measuring and settings, which gives high flexibility for all
types of lines.
The function can be used as under impedance back-up protection for transformers
and generators.
6.1.2.1 Full scheme measurement
The execution of the different fault loops within the IED are of full scheme type,
which means that each fault loop for phase-to-earth faults and phase-to-phase faults
are executed in parallel.
175
The use of full scheme technique gives faster operation time compared to switched
schemes which mostly uses a start element to select correct voltages and current
depending on fault type. So each distance protection zone performs like one
independent distance protection function with six measuring elements.
6.1.2.2 Impedance characteristic
The distance function consists of four instances. Each instance can be selected to
be either forward or reverse with positive sequence polarized mho characteristic
alternatively self polarized offset mho characteristics with reverse offset. The
operating characteristic is in accordance to figure 81.
jx
Mho, zone4
Mho, zone3
Zs=0
Mho, zone2
R
Mho, zone1
Zs=Z1
R Zs=2Z1
IEC11000223 V1 EN
Figure 81: Mho characteristic and the source impedance influence on the mho characteristic
The mho characteristic has a dynamic expansion due to the source impedance.
Instead of crossing the origin as for the mho to the left of figure 81, which is only
valid where the source impedance is zero, the crossing point is moved to the
coordinates of the negative source impedance given an expansion of the circle
shown to the right of figure 81.
The polarization quantities used for the mho circle are 100% memorized positive
sequence voltages. This will give a somewhat less dynamic expansion of the mho
circle during faults. However, if the source impedance is high, the dynamic
expansion of the mho circle might lower the security of the function too much with
high loading and mild power swing conditions.
The mho distance element has a load encroachment function which cuts off a
section of the characteristic when enabled. The function is enabled by setting the
176
setting parameter LoadEnchMode to On. Enabling of the load encroachment

function increases the possibility to detect high resistive faults without interfering
with the load impedance. The algorithm for the load encroachment is located in the
Faulty phase identification with load encroachment for mho function FMPSPDIS,
where also the relevant settings can be found. Information about the load
encroachment from FMPSPDIS to the zone measurement is given in binary format
to the input signal LDCND.
6.1.2.3 Basic operation characteristics
Each impedance zone can be switched On and Off by the setting parameter
Operation.
Each zone can also be set to Non-directional, Forward or Reverse by setting the
parameter DirMode.
The operation for phase-to-earth and phase-to-phase fault can be individually

switched On and Off by the setting parameter OpModePE and OpModePP.
For critical applications such as for lines with high SIRs as well as CVTs, it is
possible to improve the security by setting the parameter ReachMode to
Underreach. In this mode the reach for faults close to the zone reach is reduced by
20% and the filtering is also introduced to increase the accuracy in the measuring.
If the ReachMode is set to Overreach no reduction of the reach is introduced and
no extra filtering introduced. The latter setting is recommended for overreaching
pilot zone, zone 2 or zone 3 elements and reverse zone where overreaching on
transients is not a major issue either because of less likelihood of overreach with
higher settings or the fact that these elements do not initiate tripping unconditionally.
The offset mho characteristic can be set in Non-directional, Forward or Reverse by

the setting parameter OffsetMhoDir. When Forward or Reverse is selected a
directional line is introduced. Information about the directional line is given from
the directional element and given to the measuring element as binary coded signal
to the input DIRCND.
The zone reach for phase-to-earth fault and phase-to-phase fault is set individually
in polar coordinates.
The impedance is set by the parameters ZPE and ZPP and the corresponding
arguments by the parameters ZAngPE and ZAngPP.
Compensation for earth-return path for faults involving earth is done by setting the
parameter KNMag and KNAng where KNMag is the magnitude of the earth-return
path and KNAng is the difference of angles between KNMag and ZPE.
Z0-Z1
KNMag =
3 × Z1
177
KNAng = arg
( Z 0 - Z1
3 × Z1
)
where
Z0 is the complex zero sequence impedance of the line in Ω/phase
Z1 is the complex positive sequence impedance of the line in Ω/phase
The phase-to-earth and phase-to-phase measuring loops can be time delayed

individually by setting the parameter tPE and tPP respectively. To release the time
delay, the operation mode for the timers, OpModetPE and OpModetPP, has to be
set to On. This is also the case for instantaneous operation.
The function can be blocked in the following ways:
• activating of input BLOCK blocks the whole function

• activating of the input BLKZ (fuse failure) blocks all output signals
• activating of the input BLKZMTD blocks the delta based algorithm
• activating of the input BLKHSIR blocks the instantaneous part of the
algorithm for high SIR values
• activating of the input BLKTRIP blocks all output signals
• activating the input BLKPE blocks the phase-to-earth fault loop outputs
• activating the input BLKPP blocks the phase-to-phase fault loop outputs
The activation of input signal BLKZ can be made by external fuse failure function
or from the loss of voltage check in the Mho supervision logic (ZSMGAPC). In
both cases the output BLKZ in the Mho supervision logic shall be connected to the
input BLKZ in the Mho distance function block (ZMHPDIS)
The input signal BLKZMTD is activated during some ms after fault has been
detected by ZSMGAPC to avoid unwanted operations due to transients. It shall be
connected to the BLKZMTD output signal of ZSMGAPC function.
At SIR values >10, the use of electronic CVT might cause overreach due to the built-
in resonance circuit in the CVT, which reduce the secondary voltage for a while.
The input BLKHSIR shall be connected to the output signal HSIR on ZSMGAPC
for increasing of the filtering and high SIR values. This is valid only when
permissive underreach scheme is selected by setting ReachMode=Underreach.
6.1.2.4 Theory of operation
The mho algorithm is based on the phase comparison of a operating phasor and a
polarizing phasor. When the operating phasor leads the reference polarizing phasor
by more than 90 degrees, the function operates and gives a trip output.
178
Phase-to-phase fault
Mho
The plain mho circle has the characteristic as in figure 82. The condition for
deriving the angle β is according to equation 38.
b = arg(U L1 L 2 - I L1 L 2 × ZPP ) - arg(U pol )

where
U L1L2 is the voltage vector difference between phases L1 and L2

EQUATION1790 V2
EN
I L1L2 is the current vector difference between phases L1 and L2

EQUATION1791 V2
EN
ZPP is the positive sequence impedance setting for phase-to-phase fault

Upol is the polarizing voltage
The polarized voltage consists of 100% memorized positive sequence voltage

(UL1L2 for phase L1 to L2 fault). The memorized voltage will prevent collapse of
the mho circle for close in faults.
Operation occurs if 90≤β≤270
179
IL1L2·X
Ucomp = UL1L2 - IL1L2 • ZPP
IL1L2 • ZPP
ß
Upol
UL1L2
IL1L2·R
en07000109.vsd
IEC07000109 V1 EN
Figure 82: Simplified mho characteristic and vector diagram for phase L1-to-
L2 fault
Offset Mho
The characteristic for offset mho is a circle where two points on the circle are the
setting parameters ZPP and ZRevPP. The vector ZPP in the impedance plane has
the settable angle AngZPP and the angle for ZRevPP is AngZPP+180°.
The condition for operation at phase-to-phase fault is that the angle β between the
two compensated voltages Ucomp1 and Ucomp2 is greater than or equal to 90°
(figure 83). The angle will be 90° for fault location on the boundary of the circle.
The angle β for L1-to-L2 fault can be defined according to equation 39.
æ U -IL1L2 × ZPP ö
b = arg ç ÷
è U-(-IL1L2 × ZRevPP) ø
where
U is the UL1L2 voltage

EQUATION1800 V1 EN
ZRevPP is the positive sequence impedance setting for phase-to-phase fault in reverse direction
180
IL1L2jX
Ucomp1 = UL1L2 - IL1L2 • ZPP

IL1L2 • ZPP
U
Ucomp2 = U = IF•ZF=UL1L2
IL1L2R
- IL1L2 • Z RevPP
en07000110.vsd
IEC07000110 V1 EN
Figure 83: Simplified offset mho characteristic and voltage vectors for phase
L1-to-L2 fault.
Operation occurs if 90≤β≤270.
Offset mho, forward direction

When forward direction has been selected for the offset mho, an extra criteria
beside the one for offset mho (90<β<270) is introduced, that is the angle φ between
the voltage and the current must lie between the blinders in second quadrant and
fourth quadrant. See figure 84. Operation occurs if 90≤β≤270 and
ArgDir≤φ≤ArgNegRes.
where
ArgDir is the setting parameter for directional line in fourth quadrant in the directional element,
ZDMRDIR.
ArgNegRes is the setting parameter for directional line in second quadrant in the directional element,
ZDMRDIR.
β is calculated according to equation 39
The directional information is brought to the mho distance measurement from the
mho directional element as binary coded information to the input DIRCND. See
Directional impedance element for mho characteristic (ZDMRDIR) for information
about the mho directional element.
181
IL1L2jX
ZPP
UL1L2
ArgNegRes f
IL1L2
ArgDir
en07000111.vsd
IEC07000111 V1 EN
Figure 84: Simplified offset mho characteristic in forward direction for phase
L1-to-L2 fault
Offset mho, reverse direction

The operation area for offset mho in reverse direction is according to figure 85.
The operation area in second quadrant is ArgNegRes+180°.
Operation occurs if 90≤β≤270 and 180° - ArgDir ≤φ ≤ ArgNegRes + 180°
The β is derived according to equation 39 for the mho circle and φ is the angle
between the voltage and current.
182
ZPP
ArgNegRes
ϕ
IL1L2
ArgDir R
UL1L2
ZRevPP
en06000469.eps
IEC06000469 V1 EN
Figure 85: Operation characteristic for reverse phase L1-to-L2 fault
Phase-to-earth fault
Mho
The measuring of earth faults uses earth-return compensation applied in a
conventional way. The compensation voltage is derived by considering the
influence from the earth-return path.
For an earth fault in phase L1, the compensation voltage Ucomp can be derived, as
shown in figure 86.
Ucomp = U pol - I L1 × Z loop

where
Upol is the polarizing voltage (memorized UL1 for Phase L1-to- earth fault)
Zloop is the loop impedance, which in general terms can be expressed as
Z1+ZN = Z 1 × 1 + KN ( )
183
where
Z1 is the positive sequence impedance of the line (Ohm/phase)
KN is the zero-sequence compensator factor
The angle β between the Ucomp and the polarize voltage Upol for a L1-to-earth
fault is
b = arg [UL1 -(IL1 +3I0 · KN ) · ZPE ] - arg( Upol)

GUID-A9492CDF-D3B7-4DC5-8E06-6638BEE2540B V1 EN (Equation 42)
where
UL1 is the phase voltage in faulty phase L1
IL1 is the phase current in faulty phase L1
IA is the phase current in faulty phase A
3I0 is the zero-sequence current in faulty phase L1
KN Z0-Z1
EQUATION1593 V1 EN
3 × Z1
EQUATION1594 V1 EN
the setting parameter for the zero sequence compensation consisting of the
magnitude KN and the angle KNAng.
Upol is the 100% of positive sequence memorized voltage UL1
Vpol is the 100% of positive sequence memorized voltage VA
IL1·X
IL1·ZN
Ucomp
IL1 • Zloop
IL1·ZPE
Upol
f
IL1 (Ref) IL1·R
en06000472_2.vsd
IEC06000472 V2 EN
Figure 86: Simplified offset mho characteristic and vector diagram for phase
L1-to-earth fault
184
Offset mho
The characteristic for offset mho at earth fault is a circle containing the two vectors
from the origin ZPE and ZRevPE where ZPE and ZrevPE are the setting reach for
the positive sequence impedance in forward respective reverse direction. The
vector ZPE in the impedance plane has the settable angle AngZPE and the angle for
ZRevPP is AngZPE+180°.
The condition for operation at phase-to-earth fault is that the angle β between the
two compensated voltages Ucomp1 and Ucomp2 is greater or equal to 90° see
figure 87. The angle will be 90° for fault location on the boundary of the circle.
The angle β for L1-to-earth fault can be defined as
æ UL1- IL1L × ZPE ö

b = arg ç ÷
è UL1-(- IL1 × Z Re vPE ) ø
is the phase L1 voltage

U L1
EQUATION1
805 V1 EN
IL1L 2 • jX
U comp1 = UL1 - I L1• ZPE

IL1 • ZPE
UL1
U comp2 = UL1 - (-IL1 • ZRevPE)
IL1L2 • R
- I L1 • Z Re vPe
en 06000465.vsd
IEC06000465 V1 EN
Figure 87: Simplified offset mho characteristic and voltage vector for phase L1-
to-L2 fault
185
Offset mho, forward direction

In the same way as for phase-to-phase fault, selection of forward direction of offset
mho will introduce an extra criterion for operation. Beside the basic criteria for
offset mho according to equation 45 and 90≤β≤270, also the criteria that the angle
φ between the voltage and the current must lie between the blinders in second and
fourth quadrant. See figure 88. Operation occurs if 90≤β≤270 and
ArgDir≤φ≤ArgNegRes.
where
ArgDir is the setting parameter for directional line in fourth quadrant in the directional element,
ZDMRDIR.
ArgNegRes is the setting parameter for directional line in second quadrant in the directional element,
ZDMRDIR.
β is calculated according to equation 45
IL1 jX
UL1
ArgNegRes f
IL1 IL1·R
ArgDir
en 06000466.vsd
IEC06000466 V1 EN
Figure 88: Simplified characteristic for offset mho in forward direction for L1-to-
earth fault
Offset mho, reverse direction

In the same way as for offset in forward direction, the selection of offset mho in
reverse direction will introduce an extra criterion for operation compare to the
normal offset mho. The extra is that the angle between the fault voltage and the
fault current shall lie between the blinders in second and fourth quadrant. The
operation area in second quadrant is limited by the blinder defined as 180° -ArgDir
and in fourth quadrant ArgNegRes+180°, see figure 89.
The conditions for operation of offset mho in reverse direction for L1-to-earth fault
is 90≤β≤270 and 180°-Argdir≤φ≤ArgNegRes+180°.
186
The β is derived according to equation 45 for the offset mho circle and φ is the
angle between the voltage and current.
ZPE
ArgNegRes
ϕ
IL
1
ArgDir R
UL1
ZRevPE
en06000470.eps
IEC06000470 V1 EN
Figure 89: Simplified characteristic for offset mho in reverse direction for L1-to-
earth fault
6.1.2.5 Simplified logic diagrams
Distance protection zones

The design of the distance protection zones are presented for all measuring loops:
phase-to-earth as well as phase-to-phase.
Phase-to-earth related signals are designated by L1N, L2N and L3N. The phase-to-
phase signals are designated by L1L2, L2L3, and L3L1.
Fulfillment of two different measuring conditions is necessary to obtain the one

logical signal for each separate measuring loop:
• Zone measuring condition, which follows the operating equations described

above.
• Group functional input signal (STCND), as presented in figure 90.
One type of function block, ZMHPDIS are used in the IED for zone 1 - 5.
187
The STCND input signal represents a connection of six different integer values
from Phase selection with load encroachment, quadrilateral characteristic function
FMPSPDIS within the IED, which are converted within the zone measuring
function into corresponding boolean expressions for each condition separately.
Input signal STCND is connected to FMPSPDIS function output signal
STCNDPHS.
The input signal DIRCND is used to give condition for directionality for the
distance measuring zones. The signal contains binary coded information for both
forward and reverse direction. The zone measurement function filters out the
relevant signals depending on the setting of the parameter DirMode. Input signal
DIRCND must be configured to the STDIRCND output signal on ZDMRDIR
function.
OffsetMhoDir=
Non-directional
AND AND
DirMode=Offset
STCND T
AND F
AND
LoadEnchMode=
On/Off
LDCND
T
True F
AND Release
DIRCND
OffsetMhoDir=
Forward/Reverse
AND
DirMode=
Forward/Reverse
BLKZ
BLOCK OR
IEC11000216 V1 EN
Figure 90: Simplified logic for release start signal
When load encroachment mode is switched on (LoadEnchMode=On) then start

signal STCND is also checked against LDCND signal.
Results of the directional measurement enter the logic circuits, when the zone
operates in directional (forward or reverse) mode, as shown in figure 90.
Composition of the phase start signals is presented in figure 91.
188
Release STPE
OR
AND
STL1N STL1
OR
AND
STL2N
AND
STL3N
STL2
OR
AND
STL1L2
AND
STL2L3
STL3
OR
AND
STL3L1
START
OR
STPP
OR
IEC11000217 V1 EN
Figure 91: Composition of starting signals
Tripping conditions for the distance protection zone one are symbolically presented
in figure 92.
189
Timer tPP=On tPP

AND t
STPP
OR
Timer tPE=On tPE
AND t
STPE
15ms
AND TRIP
BLKTRIP t
STL1 AND TRL1
AND TRL2
STL2
STL3 AND TRL3
IEC11000218 V1 EN
Figure 92: Tripping logic for the distance protection zone

ZMHPDIS
I3P* TRIP
U3P* TRL1
CURR_INP* TRL2
VOLT_INP* TRL3
POL_VOLT* TRPE
BLOCK TRPP
BLKZ START
BLKZMTD STL1
BLKHSIR STL2
BLKTRIP STL3
BLKPE STPE
BLKPP STPP
DIRCND
STCND
LDCND
IEC06000423 V2 EN
Figure 93: ZMHPDIS function block
190

Table 88: ZMHPDIS Input signals
I3P GROUP - Connection for current sample signals
SIGNAL
U3P GROUP - Connection for voltage sample signals
SIGNAL
CURR_INP GROUP - Connection for current signals
SIGNAL
VOLT_INP GROUP - Connection for voltage signals
SIGNAL
POL_VOLT GROUP - Connection for polarizing voltage
SIGNAL
BLKZ BOOLEAN 0 Block due to fuse failure
BLKZMTD BOOLEAN 0 Block signal for blocking of time domaine function
BLKHSIR BOOLEAN 0 Blocks time domain function at high SIR
BLKTRIP BOOLEAN 0 Blocks all operate output signals
BLKPE BOOLEAN 0 Blocks phase-to-earth operation
BLKPP BOOLEAN 0 Blocks phase-to-phase operation
DIRCND INTEGER 0 External directional condition
STCND INTEGER 0 External start condition (loop enabler)
LDCND INTEGER 0 External load condition (loop enabler)
Table 89: ZMHPDIS Output signals

TRIP BOOLEAN Trip General
TRL1 BOOLEAN Trip phase L1
TRPE BOOLEAN Trip phase-to-earth
TRPP BOOLEAN Trip phase-to-phase
START BOOLEAN Start General
STL1 BOOLEAN Start phase L1
STPE BOOLEAN Start phase-to-earth
STPP BOOLEAN Start phase-to-phase
191

Table 90: ZMHPDIS Group settings (basic)
Operation Off - - On Operation Off/On
On
DirMode Off - - Forward Direction mode
Offset
Forward
Reverse
LoadEncMode Off - - Off Load encroachment mode Off/On
On
ReachMode Overreach - - Overreach Reach mode Over/Underreach
Underreach
OpModePE Off - - On Operation mode Off / On of Phase-Earth
On loops
ZPE 0.005 - 3000.000 ohm/p 0.001 30.000 Positive sequence impedance setting for
Phase-Earth loop
ZAngPE 10 - 90 Deg 1 80 Angle for positive sequence line
impedance for Phase-Earth loop
KN 0.00 - 3.00 - 0.01 0.80 Magnitud of earth return compensation
factor KN
KNAng -180 - 180 Deg 1 -15 Angle for earth return compensation
factor KN
ZRevPE 0.005 - 3000.000 ohm/p 0.001 30.000 Reverse reach of the phase to earth
loop(magnitude)
tPE 0.000 - 60.000 s 0.001 0.000 Delay time for operation of phase to
earth elements
IMinOpPE 10 - 30 %IB 1 20 Minimum operation phase to earth current
OpModePP Off - - On Operation mode Off / On of Phase-
On Phase loops
ZPP 0.005 - 3000.000 ohm/p 0.001 30.000 Impedance setting reach for phase to
phase elements
ZAngPP 10 - 90 Deg 1 85 Angle for positive sequence line
impedance for Phase-Phase elements
ZRevPP 0.005 - 3000.000 ohm/p 0.001 30.000 Reverse reach of the phase to phase
loop(magnitude)
tPP 0.000 - 60.000 s 0.001 0.000 Delay time for operation of phase to phase
IMinOpPP 10 - 30 %IB 1 20 Minimum operation phase to phase
current
192
Table 91: ZMHPDIS Group settings (advanced)

OffsetMhoDir Non-directional - - Non-directional Direction mode for offset mho
Forward
Reverse
OpModetPE Off - - On Operation mode Off / On of Zone timer,
On Ph-E
OpModetPP Off - - On Operation mode Off / On of Zone timer,
On Ph-ph

Table 92: ZMHPDIS technical data
Number of zones with selectable Max 4 with selectable direction -
directions
Minimum operate current (10–30)% of IBase -
Positive sequence impedance, (0.005–3000.000) W/phase ± 2.0% static accuracy

phase-to-earth loop Conditions:
Voltage range: (0.1-1.1) x Ur
Positive sequence impedance (10–90) degrees
Current range: (0.5-30) x Ir
angle, phase-to-earth loop
Angle: at 0 degrees and 85
Reverse reach, phase-to-earth (0.005–3000.000) Ω/phase degrees
loop (Magnitude)
Magnitude of earth return (0.00–3.00)
compensation factor KN
Angle for earth compensation (-180–180) degrees
factor KN
Dynamic overreach <5% at 85 degrees measured -
with CVT’s and 0.5<SIR<30
Timers (0.000-60.000) s ± 0.5% ± 10 ms
Operate time 20 ms typically (with static -
outputs)
Reset ratio 105% typically -
Reset time 30 ms typically -
6.2 Directional impedance element for mho

characteristic ZDMRDIR

Directional impedance element for mho ZDMRDIR 21D
characteristic
S00346 V1 EN
193
6.2.1 Introduction
The phase-to-earth impedance elements can be optionally supervised by a phase
unselective directional function based on symmetrical components.
6.2.2.1 Directional impedance element for mho characteristic ZDMRDIR
The evaluation of the directionality takes place in Directional impedance element

for mho characteristic (ZDMRDIR). Equation 46 and equation 47 are used to
classify that the fault is in the forward direction for phase-to-earth fault and phase-
to-phase fault respectively.
0.85 × U1L1 + 0.15 × U1L1M

- ArgDir < arg < ArgNeg Re s
I L1
0.85 × U1L1L 2 + 0.15 × U1L1L 2 M

- ArgDir < arg < ArgNeg Re s
I L1L 2
Where:
ArgDir Setting for the lower boundary of the forward directional characteristic, by default set to
15 (= -15 degrees)
ArgNegRes Setting for the upper boundary of the forward directional characteristic, by default set to
115 degrees, see figure 94 for mho characteristics.
U1L1 Positive sequence phase voltage in phase L1
U1L1M Positive sequence memorized phase voltage in phase L1
IL1 Phase current in phase L1
U1L1L2 Voltage difference between phase L1 and L2 (L2 lagging L1)
U1L1L2M Memorized voltage difference between phase L1 and L2 (L2 lagging L1)
IL1L2 Current difference between phase L1 and L2 (L2 lagging L1)
The default settings for ArgDir and ArgNegRes are 15 (= -15) and 115 degrees
respectively (see figure 94) and they should not be changed unless system studies
show the necessity.
If one sets DirEvalType to Comparator (which is recommended when using the

mho characteristic) then the directional lines are computed by means of a comparator-
type calculation, meaning that the directional lines are based on mho-circles (of
infinite radius). The default setting value Impedance otherwise means that the
194
directional lines are implemented based on an impedance calculation equivalent to

the one used for the quadrilateral impedance characteristics.
When Directional impedance element for mho characteristic

(ZDMRDIR) is used together with Fullscheme distance protection,
mho characteristic (ZMHPDIS) the following settings for
parameter DirEvalType is vital:
• alternative Comparator is strongly recommended
• alternative Imp/Comp should generally not be used
• alternative Impedance should not be used. This altenative is
intended for use together with Distance protection zone,
quadrilateral characteristic (ZMQPDIS)
X
Zset reach point
ArgNegRes
-ArgDir R
-Zs
en06000416.vsd
IEC06000416 V1 EN
Figure 94: Setting angles for discrimination of forward fault
The reverse directional characteristic is equal to the forward characteristic rotated

by 180 degrees.
The polarizing voltage is available as long as the positive-sequence voltage

exceeds 5% of the set base voltage UBase. So the directional element can use it for
all unsymmetrical faults including close-in faults.
For close-in three-phase faults, the U1L1M memory voltage, based on the same
positive sequence voltage, ensures correct directional discrimination.
The memory voltage is used for 100ms or until the positive sequence voltage is
restored. After 100ms, the following occurs:
195
• If the current is still above the set value of the minimum operating current the
condition seals in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element
in the reverse direction remains in operation.
• If the current decreases below the minimum operating value, no directional
indications will be given until the positive sequence voltage exceeds 10% of
its rated value.
The Directional impedance element for mho characteristic (ZDMRDIR) function

has the following output signals:
The STDIRCND output provides an integer signal that depends on the evaluation
and is derived from a binary coded signal as follows:
bit 11 bit 10 bit 9 bit 8 bit 7 bit 6

(2048) (1024) (512) (256) (128) (64)
STRVL3L1= STRVL2L3= STRVL1L2= STRVL3N=1 STRVL2N=1 STRVL1N=1
1 1 1
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(32) (16) (8) (4) (2) (1)
STFWL3L1= STFWL2L3= STFWL1L2= STFWL3N=1 STFWL2N=1 STFWL1N=1
1 1 1
The STFW output is a logical signal with value 1 or 0. It is made up as an OR-

function of all the forward starting conditions, that is, STFWL1N, STFWL2N,
STFWL3N, STFWL1L2, STFWL2L3 and STFWL3L1. The STRV output is
similar to the STFW output, the only difference being that it is made up as an OR-
function of all the reverse starting conditions, that is, STRVL1N, STRVL2N,
STRVL3N, STRVL1L2, STRVL2L3 and STRVL3L1.
Values for the following parameters are calculated, and may be viewed as service
values:
• resistance phase L1
• reactance phase L1
• direction phase L1
196

ZDMRDIR
I3P* DIR_CURR
U3P* DIR_VOLT
DIR_POL
STFW
STRV
STDIRCND
IEC06000422 V2 EN
Figure 95: ZDMRDIR function block

Table 93: ZDMRDIR Input signals
I3P GROUP - group connection for current abs 1
SIGNAL
U3P GROUP - group connection for voltage abs 1
SIGNAL
Table 94: ZDMRDIR Output signals

DIR_CURR GROUP SIGNAL Group connection
DIR_VOLT GROUP SIGNAL Group connection
DIR_POL GROUP SIGNAL Group connection
STFW BOOLEAN Start in forward direction
STRV BOOLEAN Start in reverse direction
STDIRCND INTEGER Binary coded directional information per
measuring loop

Table 95: ZDMRDIR Group settings (basic)
IBase 1 - 99999 - 1 3000 Base setting for current level
UBase 0.05 - 2000.00 - 0.05 400.00 Base setting for voltage level
DirEvalType Impedance - - Comparator Directional evaluation mode Impedance /
Comparator Comparator
Imp/Comp
ArgNegRes 90 - 175 Deg 1 115 Angle of blinder in second quadrant for
forward direction
197

ArgDir 5 - 45 Deg 1 15 Angle of blinder in fourth quadrant for
forward direction
IMinOpPE 5 - 30 %IB 1 5 Minimum operate phase current for
Phase-Earth loops
IMinOpPP 5 - 30 %IB 1 10 Minimum operate delta current for Phase-
Phase loops
6.3 Pole slip protection PSPPPAM

Pole slip protection PSPPPAM Ucos 78
6.3.1 Introduction
The phenomenon pole slip, also named out of step conditions, occurs when there is
phase opposition between different parts of a power system. This is often shown in
a simplified way as two equivalent generators connected to each other via an
equivalent transmission line and the phase difference between the equivalent
generators is 180°.
Angle = 90° Angle = -90°
Centre of Pole Slip

en07000003.vsd
IEC07000003 V1 EN
Figure 96: The centre of pole slip
The centre of the pole slip can occur in the generator itself or somewhere in the
power system. When a pole slip occurs within the generator it is essential to trip the
generator. If the centre of pole slip occurs outside any generator the power system
198
should be split into two different parts that could have the ability to get stable
operating conditions.
Pole slip protection (PSPPPAM) function in the IED can be used both for generator
protection application as well as, line protection applications.
The situation with pole slip of a generator can be caused by different reasons.
A short circuit may occur in the external power grid, close to the generator. If the
fault clearing time is too long, the generator will accelerate so much, that the
synchronism cannot be maintained.
Un-damped oscillations occur in the power system, where generator groups at

different locations, oscillate against each other. If the connection between the
generators is too weak the magnitude of the oscillations will increase until the
angular stability is lost.
The operation of a generator having pole slip will give risk of damages to the
generator, shaft and turbine.
• At each pole slip there will be significant torque impact on the generator-
turbine shaft.
• In asynchronous operation there will be induction of currents in parts of the
generator normally not carrying current, thus resulting in increased heating.
The consequence can be damages on insulation and stator/rotor iron.
The Pole slip protection (PSPPPAM) function shall detect pole slip conditions and
trip the generator as fast as possible if the locus of the measured impedance is
inside the generator-transformer block. If the centre of pole slip is outside in the
power grid, the first action should be to split the network into two parts, after line
protection action. If this fails there should be operation of the generator PSPPPAM
in zone 2, to prevent further damages to the generator, shaft and turbine.

If the generator is faster than the power system, the rotor movement in the
impedance and voltage diagram is from right to left and generating is signalled. If
the generator is slower than the power system, the rotor movement is from left to
right and motoring is signalled (the power system drives the generator as if it were
a motor).
The movements in the impedance plain can be seen in figure 97. The transient
behaviour is described by the transient EMF's EA and EB, and by X'd, XT and the
transient system impedance ZS.
199
Zone 1 Zone 2
EB X’d XT XS EA
IED
B A
jX
XS
Pole slip
impedance XT
d Apparent generator
movement impedance R
X’d
IEC06000437 V2 EN
Figure 97: Movements in the impedance plain
where:
X'd = transient reactance of the generator
XT = short-circuit reactance of the step-up transformer
ZS = impedance of the power system A
The detection of rotor angle is enabled when:
• the minimum current exceeds 0.10 IN (IN is IBase parameter set under general
setting).
• the maximum voltage falls below 0.92 UBase
• the voltage Ucosφ (the voltage in phase with the generator current) has an
angular velocity of 0.2...8 Hz and
• the corresponding direction is not blocked.
200
en07000004.vsd
IEC07000004 V1 EN
Figure 98: Different generator quantities as function of the angle between the
equivalent generators
An alarm is given when movement of the rotor is detected and the rotor angle
exceeds the angle set for 'WarnAngle'.
Slipping is detected when:
• a change of rotor angle of min. 50 ms is recognized

• the slip line is crossed between ZA and ZB.
When the impedance crosses the slip line between ZB and ZC it counts as being in
zone 1 and between ZC and ZA in zone 2. The entire distance ZA-ZB becomes zone
1 when signal EXTZONE1 is high (external device detects the direction of the
centre of slipping).
After the first slip, the signals ZONE1 or ZONE2 and – depending on the direction
of slip - either GEN or MOTOR are issued.
Every time pole slipping is detected, the impedance of the point where the slip line
is crossed and the instantaneous slip frequency are displayed as measurements.
Further slips are only detected, if they are in the same direction and if the rate of
rotor movement has reduced in relation to the preceding slip or the slip line is
crossed in the opposite direction outside ZA-ZB. A further slip in the opposite
direction within ZA-ZB resets all the signals and is then signalled itself as a first slip.
201
The TRIP1 tripping command and signal are generated after N1 slips in zone 1,
providing the rotor angle is less than TripAngle. The TRIP2 signal is generated
after N2 slips in zone 2, providing the rotor angle is less than TripAngle.
All signals are reset if:
• the direction of movement reverses

• the rotor angle detector resets without a slip being counted or
• no rotor relative movement was detected during the time ResetTime.
Imin > 0.10 IBase
Ucosj < 0.92 UBase AND
START
AND
0.2 £ Slip.Freq. £ 8 Hz
d ³ startAngle
ZONE1
AND
Z cross line ZA - ZC
ZONE2
AND
Z cross line ZC - ZB
Counter
a
a³b
N1Limit b TRIP1
AND
d £ tripAngle TRIP
OR
Counter
a
N2Limit b a³b TRIP2
AND
en07000005.vsd
IEC07000005 V1 EN
Figure 99: Simplified logic diagram for pole slip protection PSPPPAM
202

PSPPPAM
I3P* TRIP
U3P* TRIP1
BLOCK TRIP2
BLKGEN START
BLKMOTOR ZONE1
EXTZONE1 ZONE2
GEN
MOTOR
SFREQ
SLIPZOHM
SLIPZPER
UCOS
UCOSPER
IEC10000045 V1 EN
Figure 100: PSPPPAM function block

Table 96: PSPPPAM Input signals
I3P GROUP - Current group connection
SIGNAL
U3P GROUP - Voltage group connection
SIGNAL
BLKGEN BOOLEAN 0 Block operation in generating direction
BLKMOTOR BOOLEAN 0 Block operation in motor direction
EXTZONE1 BOOLEAN 0 Extension of zone1 with zone2 region
Table 97: PSPPPAM Output signals

TRIP BOOLEAN Common trip signal
TRIP1 BOOLEAN Trip1 after the N1Limit slip in zone1
TRIP2 BOOLEAN Trip2 after the N2Limit slip in zone2
START BOOLEAN Common start signal
ZONE1 BOOLEAN First slip in zone1 region
ZONE2 BOOLEAN First slip in zone2 region
GEN BOOLEAN Generator is faster than the system
MOTOR BOOLEAN Generator is slower than the system
SFREQ REAL Slip frequency
SLIPZOHM REAL Slip impedance in ohms
SLIPZPER REAL Slip impedance in percent of ZBase
UCOS REAL UCosPhi voltage
UCOSPER REAL UCosPhi voltage in percent of UBase
203

Table 98: PSPPPAM Group settings (basic)
Operation Off - - Off Operation On / Off
On
OperationZ1 Off - - On Operation Zone1 On / Off
On
OperationZ2 Off - - On Operation Zone2 On / Off
On
ImpedanceZA 0.00 - 1000.00 % 0.01 10.00 Forward impedance in % of Zbase
ImpedanceZB 0.00 - 1000.00 % 0.01 10.00 Reverse impedance in % of Zbase
ImpedanceZC 0.00 - 1000.00 % 0.01 10.00 Impedance of zone1 limit in % of Zbase
AnglePhi 72.00 - 90.00 Deg 0.01 85.00 Angle of the slip impedance line
StartAngle 0.0 - 180.0 Deg 0.1 110.0 Rotor angle for the start signal
TripAngle 0.0 - 180.0 Deg 0.1 90.0 Rotor angle for the trip1 and trip2 signals
N1Limit 1 - 20 - 1 1 Count limit for the trip1 signal
N2Limit 1 - 20 - 1 3 Count limit for the trip2 signal
Table 99: PSPPPAM Group settings (advanced)

ResetTime 0.000 - 60.000 s 0.001 5.000 Time without slip to reset all signals
Table 100: PSPPPAM Non group settings (basic)

IBase 0.1 - 99999.9 A 0.1 3000.0 Base Current (primary phase current in
Amperes)
UBase 0.1 - 9999.9 kV 0.1 20.0 Base Voltage (primary phase-to-phase
voltage in kV)
MeasureMode PosSeq - - PosSeq Measuring mode (PosSeq, L1L2, L2L3,
L1L2 L3L1)
L2L3
L3L1
InvertCTcurr No - - No Invert current direction
Yes

Table 101: PSPPPAM technical data
Impedance reach (0.00–1000.00)% of Zbase ± 2.0% of Ur/Ir
Characteristic angle (72.00–90.00) degrees ± 5.0 degrees
Start and trip angles (0.0–180.0) degrees ± 5.0 degrees
Zone 1 and Zone 2 trip counters (1-20) -
204
6.4 Loss of excitation LEXPDIS

Loss of excitation LEXPDIS 40
<
SYMBOL-MM V1 EN
6.4.1 Introduction
There are limits for the under-excited operation of a synchronous machine. A
reduction of the excitation current weakens the coupling between the rotor and the
stator. The machine may lose the synchronism and start to operate like an induction
machine. Then, the reactive power consumption will increase. Even if the machine
does not loose synchronism it may not be acceptable to operate in this state for a
long time. Reduction of excitation increases the generation of heat in the end
region of the synchronous machine. The local heating may damage the insulation
of the stator winding and the iron core.
To prevent damages to the generator it should be tripped when excitation is lost.

The Loss of excitation (LEXPDIS) protection in the IED measures the apparent
impedance seen out from the generator.The measurement loop of apparent
impedance can be chosen as the positive sequence loop or any one of the three phase-
to-phase loops depending on the available current and voltage signals. It is
recommended to use positive sequence quantities for function operation.
205
Measured mode Measured apparent impedance
Zposseq U posseq
=
I posseq
ZL1L2 U L1 - U L 2
=
I L1 - I L 2
ZL2L3 U L 2 - U L3
=
I L 2 - I L3
ZL3L1 U L 3 - U L1
=
I L 3 - I L1
There are three characteristics in LEXPDIS protection as shown in figure 101.
Naimly:
• Offset mho circle for Z1
• Offset mho circle for Z2
• Directional blinder
206
UnderexitationProtection
Underexcitation protection
Restrainarea
Restrain area
R
Directional
blinder
Z1, Fast zone
Z2, Slow zone
IEC06000455 V2 EN
Figure 101: Three characteristics in LEXPDIS protection
When the apparent impedance reaches the zone Z1 this zone will operate, normally
with a short delay. The zone is related to the dynamic stability of the generator.
When the apparent impedance reaches the zone Z2 this zone will operate, normally
with a longer delay. The zone is related to the static stability of the generator.
LEXPDIS protection also has a directional blinder (supervision). See figure 101.
In LEXPDIS function the zone measurement is done as shown in figure 102.
207
Offset
R
XoffsetZ1
Z (apparent impedance)
Z1 = Z - (XoffsetZ1 +
Z1diameter Z1diameter/2)
Z1 or Z2
en06000456-2.vsd
IEC06000456 V2 EN
Figure 102: Zone measurement in LEXPDIS protection function
The impedance Z1 is constructed out from the measured apparent impedance Z and
the impedance corresponding to the centre point of the impedance characteristic
(Z1 or Z2). If the amplitude of this impedance is less than the radius (diameter/2)
of the characteristic, this part of the protection will operate.
If the directional restrain is set off the impedance zone operation will start the
appropriate timer and LEXPDIS will trip after the set delay (tZ1 or tZ2).
If the directional restrain is set On the directional release function must also
operate to enable operation. A new impedance is constructed as XoffsetDirLine. If
the phase angle of this impedance is less than the set DirAngle LEXPDIS function
will be released, see figure 103.
208
Underexcitation Protection
Restrain area
R
XoffsetDirLine
DirAngle
Z (apparent impedance)
en06000457.vsd
IEC06000457 V1 EN
Figure 103: Impedance constructed as XoffsetDirLine in LEXPDIS protection
LEXPDIS function is schematically described in figure 104.
Positive tZ1
sequence Z in startZ1 t TripZ1
&
current Z1 char.
phasor
Positive Apparent tZ2

Z Z in
sequence startZ2 t TripZ2
impedance &
voltage Z2 char.
calculation
phasor
Dir.
Restrain
Dir.Restrain ON ³1
en06000458-2.vsd
IEC06000458 V3 EN
Figure 104: Simplified logic diagram of LEXPDIS protection
209

LEXPDIS
I3P* TRIP
U3P* TRZ1
BLOCK TRZ2
BLKTRZ1 START
BLKTRZ2 STZ1
STZ2
XOHM
XPERCENT
ROHM
RPERCENT
IEC07000031 V2 EN
Figure 105: LEXPDIS function block

Table 102: LEXPDIS Input signals
SIGNAL
SIGNAL
BLKTRZ1 BOOLEAN 0 Block trip of zone Z1
BLKTRZ2 BOOLEAN 0 Block trip of zone Z2
Table 103: LEXPDIS Output signals

TRZ1 BOOLEAN Trip signal from impedance zone Z1
TRZ2 BOOLEAN Trip signal from impedance zone Z2
STZ1 BOOLEAN Start signal from impedance zone Z1
STZ2 BOOLEAN Start signal from impedance zone Z2
XOHM REAL Reactance in Primary Ohms
XPERCENT REAL Reactance in percent of Zbase
ROHM REAL Resistance in Primary Ohms
RPERCENT REAL Resistance in percent of Zbase
210

Table 104: LEXPDIS Group settings (basic)
On
OperationZ1 Off - - On Operation Off/On zone Z1
On
XoffsetZ1 -1000.00 - 1000.00 % 0.01 -10.00 Offset of Z1 circle top point along X axis
in % of Zbase
Z1diameter 0.01 - 3000.00 % 0.01 100.00 Diameter of imedance circle for Z1 in %
of Zbase
tZ1 0.00 - 6000.00 s 0.01 0.01 Trip time delay for Z1
OperationZ2 Off - - On Operation Off/On zone Z2
On
XoffsetZ2 -1000.00 - 1000.00 % 0.01 -10.00 Offset of Z2 circle top point along X axis
in % of Zbase
Z2diameter 0.01 - 3000.00 % 0.01 200.00 Diameter of imedance circle for Z2 in %
of Zbase
tZ2 0.00 - 6000.00 s 0.01 1.00 Trip time delay for Z2
Table 105: LEXPDIS Group settings (advanced)

DirSuperv Off - - Off Operation Off/On for additional
On directional criterion
XoffsetDirLine -1000.00 - 3000.00 % 0.01 0.00 Offset of directional line along X axis in
% of Zbase
DirAngle -180.0 - 180.0 Deg 0.1 -13.0 Angle between directional line and R-
axis in degrees
Table 106: LEXPDIS Non group settings (basic)

IBase 0.1 - 99999.9 A 0.1 3000 Base Current (primary phase current in
Amperes)
UBase 0.1 - 9999.9 kV 0.1 20 Base Voltage (primary phase-to-phase
voltage in kV)
MeasureMode PosSeq - - PosSeq Measuring mode (PosSeq, L1L2, L2L3,
L1L2 L3L1)
L2L3
L3L1
Table 107: LEXPDIS Non group settings (advanced)

InvertCTcurr No - - No Invert CT current
Yes
211

Table 108: LEXPDIS technical data
X offset of Mho top point (–1000.00–1000.00)% of ZBase ± 2.0% of Ur/Ir
Diameter of Mho circle (0.00–3000.00)% of ZBase ± 2.0% of Ur/Ir
Timers (0.00–6000.00) s ± 0.5% ± 10 ms
6.5 Sensitive rotor earth fault protection, injection based

ROTIPHIZ

Sensitive rotor earth fault protection, ROTIPHIZ Rre< 64R
injection based
6.5.1 Introduction
The sensitive rotor earth fault protection (ROTIPHIZ) is used to detect earth faults
in the rotor windings of generators. ROTIPHIZ is applicable for all types of
synchronous generators.
To implement the above concept, a separate injection box is required. The injection
box generates a square wave voltage signal at a certain preset frequency which is
fed into the rotor winding.
The magnitude of the injected voltage signal and the resulting injected current is
measured through a resistive shunt located within the injection box. These two
measured values are fed to the IED. Based on these two measured quantities, the
protection IED determines the rotor winding resistance to ground. The resistance
value is then compared with the preset fault resistance alarm and trip levels.
The protection function can detect earth faults in the entire rotor winding and
associated connections.
Requires injection unit REX060 and a coupling capacitor unit REX061 for correct
operation.

The protection principle is based on injection of voltage to the exciter point of the
field circuit.
212
4 Step-up
Transformer
U> 3
Uinj 1
Rshunt
7 R C
~ Generator
5
6
REX061 2
ROTOR EF
I
RN
REX060/RIM module
REG670
Generator Protection Panel
IEC11000014 V1 EN
Figure 106: Example installation for rotor injection
1 Generator unit consisting of a synchronous generator and a step-up transformer

2 Generator field winding
3 Capacitor coupling unit which is used to provide insulation barrier between rotor circuit and
injection equipment
4 Cable used to inject the square-wave signal into the rotor circuit
5 Connection for measurement of injected current. This signal is amplified in REX060 before it is
passed on to IED for evaluation.
6 Connection for measurement of injected voltage. This signal is amplified in REX060 before it is
passed on to IED for evaluation.
7 Two VT inputs into IED which are used to measure injected current and voltage
8 Protection for excessive over-voltages posed by generator. REX060 can withstand without
damage maximum voltage of 120V and when used together with REX062 up to 240V.
The injection signals are generated in a separate unit, REX060. The signals have
square wave form and are injected to the generator via the coupling capacitor unit
REX061 to the excitation circuit.
In the REX060 unit the injection voltage and current signals are amplified to a
level adapted to the analogue voltage inputs of IED. In IED the measured signals
evaluated to detect rotor earth faults.
213
6.5.2.1 The injection unit REX060
IED and
Injection Top view Power Back view Front view
connectors connector Keylock
LED
X11 X61 X81

1 1 1
Injection Stator
Injection Rotor
18 18
X62 X82
PSM
1 1
5 5
Power
Stator
Rotor
Backplane
Front-plate Injection LED Injection switch

HMI with logic
IEC11000015 V1 EN
Figure 107: Injection unit REX060
The REX060 unit is a common unit that can be configured for either rotor or stator
earth fault protection, or for both. The REX060 have separate modules for rotor
and stator protection. The REX060 generate square wave signals, where one is
used for injection to the stator neutral point and the other to the field winding
circuit (rotor circuit), if configured for both stator and rotor protection. The injected
voltage and currents are measured by the unit and amplified, resulting in voltage
signals both for the injected voltage and current, and adapted to the analogue inputs
of IED. The injection unit REX060 shall be located close to the IED, preferably in
the same cubicle.
For the Sensitive rotor earth fault protection, there are some settings necessary for
REX060:
• System frequency: 50/60 Hz

• Injected frequency for rotor circuit injection is settable in 1 Hz steps 75 – 250
Hz.
• Gain factor in four steps
REX060 will also continuously check the measured signal for detection of
saturation which could cause error in the evaluation in IED. If saturation level is
reached a binary signal, connected to IED, is activated. Also other errors in the
injection circuit will initiate a binary signal to IED for blocking of the function.
Rotor injection output is protected against high voltages by a relay blocking the
injection circuit. This blocking remains blocked by stored status in non-volatile
memory.
The output is also protected by a fuse. If this fuse is blown, it is caused by external
voltage source, since the injection unit cannot provide enough energy to blow this
fuse.
214
Refer to the Hardware section in this manual for a detailed description of REX060.
6.5.2.2 Rotor Earth Fault Protection function
The injection to the rotor is schematically shown in figure 108.
Iinj
+
DC
Crot
Rf Crot Uinj
AC
REX061 -
Rf Iinj
+
Rotor Reference
U inj
Im pedance
-
IEC11000065 V1 EN
Figure 108: Equivalent diagram for Sensitive rotor earth fault protection principle
The impedance ZMeasured is equal to the capacitive reactance between the rotor
winding and earth (1/ωCrot) and the earth fault resistance (Rf). The series resistance
in the injection circuit is eliminated. Rf is very large in the non-faulted case and the
measured impedance, called the rotor reference impedance and can be calculated as :
1
Z ref = - j
wCrot
EQUATION2510 V1 EN
alternative
1
= jwCrot
Z ref
EQUATION2511 V1 EN
Where
w = 2p × finj
EQUATION2512 V1 EN
The injected frequency finj of the square wave, is a set value, deviating from the
fundamental frequency (50 or 60 Hz). The injected frequency can be set within the
range 75 – 250 Hz with the recommended value 113 Hz in 50 Hz systems and 137
Hz in 60 Hz systems.
215
Rseries is a resistance in the REX061 unit used to protect against overvoltage to the
injection unit. Such overvoltages can occur if the unit is fed from static excitation
system.
The injection unit REX060 is connected to the generator and to IED as shown in
figure 106.
6.5.2.3 General measurement of earth fault impedance
From the REX060 the injected voltage and current are delivered as AC voltages to
IED. The injected voltage and current is measured and analyzed in the protection
function software within IED. The measured injected voltage and current are first
processed by means of special filtering so that the signals are referred to the
injected frequency only.
The bare complex impedance is, see fig 109:
U Inj
Z bare =
I Inj
EQUATION2500 V1 EN
An equivalent circuit for the measured impedance is shown in figure 109.
ZMeasured ZBare
Z series Iinj
Rf Z shunt Uinj
IEC11000003 V1 EN
Figure 109: Equivalent of the impedance measurement
In non-faulted operation Rf is very large. A “healthy” impedance is calculated as:
Z Measured = k1 × Z bare + k 2
EQUATION2501 V1 EN
For definition of k1 and k2, see figure 110
216
The factors k1 and k2 [Ω] are derived from measurements during commissioning,
where calibration to known fault resistance will be used to convert the
measurement to true primary impedance. The factor k1 will compensate for
transformer ratio and other factors to achieve impedance values related to the
primary system. The factor k2 [Ω] will compensate for the series impedance Zseries
The healthy impedance measured at non-faulted conditions is referred to as the

reference impedance in further text.
In IED the measured impedance is compared to the reference impedance. In case of

an earth fault, the fault impedance is estimated and compared to the set values
RAlarm and RTrip.
The measured values are transferred to the primary impedance values by taking the
actual impedance value through the complex transformation given by the equation.
Ztrue = k1 × Z measured + k2
GUID-20ADF3F6-6A89-4B5F-B0DA-9740C4FD5482 V1 EN
The factors k1 and k2 [Ω] are derived during the calibration measurements under
commissioning. As support for the calibration, the Injection Commissioning tool
must be used. This tool is an integrated part of the PCM600 tool.
In connection to this calibration, the reference impedance is also derived. In case of

a rotor earth fault with fault impedance Zf, the measured admittance is:
1 1 1
= +
Z Z ref Z f
=
1 1 1
= -
Zf Z Z ref
EQUATION2405 V1 EN
The real part gives the fault conductance.
1 æ1 1 ö
= Re ç - ÷
Rf ç ÷
è Z Z ref ø
EQUATION2421 V1 EN
RAlarm and RTrip are the two resistance levels given in the settings. The values of
RAlarm and RTrip are given in Ω.
An alarm signal ALARM is given after a set delay tAlarm if Rf < RAlarm
A start signal START is given if Rf < RTrip
See figure 112
217
6.5.2.4 Simplified logic diagram
ROTIPHIZ
Uinj
Rshunt
2
1
3
4
6 5
I Inj u_i_ref
Z Measured
Z Bare
¸ I
Rf X
Compare & S U Inj u_u_ref
Evaluate
7
K2
K1
U
ZRef1
ZRef2 REX060
REG670
IEC10000327 V1 EN
Figure 110: Simplified logic diagram for sensitive rotor earth fault protection,
injection based ROTIPHIZ
1 The sensitive rotor earth fault protection function receives amplified injected voltage and
current via the REX060 unit as two voltages signals. (Voltage inputs in the IED)
2 The phasor of injected voltage UInj and phasor of injected current IInj is calculated by using
special filter from raw samples. Observe that phasors are calculated for the injected
frequency.
3 The complex bare impedance is calculated from Uinj / Iinj.
4, 5 The complex measured impedance is derived as ZMeasured = Zbare*k1 + k2 [Ω].
6 The fault resistance (Rf) is calculated from the complex measured impedance and a
selected complex reference.
7 Selection of one (out of maximum 2) ZRef.
218
Rf tAlarm
a
a<b t ALARM
b OR
RAlarm
a TRIP
a<b
b
RTrip
IEC10000326 V1 EN
Figure 111: ROTIPHIZ Alarm and trip logic
If the fault resistance Rf is smaller than RAlarm and longer than alarm delay (using
delay-on), output ALARM is set. If the fault resistance Rf is smaller than RTrip,
using internal trip time characteristic, output signal TRIP is set after the calculated
time. For trip time delay, see fig 112
When 1s filter length is used and the fault resistance is equal to the set value RTrip,
the trip time is about 10 s. If the fault resistance is estimated to be 0 Ω, the trip
delay is 2 s. For values in between, the delay follows the linear interpolation
describing the fault resistance time characteristic.
219
Trip time
10 × FilterLength
2 × FilterLength
Fault resistance
RTrip RAlarm
IEC11000002 V1 EN
Figure 112: Trip time characteristic as function of fault resistance
A third high level step for the detection of excitation system earth faults on the AC
side of the excitation rectifier is available. This step uses the network frequency (50
or 60 Hz) for the evaluation. If an earth fault occurs at the AC side of the excitation
system rectifier, there is a fundamental frequency component at the measured
voltage and current injection points.
The third high level step is not applicable if mixed signals are used, that is when
the REX060 is used for both rotor and stator earth fault protection and only two,
instead of four, analog inputs on the IED are used.
6.5.2.5 Commissioning tool ICT
The sensitive rotor earth fault protection function in IED require a number of
settings. The settings k1, k2 and the reference impedance require measurements on
the generator performed by the ICT (injection commissioning tool). The factors are
derived in connection to the calibration measurements during commissioning. ICT
is an integrated part of the PCM600 tool.
Furthermore, ICT also assists the commissioning engineer to perform a successful

installation because of its structure and validating capabilities. During installation,
commissioning and calibration, ICT performs various tests to verify that the
installation is acceptable and the calibration successful. Besides carrying out the
actual tests, ICT also provides the commissioning engineer with tips if needed
during the commissioning.
220
When ICT is started, rotor earth fault protection is chosen.
There are five different parts of the ICT tool to be performed at commissioning and
operation:
1. Installing
2. Calibrating
3. Commissioning
4. Monitoring
5. Auditing
Before proceeding make sure that all necessary connections are in place.
Installing
When the injection is started, check that the injected voltage and current are within
the permissible limits. If not, adjust the settings in the injection unit REX060. The
ICT tool will check automatically for slight differences between actual injected and
set injection frequency (for example, due to accuracy of the REX060 hardware).
Set manually the actual frequency value measured by ICT in the IED via PST.
The high accuracy of this frequency is essential for proper operation of the
protection under different operating conditions.
Calibrating
The calibration is based on three measurement steps:
1. The injection is made to the faultless generator and the measured complex
impedance is stored.
2. A known resistance is connected between one rotor pole (see Figure 113) and
earth. The injection is made to the generator and the measured complex
impedance is stored.
3. The one rotor pole (see Figure 113) is directly short-circuited to the earth. The
injection is made to the generator and the measured complex impedance is stored.
The sequence of the commissioning calibration measurements is shown in the

figure below.
Step 1 Step 2 Step 3
DC DC DC
Crot C rot Crot
AC AC AC
REX061 REX061 REX061

I inj I inj Iinj
RTest
IEC11000205 V1 EN
Figure 113: Different steps at calibration measurements
221
The sequence of the calibration session follows a scheme shown in the tool.
• Calibration sequence 1: The injection must be activated and the rotor must be
left with no impedance connected. The ICT now makes consecutive
measurements until the statistical error reaches an acceptable value. This is
graphically shown in a diagram. The user stops the sequence by acceptance of
the measurement. The result is stored for later calculations.
• Calibration sequence 2: A known resistor is connected between the rotor
winding and earth. The value of the resistance is the input to ICT. The ICT
now makes consecutive measurements until the statistical error reaches an
acceptable value. This is graphically shown in a diagram. The user stops the
sequence by acceptance of the measurement. The result is stored for later
calculations.
• Calibration sequence 3: The generator rotor winding is now directly connected
to earth. The ICT now makes consecutive measurements until the statistical
error reaches an acceptable value. This is graphically shown in a diagram. The
user stops the sequence by acceptance of the measurement. The result is stored
for later calculations.
After the three measurements ICT calculates the complex factors k1 and k2. The
reference impedance RefR1 + jRefX1 is also calculated. After this the values are
downloaded to the parameter setting in PCM600. From PCM600 the settings are
downloaded to IED.
During the three measurements described above a check is made that there are
sufficient changes in the measured impedance in order to guarantee that there is no
primary fault from the beginning or other problems due to the installation or
calibration procedure.
Now the reference impedance is derived for one operational state. It might be
necessary to make measurements to derive reference impedance for other
operational cases. For information on this, see Commissioning below.
Commissioning
There is a possibility to have two different reference impedances. The need to
change the reference impedance is due to different operating conditions of the
machine.
In the commissioning part of ICT this can be done. For each operation state of
interest a measurement is performed. If the reference impedance differs from the
first one, calculated under the calibration session, the new reference impedance is
stored by the command; Submit toParameter Setting.
If more than one reference impedance are to be used, there must be a logic
configured to detect such changes in the operation states that requires a change of
reference impedance.
222
Monitoring
In the monitoring part the calibration can be checked by applying the known fault
resistance and compare it with the actual function measurement. It is also possible
to identify operational states where change of reference impedance is required.
Auditing
In the auditing part calibration and commissioning reports are made.
6.5.3 Description of input signals

The inputs to the sensitive rotor earth-fault protection function block are as shown
in table 109.
Table 109: Description of various inputs

Input signal Description
USU The measured injection voltage. This signal is taken from a pre-processor block, the AI
output. The analog voltage input AI1 is linked to the phase L1 in the pre-processor
block in the Signal Matrix tool.
USI The measured injection current. This signal is taken from a pre-processor block, the AI
output. In the pre-configured version, the analog voltage input AI2 is linked to the
phase L2 in the pre-processor block in the Signal Matrix tool.
BLOCK Input to block the function
ZREFSEL The selection of any of the predefined reference impedances. There is a possibility to
change from one set reference impedance to another. Two different reference
impedances are available.
6.5.4 Description of output signals

The outputs of the sensitive rotor earth-fault protection function block are as shown
in table 110.
Table 110: Description of various outputs

Output signal Description
TRIP Common trip command signal
TRIPDC is the trip command signal at DC-side earth fault
TRIPAC is the trip command signal at AC-side earth fault
START is a common signal for both AC and DC side of exciter
STARTDC is the start signal at DC-side earth fault
STARTAC is the start signal at AC-side earth fault
ALARM Signal activated after a set time delay, if the calculated fault resistance gets lower
than the set alarm level
ERROR Error signal which is boolean with values 0 and 1
ERRSTAT Status coded signal giving type of error. See table 111
223

RAVE Measured resistance to earth in Ω at an injected frequency (real part of the complex
impedance)
XAVE Measured reactance to earth in Ω at the injected frequency (imaginary part of the
complex impedance)
FREQU Measured frequency of the injected voltage
RFAULT Estimated fault resistance in Ω
ZREF Selected reference impedance number
ZREFRE The real part (resistance) of the used reference impedance
ZREFIM The imaginary part (reactance) of the used reference impedance
URMSSTAT This signal is set true, if the measured RMS voltage is larger than the set limit
ULimRMS
ERRSTAT output signal
Convert the integer output signal to binary and see table below for interpretation of
individual bits:
Table 111: Definition of errors

ERRSTAT output integer
Priority 3 Priority 2 Priority 3 Priority 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Interfer- Under- Under- Over- Over- Frequ- No No
ence current voltage current voltage ency current voltage
detected difference
The ERRSTAT description will be shown in clear text in ICT.
The priority of the signals is set that the group priority 1 overrides the group
priority 2 and 3, and priority 2 overrides priority 3. Note that the ERRSTAT signal
can enable several error cases at the same time.
Following errors is detected and derived in the Error block:
• B0 = Injected voltage signal not found

• B1 = Injected current signal not found
• B2 = Voltage and current signal frequency differs
• B3 = Measured total RMS voltage too high
• B4 = Measured total RMS current too high
• B5 = Injected voltage signal too low
• B6 = Injected current signal too low
• B7 = External interference voltage detected
ERRSTAT = BitToInt[B7,…,B1,B0] The priority of the error conditions that will

be flagged out:
224
• Prio1 = B0, B1
• Prio2 = B3, B4, B5, B6
• Prio3 = B2, B7

ROTIPHIZ
USU* TRIP
USI* TRIPDC
BLOCK TRIPAC
ZREFSEL START
STARTDC
STARTAC
ALARM
ERROR
ERRSTAT
RAVE
XAVE
FREQU
RFAULT
ZREF
ZREFRE
ZREFIM
URMSSTAT
IEC10000297 V1 EN
Figure 114: ROTIPHIZ function block

Table 112: ROTIPHIZ Input signals
USU GROUP - Injected voltage signal
SIGNAL
USI GROUP - Injected current signal (voltage over shunt)
SIGNAL
ZREFSEL INTEGER 1 Reference impedance selection
Table 113: ROTIPHIZ Output signals

TRIP BOOLEAN Trip (common AC and DC side of exciter)
TRIPDC BOOLEAN Trip for DC side of exciter
TRIPAC BOOLEAN Trip for AC side of exciter
START BOOLEAN Start (common AC and DC side of exciter)
STARTDC BOOLEAN Start for DC side of exciter
STARTAC BOOLEAN Start for AC side of exciter
ALARM BOOLEAN Alarm
225

ERROR BOOLEAN Error
ERRSTAT INTEGER b7=Interf,b6=I<,b5=U<,b4=IR>,b3=UR>,b2=F
Diff,b1=NoI,b0=NoU
RAVE REAL Measured resistance to earth in Ohm at inj freq
XAVE REAL Measured reactance to earth in Ohm at inj freq
FREQU REAL Measured frequency of injected voltage into rotor
RFAULT REAL Estimated fault resistance in Ohm
ZREF INTEGER Selected reference impedance number
ZREFRE REAL Used reference impedance real part in Ohm
ZREFIM REAL Used reference impedance imaginary part in Ohm
URMSSTAT BOOLEAN RMS voltage status, TRUE when > ULimRMS

Table 114: ROTIPHIZ Group settings (basic)
Operation Off - - Off Operation (On / Off) of function
On
RTrip 100 - 100000 ohm 1 1000 Trip limit of fault resistance in Ohm
RAlarm 100 - 1000000 ohm 1 10000 Alarm limit of fault resistance in Ohm
tAlarm 0.00 - 600.00 s 1.00 30.00 Alarm time delay
FactACLim 0.01 - 2.00 - 0.01 0.25 Scale factor for rotor earth fault on AC
side of exciter
tTripAC 0.000 - 60.000 s 1.000 10.000 Time delay for trip on AC side of exciter
ULimRMS 1 - 1000 V 1 100 RMS voltage level
Table 115: ROTIPHIZ Group settings (advanced)

FreqInjected 75.000 - 250.000 Hz 0.001 113.000 Injected frequency
Table 116: ROTIPHIZ Non group settings (basic)

k1Real -10000000000.000 - 0.001 10000.000 Multiplication factor k1 for calibration,
- 10000000000.000 real part
k1Imag -10000000000.000 - 0.001 0.000 Multiplication factor k1 for calibration,
- 10000000000.000 imaginary part
k2Real -10000000000.000 ohm 0.001 0.000 Addition factor k2 for calibration, real
- 10000000000.000 part in Ohm
k2Imag -10000000000.000 ohm 0.001 0.000 Addition factor k2 for calibration,
- 10000000000.000 imaginary part in Ohm
226

RefR1 0.001 - ohm 0.001 1000000.000 Reference resistance R1 in ohm
1000000000.000
RefX1 -1000000.000 - ohm 0.001 2000.000 Reference reactance X1 in ohm
1000000.000
1000000000.000
1000000.000
Table 117: ROTIPHIZ Non group settings (advanced)

FilterLength 1s - - 1s Length of filter buffer
2s

Table 118: ROTIPHIZ technical data
Fault resistance sensitivity Can be reached 500 kΩ
Typically 50 kΩ
Injection frequency (75.000 - 250.000) Hz ±0.1 Hz
Trip limit of fault resistance (100 - 100000)Ω 5% of 1 kΩ at Rf ≤ 1 kΩ
5% of set value at 1 kΩ < Rf ≤ 20 kΩ
10% of set value at Rf > 20 kΩ
Alarm limit of fault resistance (100 - 1000000)Ω 5% of 1 kΩ at Rf ≤ 1 kΩ

5% of 10 kΩ at 1 kΩ < Rf ≤ 20 kΩ
10% of set value at 20 kΩ < Rf ≤ 200 kΩ
Operate time, start 1.00 s typically -

Operate time, trip 2.00 s typically -
Alarm time delay (0.00 - 600.00) s ±0.5% ±10 ms
6.6 100% stator earth fault protection, injection based

STTIPHIZ

100% stator earth fault protection, STTIPHIZ Rse< 64S
injection based
227
6.6.1 Introduction
The 100% stator earth-fault protection STTIPHIZ is used to detect earth faults in
the stator windings of generators and motors. STTIPHIZ is applicable for
generators connected to the power system through a unit transformer in a block
connection. An independent signal with a certain frequency different from the
generator rated frequency is injected into the stator circuit. The responce of this
injected signal is used to detect stator earth faults.
To implement the above concept, a separate injection box is required. The injection
box generates a square wave voltage signal which for example can be fed into the
secondary winding of the generator neutral point voltage transformer or grounding
transformer. This signal propagates through this transformer into the stator circuit.
The magnitude of the injected voltage signal is measured on the secondary side of
the neutral point voltage transformer or grounding transformer. In addition, the
resulting injected current is measured through a resistive shunt located within the
injection box. These two measured values are fed to the IED. Based on these two
measured quantities, the IED determines the stator winding resistance to ground.
The resistance value is then compared with the preset fault resistance alarm and
trip levels.
The protection function can not only detect the earth fault at the generator star
point, but also along the stator windings and at the generator terminals, including
the connected components such as voltage transformers, circuit breakers, excitation
transformer and so on. The measuring principle used is not influenced by the
generator operating mode and is fully functional even with the generator at
standstill. It is still required to have a standard 95% stator earth-fault protection,
based on the neutral point fundamental frequency displacement voltage, operating
in parallel with the 100% stator earth-fault protection function.
Requires injection unit REX060 and optional shunt resistor unit REX062 for
correct operation.

The protection function is based on signal injection into a stator winding. These
square wave signals are generated in a separate injection unit REX060.
The injection signals are connected to the stator winding via:

• secondary winding of a voltage transformer (VT) located at the stator neutral
point
• open delta winding of a three-phase VT set located at generator terminals
• secondary winding of a distribution transformer (DT) located at the stator
neutral point; note that REX062 is typically required for such arrangement
• open delta winding of a three-phase grounding transformer (GT) located at
generator terminals; note that REX062 is typically required for such arrangement
228
In the REX060 unit the injection voltage and current signals are amplified to a
level adapted to the analogue voltage inputs of IED. In IED the measured signals
are processed and evaluation will give detection of stator faults.
6.6.2.1 Configuration principle
Figure 115 shows a typical installation for stator injection.
10
4 Step-up
Transformer
U>
Uinj 1
Rshunt
7 5
~ Generator
6
100% SEF
I
RN
U
2
9 REX060/SIM module 8
95 % SEF
REG670 IEC11000067-2-en.vsd
Generator Protection Panel
IEC11000067 V1 EN
Figure 115: Example installation for stator injection
1 Generator unit consisting of a synchronous generator and a step-up transformer

2 Grounding resistor for the stator winding
3 Neutral point VT which is used as injection point and also to provide galvanic separation
between primary circuit and injection equipment
4 Cable used to inject the square-wave signal into the stator circuit
5 Connection for measurement of injected current. This signal is amplified in REX060 before it is
given to REG670 for evaluation.
6 Cable for measurement of injected voltage at the injection point. This signal is amplified in
REX060 before it is given to REG670 for evaluation.
7 Two VT inputs into REG670 which are used to measure injected current and voltage
8 Cable for 95% stator earth-fault protection
9 Separate VT input in REG670 used for 95% stator earth-fault protection
10 Protection for excessive over-voltages posed by generator. REX060 can withstand without
damage maximum voltage of 120V and when used together with REX062 up to 240V.
229
The injection unit REX060

IED and
Injection Top view Power Back view Front view
connectors connector Keylock
LED
X11 X61 X81

1 1 1
Injection Stator
Injection Rotor
18 18
X62 X82
PSM
1 1
5 5
Power
Stator
Rotor
Backplane
Front-plate Injection LED Injection switch

HMI with logic
IEC11000015 V1 EN
Figure 116: Injection unit REX060
The REX060 unit is a common unit that can be equipped for either rotor or stator
earth fault protection, or for both. The REX060 has specific injection modules for
rotor and stator protection. The REX060 generates square wave signals, where one
is used for injection to the stator neutral point and the other to the field winding
circuit (rotor circuit), if configured for both stator and rotor protection. The injected
voltages and currents are measured by the unit and amplified, giving voltage
signals both for the injected voltage and current, and adapted to the analogue inputs
of IED. The injection unit REX060 shall be located close to the IED.
For the stator earth fault protection, there are some settings necessary for REX060:
• System frequency: 50/60 Hz

• Injected frequency for stator neutral point is settable in 1 Hz steps 50 – 250 Hz.
• VT/DT maximum fundamental frequency voltage during earth fault in the
stator winding
REX060 will also continuously check the measured signal for detection of
saturation which could cause error in the evaluation in IED. If saturation level is
reached, a binary output contact is activated, which is connected to IED. Also other
errors in injection will activate another output contact to IED for blocking the
function.
Stator injection output is protected against voltages exceeding maximum operating

range (10% of rated VT/DT) by a relay blocking the injection circuit. This blocking
remains blocked by stored status in non-volatile memory. Note REX060 is
designed to cope with such voltages of up to 120V. When optional REX062
resistor unit is used, REX060 can cope with voltages of up to 240V at injection point.
The output is also protected by a fuse. If this fuse is blown, it is caused by external
voltage source, since the injection unit cannot provide enough energy to blow this
fuse.
230
Refer to the Hardware section in this manual for a detailed description of REX060.
6.6.2.2 Generator system earthing methods
There are several principles for system earthing of synchronous generators. The
choice of earthing method depends on different factors:
• Limitation of earth fault current at stator earth fault

• Damping of transient overvoltages in the generator system
• Required insulation level to withstand overvoltage in “healthy” phases at
single phase earth fault
• Δ or Y coupled stator windings
• Connection of a single generator via a step up transformer or connection of
more than one generator via a common step up transformer
Normally the generator system has some kind of high resistance earthing, giving
earth fault current within the range 5 – 20 A, thus preventing serious damages in
case of stator earth faults. Direct earthing will give too high earth fault current
level. Isolated generator system will give risk of transient overvoltages.
Below some alternatives for generator system earthing are shown;
A B C
IEC110000066-1-en.vsd
IEC11000066 V1 EN
Figure 117: Generator earthing alternatives
A High-resistance earthing with a neutral point resistor

B Effective high-resistance earthing via a distribution transformer
C High-resistance earthing via a delta, grounded-wye transformer
These earthing alternatives are characterized by the following properties:
231
A: High-resistance earthing with a neutral point resistor
This earthing method utilizes a high resistance in the primary circuit by inserting
resistor RN between the generator neutral and the ground. The actual resistance
value of RN is generally in order of kΩ. Such high resistance is required in order to
limit the primary earth fault current to a quite small value (i.e. always < 20A and
quite often < 10A primary). Actual primary earth fault current can be calculated as
follows:
U G _ Ph - Ph
I =
3 × RN
EF_Max
EQUATION2515 V1 EN
where:
RN is the ohmic value of the primary resistor
UG_Ph-Ph is the protected generator rated phase-to-phase voltage
Typically a VT is connected in parallel with this resistor in order to measure

voltage in the stator neutral point. This VT typically has rating around 100VA and
rated secondary winding voltage of up to 120V. Note that maximum voltage on the
secondary side of this VT for an earth fault at generator terminals can be calculated
as follows:
U G _ Ph - Ph U2
U EF_Max = ×
3 U1
EQUATION2516 V1 EN
where:
U2/U1 is the turn (i.e. rated voltage) ratio of the VT
UG_Ph-Ph is the protected generator rated phase to phase voltage
B: Effective high-resistance earthing via a distribution transformer
This earthing method utilizes a distribution transformer that provides high

resistance in the primary circuit by utilizing a small resistor RN connected to the
secondary winding of the distribution transformer. The primary winding of the
distribution transformer is connected between the generator neutral and ground.
The actual resistance value RN is generally extremely small (i.e. typically < 1Ω);
however, the imposed ohmic value to the primary circuit becomes quite high (i.e.
in the order of kΩ). The equivalent resistance in the primary circuit can be
calculated as follows:
232
2
æ U1 ö
REq = ç ÷ × RN
èU2 ø
EQUATION2517 V1 EN
where:
U1/U2 is the turn (i.e. rated voltage) ratio of the distribution transformer
RN is the ohmic value of the resistor connected to the secondary winding
The distribution transformer typically has rating of several kVA (e.g. 33kVA) and
rated secondary winding voltage of up to 240V. Note that maximum voltage on the
secondary side of the distribution transformer for an earth fault at generator
terminals can be calculated as follows:
U G _ Ph - Ph U2
U EF_Max = ×
3 U1
EQUATION2516 V1 EN
where:
U2/U1 is the turn (i.e. rated voltage) ratio of the distribution transformer
Note that in case of an earth fault in the stator, the secondary current through the
RN resistor will be often in order of couple of hundred amperes. This maximum
secondary current can be calculated as follows:
U EF _ Max
I EF _ Sec =
RN
EQUATION2518 V1 EN
C: High-resistance earthing via a delta, grounded-wye transformer
This earthing method utilizes a specially constructed three-phase, five-limb power

transformer that provides high resistance in the primary circuit by utilizing a
relatively small resistor RN connected to the secondary open-delta connected
windings. The primary windings of this transformer is star (i.e. wye) connected and
this neutral point is directly connected to ground. The actual resistance value RN is
relatively small (i.e. typically < 5Ω); however, the imposed ohmic value to the
primary circuit becomes quite high (i.e. in the order of kΩ). The equivalent
resistance in the primary circuit can be calculated as follows:
233
2
æ U1 ö
REq = ç ÷ × RN
è 3 ×U 2 ø
EQUATION2519 V1 EN
where:
U1/U2 is the turn (i.e. rated voltage) ratio of one phase of the power transformer, e.g.
8 kV
3
500V
3
EQUATION2521 V1 EN
RN is the ohmic value of a resistor connected to the secondary open-delta windings
The three-phase power transformer typically has rating of several tens of kVA (e.g.
129kVA) and rated secondary winding voltage of up to 550V. Note that maximum
voltage across secondary resistor RN for an earth fault at generator terminals can
be calculated as follows:
U2
U EF_Max = 3 ×U G _ Ph - Ph ×
U1
EQUATION2520 V1 EN
where:
U2/U1 is the turn (i.e. rated voltage) ratio of one phase of the power transformer, e.g.
500V
3
8 kV
3
EQUATION2522 V1 EN
Note that in case of an earth fault in the stator, the secondary current through the
RN resistor will be often in order of couple of hundred amperes. This maximum
secondary current can be calculated as follows:
U EF _ Max
I EF _ Sec =
RN
EQUATION2518 V1 EN
For all the alternatives the 100% stator earth fault protection can be applied.
234
6.6.2.3 100% Stator earth fault protection function
The injection to the stator is schematically shown in figure 118. It should be

observed that in this figure injection equivalent circuit is also shown with all
impedances and injection generator related to the primary side of the neutral point
voltage transformer. Points a & b indicate connection terminals for the injection
equipment. Similar equivalent circuit can be drawn for all other types of generator
stator earthing shown in latter figures.
Z Bare
Z Measured
Z series Iinj
Cstat
a +
R fault
Û UN
Rf Cstat RN ZmT Uinj
-
b
Iinj
Stator Reference
+ a Impedance ZRef
RN Uinj
- b
IEC11000008 V1 EN
Figure 118: High-resistance generator earthing with a neutral point resistor
There are some alternatives for connection of the neutral point resistor as shown in
figure 119 (low voltage neutral point resistor connected via a DT).
235
Cstat
Iinj
a
+
RN Uinj
-
b
IEC11000009 V1 EN
Figure 119: Effective high-resistance generator earthing via a distribution

transformer
Another alternative is shown in figure 120 (High-resistance earthing via a delta,

grounded-wye transformer). In this case the transformer must withstand the large
secondary current caused by primary earth fault. The resistor typically has to be
divided as shown in figure 120 to limit the voltage to the injection equipment in
case of earth fault at the generator terminal. This voltage is often in the range 400 –
500 V. As the open delta connection gives three times the zero sequence phase
voltage this gives too high voltage at the injection point if the resistance is not
divided as shown in the figure 120 . By dividing the resistor in two parts it shall be
ensured that maximum voltage imposed back on injection equipment is equal to or
less than 240V.
236
I inj
a
+
RN
C stat U inj
-
b
IEC11000010 V1 EN
Figure 120: High-resistance generator earthing via a delta, grounded-wye

transformer
It is also possible to make the injection via VT open delta connection, as shown in
figure 121.
237
U1 / U2
Y
Y
Y
I inj
a
+
Rd U inj
-
C stat b
2
æU ö
R d >>çç 1 ÷÷ × R N
èU2 ø
RN
IEC11000011 V1 EN
Figure 121: Injection via open delta VT connection
It must be observed that the resistor Rd is normally applied for ferro-resonance

damping. The resistance Rd is will have very little contribution to the earth fault
current as it has high resistance. This injection principle can be used for
applications with various generator system earthing methods. It is therefore
238
recommended to make the injection via the open delta VT on the terminal side in
most applications.
Accuracy for STTIPHIZ is installation dependent and it mainly depends on the

characteristic of grounding or voltage transformer used to inject signal into the
stator. Note that large variation of the ambient temperature and variation of stator
capacitance and conductance to ground between standstill and fully loaded
machine will also limit the possible setting level for the alarm stage. As a
consequence 10 kΩ sensitivity can be typically reached without problem.
Depending on particular installation alarm sensitivity of up to 50 kΩ may be
reached at steady state operating condition of the machine.
Note that it is possible to connect two REG670 in parallel to the REX060 injection
unit in order to obtain redundant measurement in two separate IEDs. However, at
commissioning both REG670 IEDs must be connected during calibration procedure.
6.6.2.4 General measurement of earth fault impedance
From the REX060 the injected voltage and current are delivered as AC voltages to
IED. The injected voltage and current is measured and analyzed in the protection
function software within IED. The measured injected voltage and current are first
processed by means of special filtering so that the signals are referred to the
injected frequency only.
The bare complex impedance is, see fig 118:
U Inj
Z bare =
I Inj
EQUATION2500 V1 EN
An equivalent circuit for the measured impedance is shown in figure 109.
239
ZMeasured ZBare
Z series Iinj
Rf Z shunt Uinj
IEC11000003 V1 EN
Figure 122: Equivalent of the impedance measurement
In non-faulted operation Rf is very large. A “healthy” impedance is calculated as:
Z Measured = k1 × Z bare + k 2
EQUATION2501 V1 EN
For definition of k1 and k2, see figure 110
The factors k1 and k2 [Ω] are derived from measurements during commissioning,
where calibration to known fault resistance will be used to convert the
measurement to true primary impedance. The factor k1 will compensate for
transformer ratio and other factors to achieve impedance values related to the
primary system. The factor k2 [Ω] will compensate for the series impedance Zseries
The healthy impedance measured at non-faulted conditions is referred to as the

reference impedance in further text.
In IED the measured impedance is compared to the reference impedance. In case of

an earth fault, the fault impedance is estimated and compared to the set values
RAlarm and RTrip.
If the measured impedance is larger than the setting openCircuitLimit, the output
OPCIRC is set TRUE. If OPCIRC is set, it means there is a strong likelihood that
the generator neutral resistor is not anymore connected to ground, since only the
capacitive part in the circuit is left. The open circuit is only applied on the stator
winding protection. To make the open circuit limit more stable a hysteresis is
added. If OPCIRC is TRUE, the measured fault impedance must drop below open
circuit limit * (1 - OpenCircLim) to reset. The hysteresis is hidden and set to a
default value of 10% of open Circuit limit for the stator.
240
Open- circuit
characteristics
no open- circuit open- circuit
Open Circuit
Hysteresis
{Z } re
0 Measured
openCircuitLimit
IEC11000073 V1 EN
Figure 123: Open circuit characteristics
Blocking: The output OPCIRC is blocked during an error occurring and during
initialization of function.
Detailed Set: If the total measured real part of the impedance is greater than the
setting OpenCircLim the output OPCIRC is TRUE, see figure 109.
6.6.2.5 Measuring reference impedance
The healthy impedance is equal to the parallel connection of the neutral point
resistor (RN), the capacitive reactance between the stator windings and earth (1/
ωCstat), the transformer magnetization impedance (ZmT) and the earth fault
resistance (Rf). The series resistance in the injection circuit is eliminated by k2. Rf
is very large in the non-faulted case and the measured impedance is equal to the
stator reference impedance:
1 1 1
= + jw C stat +
Z ref RN Z mT
EQUATION2502 V1 EN
Where
w = 2p × finj
EQUATION2503 V1 EN
The injected frequency finj of the square wave, is a set value, deviating from the
fundamental frequency (50 or 60 Hz). The injected frequency can be set within the
range 50 – 250 Hz with recommend value 87 Hz in 50 Hz systems and 103 Hz in
60 Hz systems.
The reference impedance can vary depending on the operational state. The reason
for this can be the following:
241
• The influence from the impedance ZmT will be different when the generator is
stand-still and when it is in operation
• The capacitance to earth will vary if the generator breaker is open or closed
• The capacitance will vary if the generator is energized or not depending on
stator end winding corona protection
• Non-linearity of used injection transformer, different properties at low and
high total voltage and temperature changes
• Impedance to ground is affected by auxiliary loads connected between
generator and unit transformer. If these loads vary, the estimated earth fault
resistance will be affected.
The difference from the first reference impedance is identified by monitoring

impedance (RAVE + jXRAVE) during different operation modes. This impedance is
available as a service value from the stator function both on built-in HMI and in
ICT tool. If the difference is significant more than one reference impedance is
required. In the ICT up to five different sets of reference impedances can be
derived during commissioning for different states of operation and downloaded to
the protection function as different values of the reference impedance; RefRn and
RefXn where n = 1, 2, and up to 5. Switching of reference impedance can be made
automatically.
During commissioning ICT also makes “cross-calculations” between acquired

references, giving basically the calculated fault resistance between each existing
reference combination. This would be the fault resistance measured by the function
when the reference change occurs from one reference to another if the real
generator impedance stays the same, in other words a worst case scenario.
RMS voltage (rmsVolt) value at the injection point can be used for detecting when
a reference needs to be changed and logical outputs can be set to reflect whether
the RMS voltage is higher or lower than a prescribed value. There is one such
output for the voltage signal and one for the current signal. It is advantageous to
use RMS to determine a change of machine condition because the RMS makes a
distinction between the measured values and the total amplitude of the signal. The
standstill condition only contains the injected frequency, while the full load
condition and full speed condition contains other frequencies, which amplitudes
may change under varying machine conditions.
In case of a stator earth fault with fault impedance Zf the measured admittance will
be:
1 1 1
= +
Z Z ref Zf
EQUATION2513 V1 EN
and this gives:
242
1 1 1
= -
Zf Z Z ref
EQUATION2514 V1 EN
and the real part gives the fault conductance:
1 æ1 1 ö
= Re ç - ÷
Rf ç ÷
è Z Z ref ø
EQUATION2421 V1 EN
In the settings there are given two resistance levels:
• RAlarm given in Ω. If
R f < RAlarm
EQUATION2524 V1 EN
an alarm signal ALARM is given after a set delay tAlarm.

• RTrip given in Ω. If
R f < RTrip
EQUATION2523 V1 EN
a start signal START is given.
If the fault resistance is slightly below the set value RTrip the trip time will be
about 10 s with default filter length of 1 s. If the fault resistance is estimated to 0 Ω
the trip delay will be 2 s with default filter length of 1 s. For values in between the
delay will follow linear interpolation describing the fault resistance time relation,
as shown in figure 124.
Note that actual tripping time is dependent on the set parameter FilterLength which
has default value of 1s.
243
Trip time
10 × FilterLength
2 × FilterLength
Fault resistance
RTrip RAlarm
IEC11000002 V1 EN
Figure 124: Trip time characteristic as function of fault resistance
During run-up and shut down of the generator, i.e. when the rotational speed of the
generator changes, there will occur harmonic voltages with varying frequency at
the injection equipment connection point (for example see voltage generator Un in
Figure 118). If such frequencies interfere with the injected frequency this might
create an error in the fault resistance estimation. Such situations are identified in
the function and the function is automatically stabilized to prevent unwanted
operation of the protection.
In connection with this calibration the reference impedance is also derived.
It is possible to have up to five different reference impedances. The need to change

reference impedance is due to different operating conditions for the generator, for
instance:
1. Generator stand still
2. Generator running, not synchronized to the power network
3. Generator in normal operation, synchronized to the power network
The following automatic choice for the actual reference impedance can for
example be made:
244
• Generator voltage < set value and generator circuit breaker open: Reference
impedance 1
• Generator voltage > set value and generator circuit breaker open: Reference
impedance 2
• Generator voltage > set value and generator circuit breaker closed: Reference
impedance 3
The monitoring, enabled in ICT, will give indication if several reference

impedance values are needed.
From the measured impedance the stator earth fault resistance can be estimated
since the reference impedance is known. An alarm level (Ω) is set at a higher value
and the ALARM signal is activated after a set alarm delay time. A trip level (Ω) is
also set at a lower value. When the trip level is reached a TRIP signal is activated
as shown in figure 124.
245
6.6.2.6 Simplified logic diagram
STTIPHIZ
Uinj
Rshunt
2
1
3
4
6 5
I Inj u_i_sef
Rf Z Measured
Z Bare I
X
Compare & S U Inj u_u_sef
Evaluate
K2 K1
U
ZRef1
7 ZRef2
ZRef3 REX060
ZRef4
SELECT REFERENCE
ZRef5
tON=0.5s UN un
95% Trip a U
t a>b
b
UN> = 5% 8
9
95% Stator earth fault protection
REG670
IEC10000325 V1 EN
Figure 125: Simplified logic diagram for 100% stator earth fault protection
STTIPHIZ
1 The 100% stator earth fault protection function receives amplified injected voltage and
current via the REX060 unit as two voltage signals. (Voltage inputs in the REG670).
2 The phasor of injected voltage UInj and phasor of injected current IInj is calculated by using
special filter from raw samples. Observe that phasors are calculated for the injected
frequency.
3 The complex bare impedance is calculated from Uinj / Iinj.
4, 5 The complex measured impedance is derived as ZMeasured = Zbare*k1 + k2.
6 The fault resistance (RFault) is calculated from the complex measured impedance and a
selected complex reference.
7 Selection of one (out of maximum 5) ZRef.
8 Fourier filter to derive the phasor of zero sequence voltage at fundamental frequency
9 The 95% stator earth fault zero sequence over voltage function must operate in parallel
with STTIPHIZ.
246
Rf tAlarm
a
a<b t ALARM
b OR
RAlarm
a TRIP
a<b
b
RTrip
IEC10000326 V1 EN
Figure 126: STTIPHIZ alarm and trip logic
If the fault impedance Rf is smaller than RAlarm and last longer than set alarm delay
(using delay-on), output ALARM is set. If the fault impedance Rf is smaller than
RTrip, output signal TRIP is set after the calculated time. For trip time delay, see fig
124
6.6.2.7 The commissioning tool ICT
The 100% earth fault protection function in REG670 require a number of settings.
The settings k1, k2 and the reference impedance require measurements made on the
generator and protection set-up. This has to be done during commissioning of the
protection. The factors are derived in connection to calibration measurements
during commissioning. In connection with this calibration also the reference
impedance is derived. To do this the ICT tool (Injection Commissioning Tool) has
to be used. This tool is an integrated part of the PCM600 tool.
Further more, ICT also helps the commissioning engineer to perform successful
installation trough its validating capabilities. Underneath the shell, during
installation, commissioning and calibration, ICT performs various tests using
signal analysis, to verify that the installation itself is acceptable and calibration has
been performed in the right manner. Besides carrying out the actual tests, ICT also
gives the commissioning engineer tips if possible issues may occur during the
commissioning stage.
When ICT is started, 100% stator earth fault protection is chosen for the
commissioning of this function.
247
There are five different parts that needs to be performed using the ICT tool:
1. Installing
2. Calibrating
3. Commissioning
4. Monitoring
5. Auditing
Installing
The injection is started and level of injected voltage and current is checked if they
are within the permissible range. If not the settings of the injection unit REX060
must be adjusted. Also the injection frequency is checked and stored for use in ICT
and in IED.
Calibration
The calibration is based on three measurement sessions:
Step 1: Injection is made to the non-faulted generator and the measured complex impedance is
stored.
Step 2: A resistor with known resistance is connected between the primary object (stator circuit).
Injection is made to the generator and the measured complex impedance is stored.
Step 3: The primary object (stator circuit) is directly short circuited to earth. Injection is made to
the generator and the measured complex impedance is stored.
The sequence of the calibration session follows a scheme shown in the tool.
After the three measurements ICT calculates the complex factors k1 and k2. The
first reference impedance RefR1 + jRefX1 is also calculated. After this the values
are downloaded to the parameter setting part of the PCM600 tool. From PCM600
the setting can be downloaded to IED.
It is important to save the settings after download to IED, otherwise the ICT cannot
perform the correct calculations. ICT compares settings in PCM600 and IED each
time a measurement is started, if these are not equal, no measurement should be made.
During the three measurements described above a check is made that there are
sufficient changes in the measured impedance in order to guarantee that the
function is capable of detecting a fault in the actual installation.
Now the reference impedance is derived for one operational state. It might be
reasonable to make measurements to derive reference impedance for other
operational cases. This is done under the point Commissioning described below.
Commissioning
There is a possibility to have up to five different reference impedances. The need to

change reference impedance is different operating conditions for the generator:
248
• Generator stand still

• Generator running up, not synchronized to the network
• Generator normal operation
Comment: The capacitance will change when switching in breaker between step-up
transformer and generator.
It might therefore be necessary to find reference impedances for different operation

states. In the commissioning part of ICT this can be done. For each operation state
of interest a measurement is performed. If the reference impedance differs from the
first one, calculated under the calibration session, the new reference impedance is
stored by the command; Submit to Parameter setting. It is possible to derive up to 5
different reference impedances to be used at different operation states of the generator.
Neutral point RMS voltage (rmsVolt) can be used for detecting when a reference
needs to be changed and logical outputs can be set to reflect whether the RMS
voltage is higher or lower than a prescribed value. There is one such output for the
voltage signal and one for the current signal
If more than one reference impedance is to be used there must be logics configured
to detect changes in operation states where the reference impedance shall be
changed. Further, the monitoring part should be consulted if the sensitivity to earth
faults is to be set at the highest possible value as this depends on the properties of
the individual site.
Monitoring
In the monitoring part the calibration can be checked. It is also possible to identify
operational states where change of reference impedances is required.
Auditing
In the auditing part reports from calibration and commissioning are made.
6.6.3 Description of input signals

The inputs to the 100% stator earth fault protection function block are as shown in
the table.
249
Table 119: Description of various inputs

Input signal Description
USU The measured injection voltage. This signal is taken from a pre-processor block, the AI
output. The analog voltage input AI1 is linked to the phase L1 in the pre-processor
block in the Signal Matrix tool.
USI The measured injection current. This signal is taken from a pre-processor block, the AI
output. In the pre-configured version, the analog voltage input AI2 is linked to the
phase L2 in the pre-processor block in the Signal Matrix tool.
BLOCK Input to block the function
ZREFSEL The selection of any of the pre-defined reference impedances. The reference
impedance can differ, for example, with the generator breaker open or closed.
Therefore, there is a possibility to change from one set reference impedance to
another. Five different reference impedances are available.
6.6.4 Description of output signals

The outputs of the 100% stator earth fault protection function block are as shown in
the table.
Table 120: Description of various outputs

TRIP Trip command signal
START Signal activated, if the calculated fault resistance gets lower than the set level
ALARM Signal activated after a set time delay, if the calculated fault resistance gets lower
than the set alarm level
OPCIRC Signal indicating open stator injection circuit (interruption)
ERROR Error signal which is boolean with values 0 and 1
ERRSTAT Status coded signal giving type of error. See below table
RAVE Measured stator resistance to earth in Ω at an injected frequency (real part of the
complex impedance)
XAVE Measured stator reactance to earth in Ω at the injected frequency (imaginary part of
the complex impedance)
FREQU Measured frequency of the injected voltage
RFAULT Estimated fault resistance in Ω
ZREF Selected reference impedance number
ZREFRE The real part (resistance) of the used reference impedance
ZREFIM The imaginary part (reactance) of the used reference impedance
URMSSTAT This signal is set true, if the measured RMS voltage is larger than the set limit ULimRMS
IRMSSTAT This signal is set true, if the measured RMS current is larger than the set limit ILimRMS
ERRSTAT output signal
Convert the integer output signal to binary and see table below for interpretation of
individual bits:
250
Table 121: Definition of errors

ERRSTAT output integer
Priority 3 Priority 2 Priority 3 Priority 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Interfer- Under- Under- Over- Over- Frequ- No No
ence current voltage current voltage ency current voltage
detected difference
The ERRSTAT description will be shown in clear text in ICT.
The priority of the signals is set that the group priority 1 overrides the group
priority 2 and 3, and priority 2 overrides priority 3. Note that the ERRSTAT signal
can enable several error cases at the same time.
Following errors is detected and derived in the Error block:
• B0 = Injected voltage signal not found

• B1 = Injected current signal not found
• B2 = Voltage and current signal frequency differs
• B3 = Measured total RMS voltage too high
• B4 = Measured total RMS current too high
• B5 = Injected voltage signal too low
• B6 = Injected current signal too low
• B7 = External interference voltage detected
ERRSTAT = BitToInt[B7,…,B1,B0] The priority of the error conditions that will

be flagged out:
• Prio1 = B0, B1
• Prio2 = B3, B4, B5, B6
• Prio3 = B2, B7

STTIPHIZ
USU* TRIP
USI* START
BLOCK ALARM
ZREFSEL OPCIRC
ERROR
ERRSTAT
RAVE
XAVE
FREQU
RFAULT
ZREF
ZREFRE
ZREFIM
URMSSTAT
IEC10000298 V1 EN
Figure 127: STTIPHIZ function block
251
6.6.6 Input and Output signals

Table 122: STTIPHIZ Input signals
USU GROUP - Injected voltage signal
SIGNAL
USI GROUP - Injected current signal (voltage over shunt)
SIGNAL
ZREFSEL INTEGER 1 Reference impedance selection
Table 123: STTIPHIZ Output signals

TRIP BOOLEAN Trip
START BOOLEAN Start
ALARM BOOLEAN Alarm
OPCIRC BOOLEAN Injection circuit open
ERROR BOOLEAN Error
ERRSTAT INTEGER b7=Interf,b6=I<,b5=U<,b4=IR>,b3=UR>,b2=F
Diff,b1=NoI,b0=NoU
RAVE REAL Measured resistance to earth in Ohm at inj freq
XAVE REAL Measured reactance to earth in Ohm at inj freq
FREQU REAL Measured frequency of injected voltage into stator
RFAULT REAL Estimated fault resistance in Ohm
ZREF INTEGER Selected reference impedance number
ZREFRE REAL Used reference impedance real part in Ohm
ZREFIM REAL Used reference impedance imaginary part in Ohm
URMSSTAT BOOLEAN RMS voltage status, TRUE when > ULimRMS

Table 124: STTIPHIZ Group settings (basic)
Operation Off - - Off Operation (On / Off) of function
On
RTrip 100 - 10000 ohm 1 1000 Trip limit of fault resistance in Ohm
RAlarm 100 - 100000 ohm 1 5000 Alarm limit of fault resistance in Ohm
tAlarm 0.00 - 600.00 s 1.00 30.00 Alarm time delay
OpenCircLim 100 - 10000000 ohm 1 10000000 Open circuit limit in Ohm
ULimRMS 1 - 1000 V 1 100 RMS voltage level
252
Table 125: STTIPHIZ Group settings (advanced)

FreqInjected 50.000 - 250.000 Hz 0.001 87.000 Injected frequency
Table 126: STTIPHIZ Non group settings (basic)

k1Real -10000000000.000 - 0.001 10000.000 Multiplication factor k1 for calibration,
- 10000000000.000 real part
k1Imag -10000000000.000 - 0.001 0.000 Multiplication factor k1 for calibration,
- 10000000000.000 imaginary part
k2Real -10000000000.000 ohm 0.001 0.000 Addition factor k2 for calibration, real
- 10000000000.000 part in Ohm
k2Imag -10000000000.000 ohm 0.001 0.000 Addition factor k2 for calibration,
- 10000000000.000 imaginary part in Ohm
1000000000.000
1000000.000
1000000000.000
1000000.000
1000000000.000
1000000.000
1000000000.000
1000000.000
1000000000.000
1000000.000
Table 127: STTIPHIZ Non group settings (advanced)

FilterLength 1s - - 1s Length of filter buffer
2s
253

Table 128: STTIPHIZ technical data
Fault resistance sensitivity Can be reached at 50 kΩ
steady state operating
condition of the
machine
Typically 10 kΩ
Injection frequency (50.000 - 250.000) Hz ±0.1 Hz
Trip limit of fault resistance (100 - 10000)Ω ±5% of 1 kΩ at Rf ≤ 1 kΩ
±10% of set value at Rf > 1 kΩ
Alarm limit of fault resistance (100 - 100000)Ω ±5% of 1 kΩ at Rf ≤ 1 kΩ

±10% of 10 kΩ at 1 kΩ < Rf ≤ 10 kΩ
±50% of set value at Rf > 10 kΩ
Operate time, start 1.00 s typically -

Operate time, trip 2.00 s typically -
Alarm time delay (0.00 - 600.00) s ±0.5% ±10 ms
254
Current protection
Section 7 Current protection
About this chapter

This chapter describes current protection functions. These include functions like
Instantaneous phase overcurrent protection, Four step phase overcurrent protection,
Pole discordance protection and Residual overcurrent protection.
7.1 Instantaneous phase overcurrent protection PHPIOC

Instantaneous phase overcurrent PHPIOC 50
protection
3I>>
SYMBOL-Z V1 EN
7.1.1 Introduction
The instantaneous three phase overcurrent function has a low transient overreach
and short tripping time to allow use as a high set short-circuit protection function.

The sampled analogue phase currents are pre-processed in a discrete Fourier filter
(DFT) block. The RMS value of each phase current is derived from the
fundamental frequency components, as well as sampled values of each phase
current. These phase current values are fed to the instantaneous phase overcurrent
protection function PHPIOC. In a comparator the RMS values are compared to the
set operation current value of the function (IP>>). If a phase current is larger than
the set operation current a signal from the comparator for this phase is set to true.
This signal will, without delay, activate the output signal TRLn (n=1,2,3) for this
phase and the TRIP signal that is common for all three phases.
There is an operation mode (OpMode) setting: 1 out of 3 or 2 out of 3. If the

parameter is set to 1 out of 3 any phase trip signal will be activated. If the
parameter is set to 2 out of 3 at least two phase signals must be activated for trip.
There is also a possibility to activate a preset change of the set operation current
(StValMult) via a binary input (ENMULT). In some applications the operation
value needs to be changed, for example due to transformer inrush currents.
255
Current protection
PHPIOC can be blocked from the binary input BLOCK.

PHPIOC
I3P* TRIP
BLOCK TRL1
ENMULT TRL2
TRL3
IEC04000391 V2 EN
Figure 128: PHPIOC function block

Table 129: PHPIOC Input signals
I3P GROUP - Three phase current
SIGNAL
ENMULT BOOLEAN 0 Enable current start value multiplier
Table 130: PHPIOC Output signals

TRIP BOOLEAN Trip signal from any phase
TRL1 BOOLEAN Trip signal from phase L1

Table 131: PHPIOC Group settings (basic)
On
OpMode 2 out of 3 - - 1 out of 3 Select operation mode 2-out of 3 / 1-out
1 out of 3 of 3
IP>> 1 - 2500 %IB 1 200 Operate phase current level in % of IBase
Table 132: PHPIOC Group settings (advanced)

StValMult 0.5 - 5.0 - 0.1 1.0 Multiplier for operate current level
256
Current protection

Table 133: PHPIOC technical data
Operate current (1-2500)% of lBase ± 1.0% of Ir at I £ Ir
± 1.0% of I at I > Ir
Reset ratio > 95% -

Operate time 25 ms typically at 0 to 2 x Iset -
Reset time 25 ms typically at 2 to 0 x Iset -
Critical impulse time 10 ms typically at 0 to 2 x Iset -
Dynamic overreach < 5% at t = 100 ms -
7.2 Four step phase overcurrent protection OC4PTOC

Four step phase overcurrent protection OC4PTOC 51/67
3I>
4
alt
4
TOC-REVA V1 EN
7.2.1 Introduction
The four step phase overcurrent protection function OC4PTOC has an inverse or
definite time delay independent for step 1 and 4 separately. Step 2 and 3 are always
definite time delayed.
All IEC and ANSI inverse time characteristics are available together with an
optional user defined time characteristic.
The directional function is voltage polarized with memory. The function can be set
to be directional or non-directional independently for each of the steps.
A 2nd harmonic blocking can be set individually for each step.

The Four step overcurrent protection function OC4PTOC is divided into four
different sub-functions, one for each step. For each step x , where x is step 1, 2, 3
257
Current protection
and 4, an operation mode is set by DirModex: Off/Non-directional/Forward/

Reverse.
The protection design can be decomposed in four parts:
• The direction element

• The harmonic Restraint Blocking function
• The four step over current function
• The mode selection
If VT inputs are not available or not connected, setting parameter

DirModex shall be left to default value, Non-directional.
4 step over current

Direction dirPh1Flt element faultState
faultState
Element One element for each
dirPh2Flt step
I3P dirPh3Flt START
U3P
TRIP
Harmonic harmRestrBlock
I3P Restraint
Element
enableDir
Mode Selection
enableStep1-4
DirectionalMode1-4
en05000740.vsd
IEC05000740 V1 EN
Figure 129: Functional overview of OC4PTOC
A common setting for all steps, StartPhSel, is used to specify the number of phase
currents to be high to enable operation. The settings can be chosen: 1 out of 3, 2 out
of 3 or 3 out of 3.
258
Current protection
The sampled analogue phase currents are processed in a pre-processing function

block. Using a parameter setting MeasType within the general settings for the four
step phase overcurrent protection function OC4PTOC, it is possible to select the
type of the measurement used for all overcurrent stages. It is possible to select
either discrete Fourier filter (DFT) or true RMS filter (RMS).
If DFT option is selected then only the RMS value of the fundamental frequency
components of each phase current is derived. Influence of DC current component
and higher harmonic current components are almost completely suppressed. If
RMS option is selected then the true RMS values is used. The true RMS value in
addition to the fundamental frequency component includes the contribution from
the current DC component as well as from higher current harmonic. The selected
current values are fed to OC4PTOC.
In a comparator, for each phase current, the DFT or RMS values are compared to
the set operation current value of the function (I1>, I2>, I3> or I4>). If a phase
current is larger than the set operation current, outputs START, STx, STL1, STL2
and STL3 are, without delay, activated. Output signals STL1, STL2 and STL3 are
common for all steps. This means that the lowest set step will initiate the
activation. The START signal is common for all three phases and all steps. It shall
be noted that the selection of measured value (DFT or RMS) do not influence the
operation of directional part of OC4PTOC.
Service value for individually measured phase currents are also available on the
local HMI for OC4PTOC function, which simplifies testing, commissioning and in
service operational checking of the function.
A harmonic restrain of the function can be chosen. A set 2nd harmonic current in
relation to the fundamental current is used. The 2nd harmonic current is taken from
the pre-processing of the phase currents and the relation is compared to a set
restrain current level.
The function can be directional. The direction of the fault current is given as
current angle in relation to the voltage angle. The fault current and fault voltage for
the directional function is dependent of the fault type. To enable directional
measurement at close in faults, causing low measured voltage, the polarization
voltage is a combination of the apparent voltage (85%) and a memory voltage
(15%). The following combinations are used.
Phase-phase short circuit:
U refL1L 2 = U L1 - U L 2 I dirL1L 2 = I L1 - I L 2
U refL 2 L 3 = U L 2 - U L 3 I dirL 2 L 3 = I L 2 - I L 3
U refL 3 L1 = U L 3 - U L1 I dirL 3 L1 = I L 3 - I L1
259
Current protection
Phase-earth short circuit:
U refL1 = U L1 I dirL1 = I L1
U refL 2 = U L 2 I dirL 2 = I L 2
U refL 3 = U L 3 I dirL 3 = I L 3
The polarizing voltage is available as long as the positive-sequence voltage

exceeds 4% of the set base voltage UBase. So the directional element can use it for
all unsymmetrical faults including close-in faults.
For close-in three-phase faults, the U1L1M memory voltage, based on the same
positive sequence voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is
restored.
After 100 ms, the following occurs:
• If the current is still above the set value of the minimum operating current
(between 10 and 30% of the set terminal rated current IBase), the condition
seals in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element
in the reverse direction remains in operation.
• If the current decreases below the minimum operating value, the memory
resets until the positive sequence voltage exceeds 10% of its rated value.
The directional setting is given as a characteristic angle AngleRCA for the function
and an angle window AngleROA.
260
Current protection
Reverse
Uref
RCA
ROA
ROA Forward
Idir
en05000745.vsd
IEC05000745 V1 EN
Figure 130: Directional characteristic of the phase overcurrent protection
The default value of AngleRCA is –65°. The parameters AngleROA gives the angle
sector from AngleRCA for directional borders.
A minimum current for directional phase start current signal can be set:
IminOpPhSel.
If no blockings are given the start signals will start the timers of the step. The time
characteristic for each step can be chosen as definite time delay or inverse time
characteristic. A wide range of standardized inverse time characteristics is
available. It is also possible to create a tailor made time characteristic. The
possibilities for inverse time characteristics are described in section "Inverse
characteristics".
All four steps in OC4PTOC can be blocked from the binary input BLOCK. The
binary input BLKSTx (x=1, 2, 3 or 4) blocks the operation of respective step.
Different types of reset time can be selected as described in section "Inverse

characteristics".
There is also a possibility to activate a preset change (IxMult x= 1, 2, 3 or 4) of the

set operation current via a binary input (enable multiplier). In some applications the
operation value needs to be changed, for example due to changed network
switching state. The function can be blocked from the binary input BLOCK. The
start signals from the function can be blocked from the binary input BLKST. The
trip signals from the function can be blocked from the binary input BLKTR.
261
Current protection

OC4PTOC
I3P* TRIP
U3P* TR1
BLOCK TR2
BLKTR TR3
BLKST1 TR4
BLKST2 TRL1
BLKST3 TRL2
BLKST4 TRL3
ENMULT1 TR1L1
ENMULT2 TR1L2
ENMULT3 TR1L3
ENMULT4 TR2L1
TR2L2
TR2L3
TR3L1
TR3L2
TR3L3
TR4L1
TR4L2
TR4L3
START
ST1
ST2
ST3
ST4
STL1
STL2
STL3
ST1L1
ST1L2
ST1L3
ST2L1
ST2L2
ST2L3
ST3L1
ST3L2
ST3L3
ST4L1
ST4L2
ST4L3
2NDHARM
DIRL1
DIRL2
DIRL3
IEC06000187 V2 EN
Figure 131: OC4PTOC function block

Table 134: OC4PTOC Input signals
I3P GROUP - Group signal for current input
SIGNAL
U3P GROUP - Group signal for voltage input
SIGNAL
BLKST1 BOOLEAN 0 Block of Step1
262
Current protection

ENMULT1 BOOLEAN 0 When activated, the current multiplier is in use for
step1
step2
step3
step4
Table 135: OC4PTOC Output signals

TRIP BOOLEAN Trip
TR1 BOOLEAN Common trip signal from step1
TR1L1 BOOLEAN Trip signal from step1 phase L1
START BOOLEAN General start signal
ST1 BOOLEAN Common start signal from step1
263
Current protection

ST1L1 BOOLEAN Start signal from step1 phase L1
2NDHARM BOOLEAN Block from second harmonic detection
DIRL1 INTEGER Direction for phase1

Table 136: OC4PTOC Group settings (basic)
On
AngleRCA 40 - 65 Deg 1 55 Relay characteristic angle (RCA)
AngleROA 40 - 89 Deg 1 80 Relay operation angle (ROA)
StartPhSel 1 out of 3 - - 1 out of 3 Number of phases required for op (1 of
2 out of 3 3, 2 of 3, 3 of 3)
3 out of 3
DirMode1 Off - - Non-directional Directional mode of step 1 (off, nodir,
Non-directional forward, reverse)
Forward
Reverse
264
Current protection

Characterist1 ANSI Ext. inv. - - ANSI Def. Time Selection of time delay curve type for
ANSI Very inv. step 1
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
I1> 1 - 2500 %IB 1 1000 Phase current operate level for step1 in
% of IBase
t1 0.000 - 60.000 s 0.001 0.000 Definitive time delay of step 1
k1 0.05 - 999.00 - 0.01 0.05 Time multiplier for the inverse time delay
for step 1
IMin1 1 - 10000 %IB 1 100 Minimum operate current for step1 in %
of IBase
t1Min 0.000 - 60.000 s 0.001 0.000 Minimum operate time for inverse curves
for step 1
I1Mult 1.0 - 10.0 - 0.1 2.0 Multiplier for current operate level for
step 1
Forward
Reverse
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
% of IBase
265
Current protection

for step 2
of IBase
for step 2
step 2
Forward
Reverse
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
% of IBase
for step 3
of IBase
for step 3
step 3
Forward
Reverse
266
Current protection

ANSI Norm. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
% of IBase
for step 4
of IBase
for step 4
step 4
Table 137: OC4PTOC Group settings (advanced)

IMinOpPhSel 1 - 100 %IB 1 7 Minimum current for phase selection in
% of IBase
2ndHarmStab 5 - 100 %IB 1 20 Operate level of 2nd harm restrain op in
% of Fundamental
ResetTypeCrv1 Instantaneous - - Instantaneous Selection of reset curve type for step 1
IEC Reset
ANSI reset
tReset1 0.000 - 60.000 s 0.001 0.020 Reset time delay used in IEC Definite
Time curve step 1
tPCrv1 0.005 - 3.000 - 0.001 1.000 Parameter P for customer programmable
curve for step 1
tACrv1 0.005 - 200.000 - 0.001 13.500 Parameter A for customer programmable
curve for step 1
tBCrv1 0.00 - 20.00 - 0.01 0.00 Parameter B for customer programmable
curve for step 1
tCCrv1 0.1 - 10.0 - 0.1 1.0 Parameter C for customer
programmable curve for step 1
tPRCrv1 0.005 - 3.000 - 0.001 0.500 Parameter PR for customer
267
Current protection

tTRCrv1 0.005 - 100.000 - 0.001 13.500 Parameter TR for customer
tCRCrv1 0.1 - 10.0 - 0.1 1.0 Parameter CR for customer
HarmRestrain1 Off - - Off Enable block of step 1 from harmonic
On restrain
IEC Reset
ANSI reset
Time curve step 2
curve for step 2
curve for step 2
curve for step 2
On restrain
IEC Reset
ANSI reset
Time curve step 3
curve for step 3
curve for step 3
curve for step 3
HarmRestrain3 Off - - Off Enable block of step3 from harmonic
On restrain
268
Current protection

IEC Reset
ANSI reset
Time curve step 4
curve for step 4
curve for step 4
curve for step 4
On restrain
Table 138: OC4PTOC Non group settings (basic)

MeasType DFT - - DFT Selection between DFT and RMS
RMS measurement

Table 139: OC4PTOC technical data
Function Setting range Accuracy
Operate current (1-2500)% of lBase ± 1.0% of Ir at I ≤ Ir
± 1.0% of I at I > Ir
Reset ratio > 95% -

Min. operating current (1-100)% of lBase ± 1.0% of Ir at I ≤ Ir
±1.0% of I at I > Ir
Relay characteristic angle (RCA) (-70.0– -50.0) degrees ± 2.0 degrees

Maximum forward angle (40.0–70.0) degrees ± 2.0 degrees
Minimum forward angle (75.0–90.0) degrees ± 2.0 degrees
2nd harmonic blocking (5–100)% of fundamental ± 2.0% of Ir
Independent time delay (0.000-60.000) s ± 0.5% ±10 ms

Minimum operate time (0.000-60.000) s ± 0.5% ±10 ms
269
Current protection

Inverse characteristics, see 19 curve types See table 582, table 583 and
table 582, table 583 and table table 584
584
Operate time, start function 25 ms typically at 0 to 2 x Iset -
Reset time, start function 25 ms typically at 2 to 0 x Iset -
Impulse margin time 15 ms typically -
7.3 Instantaneous residual overcurrent protection

EFPIOC

Instantaneous residual overcurrent EFPIOC 50N
protection
IN>>
IEF V1 EN
7.3.1 Introduction
The Instantaneous residual overcurrent protection EFPIOC has a low transient
overreach and short tripping times to allow the use for instantaneous earth-fault
protection, with the reach limited to less than the typical eighty percent of the line
at minimum source impedance. EFPIOC can be configured to measure the residual
current from the three-phase current inputs or the current from a separate current
input. EFPIOC can be blocked by activating the input BLOCK.

The sampled analog residual currents are pre-processed in a discrete Fourier filter
(DFT) block. From the fundamental frequency components of the residual current,
as well as from the sample values the equivalent RMS value is derived. This
current value is fed to the Instantaneous residual overcurrent protection (EFPIOC).
In a comparator the RMS value is compared to the set operation current value of
the function (IN>>). If the residual current is larger than the set operation current a
signal from the comparator is set to true. This signal will, without delay, activate
the output signal TRIP.
There is also a possibility to activate a preset change of the set operation current
via a binary input (enable multiplier MULTEN). In some applications the operation
value needs to be changed, for example due to transformer inrush currents.
270
Current protection
EFPIOC function can be blocked from the binary input BLOCK. The trip signals
from the function can be blocked from the binary input BLKAR, that can be
activated during single pole trip and autoreclosing sequences.

EFPIOC
I3P* TRIP
BLOCK
BLKAR
MULTEN
IEC06000269 V2 EN
Figure 132: EFPIOC function block

Table 140: EFPIOC Input signals
I3P GROUP - Three phase currents
SIGNAL
BLKAR BOOLEAN 0 Block input for auto reclose
MULTEN BOOLEAN 0 Enable current multiplier
Table 141: EFPIOC Output signals

TRIP BOOLEAN Trip signal

Table 142: EFPIOC Group settings (basic)
On
IN>> 1 - 2500 %IB 1 200 Operate residual current level in % of
IBase
Table 143: EFPIOC Group settings (advanced)

StValMult 0.5 - 5.0 - 0.1 1.0 Multiplier for operate current level
271
Current protection

Table 144: EFPIOC technical data
± 1.0% of I at I > Ir
Reset ratio > 95% -

Dynamic overreach < 5% at t = 100 ms -
7.4 Four step residual overcurrent protection EF4PTOC

Four step residual overcurrent EF4PTOC IN 51N/67N
protection
4
alt
4
TEF-REVA V1 EN
7.4.1 Introduction
The four step residual overcurrent protection EF4PTOC has an inverse or definite
time delay independent for each step separately.
All IEC and ANSI time-delayed characteristics are available together with an
optional user defined characteristic.
The directional function includes 3 options

• voltage polarized
• current polarized
• dual polarized
EF4PTOC can be set directional or non-directional independently for each of the

steps.
Second harmonic blocking can be set individually for each step.
272
Current protection
EF4PTOC can be used as main protection for phase-to-earth faults.
EF4PTOC can also be used to provide a system back-up for example, in the case of
the primary protection being out of service due to communication or voltage
transformer circuit failure.
Directional operation can be combined together with corresponding

communication logic in permissive or blocking teleprotection scheme. Current
reversal and weak-end infeed functionality are available as well.
EF4PTOC can be configured to measure the residual current from the three-phase
current inputs or the current from a separate current input.

This function has the following three “Analog Inputs” on its function block in the
configuration tool:
1. I3P, input used for “Operating Quantity”.

2. U3P, input used for “Voltage Polarizing Quantity”.
3. I3PPOL, input used for “Current Polarizing Quantity”.
These inputs are connected from the corresponding pre-processing function blocks
in the Configuration Tool within PCM600.
7.4.2.1 Operating quantity within the function
The function always uses Residual Current (3I0) for its operating quantity. The
residual current can be:
1. directly measured (when a dedicated CT input of the IED is connected in

PCM600 to the fourth analog input of the pre-processing block connected to
EF4PTOC function input I3P). This dedicated IED CT input can be for
example, connected to:
• parallel connection of current instrument transformers in all three phases
(Holm-Green connection).
• one single core balance, current instrument transformer (cable CT).
• one single current instrument transformer located between power system
star point and earth (that is, current transformer located in the star point
of a star connected transformer winding).
• one single current instrument transformer located between two parts of a
protected object (that is, current transformer located between two star
points of double star shunt capacitor bank).
2. calculated from three-phase current input within the IED (when the fourth
analog input into the pre-processing block connected to EF4PTOC function
Analog Input I3P is not connected to a dedicated CT input of the IED in
PCM600). In such case the pre-processing block will calculate 3I0 from the
first three inputs into the pre-processing block by using the following formula:
273
Current protection
Iop = 3I0 = IL1 + IL2 + IL3

where:
IL1, IL2 and IL3 are fundamental frequency phasors of three individual phase currents.
The residual current is pre-processed by a discrete Fourier filter. Thus the phasor of
the fundamental frequency component of the residual current is derived. The
phasor magnitude is used within the EF4PTOC protection to compare it with the
set operation current value of the four steps (IN1>, IN2>, IN3> or IN4>). If the
residual current is larger than the set operation current and the step is used in non-
directional mode a signal from the comparator for this step is set to true. This
signal will, without delay, activate the output signal STINx (x=step 1-4) for this
step and a common START signal.
7.4.2.2 Internal polarizing
A polarizing quantity is used within the protection in order to determine the

direction to the earth fault (Forward/Reverse).
The function can be set to use voltage polarizing, current polarizing or dual polarizing.
Voltage polarizing
When voltage polarizing is selected the protection will use the residual voltage
-3U0 as polarizing quantity U3P. This voltage can be:
1. directly measured (when a dedicated VT input of the IED is connected in

EF4PTOC function input U3P). This dedicated IED VT input shall be then
connected to open delta winding of a three phase main VT.
2. calculated from three phase voltage input within the IED (when the fourth
analog input into the pre-processing block connected to EF4PTOC analog
function input U3P is NOT connected to a dedicated VT input of the IED in
PCM600). In such case the pre-processing block will calculate -3U0 from the
UPol = -3U 0 = -(UL1 + UL2 + UL3)

where:
UL1, UL2 and UL3 are fundamental frequency phasors of three individual phase voltages.
Note! In order to use this all three phase-to-earth voltages must be connected to three IED VT inputs.
274
Current protection
The residual voltage is pre-processed by a discrete fourier filter. Thus, the phasor
of the fundamental frequency component of the residual voltage is derived. This
phasor is used together with the phasor of the operating current, in order to
determine the direction to the earth fault (Forward/Reverse). In order to enable
voltage polarizing the magnitude of polarizing voltage shall be bigger than a
minimum level defined by setting parameter UpolMin.
It shall be noted that –3U0 is used to determine the location of the earth fault. This
insures the required inversion of the polarizing voltage within the earth-fault function.
Current polarizing
When current polarizing is selected the function will use the residual current (3I0)
as polarizing quantity IPol. This current can be:
1. directly measured (when a dedicated CT input of the IED is connected in

EF4PTOC function input I3PPOL). This dedicated IED CT input is then
typically connected to one single current transformer located between power
system star point and earth (current transformer located in the star point of a
star connected transformer winding).
• For some special line protection applications this dedicated IED CT
input can be connected to parallel connection of current transformers in
all three phases (Holm-Green connection)
2. calculated from three phase current input within the IED (when the fourth
analog input into the pre-processing block connected to EF4PTOC function
analog input I3PPOL is NOT connected to a dedicated CT input of the IED in
PCM600). In such case the pre-processing block will calculate 3I0 from the
IPol = 3I0 = IL1 + IL2 + IL3

where:
The residual polarizing current is pre-processed by a discrete fourier filter. Thus

the phasor of the fundamental frequency component of the residual current is
derived. This phasor is then multiplied with pre-set equivalent zero-sequence
source Impedance in order to calculate equivalent polarizing voltage UIPol in
accordance with the following formula:
UIPol = Z 0s × IPol = (RNPol + j × XNPol) × IPol

275
Current protection
which will be then used, together with the phasor of the operating current, in order
to determine the direction to the earth fault (Forward/Reverse). In order to enable
current polarizing the magnitude of polarizing current shall be bigger than a
minimum level defined by setting parameter IPolMin.
Dual polarizing
When dual polarizing is selected the function will use the vectorial sum of the
voltage based and current based polarizing in accordance with the following formula:
UTotPol = UUPol + UIPol = -3U 0 + Z 0 s × IPol = -3U 0 + ( RNPol + jXNPol ) × IPol

Then the phasor of the total polarizing voltage UTotPol will be used, together with
the phasor of the operating current, to determine the direction of the earth fault
(Forward/Reverse).
7.4.2.3 External polarizing for earth-fault function
The individual steps within the protection can be set as non-directional. When this
setting is selected it is then possible via function binary input BLKSTx to provide
external directional control (that is, torque control) by for example using one of the
following functions if available in the IED:
1. Distance protection directional function.

2. Negative sequence polarized General current and voltage multi purpose
protection function.
7.4.2.4 Base quantities within the protection
The base quantities shall be entered as setting parameters for every earth-fault
function. Base current (IBase) shall be entered as rated phase current of the
protected object in primary amperes. Base voltage (UBase) shall be entered as
rated phase-to-phase voltage of the protected object in primary kV.
7.4.2.5 Internal earth-fault protection structure
The protection is internally divided into the following parts:
1. Four residual overcurrent steps.

2. Directional supervision element for residual overcurrent steps with integrated
directional comparison step for communication based earth-fault protection
schemes (permissive or blocking).
3. Second harmonic blocking element with additional feature for sealed-in
blocking during switching of parallel transformers.
4. Switch on to fault feature with integrated Under-Time logic for detection of
breaker problems during breaker opening or closing sequence.
276
Current protection
Each part is described separately in the following sections.
7.4.2.6 Four residual overcurrent steps
Each overcurrent step uses operating quantity Iop (residual current) as measuring
quantity. Each of the four residual overcurrent steps has the following built-in
facilities:
• Directional mode can be set to Off/Non-directional/Forward/Reverse. By this

parameter setting the directional mode of the step is selected. It shall be noted
that the directional decision (Forward/Reverse) is not made within the residual
overcurrent step itself. The direction of the fault is determined in common
“directional supervision element”.
• Residual current start value.
• Type of operating characteristic (inverse or definite time). By this parameter
setting it is possible to select inverse or definite time delay for the earth-fault
protection. Most of the standard IEC and ANSI inverse characteristics are
available. For the complete list of available inverse curves please refer to
section "Inverse characteristics".
• Type of reset characteristic (Instantaneous / IEC Reset / ANSI Reset). By this
parameter setting it is possible to select the reset characteristic of the step. For
the complete list of available reset curves please refer to section "Inverse time
characteristics".
• Time delay related settings. By these parameter settings the properties like
definite time delay, minimum operating time for inverse curves, reset time
delay and parameters to define user programmable inverse curve are defined.
• Supervision by second harmonic blocking feature (On/Off). By this parameter
setting it is possible to prevent operation of the step if the second harmonic
content in the residual current exceeds the preset level.
• Multiplier for scaling of the set residual current pickup value by external
binary signal. By this parameter setting it is possible to increase residual
current pickup value when function binary input ENMULTx has logical value
1.
Simplified logic diagram for one residual overcurrent step is shown in figure 133.
277
Current protection
BLKTR
IMinx Characteristx=DefTime
X T b
a>b
F a
TRINx
tx AND
|IOP|
a OR
a>b
b
STINx
INxMult AND
X T
INx> F tMin
AND Inverse
BLKSTx
BLOCK Characteristx=Inverse
2ndHarm_BLOCK_Int
OR
HarmRestrainx=Off
DirModex=Off OR STEPx_DIR_Int
DirModex=Non-directional
DirModex=Forward
AND OR
FORWARD_Int
DirModex=Reverse
AND
REVERSE_Int
IEC10000008 V1 EN
Figure 133: Simplified logic diagram for residual overcurrent step x, where x =
step 1, 2, 3 or 4
The protection can be completely blocked from the binary input BLOCK. Output
signals for respective step, STINx and TRINx, can be blocked from the binary
input BLKSTx. The trip signals from the function can be blocked from the binary
input BLKTR.
7.4.2.7 Directional supervision element with integrated directional

comparison function
It shall be noted that at least one of the four residual overcurrent

steps shall be set as directional in order to enable execution of the
directional supervision element and the integrated directional
comparison function.
The protection has integrated directional feature. As the operating quantity current
Iop is always used. The polarizing method is determined by the parameter setting
polMethod. The polarizing quantity will be selected by the function in one of the
following three ways:
1. When polMethod = Voltage, UPol will be used as polarizing quantity.

2. When polMethod = Current, IPol will be used as polarizing quantity.
3. WhenpolMethod = Dual, UPol + IPol · ZNPol will be used as polarizing quantity.
The operating and polarizing quantity are then used inside the directional element,
as shown in figure 134, in order to determine the direction of the earth fault.
278
Current protection
Operating area
STRV
0.6 * IN>DIR
Characteristic for reverse
release of measuring steps
-RCA -85 deg
Characteristic
for STRV 40% of
IN>DIR RCA +85 deg
RCA
65° Upol = -3U 0
-RCA +85 deg
RCA -85 deg

Characteristic for forward
release of measuring steps
IN>DIR
STFW
I op = 3I0
Operating area
Characteristic
for STFW IEC11000243-1-en.ai
IEC11000243 V1 EN
Figure 134: Operating characteristic for earth-fault directional element
Two relevant setting parameters for directional supervision element are:
• Directional element will be internally enabled to operate as soon as Iop is

bigger than 40% of IN>Dir and directional condition is fulfilled in set direction.
• Relay characteristic angle AngleRCA, which defines the position of forward
and reverse areas in the operating characteristic.
Directional comparison step, built-in within directional supervision element, will

set EF4PTOC function output binary signals:
1. STFW=1 when operating quantity magnitude Iop x cos(φ - AngleRCA) is

bigger than setting parameterIN>Dir and directional supervision element
detects fault in forward direction.
2. STRV=1 when operating quantity magnitude Iop x cos(φ - AngleRCA) is
bigger than 60% of setting parameter IN>Dir and directional supervision
element detects fault in reverse direction.
These signals shall be used for communication based earth-fault teleprotection

communication schemes (permissive or blocking).
279
Current protection
Simplified logic diagram for directional supervision element with integrated

directional comparison step is shown in figure 135:
|Iop|
a
a>b STRV
b AND
REVERSE_Int
0.6
X
a
a>b
AND STFW
IN>Dir b
FORWARD_Int
X
0.4
FWD
AND FORWARD_Int
AngleRCA
polMethod=Voltage
OR
UPolMin
Characteristic
Directional
polMethod=Dual UPol IPolMin
T
Iop
polMethod=Current 0.0 F
OR
UTotPol
IPol AND REVERSE_Int
T RVS
0.0 F
UIPol STAGE1_DIR_Int
RNPol Complex X T STAGE2_DIR_Int
XNPol Number 0.0 F STAGE3_DIR_Int OR
STAGE4_DIR_Int
BLOCK AND
IEC07000067 V4 EN
Figure 135: Simplified logic diagram for directional supervision element with integrated directional
comparison step
7.4.2.8 Second harmonic blocking element
A harmonic restrain of the Four step residual overcurrent protection function

EF4PTOC can be chosen. If the ratio of the 2nd harmonic component in relation to
the fundamental frequency component in the residual current exceeds the pre-set
level (defined by parameter setting 2ndHarmStab) any of the four residual
overcurrent stages can be selectively blocked by a parameter setting
HarmRestrainx. When 2nd harmonic restraint feature is active the EF4PTOC
function output signal 2NDHARMD will be set to logical value one.
In addition to the basic functionality explained above the 2nd harmonic blocking
can be set in such way to seal-in until residual current disappears. This feature
280
Current protection
might be required to stabilize EF4PTOC during switching of parallel transformers

in the station. In case of parallel transformers there is a risk of sympathetic inrush
current. If one of the transformers is in operation, and the parallel transformer is
switched in, the asymmetric inrush current of the switched in transformer will
cause partial saturation of the transformer already in service. This is called
transferred saturation. The 2nd harmonic of the inrush currents of the two
transformers will be in phase opposition. The summation of the two currents will
thus give a small 2nd harmonic current. The residual fundamental current will
however be significant. The inrush current of the transformer in service before the
parallel transformer energizing, will be a little delayed compared to the first
transformer. Therefore we will have high 2nd harmonic current component initially.
After a short period this current will however be small and the normal 2nd
harmonic blocking will reset. If the BlkParTransf function is activated the 2nd
harmonic restrain signal will be latched as long as the residual current measured by
the relay is larger than a selected step current level.
This feature has been called Block for Parallel Transformers. This 2nd harmonic seal-
in feature will be activated when all of the following three conditions are
simultaneously fulfilled:
1. Feature is enabled by entering setting parameter BlkParTransf = On.

2. Basic 2nd harmonic restraint feature has been active for at least 70ms.
3. Residual current magnitude is higher than the set start value for one of the four
residual overcurrent stages. By a parameter setting UseStartValue it is possible
to select which one of the four start values that will be used (IN1> or IN2> or
IN3> or IN4>).
Once Block for Parallel Transformers is activated the basic 2nd harmonic blocking
signal will be sealed-in until the residual current magnitude falls below a value
defined by parameter setting UseStartValue (see condition 3 above).
Simplified logic diagram for 2nd harmonic blocking feature is shown in figure 136.
281
Current protection
BLOCK
Extract second
IOP 2NDHARMD
harmonic current a
a>b
OR
component 2ndHarmStab b
X
Extract
fundamental
q-1
current component
t=70ms OR
t AN OR 2ndH_BLOCK_Int
D
BlkParTransf=On
|IOP|
a
a>b
b
UseStartValue
IN1>
IN2>
IN3>
IN4>
en07000068-2.vsd
IEC07000068 V2 EN
Figure 136: Simplified logic diagram for 2nd harmonic blocking feature and Block for Parallel Transformers
feature
7.4.2.9 Switch on to fault feature
Integrated in the four step residual overcurrent protection are Switch on to fault
logic (SOTF) and Under-Time logic. The setting parameter SOTF is set to activate
either SOTF or Under-Time logic or both. When the circuit breaker is closing there
is a risk to close it onto a permanent fault, for example during an autoreclosing
sequence. The SOTF logic will enable fast fault clearance during such situations.
The time during which SOTF and Under-Time logics will be active after activation
is defined by the setting parameter t4U.
The SOTF logic uses the start signal from step 2 or step 3 for its operation, selected
by setting parameter StepForSOTF. The SOTF logic can be activated either from
change in circuit breaker position or from circuit breaker close command pulse.
The setting parameter ActivationSOTF can be set for activation of CB position
open change, CB position closed change or CB close command. In case of a
residual current start from step 2 or 3 (dependent on setting) the function will give
a trip after a set delay tSOTF. This delay is normally set to a short time (default 200
ms).
The Under-Time logic always uses the start signal from the step 4. The Under-
Time logic will normally be set to operate for a lower current level than the SOTF
282
Current protection
function. The Under-Time logic can also be blocked by the 2nd harmonic restraint
feature. This enables high sensitivity even if power transformer inrush currents can
occur at breaker closing. This logic is typically used to detect asymmetry of CB
poles immediately after switching of the circuit breaker. The Under-Time logic is
activated either from change in circuit breaker position or from circuit breaker
close and open command pulses. This selection is done by setting parameter
ActUnderTime. In case of a start from step 4 this logic will give a trip after a set
delay tUnderTime. This delay is normally set to a relatively short time (default 300
ms). Practically the Under-Time logic acts as circuit breaker pole-discordance
protection, but it is only active immediately after breaker switching. The Under-
Time logic can only be used in solidly or low impedance grounded systems.
SOTF
Open
tPulse
Closed
ActivationSOTF
Close command
tSOTF
AND
AND t
STIN2
StepForSOTF
STIN3
OperationMode
BLOCK
OFF
SOTF
UNDERTIME TRIP
UnderTime
tUnderTime
SOTF or
2nd Harmonic AND
HarmResSOFT t UnderTime
OR
Open
Close OR
tPulse
Close command
ActUnderTime
AND
STIN4
IEC06000643 V2 EN
Figure 137: Simplified logic diagram for SOTF and Under-Time features
EF4PTOC Logic Diagram Simplified logic diagram for the complete EF4PTOC
function is shown in figure 138:
283
Current protection
signal to
communication
scheme
Directional Check
Element
4 step over current

INPol Direction
operatingCurrent element TRIP
Element
3U0 One element for each
earthFaultDirection step
3I0 angleValid
DirMode
enableDir
harmRestrBlock
3I0 Harmonic
Restraint ³1
Element
start step 2, 3 and

4
Blocking at parallel
transformers
SwitchOnToFault
TRIP
CB
DirMode pos
or cmd
enableDir
Mode
Selection enableStep1-4
DirectionalMode1-4
en06000376.vsd
IEC06000376 V1 EN
Figure 138: Functional overview of EF4PTOC

EF4PTOC
I3P* TRIP
U3P* TRIN1
I3PPOL* TRIN2
BLOCK TRIN3
BLKTR TRIN4
BLKST1 TRSOTF
BLKST2 START
BLKST3 STIN1
BLKST4 STIN2
ENMULT1 STIN3
ENMULT2 STIN4
ENMULT3 STSOTF
ENMULT4 STFW
CBPOS STRV
CLOSECB 2NDHARMD
OPENCB
IEC06000424 V2 EN
Figure 139: EF4PTOC function block
284
Current protection

Table 145: EF4PTOC Input signals
I3P GROUP - Three Phase Current Group Connection
SIGNAL
U3P GROUP - Three Phase Voltage Group Connection
SIGNAL
I3PPOL GROUP - Three Phase Polarisation Current
SIGNAL
BLOCK BOOLEAN 0 General block
BLKST1 BOOLEAN 0 Block of step 1 (Start and trip)
step1
step2
step3
step4
CBPOS BOOLEAN 0 Breaker position
CLOSECB BOOLEAN 0 Breaker close command
OPENCB BOOLEAN 0 Breaker open command
Table 146: EF4PTOC Output signals

TRIP BOOLEAN Trip
TRIN1 BOOLEAN Trip signal from step 1
TRSOTF BOOLEAN Trip signal from earth fault switch onto fault function
STIN1 BOOLEAN Start signal step 1
STSOTF BOOLEAN Start signal from earth fault switch onto fault
function
285
Current protection

STFW BOOLEAN Forward directional start signal
STRV BOOLEAN Reverse directional start signal
2NDHARMD BOOLEAN 2nd harmonic block signal

Table 147: EF4PTOC Group settings (basic)
On
IBase 1 - 99999 A 1 3000 Base value for current settings
UBase 0.05 - 2000.00 kV 0.05 400 Base value for voltage settings
AngleRCA -180 - 180 Deg 1 65 Relay characteristic angle (RCA)
polMethod Voltage - - Voltage Type of polarization
Current
Dual
UPolMin 1 - 100 %UB 1 1 Minimum voltage level for polarization in
% of UBase
IPolMin 2 - 100 %IB 1 5 Minimum current level for polarization in
% of IBase
RNPol 0.50 - 1000.00 ohm 0.01 5.00 Real part of source Z to be used for
current polarisation
XNPol 0.50 - 3000.00 ohm 0.01 40.00 Imaginary part of source Z to be used for
current polarisation
IN>Dir 1 - 100 %IB 1 10 Residual current level for Direction
release in % of IBase
2ndHarmStab 5 - 100 % 1 20 Second harmonic restrain operation in %
of IN amplitude
BlkParTransf Off - - Off Enable blocking at parallel transformers
On
UseStartValue IN1> - - IN4> Current level blk at parallel transf (step1,
IN2> 2, 3 or 4)
IN3>
IN4>
SOTF Off - - Off SOTF operation mode (Off/SOTF/
SOTF Undertime/SOTF&Undertime)
UnderTime
SOTF&UnderTime
ActivationSOTF Open - - Open Select signal that shall activate SOTF
Closed
CloseCommand
StepForSOTF Step 2 - - Step 2 Selection of step used for SOTF
Step 3
HarmResSOTF Off - - Off Enable harmonic restrain function in
On SOTF
tSOTF 0.000 - 60.000 s 0.001 0.200 Time delay for SOTF
t4U 0.000 - 60.000 s 0.001 1.000 Switch-onto-fault active time
286
Current protection

ActUnderTime CB position - - CB position Select signal to activate under time (CB
CB command Pos/CBCommand)
tUnderTime 0.000 - 60.000 s 0.001 0.300 Time delay for under time
Forward
Reverse
Characterist1 ANSI Ext. inv. - - ANSI Def. Time Time delay curve type for step 1
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
IN1> 1 - 2500 %IB 1 100 Operate residual current level for step 1
in % of IBase
t1 0.000 - 60.000 s 0.001 0.000 Independent (defenite) time delay of step
1
k1 0.05 - 999.00 - 0.01 0.05 Time multiplier for the dependent time
delay for step 1
IMin1 1.00 - 10000.00 %IB 1.00 100.00 Minimum current for step 1
for step 1
IN1Mult 1.0 - 10.0 - 0.1 2.0 Multiplier for scaling the current setting
value for step 1
ResetTypeCrv1 Instantaneous - - Instantaneous Reset curve type for step 1
IEC Reset
ANSI reset
tReset1 0.000 - 60.000 s 0.001 0.020 Reset time delay for step 1
HarmRestrain1 Off - - On Enable block of step 1 from harmonic
On restrain
curve for step 1
curve for step 1
curve for step 1
287
Current protection

Forward
Reverse
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
in % of IBase
t2 0.000 - 60.000 s 0.001 0.400 Independent (definitive) time delay of
step 2
delay for step 2
IMin2 1.00 - 10000.00 %IB 1.00 50 Minimum current for step 2
step 2
value for step 2
IEC Reset
ANSI reset
On restrain
curve for step 2
curve for step 2
curve for step 2
288
Current protection

Forward
Reverse
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
in % of IBase
t3 0.000 - 60.000 s 0.001 0.800 Independent time delay of step 3
delay for step 3
for step 3
value for step 3
IEC Reset
ANSI reset
On restrain
curve for step 3
curve for step 3
curve for step 3
programmable curve step 3
289
Current protection

Forward
Reverse
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
in % of IBase
step 4
delay for step 4
t4Min 0.000 - 60.000 s 0.001 0.000 Minimum operate time in inverse curves
step 4
value for step 4
IEC Reset
ANSI reset
On restrain
curve for step 4
curve step 4
curve for step 4
290
Current protection


Table 148: EF4PTOC technical data
± 1.0% of I at I > Ir
Reset ratio > 95% -

Operate current for directional (1–100)% of lBase ± 1.0% of Ir
comparison
Timers (0.000-60.000) s ± 0.5% ±10 ms
table 582, table 583 and table 584 table 584
Second harmonic restrain (5–100)% of fundamental ± 2.0% of Ir
operation
Relay characteristic angle (-180 to 180) degrees ± 2.0 degrees
Minimum polarizing voltage (1–100)% of UBase ± 0.5% of Ur
Minimum polarizing current (1-30)% of IBase ±0.25% of Ir
Real part of source Z used for (0.50-1000.00) W/phase -

current polarization
Imaginary part of source Z used (0.50–3000.00) W/phase -
for current polarization
7.5 Four step directional negative phase sequence

overcurrent protection NS4PTOC
291
Current protection
Function description IEC 61850 IEC 60617 identification ANSI/IEEE C37.2

identification device number
Four step negative sequence NS4PTOC 46I2
I2
overcurrent protection
4
alt
4
IEC10000053 V1 EN
7.5.1 Introduction
Four step negative sequence overcurrent protection (NS4PTOC) has an inverse or
definite time delay independent for each step separately.
All IEC and ANSI time delayed characteristics are available together with an
optional user defined characteristic.
The directional function is voltage polarized or dual polarized.
NS4PTOC can be set directional or non-directional independently for each of the

steps.
NS4PTOC can be used as main protection for unsymmetrical fault; phase-phase

short circuits, phase-phase-earth short circuits and single phase earth faults.
NS4PTOC can also be used to provide a system back-up for example, in the case of
the primary protection being out of service due to communication or voltage
transformer circuit failure.
Directional operation can be combined together with corresponding

communication logic in permissive or blocking teleprotection scheme. The same
logic as for directional zero sequence current can be used. Current reversal and weak-
end infeed functionality are available.

Four step negative sequence overcurrent protection NS4PTOC function has the
following three “Analog Inputs” on its function block in the configuration tool:
1. I3P, input used for “Operating Quantity”.

2. U3P, input used for “Voltage Polarizing Quantity”.
3. I3PPOL, input used for “ Polarizing Quantity”.
These inputs are connected from the corresponding pre-processing function blocks
in the Configuration Tool within PCM600.
7.5.2.1 Operating quantity within the function
Four step negative sequence overcurrent protection NS4PTOC function always

uses negative sequence current (I2) for its operating quantity. The negative
292
Current protection
sequence current is calculated from three-phase current input within the IED. The
pre-processing block calculates I2 from the first three inputs into the pre-
processing block by using the following formula:
1
I op = I 2 =
3
(
× IL1 + a × IL 2 + a × IL3
2
)
where:
a is so called operator which gives a phase shift of 120 deg, that is, a = 1∠120 deg
a2 similarly gives a phase shift of 240 deg, that is, a2 = 1∠240 deg
The negative sequence current is pre-processed by a discrete Fourier filter. Thus,

the phasor of the fundamental frequency component of the negative sequence
current is derived. The phasor magnitude is used within the NS4PTOC protection
to compare it with the set operation current value of the four steps (I1>, I2>, I3>
or I4>). If the negative sequence current is larger than the set operation current and
the step is used in non-directional mode a signal from the comparator for this step
is set to true. This signal, without delay, activates the output signal STx (x=1 - 4)
for this step and a common START signal.
7.5.2.2 Internal polarizing facility of the function
A polarizing quantity is used within the protection to determine the direction to the
fault (Forward/Reverse).
Four step negative sequence overcurrent protection NS4PTOC function can be set
to use voltage polarizing or dual polarizing.
Voltage polarizing
When voltage polarizing is selected, NS4PTOC uses the negative sequence voltage
-U2 as polarizing quantity U3P. This voltage is calculated from three phase voltage
input within the IED. The pre-processing block calculates -U2 from the first three
inputs into the pre-processing block by using the following formula:
1
UPol = -U 2 = - × (UL1 + a × UL 2 + a 2 × UL3)
3
293
Current protection
where:
UL1, UL2 and UL3 are fundamental frequency phasors of three individual phase voltages.
To use this all three phase-to-earth voltages must be connected to three IED VT inputs.
The negative sequence voltage is pre-processed by a discrete fourier filter. Thus,

the phasor of the fundamental frequency component of the negative sequence
voltage is derived. This phasor is used together with the phasor of the operating
current, in order to determine the direction to the fault (Forward/Reverse).To
enable voltage polarizing the magnitude of polarizing voltage must be bigger than a
minimum level defined by setting UpolMin.
Note that –U2 is used to determine the location of the fault. This ensures the
required inversion of the polarizing voltage within the function.
Dual polarizing
When dual polarizing is selected, the function uses the vectorial sum of the voltage
based and current based polarizing in accordance with the following formula:
UTotPol = UUPol + UIPol = -U 2 + ZPol × IPol = -U 2 + ( RPol + jXPol ) × IPol

IECEQUATION2315 V1 EN (Equation 65)
Then the phasor of the total polarizing voltage UTotPol is used, together with the
phasor of the operating current, to determine the direction to the fault (Forward/
Reverse).
7.5.2.3 External polarizing for negative sequence function
The individual steps within the protection can be set as non-directional. When this
setting is selected it is then possible via function binary input BLKSTx (where x
indicates the relevant step within the protection) to provide external directional
control (that is, torque control) by for example using one of the following functions
if available in the IED:
• Distance protection directional function

• Negative sequence polarized general current and voltage multi purpose
protection function
7.5.2.4 Base quantities within the function
The base quantities must be entered as setting parameters for every function. Base
current (IBase) must be entered as rated phase current of the protected object in
primary amperes. In line protections the primary rated current of the CT is chosen.
294
Current protection
Base voltage UBase must be entered as rated phase-to-phase voltage of the

protected object in primary kV. In line protections the primary rated voltage of the
VT is chosen.
7.5.2.5 Internal negative sequence protection structure
The protection is internally divided into the following parts:
• Four negative sequence overcurrent steps

• Directional supervision element for negative sequence overcurrent steps with
integrated directional comparison step for communication based negative
sequence protection schemes (permissive or blocking)
Each part is described separately in the following sections.
7.5.2.6 Four negative sequence overcurrent stages
Each overcurrent stage uses Operating Quantity I2 (negative sequence current) as

measuring quantity. Every of the four overcurrent stage has the following built-in
facilities:
• Operating mode (Off/ Non-directional /Forward / Reverse). By this parameter

setting the operating mode of the stage is selected. Note that the directional
decision (Forward/Reverse) is not made within the overcurrent stage itself.
The direction of the fault is determined in common “Directional Supervision
Element” described in the next paragraph.
• Negative sequence current pickup value.
• Type of operating characteristic (Inverse or Definite Time). By this parameter
setting it is possible to select Inverse or definite time delay for negative
sequence overcurrent function. Most of the standard IEC and ANSI inverse
characteristics are available. For the complete list of available inverse curves,
refer to Chapter "Inverse time characteristics"
• Type of reset characteristic (Instantaneous / IEC Reset /ANSI reset).By this
parameter setting it is possible to select the reset characteristic of the stage. For
the complete list of available reset curves, refer to Chapter "Inverse time
characteristics"
• Time delay related settings. By these parameter settings the properties like
definite time delay, minimum operating time for inverse curves, reset time
delay and parameters to define user programmable inverse curve are defined.
• Multiplier for scaling of the set negative sequence current pickup value by
external binary signal. By this parameter setting it is possible to increase
negative sequence current pickup value when function binary input
ENMULTx has logical value 1.
Simplified logic diagram for one negative sequence overcurrent stage is shown in
the following figure:
295
Current protection
BLKTR
Characteristx=DefTime tx TRx
|IOP| AND
a OR
a>b
ENMULTx b
STx
IxMult AND
X T
Ix> F
Inverse
BLKSTx
BLOCK Characteristx=Inverse
DirModex=Off OR STAGEx_DIR_Int
DirModex=Non-directional
DirModex=Forward
AND OR
FORWARD_Int
DirModex=Reverse
AND
REVERSE_Int
IEC09000683 V1 EN
Figure 140: Simplified logic diagram for negative sequence overcurrent stage x , where x=1, 2, 3 or 4
NS4PTOC can be completely blocked from the binary input BLOCK. The start
signals from NS4PTOC for each stage can be blocked from the binary input
BLKSTx. The trip signals from NS4PTOC can be blocked from the binary input
BLKTR.
7.5.2.7 Directional supervision element with integrated directional

comparison function
At least one of the four negative sequence overcurrent steps must

be set as directional in order to enable execution of the directional
supervision element and the integrated directional comparison
function.
NS4PTOC has integrated directional feature. As the operating quantity current Iop
is always used. The polarizing method is determined by the setting polMethod. The
polarizing quantity can be selected by NS4PTOC in one of the following two ways:
• When polMethod=Voltage, UVPol is used as polarizing quantity

• When polMethod=Dual, UTotPol is used as polarizing quantity
The operating and polarizing quantity are then used inside the directional element,
as shown in figure 134, to determine the direction of the fault.
296
Current protection
Reverse
Area
AngleRCA Upol=-U2
Forward
Area
Iop = I2
IEC10000031 V1 EN
Figure 141: Operating characteristic for fault directional element
Two relevant setting parameters for directional supervision element are:
• Directional element is internally enable to operate as soon as IOp is bigger than

40% of I>Dir and the directional condition is fulfilled in set direction.
• Relay characteristic angle AngleRCA which defines the position of forward
and reverse areas in the operating characteristic.
Directional comparison step, built-in within directional supervision element, set

NS4PTOC output binary signals:
1. STFW=1 when tip of I2 phasor (operating quantity magnitude) is in forward

area, see fig 134 (Operating quantity magnitude is bigger than setting I>Dir)
2. STRV=1 when tip of I2 phasor (operating quantity magnitude) is in the reverse
area, see fig 134. (Operating quantity magnitude is bigger than 60% of setting
I>Dir)
These signals must be used for communication based fault teleprotection

communication schemes (permissive or blocking).
297
Current protection
Simplified logic diagram for directional supervision element with integrated

directional comparison step is shown in figure 135:
|Iop|
a a>
STRV
b b AND
REVERSE_Int
0.6
X
a a>
STFW
I>Dir b b FORWARD_Int
AND
X
0.4
FWD
AND FORWARD_Int
AngleRCA
C h a r a c e ri s ti c
polMethod=Voltage
OR
D i r e c ti o n a l
UPolMin
polMethod=Dual UPol IPolMin
t
T
Iop
0.0 F
IPol UTotPol
AND REVERSE_Int
RVS
UIPol
RNPol Complex X T
XNPol Number 0.0 F STAGE1_DIR_Int
STAGE2_DIR_Int
STAGE3_DIR_Int OR
STAGE4_DIR_Int
BLOCK AND
IEC07000067-4 V1 EN
Figure 142: Simplified logic diagram for directional supervision element with integrated directional
comparison step
298
Current protection

NS4PTOC
I3P* TRIP
U3P* TR1
I3PPOL* TR2
BLOCK TR3
BLKTR TR4
BLKST1 START
BLKST2 ST1
BLKST3 ST2
BLKST4 ST3
ENMULT1 ST4
ENMULT2 STFW
ENMULT3 STRV
ENMULT4
IEC10000054 V1 EN
Figure 143: NS4PTOC function block

Table 149: NS4PTOC Input signals
I3P GROUP - Negative Sequence 3 phase current
SIGNAL
U3P GROUP - Negative Sequence 3 phase voltage
SIGNAL
I3PPOL GROUP - Negative Sequence 3 phase polarisation current
SIGNAL
step1
step2
step3
step4
299
Current protection
Table 150: NS4PTOC Output signals

TRIP BOOLEAN Trip
TR1 BOOLEAN Trip signal from step 1
ST1 BOOLEAN Start signal step 1
STFW BOOLEAN Forward directional start signal
STRV BOOLEAN Reverse directional start signal

Table 151: NS4PTOC Group settings (basic)
On
IBase 1 - 99999 A 1 3000 Base value for current settings
UBase 0.05 - 2000.00 kV 0.05 400 Base value for voltage settings
AngleRCA -180 - 180 Deg 1 65 Relay characteristic angle (RCA)
polMethod Voltage - - Voltage Type of polarization
Dual
UPolMin 1 - 100 %UB 1 5 Minimum voltage level for polarization in
% of UBase
IPolMin 2 - 100 %IB 1 5 Minimum current level for polarization in
% of IBase
RPol 0.50 - 1000.00 ohm 0.01 5.00 Real part of neg. seq. source imp. to be
used for current polarisation
XPol 0.50 - 3000.00 ohm 0.01 40.00 Imaginary part of neg. seq. source imp.
to be used for current polarisation
I>Dir 1 - 100 %IB 1 10 Neg. seq. curr. I2 level for Direction
release in % of IBase
Forward
Reverse
300
Current protection

ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
I1> 1 - 2500 %IB 1 100 Operate neg. seq. curr. I2 level for step 1
in % of IBase
t1 0.000 - 60.000 s 0.001 0.000 Independent (defenite) time delay of step
1
delay for step 1
IMin1 1.00 - 10000.00 %IB 1.00 100.00 Minimum current for step 1
for step 1
I1Mult 1.0 - 10.0 - 0.1 2.0 Multiplier for scaling the current setting
value for step 1
IEC Reset
ANSI reset
curve for step 1
curve for step 1
curve for step 1
Forward
Reverse
301
Current protection

ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
in % of IBase
step 2
delay for step 2
step 2
value for step 2
IEC Reset
ANSI reset
curve for step 2
curve for step 2
curve for step 2
Forward
Reverse
302
Current protection

ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
in % of IBase
t3 0.000 - 60.000 s 0.001 0.800 Independent time delay of step 3
delay for step 3
for step 3
value for step 3
IEC Reset
ANSI reset
curve for step 3
curve for step 3
curve for step 3
Forward
Reverse
303
Current protection

ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
in % of IBase
step 4
delay for step 4
t4Min 0.000 - 60.000 s 0.001 0.000 Minimum operate time in inverse curves
step 4
value for step 4
IEC Reset
ANSI reset
curve for step 4
curve step 4
curve for step 4
304
Current protection

Table 152: NS4PTOC technical data
Operate value, negative (1-2500)% of lBase ± 1.0% of Ir at I £ Ir
sequence current, step 1-4 ± 1.0% of I at I > Ir
Reset ratio > 95% -

Timers (0.000-60.000) s ± 0.5% ± 10 ms
table 582, table 583 and table 584 table 584
Minimum operate current for (1.00 - 10000.00)% of IBase ± 1.0% of Ir at I < Ir
step 1 - 4 ± 1.0% of I at I > Ir
Operate value, negative current (1–100)% of IBase ± 1.0% of Ir

for directional release
Relay characteristic angle (-180 to 180) degrees ± 2.0 degrees
Minimum polarizing voltage (1–100)% of UBase ± 0.5% of Ur
Minimum polarizing current (2-100)% of IBase ±1.0% of Ir
Real part of negative sequence (0.50-1000.00) W/phase -

source impedance used for
current polarization
Imaginary part of negative (0.50–3000.00) W/phase -
sequence source impedance
used for current polarization
Operate time, start function 25 ms typically at 0.5 to 2 x Iset -
Reset time, start function 25 ms typically at 2 to 0.5 x Iset -
Critical impulse time, start 10 ms typically at 0 to 2 x Iset -

function
Impulse margin time, start 15 ms typically -
function
Transient overreach <10% at τ = 100 ms -
7.6 Sensitive directional residual overcurrent and power

protection SDEPSDE

Sensitive directional residual over SDEPSDE - 67N
current and power protection
7.6.1 Introduction
In networks with high impedance earthing, the phase-to-earth fault current is
significantly smaller than the short circuit currents. Another difficulty for earth-
305
Current protection
fault protection is that the magnitude of the phase-to-earth fault current is almost
independent of the fault location in the network.
Directional residual current can be used to detect and give selective trip of phase-to-
earth faults in high impedance earthed networks. The protection uses the residual
current component 3I0 · cos φ, where φ is the angle between the residual current
and the residual voltage (-3U0), compensated with a characteristic angle.
Alternatively, the function can be set to strict 3I0 level with an check of angle 3I0
and cos φ.
Directional residual power can also be used to detect and give selective trip of phase-
to-earth faults in high impedance earthed networks. The protection uses the
residual power component 3I0 · 3U0 · cos φ, where φ is the angle between the
residual current and the reference residual voltage, compensated with a
characteristic angle.
A normal non-directional residual current function can also be used with definite or
inverse time delay.
A back-up neutral point voltage function is also available for non-directional

sensitive back-up protection.
In an isolated network, that is, the network is only coupled to earth via the
capacitances between the phase conductors and earth, the residual current always
has -90º phase shift compared to the reference residual voltage. The characteristic
angle is chosen to -90º in such a network.
In resistance earthed networks or in Petersen coil earthed, with a parallel resistor,

the active residual current component (in phase with the residual voltage) should be
used for the earth-fault detection. In such networks the characteristic angle is
chosen to 0º.
As the amplitude of the residual current is independent of the fault location the
selectivity of the earth-fault protection is achieved by time selectivity.
When should the sensitive directional residual overcurrent protection be used and
when should the sensitive directional residual power protection be used? Consider
the following facts:
• Sensitive directional residual overcurrent protection gives possibility for better

sensitivity
• Sensitive directional residual power protection gives possibility to use inverse
time characteristics. This is applicable in large high impedance earthed
networks, with large capacitive earth-fault current
• In some power systems a medium size neutral point resistor is used, for
example, in low impedance earthed system. Such a resistor will give a resistive
earth-fault current component of about 200 - 400 A at a zero resistive phase-to-
earth fault. In such a system the directional residual power protection gives
better possibilities for selectivity enabled by inverse time power characteristics.
306
Current protection
7.6.2.1 Function inputs
The function is using phasors of the residual current and voltage. Group signals I3P
and U3P containing phasors of residual current and voltage is taken from pre-
processor blocks.
The sensitive directional earth fault protection has the following sub-functions
included:
Directional residual current protection measuring 3I0·cos φ

φ is defined as the angle between the residual current 3I0 and the reference voltage
compensated with the set characteristic angle RCADir (φ=ang(3I0)-ang(Uref) ).
Uref = -3U0 ejRCADIr. RCADir is normally set equal to 0 in a high impedance
earthed network with a neutral point resistor as the active current component is
appearing out on the faulted feeder only. RCADir is set equal to -90° in an isolated
network as all currents are mainly capacitive. The function operates when 3I0·cos φ
gets larger than the set value.
RCADir = 0 , ROADir = 0
3I0
ϕ = ang(3I0 ) − ang(3Uref )
−3U0 = Uref
3I0 ⋅ cosϕ
IEC06000648 V3 EN
Figure 144: RCADir set to 0°
307
Current protection
Uref
RCADir = −90 , ROADir = 90
3I0
3I0 ⋅ cos ϕ
ϕ = ang (3I0 ) − ang (Uref )
−3U0
IEC06000649 V3 EN
Figure 145: RCADir set to -90°
For trip, both the residual current 3I0·cos φ and the release voltage 3U0, must be
larger than the set levels: INCosPhi> and UNRel>.
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function is activated binary output signals START and STDIRIN are
activated. If the activation is active after the set delay tDef the binary output signals
TRIP and TRDIRIN are activated. The trip from this sub-function has definite time
delay.
There is a possibility to increase the operate level for currents where the angle φ is
larger than a set value as shown in figure 146. This is equivalent to blocking of the
function if φ > ROADir. This option is used to handle angle error for the instrument
transformers.
308
Current protection
RCADir = 0o
3I0
Operate area
j
-3U0 = Uref
3I0 × cos j
ROADir
IEC06000650 V2 EN
Figure 146: Characteristic with ROADir restriction
The function indicates forward/reverse direction to the fault. Reverse direction is

defined as 3I0·cos (φ + 180°) ≥ the set value.
It is also possible to tilt the characteristic to compensate for current transformer

angle error with a setting RCAComp as shown in the figure 147:
309
Current protection
RCADir = 0º
Operate area
-3U0 =Uref
Instrument
transformer a
RCAcomp
angle error
Characteristic after
angle compensation
3I0 (to prot)

3I0 (prim)
en06000651.vsd
IEC06000651 V2 EN
Figure 147: Explanation of RCAComp
Directional residual power protection measuring 3I0 · 3U0 · cos φ

φ is defined as the angle between the residual current 3I0 and the reference voltage
compensated with the set characteristic angle RCADir (φ=ang(3I0)—ang(Uref) ).
Uref = -3U0 e-jRCA. The function operates when 3I0 · 3U0 · cos φ gets larger than
the set value.
For trip, both the residual power 3I0 · 3U0 · cos φ, the residual current 3I0 and the
release voltage 3U0, shall be larger than the set levels (SN>, INRel> and UNRel>).
activated. If the activation is active after the set delay tDef or after the inverse time
delay (setting kSN) the binary output signals TRIP and TRDIRIN are activated.
The function shall indicate forward/reverse direction to the fault. Reverse direction
is defined as 3I0 · 3U0·cos (φ + 180°) ³ the set value.
This variant has the possibility of choice between definite time delay and inverse
time delay.
310
Current protection
The inverse time delay is defined as:
kSN × (3I0 × 3U 0 × cos j(reference))

t inv =
3I0 × 3U 0 × cos j(measured)
Directional residual current protection measuring 3I0 and φ

The function will operate if the residual current is larger that the set value and the
angle φ = ang(3I0)-ang(Uref) is within the sector RCADir ± ROADir
RCADir = 0º
ROADir = 80º
Operate area
3I0
80 -3U0
en06000652.vsd
IEC06000652 V2 EN
Figure 148: Example of characteristic
For trip, both the residual current 3I0 and the release voltage 3U0, shall be larger
than the set levels INDir> and UNREL> and the angle φ shall be in the set sector
ROADir and RCADir.
activated. If the activation is active after the set delay tDef the binary output signals
TRIP and TRDIRIN are activated.
The function indicate forward/reverse direction to the fault. Reverse direction is

defined as φ is within the angle sector: RCADir + 180° ± ROADir
This variant shall have definite time delay.
311
Current protection
Directional functions
For all the directional functions there are directional start signals STFW: fault in
the forward direction, and STRV: start in the reverse direction. Even if the
directional function is set to operate for faults in the forward direction a fault in the
reverse direction will give the start signal STRV. Also if the directional function is
set to operate for faults in the reverse direction a fault in the forward direction will
give the start signal STFW.
Non-directional earth fault current protection

This function will measure the residual current without checking the phase angle.
The function will be used to detect cross-country faults. This function can serve as
alternative or back-up to distance protection with phase preference logic. To assure
selectivity the distance protection can block the non-directional earth fault current
function via the input BLKNDN.
If available the non-directional function is using the calculated residual current,

derived as sum of the phase currents. This will give a better ability to detect cross-
country faults with high residual current, also when dedicated core balance CT for
the sensitive earth fault protection will saturate.
This variant shall have the possibility of choice between definite time delay and
inverse time delay. The inverse time delay shall be according to IEC 60255-3.
For trip, the residual current 3I0 shall be larger than the set levels (INNonDir>).
Trip from this function can be blocked from the binary input BLKNDN.
When the function is activated binary output signal STNDIN is activated. If the
activation is active after the set delay tINNonDir or after the inverse time delay the
binary output signals TRIP and TRNDIN are activated.
Residual overvoltage release and protection

The directional function shall be released when the residual voltage gets higher
than a set level.
There shall also be a separate trip, with its own definite time delay, from this set
voltage level.
For trip, the residual voltage 3U0 shall be larger than the set levels (UN>).
Trip from this function can be blocked from the binary input BLKUN.
When the function is activated binary output signal STUN is activated. If the
activation is active after the set delay tUNNonDir TRIP and TRUN are activated. A
simplified logical diagram of the total function is shown in figure 149.
312
Current protection
INNonDir> STNDIN
t TRNDIN
UN> STUN
t TRUN
OpMODE=3I0cosfi
IN>
&
INcosPhi>
OpMODE=3I03U0cosfi
& ³1 & STARTDIRIN
INUNcosPhi> t
SN
& TRDIRIN
Phi in RCA +- ROA
TimeChar = InvTime
&
OpMODE=3I0 and fi
&
TimeChar = DefTime
DirMode = Forward & ³1

Forward STFW
DirMode = Reverse
&
Reverse STRV
en06000653.vsd
IEC06000653 V2 EN
Figure 149: Simplified logical diagram of the sensitive earth-fault current protection

SDEPSDE
I3P* TRIP
U3P* TRDIRIN
BLOCK TRNDIN
BLKTR TRUN
BLKTRDIR START
BLKNDN STDIRIN
BLKUN STNDIN
STUN
STFW
STRV
STDIR
UNREL
IEC07000032 V2 EN
Figure 150: SDEPSDE function block
313
Current protection

Table 153: SDEPSDE Input signals
I3P GROUP - Group signal for current
SIGNAL
U3P GROUP - Group signal for voltage
SIGNAL
BLOCK BOOLEAN 0 Blocks all the outputs of the function
BLKTR BOOLEAN 0 Blocks the operate outputs of the function
BLKTRDIR BOOLEAN 0 Blocks the directional operate outputs of the
function
BLKNDN BOOLEAN 0 Blocks the Non directional current residual outputs
BLKUN BOOLEAN 0 Blocks the Non directional voltage residual outputs
Table 154: SDEPSDE Output signals

TRIP BOOLEAN General trip of the function
TRDIRIN BOOLEAN Trip of the directional residual over current function
TRNDIN BOOLEAN Trip of non directional residual over current
TRUN BOOLEAN Trip of non directional residual over voltage
START BOOLEAN General start of the function
STDIRIN BOOLEAN Start of the directional residual over current
function
STNDIN BOOLEAN Start of non directional residual over current
STUN BOOLEAN Start of non directional residual over voltage
STFW BOOLEAN Start of directional function for a fault in forward
direction
STRV BOOLEAN Start of directional function for a fault in reverse
direction
STDIR INTEGER Direction of fault. A general signal common to all
three mode of residual over current protection
UNREL BOOLEAN Residual voltage release of operation of all
directional modes
314
Current protection

Table 155: SDEPSDE Group settings (basic)
On
OpMode 3I0Cosfi - - 3I0Cosfi Selection of operation mode for protection
3I03U0Cosfi
3I0 and fi
DirMode Forward - - Forward Direction of operation forward or reverse
Reverse
RCADir -179 - 180 Deg 1 -90 Relay characteristic angle RCA, in deg
RCAComp -10.0 - 10.0 Deg 0.1 0.0 Relay characteristic angle compensation
ROADir 0 - 90 Deg 1 90 Relay open angle ROA used as release
in phase mode, in deg
INCosPhi> 0.25 - 200.00 %IB 0.01 1.00 Set level for 3I0cosFi, directional res
over current, in %Ib
SN> 0.25 - 200.00 %SB 0.01 10.00 Set level for 3I03U0cosFi, starting inv
time count, in %Sb
INDir> 0.25 - 200.00 %IB 0.01 5.00 Set level for directional residual over
current prot, in %Ib
tDef 0.000 - 60.000 s 0.001 0.100 Definite time delay directional residual
overcurrent, in sec
SRef 0.03 - 200.00 %SB 0.01 10.00 Reference value of res power for inverse
time count, in %Sb
kSN 0.00 - 2.00 - 0.01 0.10 Time multiplier setting for directional
residual power mode
OpINNonDir> Off - - Off Operation of non-directional residual
On overcurrent protection
INNonDir> 1.00 - 400.00 %IB 0.01 10.00 Set level for non directional residual over
current, in %Ib
tINNonDir 0.000 - 60.000 s 0.001 1.000 Time delay for non-directional residual
over current, in sec
TimeChar ANSI Ext. inv. - - IEC Norm. inv. Operation curve selection for IDMT
ANSI Very inv. operation
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
315
Current protection

tMin 0.000 - 60.000 s 0.001 0.040 Minimum operate time for IEC IDMT
curves, in sec
kIN 0.00 - 2.00 - 0.01 1.00 IDMT time mult for non-dir res over
current protection
OpUN> Off - - Off Operation of non-directional residual
On overvoltage protection
UN> 1.00 - 200.00 %UB 0.01 20.00 Set level for non-directional residual over
voltage, in %Ub
tUN 0.000 - 60.000 s 0.001 0.100 Time delay for non-directional residual
over voltage, in sec
INRel> 0.25 - 200.00 %IB 0.01 1.00 Residual release current for all
directional modes, in %Ib
UNRel> 0.01 - 200.00 %UB 0.01 3.00 Residual release voltage for all direction
modes, in %Ub
Table 156: SDEPSDE Group settings (advanced)

tReset 0.000 - 60.000 s 0.001 0.040 Time delay used for reset of definite
timers, in sec
tPCrv 0.005 - 3.000 - 0.001 1.000 Setting P for customer programmable
curve
tACrv 0.005 - 200.000 - 0.001 13.500 Setting A for customer programmable
curve
tBCrv 0.00 - 20.00 - 0.01 0.00 Setting B for customer programmable
curve
tCCrv 0.1 - 10.0 - 0.1 1.0 Setting C for customer programmable
curve
ResetTypeCrv Immediate - - IEC Reset Reset mode when current drops off.
IEC Reset
ANSI reset
tPRCrv 0.005 - 3.000 - 0.001 0.500 Setting PR for customer programmable
curve
tTRCrv 0.005 - 100.000 - 0.001 13.500 Setting TR for customer programmable
curve
tCRCrv 0.1 - 10.0 - 0.1 1.0 Setting CR for customer programmable
curve
Table 157: SDEPSDE Non group settings (basic)

IBase 1 - 99999 A 1 100 Base Current, in A
UBase 0.05 - 2000.00 kV 0.05 63.50 Base Voltage, in kV Phase to Neutral
SBase 0.05 - kVA 0.05 6350.00 Base Power, in kVA. IBase*Ubase
200000000.00
316
Current protection
Table 158: SDEPSDE Non group settings (advanced)

RotResU 0 deg - - 180 deg Setting for rotating polarizing quantity if
180 deg necessary

Table 159: SDEPSDE technical data
Operate level for 3I0·cosj (0.25-200.00)% of lBase ± 1.0% of Ir at I £ Ir
directional residual overcurrent ± 1.0% of I at I > Ir
At low setting:
(2.5-10) mA ±0.5 mA
(10-50) mA ±1.0 mA
Operate level for 3I0·3U0 · cosj (0.25-200.00)% of SBase ± 1.0% of Sr at S £ Sr
directional residual power ± 1.0% of S at S > Sr
At low setting:
(0.25-5.00)% of SBase ± 10% of set value
Operate level for 3I0 and j (0.25-200.00)% of lBase ± 1.0% of Ir at £ Ir
residual overcurrent ± 1.0% of I at I > Ir
At low setting:
(2.5-10) mA ±0.5 mA
(10-50) mA ±1.0 mA
Operate level for non-directional (1.00-400.00)% of lBase ± 1.0% of Ir at I £ Ir
overcurrent ± 1.0% of I at I > Ir
At low setting:
(10-50) mA ± 1.0 mA
Operate level for non-directional (1.00-200.00)% of UBase ± 0.5% of Ur at U£Ur
residual overvoltage ± 0.5% of U at U > Ur
Residual release current for all (0.25-200.00)% of lBase ± 1.0% of Ir at I £ Ir

directional modes ± 1.0% of I at I > Ir
At low setting:
(2.5-10) mA ±0.5 mA
(10-50) mA ± 1.0 mA
Residual release voltage for all (0.01-200.00)% of UBase ± 0.5% of Ur at U£Ur
directional modes ± 0.5% of U at U > Ur
Reset ratio > 95% -

Timers (0.000-60.000) s ± 0.5% ±10 ms
table 582, table 583 and table table 584
584
Relay characteristic angle RCA (-179 to 180) degrees ± 2.0 degrees
Relay open angle ROA (0-90) degrees ± 2.0 degrees
Operate time, non-directional 60 ms typically at 0 to 2 x Iset -
residual over current
Reset time, non-directional 60 ms typically at 2 to 0 x Iset -
residual over current
317
Current protection
7.7 Thermal overload protection, two time constants

TRPTTR

Thermal overload protection, two time TRPTTR 49
constants
SYMBOL-A V1 EN
7.7.1 Introduction
If a power transformer or generator reaches very high temperatures the equipment
might be damaged. The insulation within the transformer/generator will have
forced ageing. As a consequence of this the risk of internal phase-to-phase or phase-
to-earth faults will increase. High temperature will degrade the quality of the
transformer/generator insulation.
The thermal overload protection estimates the internal heat content of the transformer/
generator (temperature) continuously. This estimation is made by using a thermal
model of the transformer/generator with two time constants, which is based on
current measurement.
Two warning levels are available. This enables actions in the power system to be
done before dangerous temperatures are reached. If the temperature continues to
increase to the trip value, the protection initiates a trip of the protected transformer/
generator.

The sampled analogue phase currents are pre-processed and for each phase current
the true RMS value of each phase current is derived. These phase current values
are fed to the Thermal overload protection, two time constants (TRPTTR).
From the largest of the three phase currents a relative final temperature (heat
content) is calculated according to the expression:
318
Current protection
2
æ I ö
Q final =ç ÷÷
ç I ref
è ø
where:
I is the largest phase current
Iref is a given reference current
If this calculated relative temperature is larger than the relative temperature level
corresponding to the set operate (trip) current a start output signal START is activated.
The actual temperature at the actual execution cycle is calculated as:
If Q final > Q n
æ Dt
ö
Qn = Qn -1 + ( Q final - Q n-1 ) × ç1 - e t ÷
-
è ø
If Q final < Qn
Dt
Qn = Q final - ( Q final - Q n -1 ) × e
-
t
where:
Qn is the calculated present temperature
Qn-1 is the calculated temperature at the

previous time step
Qfinal is the calculated final (steady state)
temperature with the actual current
Dt is the time step between calculation of the
actual and final temperature
t is the set thermal time constant Tau1 or
Tau2 for the protected transformer
The calculated transformer relative temperature can be monitored as it is exported

from the function as a real figure HEATCONT.
319
Current protection
When the transformer temperature reaches any of the set alarm levels Alarm1 or
Alarm2 the corresponding output signals ALARM1 or ALARM2 are activated.
When the temperature of the object reaches the set trip level which corresponds to
continuous current equal to ITrip the output signal TRIP is activated.
There is also a calculation of the present time to operation with the present current.
This calculation is only performed if the final temperature is calculated to be above
the operation temperature:
æQ - Qoperate ö
toperate = -t × ln ç final
ç Q final - Q n ÷÷
è ø
The calculated time to trip can be monitored as it is exported from the function as a
real figure TTRIP.
After a trip, caused by the thermal overload protection, there can be a lockout to
reconnect the tripped circuit. The output lockout signal LOCKOUT is activated
when the temperature of the object is above the set lockout release temperature
setting ResLo.
The time to lockout release is calculated, That is, a calculation of the cooling time
to a set value.
æQ - Qlockout _ release ö
tlockout _ release = -t × ln ç final ÷÷
ç Q final - Q n
è ø
In the above equation, the final temperature is calculated according to equation 67.
Since the transformer normally is disconnected, the current I is zero and thereby
the Θfinal is also zero. The calculated component temperature can be monitored as it
is exported from the function as a real figure, TRESLO.
When the current is so high that it has given a start signal START, the estimated
time to trip is continuously calculated and given as analogue output TTRIP. If this
calculated time get less than the setting time Warning, set in minutes, the output
WARNING is activated.
In case of trip a pulse with a set duration tPulse is activated.
320
Current protection
Final Temp START

> TripTemp
actual heat comtent

Calculation
of heat
content
I3P
Calculation
of final
temperature
ALARM1
Actual Temp >
Alarm1,Alarm2
ALARM2
Temp
Current base used

TRIP
Actual Temp
> TripTemp
S LOCKOUT
Binary input:
Forced cooling Management of R
On/Off setting
parameters: Tau,
Actual Temp
IBase Tau used
< Recl
Temp
time to trip
Calculation
of time to
warning if time to trip < set value
trip
Calculation
of time to time to reset of lockout
reset of
lockout
en05000833.vsd
IEC05000833 V1 EN
Figure 151: Functional overview of TRPTTR
321
Current protection

TRPTTR
I3P* TRIP
BLOCK START
COOLING ALARM1
ENMULT ALARM2
RESET LOCKOUT
WARNING
IEC06000272 V2 EN
Figure 152: TRPTTR function block

Table 160: TRPTTR Input signals
SIGNAL
COOLING BOOLEAN 0 Cooling input Off / On. Changes Ib setting and
time constant
ENMULT BOOLEAN 0 Enable Multiplier for currentReference setting
RESET BOOLEAN 0 Reset of function
Table 161: TRPTTR Output signals

TRIP BOOLEAN Trip Signal
START BOOLEAN Start signal
ALARM1 BOOLEAN First level alarm signal
ALARM2 BOOLEAN Second level alarm signal
LOCKOUT BOOLEAN Lockout signal
WARNING BOOLEAN Warning signal: Trip within set warning time

Table 162: TRPTTR Group settings (basic)
On
IBase 1 - 99999 A 1 3000 Base current in A
IRef 10.0 - 1000.0 %IB 1.0 100.0 Reference current in % of IBASE
IRefMult 0.01 - 10.00 - 0.01 1.00 Multiplication Factor for reference current
322
Current protection

IBase1 30.0 - 250.0 %IB 1.0 100.0 Base current,IBase1 without Cooling
inpout in % of IBASE
IBase2 30.0 - 250.0 %IB 1.0 100.0 Base Current,IBase2, with Cooling input
ON in % of IBASE
Tau1 1.0 - 500.0 Min 1.0 60.0 Time constant without cooling input in
min, with IBase1
Tau2 1.0 - 500.0 Min 1.0 60.0 Time constant with cooling input in min,
with IBase2
IHighTau1 30.0 - 250.0 %IB1 1.0 100.0 Current Sett, in % of IBase1 for rescaling
TC1 by TC1-IHIGH
Tau1High 5 - 2000 %tC1 1 100 Multiplier in % to TC1 when current is >
IHIGH-TC1
ILowTau1 30.0 - 250.0 %IB1 1.0 100.0 Current Set, in % of IBase1 for rescaling
TC1 by TC1-ILOW
Tau1Low 5 - 2000 %tC1 1 100 Multiplier in % to TC1 when current is <
ILOW-TC1
IHighTau2 30.0 - 250.0 %IB2 1.0 100.0 Current Set, in % of IBase2 for rescaling
TC2 by TC2-IHIGH
Tau2High 5 - 2000 %tC2 1 100 Multiplier in % to TC2 when current is
>IHIGH-TC2
ILowTau2 30.0 - 250.0 %IB2 1.0 100.0 Current Set, in % of IBase2 for rescaling
TC2 by TC2-ILOW
Tau2Low 5 - 2000 %tC2 1 100 Multiplier in % to TC2 when current is <
ILOW-TC2
ITrip 50.0 - 250.0 %IBx 1.0 110.0 Steady state operate current level in %
of IBasex
Alarm1 50.0 - 99.0 %Itr 1.0 80.0 First alarm level in % of heat content trip
value
Alarm2 50.0 - 99.0 %Itr 1.0 90.0 Second alarm level in % of heat content
trip value
ResLo 10.0 - 95.0 %Itr 1.0 60.0 Lockout reset level in % of heat content
trip value
ThetaInit 0.0 - 95.0 % 1.0 50.0 Initial Heat content, in % of heat content
trip value
Warning 1.0 - 500.0 Min 0.1 30.0 Time setting, below which warning would
be set (in min)
tPulse 0.01 - 0.30 s 0.01 0.10 Length of the pulse for trip signal (in
msec).
323
Current protection

Table 163: TRPTTR technical data
Base current 1 and 2 (30–250)% of IBase ± 1.0% of Ir
Operate time: Ip = load current before overload IEC 60255–8, class 5 + 200
occurs ms
æ I 2 - I p2 ö Time constant τ = (1–500)
t = t × ln ç 2 ÷ minutes
ç I - Ib 2 ÷
è ø
I = Imeasured
Alarm level 1 and 2 (50–99)% of heat content trip ± 2.0% of heat content trip
value
Operate current (50–250)% of IBase ± 1.0% of Ir
Reset level temperature (10–95)% of heat content trip ± 2.0% of heat content trip
7.8 Breaker failure protection CCRBRF

Breaker failure protection CCRBRF 50BF
3I>BF
SYMBOL-U V1 EN
7.8.1 Introduction
Breaker failure protection (CCRBRF) ensures fast back-up tripping of surrounding
breakers in case the own breaker fails to open. CCRBRF can be current based,
contact based, or an adaptive combination of these two conditions.
Current check with extremely short reset time is used as check criterion to achieve
high security against unnecessary operation.
Contact check criteria can be used where the fault current through the breaker is small.
CCRBRF can be single- or three-phase initiated to allow use with single phase
tripping applications. For the three-phase version of CCRBRF the current criteria
can be set to operate only if two out of four for example, two phases or one phase
plus the residual current start. This gives a higher security to the back-up trip
command.
324
Current protection
CCRBRF function can be programmed to give a single- or three-phase re-trip of

the own breaker to avoid unnecessary tripping of surrounding breakers at an
incorrect initiation due to mistakes during testing.

Breaker failure protection CCRBRF is initiated from protection trip command,
either from protection functions within the IED or from external protection devices.
The start signal can be phase selective or general (for all three phases). Phase
selective start signals enable single pole re-trip function. This means that a second
attempt to open the breaker is done. The re-trip attempt can be made after a set
time delay. For transmission lines single pole trip and autoreclosing is often used.
The re-trip function can be phase selective if it is initiated from phase selective line
protection. The re-trip function can be done with or without current check. With
the current check the re-trip is only performed if the current through the circuit
breaker is larger than the operate current level.
The start signal can be an internal or external protection trip signal. This signal will
start the back-up trip timer. If the opening of the breaker is successful this is
detected by the function, by detection of either low current through RMS
evaluation and a special adapted current algorithm or by open contact indication.
The special algorithm enables a very fast detection of successful breaker opening,
that is, fast resetting of the current measurement. If the current and/or contact
detection has not detected breaker opening before the back-up timer has run its
time a back-up trip is initiated.
Further the following possibilities are available:
• The minimum length of the re-trip pulse, the back-up trip pulse and the back-
up trip pulse 2 are settable. The re-trip pulse, the back-up trip pulse and the back-
up trip pulse 2 will however sustain as long as there is an indication of closed
breaker.
• In the current detection it is possible to use three different options: 1 out of 3
where it is sufficient to detect failure to open (high current) in one pole, 1 out
of 4 where it is sufficient to detect failure to open (high current) in one pole or
high residual current and 2 out of 4 where at least two current (phase current and/
or residual current) shall be high for breaker failure detection.
• The current detection level for the residual current can be set different from the
setting of phase current detection.
• It is possible to have different back-up time delays for single-phase faults and
for multi-phase faults.
• The back-up trip can be made without current check. It is possible to have this
option activated for small load currents only.
• It is possible to have instantaneous back-up trip function if a signal is high if
the circuit breaker is insufficient to clear faults, for example at low gas pressure.
325
Current protection
START 30 ms
STL1 OR BFP Started L1

150 ms
AND S
SR Q t
Time out L1
R AND
BLOCK
OR
Reset L1
Retrip Time Out L1
BackupTrip L1 OR
IEC09000976 V1 EN
Figure 153: Simplified logic scheme of the CCRBRF starting logic
IP>
a
a>b
b
FunctionMode Current
OR AND Reset L1
OR
Contact
1 Time out L1
Current and Contact OR
AND
Current High L1
IL1 CB Closed L1
AND
OR
BFP Started L1
a AND AND
a>b OR AND
I>BlkCont b
CBCLDL1 Contact Closed L1

AND
IEC09000977 V1 EN
Figure 154: Simplified logic scheme of the CCRBRF, CB position evaluation
t1 TRRETL3
BFP Started L1 From other
t Retrip Time Out L1
phases TRRETL2 OR
TRRET
tPulse
RetripMode No CBPos Check AND
OR TRRETL1
OR
1
OR AND
CB Pos Check
AND
CB Closed L1
CBFLT
IEC09000978 V1 EN
Figure 155: Simplified logic scheme of the retrip logic function
326
Current protection
IN
a
a>b AND
IN> b
BUTripMode Contact Closed L1

2 out of 4
1 out of 4 OR
1
1 out of 3 OR
Current High L2
From other
Current High L3
phases
Current High L1 AND
CBFLT
AND
t2
BFP Started L1 Backup Trip L1
t AND
OR
t2MPh
AND t
AND
OR OR
tPulse
From other Backup Trip L2 OR TRBU
OR
phases Backup Trip L3
From other BFP Started L2 2 of 3
phases BFP Started L3 tPulse
t3
OR
TRBU2
S Q t
R SR
AND
IEC09000979 V1 EN
Figure 156: Simplified logic scheme of the back-up trip logic function
Internal logical signals Current High L1, Current High L2, Current High L3 have
logical value 1 when current in respective phase has magnitude larger than setting
parameter IP>.

CCRBRF
I3P* TRBU
BLOCK TRBU2
START TRRET
STL1 TRRETL1
STL2 TRRETL2
STL3 TRRETL3
CBCLDL1 CBALARM
CBCLDL2
CBCLDL3
CBFLT
IEC06000188 V2 EN
Figure 157: CCRBRF function block
327
Current protection

Table 164: CCRBRF Input signals
I3P GROUP - Three phase group signal for current inputs
SIGNAL
START BOOLEAN 0 Three phase start of breaker failure protection
function
STL1 BOOLEAN 0 Start signal of phase L1
CBCLDL1 BOOLEAN 1 Circuit breaker closed in phase L1
CBFLT BOOLEAN 0 CB faulty, unable to trip. Back-up trip
instantaneously
Table 165: CCRBRF Output signals

TRBU BOOLEAN Back-up trip by breaker failure protection function
TRBU2 BOOLEAN Second back-up trip by breaker failure protection
function
TRRET BOOLEAN Retrip by breaker failure protection function
TRRETL1 BOOLEAN Retrip by breaker failure protection function
phase L1
phase L2
phase L3
CBALARM BOOLEAN Alarm for faulty circuit breaker

Table 166: CCRBRF Group settings (basic)
On
FunctionMode Current - - Current Detection principle for back-up trip
Contact
Current&Contact
328
Current protection

BuTripMode 2 out of 4 - - 1 out of 3 Back-up trip mode
1 out of 3
1 out of 4
RetripMode Retrip Off - - Retrip Off Operation mode of re-trip logic
CB Pos Check
No CBPos Check
IP> 5 - 200 %IB 1 10 Operate phase current level in % of IBase
IN> 2 - 200 %IB 1 10 Operate residual current level in % of
IBase
t1 0.000 - 60.000 s 0.001 0.000 Time delay of re-trip
t2 0.000 - 60.000 s 0.001 0.150 Time delay of back-up trip
t2MPh 0.000 - 60.000 s 0.001 0.150 Time delay of back-up trip at multi-phase
start
tPulse 0.000 - 60.000 s 0.001 0.200 Trip pulse duration
Table 167: CCRBRF Group settings (advanced)

I>BlkCont 5 - 200 %IB 1 20 Current for blocking of CB contact
operation in % of IBase
t3 0.000 - 60.000 s 0.001 0.030 Additional time delay to t2 for a second
back-up trip
tCBAlarm 0.000 - 60.000 s 0.001 5.000 Time delay for CB faulty signal

Table 168: CCRBRF technical data
Operate phase (5-200)% of lBase ± 1.0% of Ir at I £ Ir
current ± 1.0% of I at I > Ir
Reset ratio, phase > 95% -

current
Operate residual (2-200)% of lBase ± 1.0% of Ir at I £ Ir
current ± 1.0% of I at I > Ir
Reset ratio, residual > 95% -

current
Phase current level (5-200)% of lBase ± 1.0% of Ir at I £ Ir
for blocking of ± 1.0% of I at I > Ir
contact function
Reset ratio > 95% -
Timers (0.000-60.000) s ± 0.5% ±10 ms
Operate time for 10 ms typically -
current detection
Reset time for 15 ms maximum -
current detection
329
Current protection
7.9 Pole discordance protection CCRPLD

Pole discordance protection CCRPLD 52PD
PD
SYMBOL-S V1 EN
7.9.1 Introduction
An open phase can cause negative and zero sequence currents which cause thermal
stress on rotating machines and can cause unwanted operation of zero sequence or
negative sequence current functions.
Normally the own breaker is tripped to correct such a situation. If the situation
persists the surrounding breakers should be tripped to clear the unsymmetrical load
situation.
The Polediscordance protection function CCRPLD operates based on information

from auxiliary contacts of the circuit breaker for the three phases with additional
criteria from unsymmetrical phase currents when required.

The detection of pole discordance can be made in two different ways. If the contact
based function is used an external logic can be made by connecting the auxiliary
contacts of the circuit breaker so that a pole discordance is indicated, see figure 158.
circuit breaker
Pole discordance signal from circuit breaker
en05000287.vsd
IEC05000287 V2 EN
Figure 158: Pole discordance external detection logic
This binary signal is connected to a binary input of the IED. The appearance of this
signal will start a timer that will give a trip signal after the set time delay.
330
Current protection
There is also a possibility to connect all phase selective auxiliary contacts (phase
contact open and phase contact closed) to binary inputs of the IED, see figure 159.
C.B.
poleOneClosed from C.B.
poleTwoClosed from C.B.
poleThreeClosed from C.B.
+
poleOneOpened from C.B.
poleTwoOpened from C.B.
poleThreeOpened from C.B.
en05000288.vsd
IEC05000288 V1 EN
Figure 159: Pole discordance signals for internal logic
In this case the logic is realized within the function. If the inputs are indicating pole
discordance the trip timer is started. This timer will give a trip signal after the set
delay.
Pole discordance can also be detected by means of phase selective current

measurement. The sampled analog phase currents are pre-processed in a discrete
Fourier filter (DFT) block. From the fundamental frequency components of each
phase current the RMS value of each phase current is derived. The smallest and the
largest phase current are derived. If the smallest phase current is lower than the
setting CurrUnsymLevel times the largest phase current the settable trip timer
(tTrip) is started. The tTrip timer gives a trip signal after the set delay. The TRIP
signal is a pulse 150 ms long. The current based pole discordance function can be
set to be active either continuously or only directly in connection to breaker open
or close command.
The function also has a binary input that can be configured from the autoreclosing
function, so that the pole discordance function can be blocked during sequences
with a single pole open if single pole autoreclosing is used.
The simplified block diagram of the current and contact based Pole discordance
protection function CCRPLD is shown in figure 160.
331
Current protection
BLOCK
OR
BLKDBYAR
PolPosAuxCont
AND
POLE1OPN
POLE1CL
POLE2OPN
Discordance
POLE2CL
detection
POLE3OPN
POLE3CL t 150 ms
t TRIP
AND
OR
PD Signal from CB
AND
EXTPDIND
CLOSECMD t+200 ms
OR
OPENCMD
AND
Unsymmetry current
detection
en05000747.vsd
IEC05000747 V1 EN
Figure 160: Simplified block diagram of pole discordance function CCRPLD -

contact and current based
CCRPLDis blocked if:
• The IED is in TEST mode and CCRPLD has been blocked from the local HMI
• The input signal BLOCK is high
• The input signal BLKDBYAR is high
The BLOCK signal is a general purpose blocking signal of the pole discordance
protection. It can be connected to a binary input in the IED in order to receive a
block command from external devices or can be software connected to other
internal functions in the IED itself in order to receive a block command from
internal functions. Through OR gate it can be connected to both binary inputs and
internal function outputs.
The BLKDBYAR signal blocks the pole discordance operation when a single
phase autoreclosing cycle is in progress. It can be connected to the output signal
1PT1 on SMBRRECfunction block. If the autoreclosing function is an external
device, then BLKDBYAR has to be connected to a binary input in the IED and this
binary input is connected to a signalization “1phase autoreclosing in progress”
from the external autoreclosing device.
If the pole discordance protection is enabled, then two different criteria can
generate a trip signal TRIP:
• Pole discordance signaling from the circuit breaker.

• Unsymmetrical current detection.
332
Current protection
7.9.2.1 Pole discordance signaling from circuit breaker
If one or two poles of the circuit breaker have failed to open or to close the pole
discordance status, then the function input EXTPDIND is activated from the pole
discordance signal derived from the circuit breaker auxiliary contacts (one NO
contact for each phase connected in parallel, and in series with one NC contact for
each phase connected in parallel) and, after a settable time interval tTrip (0-60 s), a
150 ms trip pulse command TRIP is generated by the Polediscordance function.
7.9.2.2 Unsymmetrical current detection
Unsymmetrical current indicated if:
• any phase current is lower than CurrUnsymLevel of the highest current in the
three phases.
• the highest phase current is greater than CurrRelLevel of IBase.
If these conditions are true, an unsymmetrical condition is detected and the internal
signal INPS is turned high. This detection is enabled to generate a trip after a set
time delay tTrip if the detection occurs in the next 200 ms after the circuit breaker
has received a command to open trip or close and if the unbalance persists. The 200
ms limitation is for avoiding unwanted operation during unsymmetrical load
conditions.
The pole discordance protection is informed that a trip or close command has been
given to the circuit breaker through the inputs CLOSECMD (for closing command
information) and OPENCMD (for opening command information). These inputs
can be connected to terminal binary inputs if the information are generated from
the field (that is from auxiliary contacts of the close and open push buttons) or may
be software connected to the outputs of other integrated functions (that is close
command from a control function or a general trip from integrated protections).

CCRPLD
I3P* TRIP
BLOCK START
BLKDBYAR
CLOSECMD
OPENCMD
EXTPDIND
POLE1OPN
POLE1CL
POLE2OPN
POLE2CL
POLE3OPN
POLE3CL
IEC06000275 V2 EN
Figure 161: CCRPLD function block
333
Current protection

Table 169: CCRPLD Input signals
I3P GROUP - Three phase currents
SIGNAL
BLKDBYAR BOOLEAN 0 Block of function at CB single phase auto re-
closing cycle
CLOSECMD BOOLEAN 0 Close order to CB
OPENCMD BOOLEAN 0 Open order to CB
EXTPDIND BOOLEAN 0 Pole discordance signal from CB logic
POLE1OPN BOOLEAN 1 Pole one opened indication from CB
POLE1CL BOOLEAN 0 Pole one closed indication from CB
POLE2OPN BOOLEAN 1 Pole two opened indication from CB
POLE2CL BOOLEAN 0 Pole two closed indication from CB
POLE3OPN BOOLEAN 1 Pole three opened indication from CB
POLE3CL BOOLEAN 0 Pole three closed indication from CB
Table 170: CCRPLD Output signals

TRIP BOOLEAN Trip signal to CB
START BOOLEAN Trip condition TRUE, waiting for time delay

Table 171: CCRPLD Group settings (basic)
On
IBase 1 - 99999 - 1 3000 Base current
tTrip 0.000 - 60.000 s 0.001 0.300 Time delay between trip condition and
trip signal
ContSel Off - - Off Contact function selection
PD signal from CB
Pole pos aux cont.
CurrSel Off - - Off Current function selection
CB oper monitor
Continuous monitor
CurrUnsymLevel 0 - 100 % 1 80 Unsym magn of lowest phase current
compared to the highest.
CurrRelLevel 0 - 100 %IB 1 10 Current magnitude for release of the
function in % of IBase
334
Current protection

Table 172: CCRPLD technical data
Operate current (0–100)% of IBase ± 1.0% of Ir
Time delay (0.000-60.000) s ± 0.5% ± 10 ms
7.10 Directional underpower protection GUPPDUP

Directional underpower protection GUPPDUP 37
P<
SYMBOL-LL V1 EN
7.10.1 Introduction
The task of a generator in a power plant is to convert mechanical energy available
as a torque on a rotating shaft to electric energy.
Sometimes, the mechanical power from a prime mover may decrease so much that
it does not cover bearing losses and ventilation losses. Then, the synchronous
generator becomes a synchronous motor and starts to take electric power from the
rest of the power system. This operating state, where individual synchronous
machines operate as motors, implies no risk for the machine itself. If the generator
under consideration is very large and if it consumes lots of electric power, it may
be desirable to disconnect it to ease the task for the rest of the power system.
Often, the motoring condition may imply that the turbine is in a very dangerous
state. The task of the reverse power protection is to protect the turbine and not to
protect the generator itself.
Figure 162 illustrates the low forward power and reverse power protection with
underpower and overpower functions respectively. The underpower IED gives a
higher margin and should provide better dependability. On the other hand, the risk
for unwanted operation immediately after synchronization may be higher. One
should set the underpower IED to trip if the active power from the generator is less
than about 2%. One should set the overpower IED to trip if the power flow from
the network to the generator is higher than 1% depending on the type of turbine.
When IED with a metering class input CTs is used pickup can be set to more
sensitive value (e.g.0,5% or even to 0,2%).
335
Current protection
Underpower IED Overpower IED
Operate
Q Q
Operate
Line Line
Margin Margin
P P
Operating point Operating point

without without
turbine torque turbine torque
IEC06000315 V2 EN
Figure 162: Protection with underpower IED and overpower IED

A simplified scheme showing the principle of the power protection function is
shown in figure 163. The function has two stages with individual settings.
Chosen current
phasors P
Complex Derivation of S(angle)

S(angle) < t TRIP1
power S(composant)
Chosen voltage Power1
calculation in Char angle
phasors Q
START1
S(angle) < t TRIP2

Power2
START2
P = POWRE
Q = POWIM
IEC09000018 V2 EN
Figure 163: Simplified logic diagram of the power protection function
The function will use voltage and current phasors calculated in the pre-processing
blocks. The apparent complex power is calculated according to chosen formula as
shown in table 173.
336
Current protection
Table 173: Complex power calculation

Set value: Mode Formula used for complex power calculation
L1, L2, L3
S = U L1 × I L1* + U L 2 × I L 2* + U L 3 × I L 3*
Arone
S = U L1L 2 × I L1* - U L 2 L 3 × I L 3*
PosSeq
S = 3 × U PosSeq × I PosSeq *
L1L2
S = U L1L 2 × ( I L1* - I L 2* )
L2L3
S = U L 2 L 3 × ( I L 2* - I L 3* )
L3L1
S = U L 3 L1 × ( I L 3* - I L1* )
L1
S = 3 × U L1 × I L1*
L2
S = 3 × U L 2 × I L 2*
L3
S = 3 × U L 3 × I L 3*
The active and reactive power is available from the function and can be used for
monitoring and fault recording.
The component of the complex power S = P + jQ in the direction Angle1(2) is

calculated. If this angle is 0° the active power component P is calculated. If this
angle is 90° the reactive power component Q is calculated.
The calculated power component is compared to the power pick up setting

Power1(2). For directional underpower protection, a start signal START1(2) is
activated if the calculated power component is smaller than the pick up value. For
directional overpower protection, a start signal START1(2) is activated if the
calculated power component is larger than the pick up value. After a set time delay
TripDelay1(2) a trip TRIP1(2) signal is activated if the start signal is still active. At
activation of any of the two stages a common signal START will be activated. At
trip from any of the two stages also a common signal TRIP will be activated.
To avoid instability there is a settable hysteresis in the power function. The

absolute hysteresis of the stage1(2) is Hysteresis1(2) = abs (Power1(2) + drop-
power1(2)). For generator low forward power protection the power setting is very
337
Current protection
low, normally down to 0.02 p.u. of rated generator power. The hysteresis should
therefore be set to a smaller value. The drop-power value of stage1 can be
calculated with the Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2) +
Hysteresis1(2)
For small power1 values the hysteresis1 may not be too big, because the drop-
power1(2) would be too small. In such cases, the hysteresis1 greater than (0.5 ·
Power1(2)) is corrected to the minimal value.
If the measured power drops under the drop-power1(2) value, the function will
reset after a set time DropDelay1(2). The reset means that the start signal will drop
out and that the timer of the stage will reset.
7.10.2.1 Low pass filtering
In order to minimize the influence of the noise signal on the measurement it is

possible to introduce the recursive, low pass filtering of the measured values for S
(P, Q). This will make slower measurement response to the step changes in the
measured quantity. Filtering is performed in accordance with the following
recursive formula:
S = k × SOld + (1 - k ) × SCalculated
Where
S is a new measured value to be used for the protection function
Sold is the measured value given from the function in previous execution cycle
SCalculated is the new calculated value in the present execution cycle
k is settable parameter by the end user which influence the filter properties
TD
Default value for parameter k is 0.00. With this value the new calculated value is
immediately given out without any filtering (that is without any additional delay).
When k is set to value bigger than 0, the filtering is enabled. A typical value for
k=0.92 in case of slow operating functions.
7.10.2.2 Calibration of analog inputs
Measured currents and voltages used in the Power function can be calibrated to get
class 0.5 measuring accuracy. This is achieved by amplitude and angle
compensation at 5, 30 and 100% of rated current and voltage. The compensation
below 5% and above 100% is constant and linear in between, see example in figure
164.
338
Current protection
IEC05000652 V2 EN
Figure 164: Calibration curves
The first current and voltage phase in the group signals will be used as reference
and the amplitude and angle compensation will be used for related input signals.
Analog outputs (Monitored data) from the function can be used for service values
or in the disturbance report. The active power is provided as MW value: P, or in
percent of base power: PPERCENT. The reactive power is provided as Mvar value:
Q, or in percent of base power: QPERCENT.

GUPPDUP
I3P* TRIP
U3P* TRIP1
BLOCK TRIP2
BLOCK1 START
BLOCK2 START1
START2
P
PPERCENT
Q
QPERCENT
IEC07000027 V2 EN
Figure 165: GUPPDUP function block
339
Current protection

Table 174: GUPPDUP Input signals
SIGNAL
SIGNAL
BLOCK1 BOOLEAN 0 Block of stage 1
Table 175: GUPPDUP Output signals

TRIP1 BOOLEAN Trip of stage 1
START BOOLEAN Common start
START1 BOOLEAN Start of stage 1
P REAL Active Power in MW
PPERCENT REAL Active power in % of SBASE
Q REAL Reactive power in Mvar
QPERCENT REAL Reactive power in % of SBASE

Table 176: GUPPDUP Group settings (basic)
On
OpMode1 Off - - UnderPower Operation mode 1
UnderPower
Power1 0.0 - 500.0 %SB 0.1 1.0 Power setting for stage 1 in % of Sbase
Angle1 -180.0 - 180.0 Deg 0.1 0.0 Angle for stage 1
TripDelay1 0.010 - 6000.000 s 0.001 1.000 Trip delay for stage 1
DropDelay1 0.010 - 6000.000 s 0.001 0.060 Drop delay for stage 1
OpMode2 Off - - UnderPower Operation mode 2
UnderPower
340
Current protection
Table 177: GUPPDUP Group settings (advanced)

k 0.000 - 0.999 - 0.001 0.000 Low pass filter coefficient for power
measurement, P and Q
Hysteresis1 0.2 - 5.0 pu 0.1 0.5 Absolute hysteresis of stage 1 in % Sbase
Hysteresis2 0.2 - 5.0 pu 0.1 0.5 Absolute hysteresis of stage 2 in % Sbase
IAmpComp5 -10.000 - 10.000 % 0.001 0.000 Amplitude factor to calibrate current at
5% of Ir
30% of Ir
100% of Ir
UAmpComp5 -10.000 - 10.000 % 0.001 0.000 Amplitude factor to calibrate voltage at
5% of Ur
30% of Ur
100% of Ur
IAngComp5 -10.000 - 10.000 Deg 0.001 0.000 Angle calibration for current at 5% of Ir
Table 178: GUPPDUP Non group settings (basic)

IBase 1 - 99999 A 1 3000 Base setting for current level
UBase 0.05 - 2000.00 kV 0.05 400.00 Base setting for voltage level
Mode L1, L2, L3 - - Pos Seq Selection of measured current and
Arone voltage
Pos Seq
L1L2
L2L3
L3L1
L1
L2
L3

Table 179: GUPPDUP technical data
Power level (0.0–500.0)% of SBase ± 1.0% of Sr at S < Sr
± 1.0% of S at S > Sr
At low setting:
(0.5-2.0)% of SBase < ± 50% of set value
(2.0-10)% of SBase < ± 20% of set value
Characteristic angle (-180.0–180.0) degrees 2 degrees
Timers (0.00-6000.00) s ± 0.5% ± 10 ms
341
Current protection
7.11 Directional overpower protection GOPPDOP

Directional overpower protection GOPPDOP 32
P>
DOCUMENT172362-IMG158942
V1 EN
7.11.1 Introduction
The task of a generator in a power plant is to convert mechanical energy available
as a torque on a rotating shaft to electric energy.
Sometimes, the mechanical power from a prime mover may decrease so much that
it does not cover bearing losses and ventilation losses. Then, the synchronous
generator becomes a synchronous motor and starts to take electric power from the
rest of the power system. This operating state, where individual synchronous
machines operate as motors, implies no risk for the machine itself. If the generator
under consideration is very large and if it consumes lots of electric power, it may
be desirable to disconnect it to ease the task for the rest of the power system.
Often, the motoring condition may imply that the turbine is in a very dangerous
state. The task of the reverse power protection is to protect the turbine and not to
protect the generator itself.
Figure 166 illustrates the low forward power and reverse power protection with
underpower and overpower functions respectively. The underpower IED gives a
higher margin and should provide better dependability. On the other hand, the risk
for unwanted operation immediately after synchronization may be higher. One
should set the underpower IED to trip if the active power from the generator is less
than about 2%. One should set the overpower IED to trip if the power flow from
the network to the generator is higher than 1%.
When IED with a metering class input CTs is used pickup can be set to more
sensitive value (e.g.0,5% or even to 0,2%).
342
Current protection
Underpower IED Overpower IED
Operate
Q Q
Operate
Line Line
Margin Margin
P P
Operating point Operating point

without without
turbine torque turbine torque
IEC06000315 V2 EN
Figure 166: Reverse power protection with underpower IED and overpower IED

A simplified scheme showing the principle of the power protection function is
shown in figure 167. The function has two stages with individual settings.
Chosen current
phasors P
Complex Derivation of S(angle)

S(angle) > t TRIP1
power S(composant)
Chosen voltage Power1
calculation in Char angle
phasors Q
START1
S(angle) > t TRIP2

Power2
START2
P = POWRE
Q = POWIM
IEC06000567 V2 EN
Figure 167: Simplified logic diagram of the power protection function
The function will use voltage and current phasors calculated in the pre-processing
blocks. The apparent complex power is calculated according to chosen formula as
shown in table 180.
343
Current protection
Table 180: Complex power calculation

Set value: Mode Formula used for complex power calculation
L1, L2, L3
S = U L1 × I L1* + U L 2 × I L 2* + U L 3 × I L 3*
Arone
S = U L1L 2 × I L1* - U L 2 L 3 × I L 3*
PosSeq
S = 3 × U PosSeq × I PosSeq *
L1L2
S = U L1L 2 × ( I L1* - I L 2* )
L2L3
S = U L 2 L 3 × ( I L 2* - I L 3* )
L3L1
S = U L 3 L1 × ( I L 3* - I L1* )
L1
S = 3 × U L1 × I L1*
L2
S = 3 × U L 2 × I L 2*
L3
S = 3 × U L 3 × I L 3*
The active and reactive power is available from the function and can be used for
monitoring and fault recording.
The component of the complex power S = P + jQ in the direction Angle1(2) is

calculated. If this angle is 0° the active power component P is calculated. If this
angle is 90° the reactive power component Q is calculated.
The calculated power component is compared to the power pick up setting

Power1(2). A start signal START1(2) is activated if the calculated power
component is larger than the pick up value. After a set time delay TripDelay1(2) a
trip TRIP1(2) signal is activated if the start signal is still active. At activation of
any of the two stages a common signal START will be activated. At trip from any
of the two stages also a common signal TRIP will be activated.
To avoid instability there is a settable hysteresis in the power function. The

absolute hysteresis of the stage1(2) is Hysteresis1(2) = abs (Power1(2) – drop-
power1(2)). For generator reverse power protection the power setting is very low,
normally down to 0.02 p.u. of rated generator power. The hysteresis should
therefore be set to a smaller value. The drop-power value of stage1 can be
344
Current protection
calculated with the Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2) –

Hysteresis1(2)
For small power1 values the hysteresis1 may not be too big, because the drop-
power1(2) would be too small. In such cases, the hysteresis1 greater than (0.5 ·
Power1(2)) is corrected to the minimal value.
If the measured power drops under the drop-power1(2) value the function will reset
after a set time DropDelay1(2). The reset means that the start signal will drop out
ant that the timer of the stage will reset.
7.11.2.1 Low pass filtering

possible to introduce the recursive, low pass filtering of the measured values for S
(P, Q). This will make slower measurement response to the step changes in the
measured quantity. Filtering is performed in accordance with the following
recursive formula:
S = k × SOld + (1 - k ) × SCalculated
Where
S is a new measured value to be used for the protection function
Sold is the measured value given from the function in previous execution cycle
SCalculated is the new calculated value in the present execution cycle
immediately given out without any filtering (that is, without any additional delay).
When k is set to value bigger than 0, the filtering is enabled. A typical value for k =
0.92 in case of slow operating functions.
7.11.2.2 Calibration of analog inputs
Measured currents and voltages used in the Power function can be calibrated to get
class 0.5 measuring accuracy. This is achieved by amplitude and angle
below 5% and above 100% is constant and linear in between, see example in figure
168.
345
Current protection
IEC05000652 V2 EN
Analog outputs from the function can be used for service values or in the
disturbance report. The active power is provided as MW value: P, or in percent of
base power: PPERCENT. The reactive power is provided as Mvar value: Q, or in
percent of base power: QPERCENT.

GOPPDOP
I3P* TRIP
U3P* TRIP1
BLOCK TRIP2
BLOCK1 START
BLOCK2 START1
START2
P
PPERCENT
Q
QPERCENT
IEC07000028 V2 EN
Figure 169: GOPPDOP function block
346
Current protection

Table 181: GOPPDOP Input signals
SIGNAL
SIGNAL
Table 182: GOPPDOP Output signals

START BOOLEAN Common start
P REAL Active Power in MW
PPERCENT REAL Active power in % of SBASE
Q REAL Reactive power in Mvar
QPERCENT REAL Reactive power in % of SBASE

Table 183: GOPPDOP Group settings (basic)
On
OpMode1 Off - - OverPower Operation mode 1
OverPower
OpMode2 Off - - OverPower Operation mode 2
OverPower
347
Current protection
Table 184: GOPPDOP Group settings (advanced)

measurement, P and Q
Hysteresis1 0.2 - 5.0 pu 0.1 0.5 Absolute hysteresis of stage 1 in % of
Sbase
Hysteresis2 0.2 - 5.0 pu 0.1 0.5 Absolute hysteresis of stage 2 in % of
Sbase
5% of Ir
30% of Ir
100% of Ir
5% of Ur
30% of Ur
100% of Ur
Table 185: GOPPDOP Non group settings (basic)

IBase 1 - 99999 A 1 3000 Base setting for current level
UBase 0.05 - 2000.00 kV 0.05 400.00 Base setting for voltage level
Mode L1, L2, L3 - - Pos Seq Selection of measured current and
Arone voltage
Pos Seq
L1L2
L2L3
L3L1
L1
L2
L3
348
Current protection

Table 186: GOPPDOP technical data
Power level (0.0–500.0)% of Sbase ± 1.0% of Sr at S < Sr
± 1.0% of S at S > Sr
At low setting:
(0.5-2.0)% of Sbase < ± 50% of set value
(2.0-10)% of Sbase < ± 20% of set value
Characteristic angle (-180.0–180.0) degrees 2 degrees

Timers (0.00-6000.00) s ± 0.5% ± 10 ms
7.12 Negativ sequence time overcurrent protection for

machines NS2PTOC

Negative sequence time overcurrent NS2PTOC 2I2> 46I2
protection for machines
7.12.1 Introduction
Negative-sequence time overcurrent protection for machines NS2PTOC is intended
primarily for the protection of generators against possible overheating of the rotor
caused by negative sequence component in the stator current.
The negative sequence currents in a generator may, among others, be caused by:
• Unbalanced loads
• Line to line faults
• Line to earth faults
• Broken conductors
• Malfunction of one or more poles of a circuit breaker or a disconnector
NS2PTOC can also be used as a backup protection, that is, to protect the generator
in case line protections or circuit breakers fail to clear unbalanced system faults.
To provide an effective protection for the generator for external unbalanced

conditions, NS2PTOC is able to directly measure the negative sequence current.
NS2PTOC also has a time delay characteristic which matches the heating
2
characteristic of the generator I 2 t = K as defined in standard IEEE C50.13.
where:
349
Current protection
I2 is negative sequence current expressed in per unit of the rated

generator current
t is operating time in seconds
K is a constant which depends of the generators size and design
NS2PTOC has a wide range of K settings and the sensitivity and capability of
detecting and tripping for negative sequence currents down to the continuous
capability of a generator.
A separate output is available as an alarm feature to warn the operator of a

potentially dangerous situation.

The negative sequence time overcurrent protection for machines (NS2PTOC)
function directly measures the amplitude of the negative phase sequence
component of the measured current. NS2PTOC sets the START, ST1 or ST2
outputs active and starts to count trip time only when the measured negative
sequence current value rises above the set value of parameters I2-1> or I2-2>
respectively.
To avoid oscillation in the output signals, a certain hysteresis has been included.
For both steps, the reset ratio is 0.97.
Step 1 of NS2PTOC can operate in the Definite Time (DT) or Inverse Time
(IDMT) mode depending on the selected value for the CurveType1 parameter. If
CurveType1= Definite, NS2PTOC operates with a Definite Time Delay
characteristic and if CurveType1 = Inverse, NS2PTOC operates with an Inverse
Time Delay characteristic. Step 2 can only operate in the Definite Time (DT)
mode. The characteristic defines the time period between the moment when
measured negative sequence current exceeds the set start levels in parameter I2-1>
or I2-2> until the trip signal is initiated.
Definite time delay is not dependent on the magnitude of measured negative

sequence current. Once the measured negative sequence current exceeds the set
level, the settable definite timer t1 or t2 respectively, starts to count and the
corresponding trip signal gets activated after the pre-set definite time delay has
elapsed. Reset time in definite time mode is determined by the setting parameters
tResetDef1 or tResetDef2 respectively. If NS2PTOC has already started but not
tripped and measured negative sequence current goes below the start value, the
start outputs remains active for the time defined by the resetting parameters.
A BLOCK input signal resets NS2PTOC momentarily.
When the parameter CurveType1 is set to Inverse, an inverse curve is selected

according to selected value for parameter K1. The minimum trip time setting of
parameter t1Min and reset time parameter ResetMultip1 also influence step
operation. However, to match the heating characteristics of the generator, the reset
350
Current protection
time is depending on the setting of parameter K1, which must be set according to
the generators negative sequence current capacity.
K = I 2 2t
EQUATION2112 V1 EN
Where:
I2 is negative sequence current expressed in per unit of the rated generator current
t is operating time in seconds

K is a constant [s], which depends on generator size and design
Operate
time
t1Max
(Default= 1000 s)
t1Min
(Default= 5 s)
K1
Current I2-1>
IEC09000691 V2 EN
Figure 170: Inverse time characteristic with t1Min and t1Max
For a detailed description of inverse time characteristic, see chapter "Inverse

characteristics".
The reset time is exponential and is given by the following expression:
 
 
 ResetMultip 
ResetTime [ s ] = ⋅ K1
  I 2 
  NS  − 1 
  I Start  
Where
351
Current protection
INS is the measured negative sequence current
IStart is the desired start level in pu of rated generator current
ResetMultip is multiplier of the generator capability constant K equal to setting K1 and thus
defines reset time of inverse time characteristic
7.12.2.1 Start sensitivity
The trip start levels Current I2-1> and I2-2> of NS2PTOC are freely settable over
a range of 3 to 500 % of rated generator current IBase. The wide range of start
setting is required in order to be able to protect generators of different types and sizes.
After start, a certain hysteresis is used before resetting NS2PTOC. For both steps
the reset ratio is 0.97.
7.12.2.2 Alarm function
The alarm function is operated by START signal and used to warn the operator for
an abnormal situation, for example, when generator continuous negative sequence
current capability is exceeded, thereby allowing corrective action to be taken
before removing the generator from service. A settable time delay tAlarm is
provided for the alarm function to avoid false alarms during short-time unbalanced
conditions.
DT time
selected t1
TR1
Negative sequence current OR
a
a>b
b
I2-1> ST1
AND
Inverse
Operation=ON
Inverse time
BLKST1 selected
BLOCK
IEC08000466-1-EN V2 EN
Figure 171: Simplified logic diagram for step 1 of Negative sequence time
overcurrent protection for machines (NS2PTOC)
Step 2 for Negative sequence time overcurrent protection for machines

(NS2PTOC) is similar to step 1 above except that it lacks the inverse characteristic.
352
Current protection
ST1
START
ST2 OR
tAlarm ALARM
TR1
TRIP
TR2 OR
IEC09000690 V2 EN
Figure 172: Simplified logic diagram for the START, ALARM and TRIP signals
for NS2PTOC

NS2PTOC
I3P* TRIP
BLOCK TR1
BLKST1 TR2
BLKST2 START
ST1
ST2
ALARM
NSCURR
IEC08000359-1-EN V2 EN
Figure 173: NS2PTOC function block

Table 187: NS2PTOC Input signals
I3P GROUP - Group connection for neg seq.
SIGNAL
BLKST1 BOOLEAN 0 Block of step 1
BLKTR BOOLEAN 0 Block of trip signals
Table 188: NS2PTOC Output signals

TR1 BOOLEAN Trip signal for step 1
TR2 BOOLEAN Trip signal for step 2
ST1 BOOLEAN Start signal for step 1
353
Current protection

ST2 BOOLEAN Start signal for step 2
ALARM BOOLEAN Alarm signal
NSCURR REAL Negative sequence current in primary amps

Table 189: NS2PTOC Group settings (basic)
On
IBase 1 - 99999 A 1 3000 Rated generator current in primary
Amperes
tAlarm 0.00 - 6000.00 s 0.01 3.00 Time delay for Alarm (operated by
START signal), in sec
OpStep1 Off - - On Enable execution of step 1
On
I2-1> 3 - 500 %IB 1 10 Step 1 Neg. Seq. Current pickup level, in
% of IBase
CurveType1 Definite - - Definite Selection of definite or inverse time-
Inverse characteri. for step 1
t1 0.00 - 6000.00 s 0.01 10.00 Definite time delay for trip of step 1, in sec
tResetDef1 0.000 - 60.000 s 0.001 0.000 Time delay for reset of definite timer of
step 1, in sec
K1 1.0 - 99.0 s 0.1 10.0 Neg. seq. capability value of generator
for step 1, in sec
t1Min 0.000 - 60.000 s 0.001 5.000 Minimum trip time for inverse delay of
step 1, in sec
t1Max 0.00 - 6000.00 s 0.01 1000.00 Maximum trip delay for step 1, in sec
ResetMultip1 0.01 - 20.00 - 0.01 1.00 Reset multiplier for K1, defines reset
time of inverse curve
OpStep2 Off - - On Enable execution of step 2
On
I2-2> 3 - 500 %IB 1 10 Step 2 Neg. Seq. Current pickup level, in
% of IBase
CurveType2 Definite - - Definite Selection of definite or inverse time-
Inverse characteri. for step 2
t2 0.00 - 6000.00 s 0.01 10.00 Definite time delay for trip of step 2, in sec
tResetDef2 0.000 - 60.000 s 0.001 0.000 Time delay for reset of definite timer of
step 2, in sec
K2 1.0 - 99.0 s 0.1 10.0 Neg. seq. capability value of generator
for step 2, in sec
t2Min 0.000 - 60.000 s 0.001 5.000 Minimum trip time for inverse delay of
step 2, in sec
t2Max 0.00 - 6000.00 s 0.01 1000.00 Maximum trip delay for step 2, in sec
ResetMultip2 0.01 - 20.00 - 0.01 1.00 Reset multiplier for K2, defines reset
time of inverse curve
354
Current protection

Table 190: NS2PTOC technical data
Operate value, step (3-500)% of IBase ± 1.0% of Ir at I < Ir
1 and 2, negative ± 1.0% of I at I > Ir
sequence
overcurrent
Reset ratio, step 1 >95% -
and 2
Operate time, start 20 ms typically at 0 to 2 x Iset -
15 ms typically at 0 to 10 x Iset
Reset time, start 30 ms typically at 2 to 0 x Iset -
Time characteristics Definite or Inverse -

Inverse time K=1.0-99.0 Class 5 + 40 ms
characteristic step 1,
I 22t = K
Reset time, inverse K=0.01-20.00 Class 10 + 40 ms

characteristic step 1,
I 22t = K
Maximum trip delay, (0.00-6000.00) s ± 0.5% ± 10 ms

step 1 IDMT
Minimum trip delay, (0.000-60.000) s ± 0.5% ± 10 ms
step 1 IDMT
Timers (0.00-6000.00) s ± 0.5% ± 10 ms
7.13 Accidental energizing protection for synchronous

generator AEGGAPC

Accidental energizing protection for AEGGAPC U 50AE
synchronous generator
7.13.1 Introduction
Inadvertent or accidental energizing of off-line generators has occurred often
enough due to operating errors, breaker head flashovers, control circuit
malfunctions, or a combination of these causes. Inadvertently energized generator
operates as induction motor drawing a large current from the system. The voltage
supervised overcurrent protection is used to protect the inadvertently energized
generator.
355
Current protection
Accidental energizing protection for synchronous generator (AEGGAPC) takes the

maximum phase current input from the generator terminal side or from generator
neutral side and maximum phase to phase voltage inputs from the terminal side.
AEGGAPC is enabled when the terminal voltage drops below the specified voltage
level for the preset time.

Accidental energizing protection for synchronous generator AEGGAPC function is
connected to three phase current input either from the generator terminal side or
from generator neutral point side and three phase voltage from the generator
terminals. The maximum of the three phase-to-phase voltages and maximum of the
three phase currents are measured.
When the maximum phase-to-phase voltage is less than the ArmU< for the period
tArm, it is ensured that the generator is off-line. The ARMED signal will initiate
the overcurrent function. If the calculated maximum current of the three phases is
larger than I> for the period tOC then the TRIP signal becomes activated. Also
START signal becomes activated when overcurrent is detected.
When the maximum phase-to-phase voltage is larger than DisarmU> for the period
tDisarm, it is ensured generator is on line. During this state, undervoltage operation
is disarmed, blocking the overcurrent operation and thus the function becomes
inoperative.
BLOCK input can be used to block AEGGAPC . In addition, the BLKTR input that
blocks the TRIP signal is also present. The input BLKTR can be used if
AEGGAPC is to be used only for monitoring purposes.
Imax_DFT
a
a>b
I> b
tOC
AND TRIP
Operation = ON t
BLOCK
START
ARMED
Uph-ph_max_DFT tArm
a
ab
DisarmU> b
ON - Delay
IEC09000784 V2 EN
Figure 174: AEGGAPC logic diagram
356
Current protection

AEGGAPC
I3P* TRIP
U3P* START
BLOCK ARMED
BLKTR
IEC09000783 V1 EN
Figure 175: AEGGAPC Function block

Table 191: AEGGAPC Input signals
I3P GROUP - Three Phase Current input
SIGNAL
U3P GROUP - Three Phase Voltage input
SIGNAL
Table 192: AEGGAPC Output signals

TRIP BOOLEAN Trip signal from accidental energizing protection
START BOOLEAN Start signal from accidental energizing protection
ARMED BOOLEAN One when accidental energizing protection is
armed

Table 193: AEGGAPC Group settings (basic)
On
IBase 1 - 99999 A 1 3000 Base current (primary phase current in A)
UBase 0.05 - 2000.00 kV 0.05 20.00 Base voltage (primary phase-to-phase
voltage in kV)
I> 2 - 900 %IB 1 120 Operate phase current level in % of IBase
tOC 0.000 - 60.000 s 0.001 0.030 Trip time delay for over current level
ArmU< 2 - 200 %UB 1 50 Under-voltage level to arm protection in
% of UBase
357
Current protection

tArm 0.000 - 60.000 s 0.001 5.000 Time delay to arm protection with U< level
DisarmU> 2 - 200 %UB 1 80 Over-voltage level to disarm protection in
% of UBase
tDisarm 0.000 - 60.000 s 0.001 0.500 Time delay to disarm protection with U>
level

Table 194: AEGGAPC technical data
Operate value, (2-900)% of IBase ± 1,0% of Ir at I<Ir
overcurrent ± 1.0% of I at I>Ir
Reset ratio, >95% -

overcurrent
Transient overreach, <10% at τ = 100 ms -
overcurrent function
Critical impulse time, 10 ms typically at 0 to 2 x Iset -
overcurrent
Impulse margin time, 10 ms typically -
overcurrent
Operate value, (2-200)% of UBase ± 0.5% of Ur at U<Ur
undervoltage ± 0.5% of U at U>Ur
Critical impulse time, 10 ms typically at 2 to 0 x Uset -

undervoltage
Impulse margin time, 15 ms typically -
undervoltage
Operate value, (2-200)% of UBase ± 0.5% of Ur at U<Ur
overvoltage ± 0.5% of U at U>Ur
Timers (0.000-60.000) s ± 0.5% ± 10 ms
358
Voltage protection
Section 8 Voltage protection
About this chapter

This chapter describes voltage related protection functions. The way the functions
work, their setting parameters, function blocks, input and output signals and
technical data are included for each function.
8.1 Two step undervoltage protection UV2PTUV

Two step undervoltage protection UV2PTUV 27
2U<
SYMBOL-R-2U-GREATER THAN
V1 EN
8.1.1 Introduction
Undervoltages can occur in the power system during faults or abnormal conditions.
Two step undervoltage protection (UV2PTUV) function can be used to open circuit
breakers to prepare for system restoration at power outages or as long-time delayed
back-up to primary protection.
UV2PTUV has two voltage steps, each with inverse or definite time delay.

Two-step undervoltage protection (UV2PTUV) is used to detect low power system
voltage. UV2PTUV has two voltage measuring steps with separate time delays. If
one, two or three phase voltages decrease below the set value, a corresponding
START signal is generated. UV2PTUV can be set to START/TRIP based on 1 out
of 3, 2 out of 3 or 3 out of 3 of the measured voltages, being below the set point. If
the voltage remains below the set value for a time period corresponding to the
chosen time delay, the corresponding trip signal is issued. To avoid an unwanted
trip due to disconnection of the related high voltage equipment, a voltage
controlled blocking of the function is available, that is, if the voltage is lower than
the set blocking level the function is blocked and no START or TRIP signal is
generated.The time delay characteristic is individually chosen for each step and can
be either definite time delay or inverse time delay.
359
Voltage protection
UV2PTUV can be set to measure phase-to-earth fundamental value, phase-to-phase

fundamental value, phase-to-earth true RMS value or phase-to-phase true RMS
value. The choice of the measuring is done by the parameter ConnType. The
voltage related settings are made in percent of base voltage which is set in kV phase-
to-phase voltage. This means operation for phase-to-earth voltage under:
U < (%) ⋅UBase(kV )

3
and operation for phase-to-phase voltage under:
U < (%) × UBase(kV)

When phase-to-earth voltage measurement is selected the function

automatically introduces division of the base value by the square
root of three.
8.1.2.1 Measurement principle
Depending on the set ConnType value, UV2PTUV measures phase-to-earth or phase-

to-phase voltages and compare against set values, U1< and U2<. The parameters
OpMode1 and OpMode2 influence the requirements to activate the START
outputs. Either 1 out of 3, 2 out of 3, or 3 out of 3 measured voltages have to be
lower than the corresponding set point to issue the corresponding START signal.
To avoid oscillations of the output START signal, a hysteresis has been included.
8.1.2.2 Time delay
The time delay for the two steps can be either definite time delay (DT) or inverse
time delay (IDMT). For the inverse time delay three different modes are available:
• inverse curve A
• inverse curve B
• customer programmable inverse curve
The type A curve is described as:
k
t=
æ U < -U ö
ç ÷
è U< ø
360
Voltage protection
The type B curve is described as:
k × 480
t= 2.0
+ 0.055
æ U < -U ö
ç 32 × - 0.5 ÷
è U< ø
The customer programmable curve can be created as:
é ù
ê ú
ê k×A ú+D
t=
êæ U < -U ö ú
p
êç B × -C÷ ú
ëè U< ø û
When the denominator in the expression is equal to zero the time delay will be
infinity. There will be an undesired discontinuity. Therefore a tuning parameter
CrvSatn is set to compensate for this phenomenon. In the voltage interval U<
down to U< · (1.0 – CrvSatn/100) the used voltage will be: U< · (1.0 – CrvSatn/
100). If the programmable curve is used this parameter must be calculated so that:
CrvSatn
B× -C > 0
100
The lowest voltage is always used for the inverse time delay integration. The
details of the different inverse time characteristics are shown in section 22.3
"Inverse characteristics".
Trip signal issuing requires that the undervoltage condition continues for at least
the user set time delay. This time delay is set by the parameter t1 and t2 for definite
time mode (DT) and by some special voltage level dependent time curves for the
inverse time mode (IDMT). If the start condition, with respect to the measured
voltage ceases during the delay time, and is not fulfilled again within a user defined
reset time (tReset1 and tReset2 for the definite time and tIReset1 and
tIReset2pickup for the inverse time) the corresponding start output is reset. Here it
should be noted that after leaving the hysteresis area, the start condition must be
fulfilled again and it is not sufficient for the signal to only return back to the
hysteresis area. Note that for the undervoltage function the IDMT reset time is
constant and does not depend on the voltage fluctuations during the drop-off
period. However, there are three ways to reset the timer, either the timer is reset
instantaneously, or the timer value is frozen during the reset time, or the timer
value is linearly decreased during the reset time. See figure 176 and figure 177.
361
Voltage protection
tReset1
Voltage tReset1
Measured
START Voltage
Hysteresis
TRIP
U1<
Time
START t1
TRIP
Time
Integrator Frozen Timer
t1
Time
Instantaneous
Linear Decrease
Reset IEC05000010-3-en.vsd
IEC05000010 V3 EN
Figure 176: Voltage profile not causing a reset of the start signal for step 1, and inverse time delay
362
Voltage protection
tReset1
Voltage
tReset1
START
START
Hysteresis Measured Voltage
TRIP
U1<
Time
START t1
TRIP
Time Integrator
Frozen Timer
t1
Time
Instantaneous
Linear Decrease
Reset IEC05000011-en-2.vsd
IEC05000011 V2 EN
Figure 177: Voltage profile causing a reset of the start signal for step 1, and inverse time delay
Definite timer delay
When definite time delay is selected the function will operate as shown in figure
178. Detailed information about individual stage reset/operation behavior is shown
in figure 179 and figure 180 receptively. Note that by setting tResetn = 0.0s
instantaneous reset of the definite time delayed stage is ensured.
363
Voltage protection
ST1
U tReset1 t1
a
b>a t t
TR1
U1<
b AND
OFF ON
Delay Delay
IEC09000785 V1 EN
Figure 178: Detailed logic diagram for step 1, DT operation
Un<
START
TRIP
tResetn
tn
IEC10000039 V1 EN
Figure 179: Example for Definite Time Delay stage rest
364
Voltage protection
Un<
START
TRIP
tResetn
tn
IEC10000040 V1 EN
Figure 180: Example for Definite Time Delay stage operation
8.1.2.3 Blocking
It is possible to block Two step undervoltage protection UV2PTUV partially or

completely, by binary input signals or by parameter settings, where:
BLOCK: blocks all outputs

BLKTR1: blocks all trip outputs of step 1
BLKST1: blocks all start and trip outputs related to step 1
If the measured voltage level decreases below the setting of IntBlkStVal1, either the
trip output of step 1, or both the trip and the START outputs of step 1, are blocked.
The characteristic of the blocking is set by the IntBlkSel1 parameter. This internal
blocking can also be set to Off resulting in no voltage based blocking.
Corresponding settings and functionality are valid also for step 2.
In case of disconnection of the high voltage component the measured voltage will
get very low. The event will START both the under voltage function and the
blocking function, as seen in figure 181. The delay of the blocking function must
be set less than the time delay of under voltage function.
365
Voltage protection
U Disconnection
Normal voltage
U1<
U2<
tBlkUV1 <
t1,t1Min
IntBlkStVal1
tBlkUV2 <
t2,t2Min
IntBlkStVal2
Time
Block step 1
Block step 2
en05000466.vsd
IEC05000466 V1 EN
Figure 181: Blocking function
8.1.2.4 Design
The voltage measuring elements continuously measure the three phase-to-neutral

voltages or the three phase-to-phase voltages. Recursive fourier filters or true RMS
filters of input voltage signals are used. The voltages are individually compared to
the set value, and the lowest voltage is used for the inverse time characteristic
integration. A special logic is included to achieve the 1 out of 3, 2 out of 3 and 3
out of 3 criteria to fulfill the START condition. The design of Two step
undervoltage protection UV2PTUV is schematically shown in Figure 182.
366
Voltage protection
UL1 Comparator ST1L1

UL1 < U1< Phase 1
Voltage Phase
Selector ST1L2
UL2 Comparator OpMode1 Phase 2
UL2 < U1< 1 out of 3
2 out of 3 ST1L3
Phase 3 Start
UL3 Comparator 3 out of 3
&
UL3 < U1< Trip ST1
OR
Output
START Logic TR1L1
Step 1
Time integrator TR1L2
MinVoltSelect t1 TRIP
or tReset1
ResetTypeCrv1 TR1L3
TR1
OR
Comparator ST2L1
UL1 < U2< Phase 1
Voltage Phase
Selector ST2L2
Comparator OpMode2 Phase 2
UL2 < U2< 1 out of 3
2 outof 3 ST2L3
Phase 3 Start
Comparator 3 out of 3
&
UL3 < U2< Trip ST2
Output OR
START Logic TR2L1
Step 2
MinVoltSelect t2 TRIP
or tReset2
ResetTypeCrv2 TR2L3
TR2
OR
OR START
TRIP
OR
en05000012.vsd
IEC05000834 V1 EN
Figure 182: Schematic design of Two step undervoltage protection UV2PTUV
367
Voltage protection

UV2PTUV
U3P* TRIP
BLOCK TR1
BLKTR1 TR1L1
BLKST1 TR1L2
BLKTR2 TR1L3
BLKST2 TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
IEC06000276 V2 EN
Figure 183: UV2PTUV function block

Table 195: UV2PTUV Input signals
U3P GROUP - Three phase voltages
SIGNAL
BLKTR1 BOOLEAN 0 Block of operate signal, step 1
Table 196: UV2PTUV Output signals

TRIP BOOLEAN Trip
368
Voltage protection


Table 197: UV2PTUV Group settings (basic)
On
OperationStep1 Off - - On Enable execution of step 1
On
Characterist1 Definite time - - Definite time Selection of time delay curve type for
Inverse curve A step 1
Inverse curve B
Prog. inv. curve
OpMode1 1 out of 3 - - 1 out of 3 Number of phases required for op (1 of
2 out of 3 3, 2 of 3, 3 of 3) from step 1
3 out of 3
U1< 1 - 100 %UB 1 70 Voltage setting/start val (DT & IDMT) in
% of UBase, step 1
for step 1
for step 1
IntBlkSel1 Off - - Off Internal (low level) blocking mode, step 1
Block of trip
Block all
IntBlkStVal1 1 - 100 %UB 1 20 Voltage setting for internal blocking in %
of UBase, step 1
tBlkUV1 0.000 - 60.000 s 0.001 0.000 Time delay of internal (low level)
blocking for step 1
HystAbs1 0.0 - 100.0 %UB 0.1 0.5 Absolute hysteresis in % of UBase, step 1
On
Inverse curve B
Prog. inv. curve
369
Voltage protection

3 out of 3
U2< 1 - 100 %UB 1 50 Voltage setting/start val (DT & IDMT) in
% of UBase, step 2
for step 2
for step 2
IntBlkSel2 Off - - Off Internal (low level) blocking mode, step 2
Block of trip
Block all
IntBlkStVal2 1 - 100 %UB 1 20 Voltage setting for internal blocking in %
of UBase, step 2
tBlkUV2 0.000 - 60.000 s 0.001 0.000 Time delay of internal (low level)
blocking for step 2
Table 198: UV2PTUV Group settings (advanced)

Time curve step 1
ResetTypeCrv1 Instantaneous - - Instantaneous Selection of used IDMT reset curve type
Frozen timer for step 1
Linearly decreased
tIReset1 0.000 - 60.000 s 0.001 0.025 Time delay in IDMT reset (s), step 1
ACrv1 0.005 - 200.000 - 0.001 1.000 Parameter A for customer programmable
curve for step 1
BCrv1 0.50 - 100.00 - 0.01 1.00 Parameter B for customer programmable
curve for step 1
CCrv1 0.0 - 1.0 - 0.1 0.0 Parameter C for customer
DCrv1 0.000 - 60.000 - 0.001 0.000 Parameter D for customer
PCrv1 0.000 - 3.000 - 0.001 1.000 Parameter P for customer programmable
curve for step 1
CrvSat1 0 - 100 % 1 0 Tuning param for prog. under voltage
IDMT curve, step 1
Time curve step 2
Linearly decreased
curve for step 2
370
Voltage protection

curve for step 2
curve for step 2
CrvSat2 0 - 100 % 1 0 Tuning param for prog. under voltage
IDMT curve, step 2
Table 199: UV2PTUV Non group settings (basic)

ConnType PhN DFT - - PhN DFT Group selector for connection type
PhPh RMS
PhN RMS
PhPh DFT

Table 200: UV2PTUV technical data
Operate voltage, low (1–100)% of UBase ± 0.5% of Ur
and high step
Absolute hysteresis (0–100)% of UBase ± 0.5% of Ur
Internal blocking (1–100)% of UBase ± 0.5% of Ur

level, low and high
step
Inverse time - See table 586
characteristics for
low and high step,
see table 586
Definite time delays (0.000-60.000) s ± 0.5% ±10 ms
Minimum operate (0.000–60.000) s ± 0.5% ± 10 ms
time, inverse
characteristics
Operate time, start 25 ms typically at 2 to 0 x Uset -
function
Reset time, start 25 ms typically at 0 to 2 x Uset -
function
Critical impulse time 10 ms typically at 1.2 to 0.8 x Uset -
371
Voltage protection
8.2 Two step overvoltage protection OV2PTOV

Two step overvoltage protection OV2PTOV 59
2U>
SYMBOL-C-2U SMALLER THAN

V1 EN
8.2.1 Introduction
Overvoltages may occur in the power system during abnormal conditions such as
sudden power loss, tap changer regulating failures, open line ends on long lines etc.
Two step overvoltage protection (OV2PTOV) function can be used to detect open
line ends, normally then combined with a directional reactive over-power function
to supervise the system voltage. When triggered, the function will cause an alarm,
switch in reactors, or switch out capacitor banks.
OV2PTOV has two voltage steps, each of them with inverse or definite time delayed.
OV2PTOV has an extremely high reset ratio to allow settings close to system
service voltage.

Two step overvoltage protection OV2PTOV is used to detect high power system
voltage. OV2PTOV has two steps with separate time delays. If one-, two- or three-
phase voltages increase above the set value, a corresponding START signal is
issued. OV2PTOV can be set to START/TRIP, based on 1 out of 3, 2 out of 3 or 3
out of 3 of the measured voltages, being above the set point. If the voltage remains
above the set value for a time period corresponding to the chosen time delay, the
corresponding trip signal is issued.
The time delay characteristic is individually chosen for the two steps and can be
either, definite time delay or inverse time delay.
The voltage related settings are made in percent of the global set base voltage
UBase, which is set in kV, phase-to-phase.
OV2PTOV can be set to measure phase-to-earth fundamental value, phase-to-phase

fundamental value, phase-to-earth RMS value or phase-to-phase RMS value. The
choice of measuring is done by the parameter ConnType.
The setting of the analog inputs are given as primary phase-to-earth or phase-to-
phase voltage. OV2PTOV will operate if the voltage gets higher than the set
372
Voltage protection
percentage of the set base voltage UBase. This means operation for phase-to-earth
voltage over:
U > (%) × UBase( kV )

3
and operation for phase-to-phase voltage over:
U > (%) × UBase(kV)

When phase-to-earth voltage measurement is selected the function

automatically introduces division of the base value by the square
root of three.
All the three voltages are measured continuously, and compared with the set
values, U1> and U2>. The parameters OpMode1 and OpMode2 influence the
requirements to activate the START outputs. Either 1 out of 3, 2 out of 3 or 3 out of
3 measured voltages have to be higher than the corresponding set point to issue the
corresponding START signal.
8.2.2.2 Time delay
time delay (IDMT). For the inverse time delay four different modes are available:
• inverse curve A
• inverse curve B
• inverse curve C
k
t=
æ U -U > ö
ç ÷
è U> ø
IEC09000051 V1 EN (Equation 104)
373
Voltage protection
k × 480
t= 2.0
- 0.035
æ 32 × U - U > - 0.5 ö
ç ÷
è U > ø
The type C curve is described as:
k × 480
t= 3.0
+ 0.035
æ 32 × U - U > - 0.5 ö
ç ÷
è U > ø
k×A
t= p
+D
æ U -U > ö
çB× -C÷
è U> ø
infinity. There will be an undesired discontinuity. Therefore, a tuning parameter
CrvSatn is set to compensate for this phenomenon. In the voltage interval U< down
to U< · (1.0 – CrvSatn/100) the used voltage will be: U< · (1.0 – CrvSatn/100). If
the programmable curve is used this parameter must be calculated so that:
CrvSatn
B× -C > 0
100
The highest phase (or phase-to-phase) voltage is always used for the inverse time
delay integration, see figure 184. The details of the different inverse time
characteristics are shown in section "Inverse characteristics"
374
Voltage protection
Voltage
IDMT Voltage
UL1
UL2
UL3
Time
en05000016.vsd
IEC05000016 V1 EN
Figure 184: Voltage used for the inverse time characteristic integration
Trip signal issuing requires that the overvoltage condition continues for at least the
user set time delay. This time delay is set by the parameter t1 and t2 for definite
time mode (DT) and by selected voltage level dependent time curves for the
inverse time mode (IDMT). If the START condition, with respect to the measured
voltage ceases during the delay time, and is not fulfilled again within a user defined
reset time (tReset1 and tReset2 for the definite time and tIReset1 and tIReset2 for
the inverse time) the corresponding START output is reset, after that the defined
reset time has elapsed. Here it should be noted that after leaving the hysteresis area,
the START condition must be fulfilled again and it is not sufficient for the signal to
only return back to the hysteresis area. The hysteresis value for each step is settable
(HystAbs2) to allow an high and accurate reset of the function. It should be noted
that for Two step overvoltage protection OV2PTOV the IDMT reset time is
value is linearly decreased during the reset time..
375
Voltage protection
tReset
1
tReset1
Voltage
START
TRIP
U1>
Hysteresis
Measured
Voltage
Time
START t1
TRIP
Time
Integrator Linear Decrease
Frozen Timer
t1
Instantaneous Time
IEC09000055 V1 EN
Figure 185: Voltage profile not causing a reset of the START signal for step 1, and inverse time delay
376
Voltage protection
tReset1
Voltage tReset1
START TRIP
START
Hysteresis
U1>
Measured Voltage
Time
START t1
TRIP
Time Integrator
Frozen Timer
t1
Time
Instantaneous IEC05000020-en-2.vsd
Linear Decrease
Reset
IEC05000020 V2 EN
Figure 186: Voltage profile causing a reset of the START signal for step 1, and inverse time delay
Definite time delay
instantaneous reset of the definite time delayed stage is ensured
377
Voltage protection
ST1
U tReset1 t1
a
b<a t t
TR1
U1>
b AND
OFF ON
Delay Delay
IEC10000100 V1 EN
Un>
START
TRIP
tResetn
tn
IEC10000037 V1 EN
378
Voltage protection
Un>
START
TRIP
tResetn
tn
IEC10000038 V1 EN
8.2.2.3 Blocking
It is possible to block Two step overvoltage protection OV2PTOV partially or

completely, by binary input signals where:

8.2.2.4 Design
The voltage measuring elements continuously measure the three phase-to-earth

voltages or the three phase-to-phase voltages. Recursive Fourier filters filter the
input voltage signals. The phase voltages are individually compared to the set
value, and the highest voltage is used for the inverse time characteristic integration.
A special logic is included to achieve the 1 out of 3, 2 out of 3 or 3 out of 3 criteria
to fulfill the START condition. The design of Two step overvoltage protection
(OV2PTOV) is schematically described in figure 190.
379
Voltage protection
UL1 Comparator ST1L1

UL1 > U1> Phase 1
Voltage Phase
Selector ST1L2
UL2 Comparator OpMode1 Phase 2
UL2 > U1> 1 out of 3
2 outof 3 ST1L3
3 out of 3 Phase 3 Start
UL3 Comparator &
UL3 > U1> Trip ST1
OR
Output
START Logic TR1L1
Step 1
MaxVoltSelect t1 TRIP
or tReset1
ResetTypeCrv1 TR1L3
OR TR1
Comparator ST2L1
UL1 > U2> Phase 1
Voltage Phase
Selector ST2L2
Comparator OpMode2 Phase 2
UL2 > U2> 1 out of 3
2 outof 3 ST2L3
3 out of 3 Phase 3 Start
Comparator &
UL3 > U2> Trip ST2
OR
Output
START Logic TR2L1
Step 2
MaxVoltSelect t2 TRIP
or tReset2
ResetTypeCrv2 TR2L3
TR2
OR
START
OR
TRIP
OR
en05000013.vsd
IEC05000013-WMF V1 EN
Figure 190: Schematic design of Two step overvoltage protection OV2PTOV
380
Voltage protection

OV2PTOV
U3P* TRIP
BLOCK TR1
BLKTR1 TR1L1
BLKST1 TR1L2
BLKTR2 TR1L3
BLKST2 TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
IEC06000277 V2 EN
Figure 191: OV2PTOV function block

Table 201: OV2PTOV Input signals
U3P GROUP - Group signal for three phase voltage input
SIGNAL
Table 202: OV2PTOV Output signals

TRIP BOOLEAN Trip
381
Voltage protection


Table 203: OV2PTOV Group settings (basic)
On
On
Inverse curve B
Inverse curve C
Prog. inv. curve
3 out of 3
U1> 1 - 200 %UB 1 120 Voltage setting/start val (DT & IDMT) in
% of UBase, step 1
for step 1
for step 1
On
Inverse curve B
Inverse curve C
Prog. inv. curve
3 out of 3
U2> 1 - 200 %UB 1 150 Voltage setting/start val (DT & IDMT) in
% of UBase, step 2
382
Voltage protection

for step 2
for step 2
Table 204: OV2PTOV Group settings (advanced)

Time curve step 1
Linearly decreased
curve for step 1
curve for step 1
curve for step 1
CrvSat1 0 - 100 % 1 0 Tuning param for prog. over voltage
IDMT curve, step 1
Time curve step 2
Linearly decreased
curve for step 2
curve for step 2
curve for step 2
IDMT curve, step 2
383
Voltage protection
Table 205: OV2PTOV Non group settings (basic)

ConnType PhN DFT - - PhN DFT Group selector for connection type
PhPh DFT
PhN RMS
PhPh RMS

Table 206: OV2PTOV technical data
Operate voltage, low (1-200)% of UBase ± 0.5% of Ur at U < Ur
and high step ± 0.5% of U at U > Ur
Absolute hysteresis (0–100)% of UBase ± 0.5% of Ur at U < Ur

± 0.5% of U at U > Ur

characteristics for
low and high step,
see table 585
Definite time delays (0.000-60.000) s ± 0.5% ± 10 ms
Minimum operate (0.000-60.000) s ± 0.5% ± 10 ms
time, Inverse
characteristics
function
function
Critical impulse time 10 ms typically at 0 to 2 x Uset -
8.3 Two step residual overvoltage protection

ROV2PTOV

Two step residual overvoltage ROV2PTOV 59N
protection
3U0
TRV V1 EN
8.3.1 Introduction
Residual voltages may occur in the power system during earth faults.
384
Voltage protection
Two step residual overvoltage protection ROV2PTOV function calculates the

residual voltage from the three-phase voltage input transformers or measures it
from a single voltage input transformer fed from an open delta or neutral point
voltage transformer.
ROV2PTOV has two voltage steps, each with inverse or definite time delay.
Reset delay ensures operation for intermittent earth faults.

Two step residual overvoltage protection ROV2PTOV is used to detect high single-
phase voltage, such as high residual voltage, also called 3U0. The residual voltage
can be measured directly from a voltage transformer in the neutral of a power
transformer or from a three-phase voltage transformer, where the secondary
windings are connected in an open delta. Another possibility is to measure the three-
phase voltages and internally in the IED calculate the corresponding residual
voltage and connect this calculated residual voltage to ROV2PTOV. ROV2PTOV
has two steps with separate time delays. If the single-phase (residual) voltage
remains above the set value for a time period corresponding to the chosen time
delay, the corresponding TRIP signal is issued.
The time delay characteristic is individually chosen for the two steps and can be
either, definite time delay or inverse time delay.
The voltage related settings are made in percent of the base voltage, which is set in
kV, phase-phase.
The residual voltage is measured continuously, and compared with the set values,
U1> and U2>.
8.3.2.2 Time delay
time delay (IDMT). For the inverse time delay four different modes are available:
• inverse curve A
• inverse curve B
• inverse curve C
385
Voltage protection
k
t=
æ U -U > ö
ç ÷
è U> ø
IEC09000051 V1 EN (Equation 109)
k × 480
t= 2.0
- 0.035
æ 32 × ö
U -U >
ç - 0.5 ÷
è U > ø
The type C curve is described as:
k × 480
t= 3.0
+ 0.035
æ 32 × U - U > - 0.5 ö
ç ÷
è U > ø
k×A
t= p
+D
æ U -U > ö
çB× -C÷
è U> ø
infinity. There will be an undesired discontinuity. Therefore a tuning parameter
CrvSatn is set to compensate for this phenomenon. In the voltage interval U> up to
U> · (1.0 + CrvSatn/100) the used voltage will be: U> · (1.0 + CrvSatn/100). If the
programmable curve is used this parameter must be calculated so that:
CrvSatn
B× -C > 0
100
The details of the different inverse time characteristics are shown in section
"Inverse characteristics".
TRIP signal issuing requires that the residual overvoltage condition continues for at
least the user set time delay. This time delay is set by the parameter t1 and t2 for
definite time mode (DT) and by some special voltage level dependent time curves
for the inverse time mode (IDMT).
386
Voltage protection
If the START condition, with respect to the measured voltage ceases during the
delay time, and is not fulfilled again within a user defined reset time (tReset1 and
tReset2 for the definite time and tIReset1 and tIReset2 for the inverse time) the
corresponding START output is reset, after that the defined reset time has elapsed.
Here it should be noted that after leaving the hysteresis area, the START condition
must be fulfilled again and it is not sufficient for the signal to only return back to
the hysteresis area. Also notice that for the overvoltage function IDMT reset time is
value is linearly decreased during the reset time. See figure 185 and figure 186.
tReset
1
tReset1
Voltage
START
TRIP
U1>
Hysteresis
Measured
Voltage
Time
START t1
TRIP
Time
Integrator Linear Decrease
Frozen Timer
t1
Instantaneous Time
IEC09000055 V1 EN
Figure 192: Voltage profile not causing a reset of the START signal for step 1, and inverse time delay
387
Voltage protection
tReset1
Voltage tReset1
START TRIP
START
Hysteresis
U1>
Measured Voltage
Time
START t1
TRIP
Time Integrator
Frozen Timer
t1
Time
Instantaneous IEC05000020-en-2.vsd
Linear Decrease
Reset
IEC05000020 V2 EN
Figure 193: Voltage profile causing a reset of the START signal for step 1, and inverse time delay
Definite timer delay
instantaneous reset of the definite time delayed stage is ensured
388
Voltage protection
ST1
U tReset1 t1
a
b<a t t
TR1
U1>
b AND
OFF ON
Delay Delay
IEC10000100 V1 EN
Un<
START
TRIP
tResetn
tn
IEC10000039 V1 EN
389
Voltage protection
Un<
START
TRIP
tResetn
tn
IEC10000040 V1 EN
8.3.2.3 Blocking
It is possible to block Two step residual overvoltage protection ROV2PTOV

partially or completely, by binary input signals where:

BLKST2: blocks all START and trip inputs related to step 2
8.3.2.4 Design
The voltage measuring elements continuously measure the residual voltage.

Recursive Fourier filters filter the input voltage signal. The single input voltage is
compared to the set value, and is also used for the inverse time characteristic
integration. The design of Two step residual overvoltage protection (ROV2PTOV)
is schematically described in figure 197.
390
Voltage protection
UN Comparator Phase 1 ST1

UN > U1>
TR1
START Start
&
Trip
Time integrator Output
t1 Logic
TRIP
tReset1
ResetTypeCrv1 Step 1
ST2
Comparator Phase 1
UN > U2> TR2
Start
START &
Trip START
Output OR
Time integrator
Logic
t2 TRIP
tReset2
Step 2
ResetTypeCrv2 TRIP
OR
en05000748.vsd
IEC05000748 V1 EN
Figure 197: Schematic design of Two step residual overvoltage protection

ROV2PTOV

ROV2PTOV
U3P* TRIP
BLOCK TR1
BLKTR1 TR2
BLKST1 START
BLKTR2 ST1
BLKST2 ST2
IEC06000278 V2 EN
Figure 198: ROV2PTOV function block
391
Voltage protection

Table 207: ROV2PTOV Input signals
U3P GROUP - Three phase voltages
SIGNAL
Table 208: ROV2PTOV Output signals

TRIP BOOLEAN Trip

Table 209: ROV2PTOV Group settings (basic)
On
On
Inverse curve B
Inverse curve C
Prog. inv. curve
U1> 1 - 200 %UB 1 30 Voltage setting/start val (DT & IDMT),
step 1 in % of UBase
for step 1
for step 1
392
Voltage protection

On
Inverse curve B
Inverse curve C
Prog. inv. curve
U2> 1 - 100 %UB 1 45 Voltage setting/start val (DT & IDMT),
step 2 in % of UBase
for step 2
for step 2
Table 210: ROV2PTOV Group settings (advanced)

Time curve step 1
Linearly decreased
curve for step 1
curve for step 1
curve for step 1
IDMT curve, step 1
tReset2 0.000 - 60.000 s 0.001 0.025 Time delay in DT reset (s), step 2
Linearly decreased
curve for step 2
curve for step 2
393
Voltage protection

curve for step 2
IDMT curve, step 2

Table 211: ROV2PTOV technical data
Operate voltage, low (1-200)% of UBase ± 0.5% of Ur at U < Ur
and high step ± 1.0% of U at U > Ur
Absolute hysteresis (0–100)% of UBase ± 0.5% of Ur at U < Ur

± 1.0% of U at U > Ur

characteristics for
low and high step,
see table 587
Definite time setting (0.000–60.000) s ± 0.5% ± 10 ms
Minimum operate (0.000-60.000) s ± 0.5% ± 10 ms
time
function
function
8.4 Overexcitation protection OEXPVPH

Overexcitation protection OEXPVPH 24
U/f >
SYMBOL-Q V1 EN
8.4.1 Introduction
When the laminated core of a power transformer or generator is subjected to a
magnetic flux density beyond its design limits, stray flux will flow into non-
laminated components not designed to carry flux and cause eddy currents to flow.
394
Voltage protection
The eddy currents can cause excessive heating and severe damage to insulation and
adjacent parts in a relatively short time. The function has settable inverse operating
curves and independent alarm stages.

The importance of Overexcitation protection (OEXPVPH) function is growing as
the power transformers as well as other power system elements today operate most
of the time near their designated limits.
Modern design transformers are more sensitive to overexcitation than earlier types.
This is a result of the more efficient designs and designs which rely on the
improvement in the uniformity of the excitation level of modern systems. Thus, if
emergency that includes overexcitation does occur, transformers may be damaged
unless corrective action is promptly taken. Transformer manufacturers recommend
an overexcitation protection as a part of the transformer protection system.
Overexcitation results from excessive applied voltage, possibly in combination

with below-normal frequency. Such condition may occur when a transformer unit
is on load, but are more likely to arise when it is on open circuit, or at a loss of load
occurrence. Transformers directly connected to generators are in particular danger
to experience overexcitation condition. It follows from the fundamental
transformer equation, see equation 114, that peak flux density Bmax is directly
proportional to induced voltage E, and inversely proportional to frequency f, and
turns n.
E = 4.44 × f × n × Bmax× A
The relative excitation M is therefore according to equation 115.
E f
M ( p.u.) =
( Ur ) ( fr )
Disproportional variations in quantities E and f may give rise to core overfluxing.

If the core flux density Bmax increases to a point above saturation level (typically
1.9 Tesla), the flux will no longer be contained within the core, but will extend into
other (non-laminated) parts of the power transformer and give rise to eddy current
circulations.
Overexcitation will result in:
• overheating of the non-laminated metal parts

• a large increase in magnetizing currents
• an increase in core and winding temperature
• an increase in transformer vibration and noise
395
Voltage protection
Protection against overexcitation is based on calculation of the relative volt per

hertz (V/Hz) ratio. Protection initiates a reduction of excitation, and if this fails, or
is not possible, the TRIP signal will disconnect the transformer from the source
after a delay ranging from seconds to minutes, typically 5-10 seconds.
Overexcitation protection may be of particular concern on directly connected

generator unit transformers. Directly connected generator-transformers are
subjected to a wide range of frequencies during the acceleration and deceleration of
the turbine. In such cases, OEXPVPH (24) may trip the field breaker during a start-
up of a machine, by means of the overexcitation ALARM signal. If this is not
possible, the power transformer can be disconnected from the source, after a delay,
by the TRIP signal.
The IEC 60076 - 1 standard requires that transformers operate continuously at 10%
above rated voltage at no load, and rated frequency. At no load, the ratio of the
actual generator terminal voltage to the actual frequency should not exceed 1.1
times the ratio of transformer rated voltage to the rated frequency on a sustained
basis, see equation 116.
---- £ 1.1 × Ur
E ------
f fr
or equivalently, with 1.1 · Ur = V/Hz> according to equation 117.
E V Hz >
£
f fr
where:
V/Hz> is the maximum continuously allowed voltage at no load, and rated frequency.
V/Hz> is a setting parameter. The setting range is 100% to 180%. If the user does
not know exactly what to set, then the default value for V/Hz> = 110 % for the
standard IEC 60076-1 shall be used.
In OEXPVPH, the relative excitation M is expressed according to equation 118.
E f
M ( p.u. ) =
Ur fr
It is clear from the above formula that, for an unloaded power transformer, M = 1
for any E and f, where the ratio E/f is equal to Ur/fr. A power transformer is not
overexcited as long as the relative excitation is M ≤ V/Hz>, V/Hz> expressed in %
of Ur/fr.
396
Voltage protection
The overexcitation protection algorithm is fed with an input voltage U which is in

general not the induced voltage E from the fundamental transformer equation. For
no load condition, these two voltages are the same, but for a loaded power
transformer the internally induced voltage E may be lower or higher than the
voltage U which is measured and fed to OEXPVPH , depending on the direction of
the power flow through the power transformer, the power transformer side where
OEXPVPH is applied, and the power transformer leakage reactance of the winding.
It is important to specify in the application configuration on which side of the
power transformer OEXPVPH is placed.
As an example, at a transformer with a 15% short circuit impedance Xsc, the full
load, 0.8 power factor, 105% voltage on the load side, the actual flux level in the
transformer core, will not be significantly different from that at the 110% voltage,
no load, rated frequency, provided that the short circuit impedance X can be
equally divided between the primary and the secondary winding: Xleak = Xleak1 =
Xleak2 = Xsc / 2 = 0.075 pu.
OEXPVPH calculates the internal induced voltage E if Xleak (meaning the leakage
reactance of the winding where OEXPVPH is connected) is known to the user. The
assumption taken for two-winding power transformers that Xleak = Xsc / 2 is
unfortunately most often not true. For a two-winding power transformer the
leakage reactances of the two windings depend on how the windings are located on
the core with respect to each other. In the case of three-winding power transformers
the situation is still more complex. If a user has the knowledge on the leakage
reactance, then it should applied. If a user has no idea about it, Xleak can be set to
Xc/2. OEXPVPH protection will then take the given measured voltage U, as the
induced voltage E.
It is assumed that overexcitation is a symmetrical phenomenon, caused by events

such as loss-of-load, etc. It will be observed that a high phase-to-earth voltage does
not mean overexcitation. For example, in an unearthed power system, a single phase-
to-earth fault means high voltages of the “healthy” two phases-to-earth, but no
overexcitation on any winding. The phase-to-phase voltages will remain essentially
unchanged. The important voltage is the voltage between the two ends of each
winding.
8.4.2.1 Measured voltage
If one phase-to-phase voltage is available from the side where overexcitation

protection is applied, then Overexcitation protection OEXPVPH shall be set to
measure this voltage, MeasuredU. The particular voltage which is used determines
the two currents that must be used. This must be chosen with the setting MeasuredI.
It is extremely important that MeasuredU and MeasuredI are set to

same value.
If, for example, voltage UL1L2 is fed to OEXPVPH, then currents IL1, and IL2
must be applied. From these two input currents, current IL1L2 = IL1 - IL2 is
397
Voltage protection
calculated internally by the OEXPVPH algorithm. The phase-to-phase voltage

must be higher than 70% of the rated value, otherwise the protection algorithm
exits without calculating the excitation. ERROR output is set to 1, and the
displayed value of relative excitation V/Hz shows 0.000.
If three phase-to-earth voltages are available from the side where overexcitation is
connected, then OEXPVPH shall be set to measure positive sequence voltage and
current. In this case the positive sequence voltage and the positive sequence current
are used by OEXPVPH. A check is made if the positive sequence voltage is higher
than 70% of rated phase-to-earth voltage, when below this value, OEXPVPH exits
immediately, and no excitation is calculated. ERROR output is set to 1, and the
displayed value of relative excitation V/Hz shows 0.000.
The frequency value is received from the pre-processing block. The function is in
operation for frequencies within the range of 33-60 Hz and of 42-75 Hz for 50 Hz
and 60 Hz respectively.
• OEXPVPH can be connected to any power transformer side, independent from

the power flow.
• The side with a possible load tap changer must not be used.
8.4.2.2 Operate time of the overexcitation protection
The operate time of OEXPVPH is a function of the relative overexcitation.
Basically there are two different delay laws available to choose between:
• the so called IEEE law, and

• a tailor-made law.
The so called IEEE law approximates a square law and has been chosen based on
analysis of the various transformers’ overexcitation capability characteristics. They
can match the transformer core capability well.
The square law is according to equation 119.
0.18 × k 0.18 × k
top = 2
= 2
æ M ö overexcitation
ç V Hz> - 1 ÷
è ø
where:
M the relative excitation
V/Hz> is maximum continuously allowed voltage at no load, and rated frequency, in pu and
k is time multiplier for inverse time functions, see figure 200.
Parameter k (“time multiplier setting”) selects one delay curve from the family of curves.
398
Voltage protection
The relative excitation M is calculated using equation198
æ Umeasured ö
ç ÷ Umeasured frated
=è
fmeasured ø
M = ×
æ UBase ö UBase fmeasured
ç ÷
è frated ø
IECEQUATION2404 V1 EN
An analog overexcitation relay would have to evaluate the following integral

expression, which means to look for the instant of time t = top according to
equation 120.
top
ò (M (t) - V Hz > ) dt ³ 0.18 × k

2
A digital, numerical relay will instead look for the lowest j (that is, j = n) where it
becomes true that:
n
2
Dt × å ( M(j) – V/Hz> ) ³ 0.18 × k
j=k
where:
Dt is the time interval between two successive executions of OEXPVPH and
M(j) - V/Hz> is the relative excitation at (time j) in excess of the normal (rated) excitation which is
given as Ur/fr.
As long as M > V/Hz> (that is, overexcitation condition), the above sum can only
be larger with time, and if the overexcitation persists, the protected transformer will
be tripped at j = n.
Inverse delays as per figure 200, can be modified (limited) by two special definite
delay settings, namely tMax and tMin, see figure 199.
399
Voltage protection
delay in s
tMax
under - inverse delay law

excitation
overexcitation
tMin
0 Mmax - V/Hz> Overexcitation M-V/Hz>
M=V/Hz> Mmax Excitation M
V/Hz> Emax E (only if f = fr = const)
99001067.vsd
IEC99001067 V1 EN
Figure 199: Restrictions imposed on inverse delays by tMax and tMin
A definite maximum time, tMax, can be used to limit the operate time at low
degrees of overexcitation. Inverse delays longer than tMax will not be allowed. In
case the inverse delay is longer than tMax, OEXPVPH trips after tMax seconds.
A definite minimum time, tMin, can be used to limit the operate time at high
degrees of overexcitation. In case the inverse delay is shorter than tMin,
OEXPVPH function trips after tMin seconds. The inverse delay law is not valid for
values exceeding Mmax. The delay will be tMin, irrespective of the overexcitation
level, when values exceed Mmax (that is, M>V/Hz>).
400
Voltage protection
Time (s) IEEE OVEREXCITATION CURVES
1000
100
k = 60
k = 20
k = 10
10 k=9
k=8
k=7
k=6
k=5
k=4
k=3
k=2
k=1
1
1 2 3 4 5 10 20 30 40
OVEREXCITATION IN % (M-Emaxcont)*100)
en01000373.vsd
IEC01000373 V1 EN
Figure 200: Delays inversely proportional to the square of the overexcitation
The critical value of excitation M is determined indirectly via OEXPVPH setting V/

Hz>>. V/Hz>> can be thought of as a no-load-rated-frequency voltage, where the
inverse law should be replaced by a short definite delay, tMin. If, for example, V/
Hz>> = 140 %, then M is according to equation 122.
(V Hz>> ) / f
M= = 1.40
Ur/fr
The Tailor-Made law allows a user to design an arbitrary delay characteristic. In

this case the interval between M = V/Hz>, and M = Mmax is automatically divided
into five equal subintervals, with six delays. (settings t1, t2, t3, t4, t5 and t6) as
shown in figure 201. These times should be set so that t1 => t2 => t3 => t4 => t5
=> t6.
401
Voltage protection
delay in s
tMax
under- tMin
excitation Overexcitation M-Emaxcont
0 Mmax - Emaxcont Excitation M
Emaxcont Mmax
99001068.vsd
IEC99001068 V1 EN
Figure 201: An example of a Tailor-Made delay characteristic
Delays between two consecutive points, for example t3 and t4, are obtained by
linear interpolation.
Should it happen that tMax be lower than, for example, delays t1, and t2, the actual
delay would be tMax. Above Mmax, the delay can only be tMin.
8.4.2.3 Cooling
Overexcitation protection OEXPVPH is basically a thermal protection; therefore a

cooling process has been introduced. Exponential cooling process is applied.
Parameter Setting tool is an OEXPVPH setting, with a default time constant
tCooling of 20 minutes. This means that if the voltage and frequency return to their
previous normal values (no more overexcitation), the normal temperature is
assumed to be reached not before approximately 5 times tCooling minutes. If an
overexcitation condition would return before that, the time to trip will be shorter
than it would be otherwise.
8.4.2.4 Overexcitation protection function measurands
A monitored data value, TMTOTRIP, is available on the local HMI and in

PCM600. This value is an estimation of the remaining time to trip (in seconds), if
the overexcitation remained on the level it had when the estimation was done. This
information can be useful with small or moderate overexcitations.
If the overexcitation is so low that the valid delay is tMax, then the estimation of
the remaining time to trip is done against tMax.
The relative excitation M, shown on the local HMI and in PCM600 has a
monitored data value VPERHZ, is calculated from the expression:
E f
M ( p.u. ) =
Ur fr
402
Voltage protection
If VPERHZ value is less than setting V/Hz> (in %), the power transformer is
underexcited. If VPERHZ is equal to V/Hz> (in %), the excitation is exactly equal
to the power transformer continuous capability. If VPERHZ is higher than V/Hz>,
the protected power transformer is overexcited. For example, if VPERHZ = 1.100,
while V/Hz> = 110 %, then the power transformer is exactly on its maximum
continuous excitation limit.
Monitored data value THERMSTA shows the thermal status of the protected
power transformer iron core. THERMSTA gives the thermal status in % of the trip
value which corresponds to 100%. THERMSTA should reach 100% at the same
time, as TMTOTRIP reaches 0 seconds. If the protected power transformer is then
for some reason not switched off, THERMSTA shall go over 100%.
If the delay as per IEEE law, or Tailor-made Law, is limited by tMax, and/or tMin,
then the Thermal status will generally not reach 100% at the same time, when
tTRIP reaches 0 seconds. For example, if, at low degrees of overexcitation, the
very long delay is limited by tMax, then the OEXPVPH TRIP output signal will be
set to 1 before the Thermal status reaches 100%.
8.4.2.5 Overexcitation alarm
A separate step, AlarmLevel, is provided for alarming purpose. It is normally set

2% lower than (V/Hz>) and has a definite time delay, tAlarm. This will give the
operator an early abnormal voltages warning.
BLOCK
AlarmLevel
ALARM
t>tAlarm &
t
tAlarm
M>V/Hz>
t>tMin TRIP
t &
V/Hz> tMin
U3P Calculation
Ei k
M
of internal M=
I3P induced (Ei / f) M IEEE law
voltage Ei (Ur / fr)
³1
M t
Tailor-made law
M>V/Hz>> tMax
Xleak
V/Hz>>
M = relative V/Hz as service value

IEC05000162 V2 EN
Figure 202: A simplified logic diagram of the Overexcitation protection

OEXPVPH
403
Voltage protection
Simplification of the diagram is in the way the IEEE and Tailor-made delays are
calculated. The cooling process is not shown. It is not shown that voltage and
frequency are separately checked against their respective limit values.

OEXPVPH
I3P* TRIP
U3P* START
BLOCK ALARM
RESET
IEC05000329 V3 EN
Figure 203: OEXPVPH function block

Table 212: OEXPVPH Input signals
I3P GROUP - Current connection
SIGNAL
U3P GROUP - Voltage connection
SIGNAL
RESET BOOLEAN 0 Reset operation
Table 213: OEXPVPH Output signals

TRIP BOOLEAN Trip from overexcitation function
START BOOLEAN Overexcitation above set operate level
(instantaneous)
ALARM BOOLEAN Overexcitation above set alarm level (delayed)

Table 214: OEXPVPH Group settings (basic)
On
IBase 1 - 99999 A 1 3000 Base current (rated phase current) in A
UBase 0.05 - 2000.00 kV 0.05 400.00 Base voltage (main voltage) in kV
V/Hz> 100.0 - 180.0 %UB/f 0.1 110.0 Operate level of V/Hz at no load and
rated freq in % of (Ubase/frated)
404
Voltage protection

V/Hz>> 100.0 - 200.0 %UB/f 0.1 140.0 High level of V/Hz above which tMin is
used, in % of (Ubase/frated)
XLeak 0.000 - 200.000 ohm 0.001 0.000 Winding leakage reactance in primary
ohms
TrPulse 0.000 - 60.000 s 0.001 0.100 Length of the pulse for trip signal (in sec)
tMin 0.000 - 60.000 s 0.001 7.000 Minimum trip delay for V/Hz inverse
curve, in sec
tMax 0.00 - 9000.00 s 0.01 1800.00 Maximum trip delay for V/Hz inverse
curve, in sec
tCooling 0.10 - 9000.00 s 0.01 1200.00 Transformer magnetic core cooling time
constant, in sec
CurveType IEEE - - IEEE Inverse time curve selection, IEEE/Tailor
Tailor made made
kForIEEE 1 - 60 - 1 1 Time multiplier for IEEE inverse type
curve
AlarmLevel 50.0 - 120.0 % 0.1 100.0 Alarm operate level as % of operate level
tAlarm 0.00 - 9000.00 s 0.01 5.00 Alarm time delay, in sec
Table 215: OEXPVPH Group settings (advanced)

t1Tailor 0.00 - 9000.00 s 0.01 7200.00 Time delay t1 (longest) for tailor made
curve, in sec
t2Tailor 0.00 - 9000.00 s 0.01 3600.00 Time delay t2 for tailor made curve, in sec
t6Tailor 0.00 - 9000.00 s 0.01 225.00 Time delay t6 (shortest) for tailor made
curve, in sec
Table 216: OEXPVPH Non group settings (basic)

MeasuredU PosSeq - - L1L2 Selection of measured voltage
L1L2
L2L3
L3L1
MeasuredI L1L2 - - L1L2 Selection of measured current
L2L3
L3L1
PosSeq
405
Voltage protection

Table 217: OEXPVPH technical data
Operate value, start (100–180)% of (UBase/frated) ± 0.5% of U
Operate value, alarm (50–120)% of start level ± 0.5% of Ur at U ≤ Ur

± 0.5% of U at U > Ur
Operate value, high level (100–200)% of (UBase/frated) ± 0.5% of U
Curve type IEEE or customer defined Class 5 + 40 ms
(0.18 × k )
IEEE : t =
( M - 1) 2
where M = (E/f)/(Ur/fr)
Minimum time delay for inverse (0.000–60.000) s ± 0.5% ± 10 ms
function
Maximum time delay for inverse (0.00–9000.00) s ± 0.5% ± 10 ms
function
Alarm time delay (0.000–60.000) s ± 0.5% ± 10 ms
8.5 Voltage differential protection VDCPTOV

Voltage differential protection VDCPTOV - 60
8.5.1 Introduction
A voltage differential monitoring function is available. It compares the voltages
from two three phase sets of voltage transformers and has one sensitive alarm step
and one trip step.

The Voltage differential protection function VDCPTOV (60) is based on
comparison of the amplitudes of the two voltages connected in each phase.
Possible differences between the ratios of the two Voltage/Capacitive voltage
transformers can be compensated for with a ratio correction factors RFLx. The
voltage difference is evaluated and if it exceeds the alarm level UDAlarm or trip
level UDATrip signals for alarm (ALARM output) or trip (TRIP output) is given
after definite time delay tAlarm respectively tTrip. The two three phase voltage
supplies are also supervised with undervoltage settings U1Low and U2Low. The
outputs for loss of voltage U1LOW resp U2LOW will be activated. The U1 voltage
406
Voltage protection
is supervised for loss of individual phases whereas the U2 voltage is supervised for
loss of all three phases.
Loss of all U1or all U2 voltages will block the differential measurement. This
blocking can be switched off with setting BlkDiffAtULow = No.
VDCPTOV function can be blocked from an external condition with the binary
BLOCK input. It can for example, be activated from Fuse failure supervision
function SDDRFUF.
To allow easy commissioning the measured differential voltage is available as

service value. This allows simple setting of the ratio correction factor to achieve
full balance in normal service.
The principle logic diagram is shown in figure 204.
UDTripL1>
AND
UDTripL2> O tReset tTrip

AND
R t t
AND TRIP
UDTripL3>
AND
AND START
UDAlarmL1>
AND
UDAlarmL2> O tAlarm
AND
R t AND ALARM
UDAlarmL3>
AND
U1<L1
tAlarm
U1<L2 AND t U1LOW
AND
U1<L3 AND
OR
BlkDiffAtULow
U2<L1
t1
U2<L2 AND t U2LOW
AND
U2<L3
BLOCK
en06000382-2.vsd
IEC06000382 V3 EN
Figure 204: Principle logic for Voltage differential function VDCPTOV
407
Voltage protection

VDCPTOV
U3P1* TRIP
U3P2* START
BLOCK ALARM
U1LOW
U2LOW
UL1DIFF
UL2DIFF
UL3DIFF
IEC06000528 V2 EN
Figure 205: VDCPTOV function block

Table 218: VDCPTOV Input signals
U3P1 GROUP - Bus voltage
SIGNAL
U3P2 GROUP - Capacitor voltage
SIGNAL
Table 219: VDCPTOV Output signals

TRIP BOOLEAN Voltage differential protection operated
START BOOLEAN Start of voltage differential protection
ALARM BOOLEAN Voltage differential protection alarm
U1LOW BOOLEAN Loss of U1 voltage
U2LOW BOOLEAN Loss of U2 voltage
UL1DIFF REAL Differential Voltage phase L1

Table 220: VDCPTOV Group settings (basic)
Operation Off - - Off Operation Off/On
On
UBase 0.50 - 2000.00 kV 0.01 400.00 Base Voltage
BlkDiffAtULow No - - Yes Block operation at low voltage
Yes
408
Voltage protection

UDTrip 0.0 - 100.0 %UB 0.1 5.0 Operate level, in % of UBase
tTrip 0.000 - 60.000 s 0.001 1.000 Time delay for voltage differential
operate, in milliseconds
tReset 0.000 - 60.000 s 0.001 0.000 Time delay for voltage differential reset,
in seconds
U1Low 0.0 - 100.0 %UB 0.1 70.0 Input 1 undervoltage level, in % of UBase
U2Low 0.0 - 100.0 %UB 0.1 70.0 Input 2 undervoltage level, in % of UBase
tBlock 0.000 - 60.000 s 0.001 0.000 Reset time for undervoltage block
UDAlarm 0.0 - 100.0 %UB 0.1 2.0 Alarm level, in % of UBase
tAlarm 0.000 - 60.000 s 0.001 2.000 Time delay for voltage differential alarm,
in seconds
Table 221: VDCPTOV Group settings (advanced)

RFL1 0.000 - 3.000 - 0.001 1.000 Ratio compensation factor phase L1
U2L1*RFL1=U1L1
U2L2*RFL2=U1L2
U2L3*RFL3=U1L3

Table 222: VDCPTOV technical data
Voltage difference for alarm and (0.0–100.0) % of UBase ± 0.5 % of Ur
trip
Under voltage level (0.0–100.0) % of UBase ± 0.5% of Ur
Timers (0.000–60.000)s ± 0.5% ± 10 ms
8.6 100% Stator earth fault protection, 3rd harmonic

based STEFPHIZ

100% Stator earth fault protection, 3rd STEFPHIZ - 59THD
harmonic based
409
Voltage protection
8.6.1 Introduction
Stator earth fault is a fault type having relatively high fault rate. The generator
systems normally have high impedance earthing, that is, earthing via a neutral point
resistor. This resistor is normally dimensioned to give an earth fault current in the
range 3 – 15 A at a solid earth-fault directly at the generator high voltage terminal.
The relatively small earth fault currents give much less thermal and mechanical
stress on the generator, compared to the short circuit case, which is between
conductors of two phases. Anyhow, the earth faults in the generator have to be
detected and the generator has to be tripped, even if longer fault time compared to
internal short circuits, can be allowed.
In normal non-faulted operation of the generating unit the neutral point voltage is
close to zero, and there is no zero sequence current flow in the generator. When a
phase-to-earth fault occurs the neutral point voltage will increase and there will be
a current flow through the neutral point resistor.
To detect an earth fault on the windings of a generating unit one may use a neutral
point overvoltage protection, a neutral point overcurrent protection, a zero
sequence overvoltage protection or a residual differential protection. These
protections are simple and have served well during many years. However, at best
these simple schemes protect only 95% of the stator winding. They leave 5% close
to the neutral end unprotected. Under unfavorable conditions the blind zone may
extend up to 20% from the neutral.
The 95% stator earth fault protection measures the fundamental frequency voltage
component in the generator star point and it operates when it exceeds the preset
value. By applying this principle approximately 95% of the stator winding can be
protected. In order to protect the last 5% of the stator winding close to the neutral
end the 3rd harmonic voltage measurement can be performed. In 100% Stator E/F
3rd harmonic protection either the 3rd harmonic voltage differential principle, the
neutral point 3rd harmonic undervoltage principle or the terminal side 3rd
harmonic overvoltage principle can be applied. However, differential principle is
strongly recommended. Combination of these two measuring principles provides
coverage for entire stator winding against earth faults.
410
Voltage protection
stator winding CB 1 may not exist

x E3 (1- x) E3 CB 1 CB 2
N T
RN Rf Transformer
uN x 1- x uT
Samples of the Samples of the
neutral voltage 1 or 100 % terminal voltage
from which the from which the
fundamental and 3rd harmonic
3rd harmonic voltage is filtered
Neutral point fundamental frequency
voltages are out
over-voltage protection 5% - 100%
filtered out overvoltage protection 10%– 100%
3rd harmonic
Differential
differential
0% – 30%
0% - 30% IEC10000202-1-en.vsd
IEC10000202 V1 EN
Figure 206: Protection principles for STEFPHIZ function

The protection is a combination of the 95% fundamental frequency earth fault
protection and the 3 rd harmonic based stator earth fault protection, (STEFPHIZ).
The 3rd harmonic based 100% stator earth fault protection is using the 3rd harmonic
voltage generated by the generator itself. To assure reliable function of the
protection it is necessary that the 3rd harmonic voltage generation is at least 0.8 V
RMS on VT secondary side.
The 3rd harmonic voltage generated by the generator has the same phase angle in
the three phases. It has the characteristic of a zero sequence component. If the
generator is connected to the power system via a block transformer that cannot
transform zero sequence voltages between the voltage levels, the 3rd harmonic
voltage, that is U3N and U3T in fig 207, in the generator system is not influenced by
the external power system. At normal operation the generator third harmonic
voltage characteristic can be described as in figure 207.
Note that angle between U3N and U3T is typically close to 180°.
411
Voltage protection
- U3 +
- DU3 +
+
U3T,L1
-
+
- U3N + U3T,L2
-
+
U3T,L3
-
U3T
U3N
en06000448.vsd
IEC06000448 V2 EN
Figure 207: Generator 3rd harmonic voltage characteristic at normal operation
The generator is modeled as parts of a winding where a 3rd harmonic voltage is

induced along the winding, represented by the end voltages U3N and U3T in the
figure. Via the winding capacitances to earth and the neutral point resistor there
will be a small 3rd harmonic current flow, giving the voltages U3N and U3T. It can
easily be seen that the 3rd harmonic voltage in the generator neutral point (U3N)
will be close to zero in case of a stator earth-fault close to the neutral. This fact
alone can be used as an indication of stator earth-fault. To enable better sensitivity
and stability also measurement of the generator's 3rd harmonic voltage U3T is also
used. In addition to the decrease of U3N the generator voltage U3T will increase
under the stator earth-fault close to the generator neutral point. Therefore the 3rd
harmonic voltage U3T , (which is a zero sequence voltage) is used by the
protection. In the 3rd harmonic voltage differential protection algorithm
equation 125 is used:
412
Voltage protection
U3N + U3T ³ Beta U 3N

U3N, and U3T are third harmonic phasors with real and imaginary parts. The factor
Beta must be set not to risk operation under non-faulted conditions.
The voltage U3N is measured via a voltage transformer between the generator
neutral point and earth. The voltage U3T can be measured in different ways. The
setting TVoltType defines how the protection function is fed from voltage
transformers at the high voltage side of the generator. (If U3T is lower than the set
level UT3BlkLevel, STEFPHIZ function is blocked. The choices of TVoltType are:
NoVoltage: There is no voltage measured from the generator terminal side. This
can be the case when there are only phase-to-phase voltage transformers available
at the generator terminal side. In this case the protection will operate as a simple
neutral point 3rd harmonic undervoltage protection, which must be blocked
externally during generator start-up and shut-down.
ResidualVoltage: The function is fed from an open delta connection of the phase to
earth connected voltage transformers at the generator terminal side,
U3T=(1/3)*U_Open_Delta.
AllThreePhases: The function is fed from the three phase to earth connected
voltage transformers at the generator terminal side. The 3rd harmonic voltage U3T
is calculated in the IED, U3T=(1/3)*(U3L1+U3L2+U3L3).
PhaseL1, PhaseL2, or PhaseL3: The function is fed from one phase voltage
transformer only. The 3rd harmonic zero sequence voltage is assumed to be equal
to any of the phase voltages, as the third harmonic voltage is of zero sequence type,
U3T=U3Lx.
A simplified block diagram describing the stator earth fault protection function
shown in figure 208.
413
Voltage protection
Samples:
Generator 3rd
terminal TRIP
harmonic
voltage Complex UT3 Stator Earth
Fourier
filtering Fault
detection TRIP3H
giving UT3
3rd
harmonic
TRIPUN
based Start
Start
and trip
logic START3H
Samples:
Generator 3rd
neutral point STARTUN
harmonic Complex UN3
voltage Fourier
filtering
giving UN3
Fundamental frequency residual Stator Earth

voltage Fault Start
detection
95 %
CB Status
Block
en06000449.vsd
IEC06000449 V2 EN
Figure 208: Simplified logic diagram for stator earth fault protection
STEFPHIZ function can be described in a simplified logical diagram as shown in

figure 209. Note that the 3rd harmonic numerical filters are not part of the stator earth-
fault protection function.
These third harmonic voltages are calculated by the preprocessing blocks

connected to the function.
414
Voltage protection
IEC07000186 V1 EN
Figure 209: Simplified Start and Trip logical diagram of the 100% Stator earth
fault protection, 3rd harmonic based STEFPHIZ protection
There are two different cases of generator block configuration; with or without
generator circuit breaker. If there is no generator breaker the capacitive coupling to
earth is the same under all operating conditions. When there is a generator breaker,
the capacitive coupling to earth differs between the operating conditions when the
generator is running with the generator breaker open (before synchronization) and
with the circuit breaker closed. This can be shown as in figure 210.
- U3 +
- DU3 +
+ Ctr/3
U3T,L1
-
+
- U3N + Ctr/3
U3T,L2
-
+
U3T,L3 Ctr/3
-
en07000002-2.vsd
IEC07000002 V2 EN
Figure 210: Generator block with generator circuit breaker
With the circuit breaker open, the total capacitance will be smaller compared to
normal operating conditions. This means that the neutral point 3rd harmonic
voltage will be reduced compared to the normal operating condition. Therefore,
415
Voltage protection
there is a possibility to reduce the sensitivity of the protection when the generator
circuit breaker is open.
With the setting CBexists change of the sensitivity is enabled. If the binary input
signal CBCLOSED is activated the set sensitivity is valid. If the generator circuit
breaker is opened the binary input CBCLOSED is deactivated and the sensitivity is
changed. This is done by changing the factor Beta which is multiplied with a set
constant FactorCBopen.
In addition to the binary outputs also some analog outputs are available from the
protection function in order to enable easier commissioning:
E3: the magnitude of the 3rd harmonic voltage induced in the stator given in
primary volts
UN3: the magnitude of the 3rd harmonic voltage measured in the neutral point of
the generator
UT3: the magnitude of the 3rd harmonic voltage measured in the terminal point of
the generator
ANGLE: the angle between the phasors UN3 and UT3 given in radians
DU3: the magnitude of the 3rd harmonic differential voltage
BU3: the magnitude of the 3rd harmonic bias voltage
UN: the fundamental frequency voltage measured in the neutral point of the generator

STEFPHIZ
NEUTVOLT TRIP
TERMVOLT TRIP3H
CBCLOSED TRIPUN
BLOCK START
BLOCK3RD START3H
BLOCKUN STARTUN
UT3
UN3
E3
ANGLE
DU3
BU3
UN
IEC11000211 V1 EN
Figure 211: STEFPHIZ function block
416
Voltage protection

Table 223: STEFPHIZ Input signals
NEUTVOLT GROUP - Voltage connection neutral side
SIGNAL
TERMVOLT GROUP - Open-Delta connection on Terminal side
SIGNAL
CBCLOSED BOOLEAN 1 TRUE means breaker between gen. & trafo is
closed
BLOCK BOOLEAN 0 Complete block of the stator earth fault protecion
function
BLOCK3RD BOOLEAN 0 Block of the 3rd harmonic-based parts of the
protection
BLOCKUN BOOLEAN 0 Block of the fund. harmonic-based part of the
protection
Table 224: STEFPHIZ Output signals

TRIP BOOLEAN Main, common trip command
TRIP3H BOOLEAN Trip by one of two 3rd harmonic voltage-based prot.
TRIPUN BOOLEAN Trip by fund. freq. neutral over-voltage protection
START BOOLEAN Main, common start signal
START3H BOOLEAN Start by one of two 3rd harmonic voltage-based
prot.
STARTUN BOOLEAN Start signal by fund. freq. neutral over-voltage prot.
UT3 REAL Mag. of 3rd harm. voltage at generator terminal
side, Volts
UN3 REAL Mag. of 3rd harm. voltage at generator neutral
side, Volts
E3 REAL Total induced stator 3rd harmonic voltage,
primary Volts
ANGLE REAL Angle between 3rd harmonic votage phasors,
radians
DU3 REAL Diff. between 3rd harm. volt. at both sides of gen.,
Volts
BU3 REAL Bias voltage, a part of voltN3rdHarmonic, primary
Volts
UN REAL Fund. frequency voltage at generator neutral,
primary Volts
417
Voltage protection

Table 225: STEFPHIZ Group settings (basic)
On
Beta 0.50 - 10.00 - 0.01 3.00 Portion of voltN3rdHarmonic used as bias
CBexists No - - No Defines if generator CB exists (between
Yes Gen & Transformer)
FactorCBopen 1.00 - 10.00 - 0.01 1.00 Beta is multiplied by this factor when CB
is open
UN3rdH< 0.5 - 10.0 % 0.1 2.0 Pickup 3rd Harm U< protection (when
activated) % of UB/1,732
UT3BlkLevel 0.1 - 10.0 % 0.1 1.0 If UT3 is below limit 3rdH Diff is blocked,
in % of UB/1,732
UNFund> 1.0 - 50.0 % 0.1 5.0 Pickup fundamental UN> protection
(95% SEF), % of UB/1,732
t3rdH 0.020 - 60.000 s 0.001 1.000 Operation delay of 3rd harm-based
protection (100% SEF) in s
tUNFund 0.020 - 60.000 s 0.001 0.500 Operation delay of fundamental UN>
protection (95% SEF) in s
Table 226: STEFPHIZ Non group settings (basic)

GenRatedVolt 1.0 - 100.0 kV 0.1 10.0 Generator rated (nominal) phase-to-
phase voltage in kV
TVoltType NoVoltage - - ResidualVoltage Used connection type for gen. terminal
ResidualVoltage voltage transformer
AllThreePhases
PhaseL1
PhaseL2
PhaseL3

Table 227: STEFPHIZ technical data
Fundamental frequency level (1.0–50.0)% of UBase ± 0.5% of Ur
UN (95% Stator EF)
Third harmonic differential level (0.5–10.0)% of UBase ± 0.5% of Ur
Third harmonic differential block (0.1–10.0)% of UBase ± 0.5% of Ur

level
Timers (0.020–60.000) s ± 0.5% ± 10 ms
Filter characteristic: -
Fundamental Reject third harmonic by 1–40
Third harmonic Reject fundamental harmonic by
1–40
418
Frequency protection
Section 9 Frequency protection
About this chapter

This chapter describes the frequency protection functions. The way the functions
work, their setting parameters, function blocks, input and output signals and
technical data are included for each function.
9.1 Underfrequency protection SAPTUF

Underfrequency protection SAPTUF 81
f<
SYMBOL-P V1 EN
9.1.1 Introduction
Underfrequency occurs as a result of lack of generation in the network.
Underfrequency protection SAPTUF is used for load shedding systems, remedial

action schemes, gas turbine startup and so on.
SAPTUF is provided with an undervoltage blocking.
The operation is based on positive sequence voltage measurement and requires two
phase-phase or three phase-neutral voltages to be connected. For information about
how to connect analog inputs, refer to Application manual/IED application/
Analog inputs/Setting guidelines

Underfrequency protection SAPTUF is used to detect low power system frequency.
SAPTUF can either have a definite time delay or a voltage magnitude dependent
time delay. If the voltage magnitude dependent time delay is applied, the time
delay will be longer if the voltage is higher, and the delay will be shorter if the
voltage is lower. If the frequency remains below the set value for a time period
corresponding to the chosen time delay, the corresponding trip signal is issued. To
avoid an unwanted trip due to uncertain frequency measurement at low voltage
419
magnitude, a voltage controlled blocking of the function is available, that is, if the
voltage is lower than the set blocking voltage IntBlockLevel the function is blocked
and no START or TRIP signal is issued.
The fundamental frequency of the measured input voltage is measured

continuously, and compared with the set value, StartFrequency. The frequency
function is dependent on the voltage magnitude. If the voltage magnitude decreases
the setting IntBlockLevel, SAPTUF gets blocked, and the output BLKDMAGN is
issued. All voltage settings are made in percent of the setting UBase, which should
be set as a phase-phase voltage in kV.
9.1.2.2 Time delay
The time delay for underfrequency protection SAPTUF can be either a settable
definite time delay or a voltage magnitude dependent time delay, where the time
delay depends on the voltage level; a high voltage level gives a longer time delay
and a low voltage level causes a short time delay. For the definite time delay, the
setting TimeDlyOperate sets the time delay.
For the voltage dependent time delay the measured voltage level and the settings
UNom, UMin, Exponent, tMax and tMin set the time delay according to figure 212
and equation 126. The setting TimerOperation is used to decide what type of time
delay to apply.
Trip signal issuing requires that the underfrequency condition continues for at least
the user set time delay TimeDlyOperate. If the START condition, with respect to
the measured frequency ceases during this user set delay time, and is not fulfilled
again within a user defined reset time, TimeDlyReset, the START output is reset,
after that the defined reset time has elapsed. Here it should be noted that after
leaving the hysteresis area, the START condition must be fulfilled again and it is
not sufficient for the signal to only return back to the hysteresis area.
On the output of SAPTUF a 100ms pulse is issued, after a time delay

corresponding to the setting of TimeDlyRestore, when the measured frequency
returns to the level corresponding to the setting RestoreFreq.
9.1.2.3 Voltage dependent time delay
Since the fundamental frequency in a power system is the same all over the system,
except some deviations during power oscillations, another criterion is needed to
decide, where to take actions, based on low frequency. In many applications the
voltage level is very suitable, and in most cases is load shedding preferable in areas
with low voltage. Therefore, a voltage dependent time delay has been introduced,
to make sure that load shedding, or other actions, take place at the right location. At
constant voltage, U, the voltage dependent time delay is calculated according to
420
equation 126. At non-constant voltage, the actual time delay is integrated in a

similar way as for the inverse time characteristic for the undervoltage and
overvoltage functions.
Exponent
é U - UMin ù
t=ê × ( tMax - tMin ) + tMin
UNom - UMin ú ë û
where:
t is the voltage dependent time delay (at constant voltage),
U is the measured voltage
Exponent is a setting,
UMin, UNom are voltage settings corresponding to
tMax, tMin are time settings.
The inverse time characteristics are shown in figure 212, for:
UMin = 90%
UNom = 100%
tMax = 1.0 s
tMin = 0.0 s
Exponent = 0, 1, 2, 3 and 4
1
0
1
Exponenent
TimeDlyOperate [s]
2
3
0.5 4
0
90 95 100
U [% of UBase]
en05000075.vsd
IEC05000075 V1 EN
Figure 212: Voltage dependent inverse time characteristics for underfrequency

protection SAPTUF. The time delay to operate is plotted as a
function of the measured voltage, for the Exponent = 0, 1, 2, 3, 4
respectively.
421
9.1.2.4 Blocking
It is possible to block underfrequency protection SAPTUF partially or completely,

by binary input signals or by parameter settings, where:

BLKTRIP: blocks the TRIP output
BLKREST: blocks the RESTORE output
If the measured voltage level decreases below the setting of IntBlockLevel, both the
START and the TRIP outputs, are blocked.
9.1.2.5 Design
The frequency measuring element continuously measures the frequency of the

positive sequence voltage and compares it to the setting StartFrequency. The
frequency signal is filtered to avoid transients due to switchings and faults. The
time integrator can operate either due to a definite delay time or to the special
voltage dependent delay time. When the frequency has returned back to the setting
of RestoreFreq, the RESTORE output is issued after the time delay
TimeDlyRestore. The design of underfrequency protection SAPTUF is
schematically described in figure 213.
Block
BLOCK BLKDMAGN
OR
Comparator
U < IntBlockLevel
Voltage Time integrator

Start
TimerOperation Mode & START
Selector START
Frequency Comparator Trip
f < StartFrequency Output
TimeDlyOperate TRIP Logic
TimeDlyReset TRIP
100 ms
Comparator RESTORE
TimeDlyRestore
f > RestoreFreq
en05000726.vsd
IEC05000726 V1 EN
Figure 213: Simplified logic diagram for SAPTUF
422

SAPTUF
U3P* TRIP
BLOCK START
BLKTRIP RESTORE
BLKREST BLKDMAGN
FREQ
IEC06000279 V2 EN
Figure 214: SAPTUF function block

Table 228: SAPTUF Input signals
SIGNAL
BLKTRIP BOOLEAN 0 Blocking operate output.
BLKREST BOOLEAN 0 Blocking restore output.
Table 229: SAPTUF Output signals

TRIP BOOLEAN Operate/trip signal for frequency.
START BOOLEAN Start/pick-up signal for frequency.
RESTORE BOOLEAN Restore signal for load restoring purposes.
BLKDMAGN BOOLEAN Blocking indication due to low amplitude.
FREQ REAL Measured frequency

Table 230: SAPTUF Group settings (basic)
On
StartFrequency 35.00 - 75.00 Hz 0.01 48.80 Frequency setting/start value.
IntBlockLevel 0 - 100 %UB 1 50 Internal blocking level in % of UBase.
TimeDlyOperate 0.000 - 60.000 s 0.001 0.200 Operate time delay in over/under-
frequency mode.
TimeDlyReset 0.000 - 60.000 s 0.001 0.000 Time delay for reset.
TimeDlyRestore 0.000 - 60.000 s 0.001 0.000 Restore time delay.
423

RestoreFreq 45.00 - 65.00 Hz 0.01 50.10 Restore frequency if frequency is above
frequency value.
TimerOperation Definite timer - - Definite timer Setting for choosing timer mode.
Volt based timer
UNom 50 - 150 %UB 1 100 Nominal voltage in % of UBase for
voltage based timer.
UMin 50 - 150 %UB 1 90 Lower operation limit in % of UBase for
Exponent 0.0 - 5.0 - 0.1 1.0 For calculation of the curve form for
tMax 0.010 - 60.000 s 0.001 1.000 Maximum time operation limit for voltage
based timer.
tMin 0.010 - 60.000 s 0.001 1.000 Minimum time operation limit for voltage
based timer.

Table 231: SAPTUF technical data
Operate value, start function (35.00-75.00) Hz ± 2.0 mHz
Operate time, start function 100 ms typically -
Reset time, start function 100 ms typically -
Operate time, definite time function (0.000-60.000)s ± 0.5% ±
10 ms
Reset time, definite time function (0.000-60.000)s ± 0.5% ±
10 ms
Voltage dependent time delay Settings: Class 5 +
UNom=(50-150)% of Ubase 200 ms
é U - UMin ù
Exponent
UMin=(50-150)% of Ubase
t=ê × ( tMax - tMin ) + tMin
ë UNom - UMin ú û Exponent=0.0-5.0
tMax=(0.000-60.000)s
tMin=(0.000-60.000)s
U=Umeasured
9.2 Overfrequency protection SAPTOF

Overfrequency protection SAPTOF 81
f>
SYMBOL-O V1 EN
424
9.2.1 Introduction
Overfrequency protection function SAPTOF is applicable in all situations, where
reliable detection of high fundamental power system frequency is needed.
Overfrequency occurs at sudden load drops or shunt faults in the power network.
Close to the generating plant, generator governor problems can also cause over
frequency.
SAPTOF is used mainly for generation shedding and remedial action schemes. It is
also used as a frequency stage initiating load restoring.
SAPTOF is provided with an undervoltage blocking.
The operation is based on positive sequence voltage measurement and requires two
phase-phase or three phase-neutral voltages to be connected. For information about
how to connect analog inputs, refer to Application manual/IED application/
Analog inputs/Setting guidelines

Overfrequency protection SAPTOF is used to detect high power system frequency.
SAPTOF has a settable definite time delay. If the frequency remains above the set
value for a time period corresponding to the chosen time delay, the corresponding
TRIP signal is issued. To avoid an unwanted TRIP due to uncertain frequency
measurement at low voltage magnitude, a voltage controlled blocking of the
function is available from the preprocessing function, that is, if the voltage is lower
than the set blocking voltage in the preprocessing function, the function is blocked
and no START or TRIP signal is issued.
The fundamental frequency of the positive sequence voltage is measured

continuously, and compared with the set value, StartFrequency. Overfrequency
protection SAPTOF is dependent on the voltage magnitude. If the voltage
magnitude decreases below the setting IntBlockLevel, SAPTOF is blocked, and the
output BLKDMAGN is issued. All voltage settings are made in percent of the
UBase, which should be set as a phase-phase voltage in kV. To avoid oscillations
of the output START signal, a hysteresis has been included.
9.2.2.2 Time delay
The time delay for Overfrequency protection SAPTOF (81) is a settable definite
time delay, specified by the setting TimeDlyOperate.
TRIP signal issuing requires that the overfrequency condition continues for at least
the user set time delay, TimeDlyReset. If the START condition, with respect to the
measured frequency ceases during this user set delay time, and is not fulfilled again
425
within a user defined reset time, TimeDlyReset, the START output is reset, after
that the defined reset time has elapsed. It is to be noted that after leaving the
hysteresis area, the START condition must be fulfilled again and it is not sufficient
for the signal to only return back to the hysteresis area.
9.2.2.3 Blocking
It is possible to block overfrequency protection SAPTOF partially or completely,


9.2.2.4 Design
The frequency measuring element continuously measures the frequency of the

positive sequence voltage and compares it to the setting StartFrequency. The
frequency signal is filtered to avoid transients due to switchings and faults in the
power system. The time integrator operates due to a definite delay time. The design
of overfrequency protection SAPTOF is schematically described in figure 215.
BLOCK
BLKTRIP BLOCK
OR BLKDMAGN
Comparator
U < IntBlockLevel
Start
&
Trip
Voltage Time integrator Output
Logic
Definite Time Delay START START
Frequency Comparator
f > StartFrequency TimeDlyOperate
TRIP
TimeDlyReset
TRIP
en05000735.vsd
IEC05000735 V1 EN
Figure 215: Schematic design of overfrequency protection SAPTOF
426

SAPTOF
U3P* TRIP
BLOCK START
BLKTRIP BLKDMAGN
FREQ
IEC06000280 V2 EN
Figure 216: SAPTOF function block

Table 232: SAPTOF Input signals
SIGNAL
Table 233: SAPTOF Output signals

TRIP BOOLEAN Operate/trip signal for frequency.
START BOOLEAN Start/pick-up signal for frequency.
FREQ REAL Measured frequency

Table 234: SAPTOF Group settings (basic)
On
StartFrequency 35.00 - 75.00 Hz 0.01 51.20 Frequency setting/start value.
TimeDlyOperate 0.000 - 60.000 s 0.001 0.000 Operate time delay in over/under-
frequency mode.
TimeDlyReset 0.000 - 60.000 s 0.001 0.000 Time delay for reset.
427

Table 235: SAPTOF technical data
Operate value, start function (35.00-75.00) Hz ± 2.0 mHz at
symmetrical three-
phase voltage
Operate time, start function 100 ms typically at fset -0.5 Hz to fset +0.5 Hz -
Reset time, start function 100 ms typically -

Operate time, definite time (0.000-60.000)s ± 0.5% ± 10 ms
function
Reset time, definite time (0.000-60.000)s ± 0.5% ± 10 ms
function
9.3 Rate-of-change frequency protection SAPFRC

Rate-of-change frequency protection SAPFRC 81
df/dt >
<
SYMBOL-N V1 EN
9.3.1 Introduction
Rate-of-change frequency protection function (SAPFRC) gives an early indication
of a main disturbance in the system. SAPFRC can be used for generation shedding,
load shedding and remedial action schemes. SAPFRC can discriminate between
positive or negative change of frequency.
SAPFRC is provided with an undervoltage blocking. The operation is based on

positive sequence voltage measurement and requires two phase-phase or three phase-
neutral voltages to be connected. For information about how to connect analog
inputs, refer to Application manual/IED application/Analog inputs/Setting
guidelines.

Rate-of-change frequency protection SAPFRC is used to detect fast power system
frequency changes, increase as well as, decrease at an early stage. SAPFRC has a
settable definite time delay. If the rate-of-change of frequency remains below the
set value, for negative rate-of-change, for a time period equal to the chosen time
delay, the TRIP signal is issued. If the rate-of-change of frequency remains above
the set value, for positive rate-of-change, for a time period equal to the chosen time
428
delay, the TRIP signal is issued. To avoid an unwanted TRIP due to uncertain
frequency measurement at low voltage magnitude, a voltage controlled blocking of
the function is available, that is if the voltage is lower than the set blocking voltage
IntBlockLevel, the function is blocked and no START or TRIP signal is issued. If
the frequency recovers, after a frequency decrease, a restore signal is issued.
The rate-of-change of the fundamental frequency of the selected voltage is

measured continuously, and compared with the set value, StartFreqGrad. Rate-of-
change frequency protection SAPFRC is also dependent on the voltage magnitude.
If the voltage magnitude decreases below the setting IntBlockLevel, SAPFRC is
blocked, and the output BLKDMAGN is issued. The sign of the setting
StartFreqGrad, controls if SAPFRC reacts on a positive or on a negative change in
frequency. If SAPFRC is used for decreasing frequency that is, the setting
StartFreqGrad has been given a negative value, and a trip signal has been issued,
then a 100 ms pulse is issued on the RESTORE output, when the frequency
recovers to a value higher than the setting RestoreFreq. A positive setting of
StartFreqGrad, sets SAPFRC to START and TRIP for frequency increases.
9.3.2.2 Time delay
Rate-of-change frequency protection SAPFRC has a settable definite time delay,

tTrip. .
Trip signal issuing requires that the rate-of-change of frequency condition

continues for at least the user set time delay, tTrip. If the START condition, with
respect to the measured frequency ceases during the delay time, and is not fulfilled
again within a user defined reset time, tReset, the START output is reset, after that
the defined reset time has elapsed. Here it should be noted that after leaving the
hysteresis area, the START condition must be fulfilled again and it is not sufficient
for the signal to only return back into the hysteresis area.
The RESTORE output of SAPFRC is set, after a time delay equal to the setting of
tRestore, when the measured frequency has returned to the level corresponding to
RestoreFreq, after an issue of the TRIP output signal. If tRestore is set to 0.000 s
the restore functionality is disabled, and no output will be given. The restore
functionality is only active for lowering frequency conditions and the restore
sequence is disabled if a new negative frequency gradient is detected during the
restore period, defined by the settings RestoreFreq and tRestore.
9.3.2.3 Blocking
Rate-of-change frequency protection (SAPFRC) can be partially or totally blocked,

429

BLKREST: blocks the RESTORE output
9.3.2.4 Design
Rate-of-change frequency protection (SAPFRC) measuring element continuously

measures the frequency of the selected voltage and compares it to the setting
StartFreqGrad. The frequency signal is filtered to avoid transients due to power
system switchings and faults. The time integrator operates with a definite delay
time. When the frequency has returned back to the setting of RestoreFreq, the
RESTORE output is issued after the time delay tRestore, if the TRIP signal has
earlier been issued. The sign of the setting StartFreqGrad is essential, and controls
if the function is used for raising or lowering frequency conditions. The design of
SAPFRC is schematically described in figure 217.
BLOCK
BLKTRIP
BLKRESET BLOCK
OR
Voltage Comparator BLKDMAGN

U < IntBlockLevel
Start
Rate-of-Change Time integrator &
Comparator
of Frequency Trip
If
Definite Time Delay Output
[StartFreqGrad<0 START START
Logic
AND
TimeDlyOperate
df/dt < StartFreqGrad]
OR
TimeDlyReset
[StartFreqGrad>0
AND
TRIP
df/dt > StartFreqGrad]
Then
START
100 ms
Frequency Comparator RESTORE

TimeDlyRestore
f > RestoreFreq
en05000835.vsd
IEC05000835 V1 EN
Figure 217: Schematic design of Rate-of-change frequency protection SAPFRC
430

SAPFRC
U3P* TRIP
BLOCK START
BLKTRIP RESTORE
BLKREST BLKDMAGN
IEC06000281 V2 EN
Figure 218: SAPFRC function block

Table 236: SAPFRC Input signals
SIGNAL
BLKREST BOOLEAN 0 Blocking restore output.
Table 237: SAPFRC Output signals

TRIP BOOLEAN Operate/trip signal for frequencyGradient
START BOOLEAN Start/pick-up signal for frequencyGradient
RESTORE BOOLEAN Restore signal for load restoring purposes.

Table 238: SAPFRC Group settings (basic)
On
UBase 0.05 - 2000.00 kV 0.05 400.00 Base setting for the phase-phase voltage
in kV
StartFreqGrad -10.00 - 10.00 Hz/s 0.01 0.50 Frequency gradient start value. Sign
defines direction.
tTrip 0.000 - 60.000 s 0.001 0.200 Operate time delay in pos./neg.
frequency gradient mode.
RestoreFreq 45.00 - 65.00 Hz 0.01 49.90 Restore frequency if frequency is above
frequency value (Hz)
tRestore 0.000 - 60.000 s 0.001 0.000 Restore time delay.
tReset 0.000 - 60.000 s 0.001 0.000 Time delay for reset.
431

Table 239: SAPFRC Technical data
Operate value, start function (-10.00-10.00) Hz/s ± 10.0 mHz/s
Operate value, internal (0-100)% of UBase ± 0.5% of Ur
blocking level
Operate time, start function 100 ms typically -
432
Multipurpose protection
Section 10 Multipurpose protection
About this chapter

This chapter describes Multipurpose protection and includes the General current
and voltage function. The way the functions work, their setting parameters,
function blocks, input and output signals and technical data are included for each
function.
10.1 General current and voltage protection CVGAPC

General current and voltage protection CVGAPC - -
10.1.1 Introduction
The protection module is recommended as a general backup protection with many
possible application areas due to its flexible measuring and setting facilities.
The built-in overcurrent protection feature has two settable current levels. Both of
them can be used either with definite time or inverse time characteristic. The
overcurrent protection steps can be made directional with selectable voltage
polarizing quantity. Additionally they can be voltage and/or current controlled/
restrained. 2nd harmonic restraining facility is available as well. At too low
polarizing voltage the overcurrent feature can be either blocked, made non
directional or ordered to use voltage memory in accordance with a parameter setting.
Additionally two overvoltage and two undervoltage steps, either with definite time
or inverse time characteristic, are available within each function.
The general function suits applications with underimpedance and voltage

controlled overcurrent solutions. The general function can also be utilized for
generator transformer protection applications where positive, negative or zero
sequence components of current and voltage quantities are typically required.
Additionally, generator applications such as loss of field, inadvertent energizing,

stator or rotor overload, circuit breaker head flash-over and open phase detection
are just a few of possible protection arrangements with these functions.
433
10.1.1.1 Inadvertent generator energization
When the generator is taken out of service, and non-rotating, there is a risk that the
generator circuit breaker flashes over or is closed by mistake.
To prevent damages on the generator or turbine, it is essential that high speed

tripping is provided in case of inadvertent energization of the generator. This
tripping should be almost instantaneous (< 100 ms).
There is a risk that the current into the generator at inadvertent energization will be
limited so that the “normal” overcurrent or underimpedance protection will not
detect the dangerous situation. The delay of these protection functions might be too
long. For big and important machines, fast protection against inadvertent
energizing should, therefore, be included in the protective scheme.
10.1.2.1 Measured quantities within CVGAPC
General current and voltage protection (CVGAPC) function is always connected to

three-phase current and three-phase voltage input in the configuration tool, but it
will always measure only one current and one voltage quantity selected by the end
user in the setting tool.
The user can select to measure one of the current quantities shown in table 240.
Table 240: Current selection for CVGAPC function

Set value for the
parameter Comment
CurrentInput
1 Phase1 CVGAPC function will measure the phase L1 current phasor
4 PosSeq CVGAPC function will measure internally calculated positive sequence
current phasor
5 NegSeq CVGAPC function will measure internally calculated negative
sequence current phasor
6 3ZeroSeq CVGAPC function will measure internally calculated zero sequence
current phasor multiplied by factor 3
7 MaxPh CVGAPC function will measure current phasor of the phase with
maximum magnitude
8 MinPh CVGAPC function will measure current phasor of the phase with
minimum magnitude
9 UnbalancePh CVGAPC function will measure magnitude of unbalance current, which
is internally calculated as the algebraic magnitude difference between
the current phasor of the phase with maximum magnitude and current
phasor of the phase with minimum magnitude. Phase angle will be set
to 0° all the time
434
Set value for the

parameter Comment
CurrentInput
10 Phase1-Phase2 CVGAPC function will measure the current phasor internally calculated
as the vector difference between the phase L1 current phasor and
phase L2 current phasor (IL1-IL2)
phase L3 current phasor (IL2-IL3)
phase L1 current phasor ( IL3-IL1)
13 MaxPh-Ph CVGAPC function will measure ph-ph current phasor with the
maximum magnitude
14 MinPh-Ph CVGAPC function will measure ph-ph current phasor with the
minimum magnitude
15 UnbalancePh-Ph CVGAPC function will measure magnitude of unbalance current, which
is internally calculated as the algebraic magnitude difference between
the ph-ph current phasor with maximum magnitude and ph-ph current
phasor with minimum magnitude. Phase angle will be set to 0° all the
time
The user can select to measure one of the voltage quantities shown in table 241:
Table 241: Voltage selection for CVGAPC function

Set value for the
parameter Comment
VoltageInput
1 Phase1 CVGAPC function will measure the phase L1 voltage phasor
voltage phasor
5 -NegSeq CVGAPC function will measure internally calculated negative
sequence voltage phasor. This voltage phasor will be intentionally
rotated for 180° in order to enable easier settings for the directional
feature when used.
6 -3ZeroSeq CVGAPC function will measure internally calculated zero sequence
voltage phasor multiplied by factor 3. This voltage phasor will be
intentionally rotated for 180° in order to enable easier settings for the
directional feature when used.
7 MaxPh CVGAPC function will measure voltage phasor of the phase with
maximum magnitude
8 MinPh CVGAPC function will measure voltage phasor of the phase with
minimum magnitude
9 UnbalancePh CVGAPC function will measure magnitude of unbalance voltage,
which is internally calculated as the algebraic magnitude difference
between the voltage phasor of the phase with maximum magnitude
and voltage phasor of the phase with minimum magnitude. Phase
angle will be set to 0° all the time
435
Set value for the

parameter Comment
VoltageInput
10 Phase1-Phase2 CVGAPC function will measure the voltage phasor internally
calculated as the vector difference between the phase L1 voltage
phasor and phase L2 voltage phasor (UL1-UL2)

phasor and phase L3 voltage phasor (UL2-UL3)

phasor and phase L1 voltage phasor ( UL3-UL1)
13 MaxPh-Ph CVGAPC function will measure ph-ph voltage phasor with the
maximum magnitude
14 MinPh-Ph CVGAPC function will measure ph-ph voltage phasor with the
minimum magnitude
15 UnbalancePh-Ph CVGAPC function will measure magnitude of unbalance voltage,
which is internally calculated as the algebraic magnitude difference
between the ph-ph voltage phasor with maximum magnitude and ph-
ph voltage phasor with minimum magnitude. Phase angle will be set to
0° all the time
It is important to notice that the voltage selection from table 241 is always
applicable regardless the actual external VT connections. The three-phase VT
inputs can be connected to IED as either three phase-to-ground voltages UL1, UL2
& UL3 or three phase-to-phase voltages UL1L2, UL2L3 & UL3L1). This information
about actual VT connection is entered as a setting parameter for the pre-processing
block, which will then take automatic care about it.
The user can select one of the current quantities shown in table 242 for built-in
current restraint feature:
Table 242: Restraint current selection for CVGAPC function

Set value for the
parameter RestrCurr Comment
current phasor
2 NegSeq CVGAPC function will measure internally calculated negative
sequence current phasor
3 3ZeroSeq CVGAPC function will measure internally calculated zero sequence
current phasor multiplied by factor 3
4 MaxPh CVGAPC function will measure current phasor of the phase with
maximum magnitude
10.1.2.2 Base quantities for CVGAPC function
The parameter settings for the base quantities, which represent the base (100%) for
pickup levels of all measuring stages, shall be entered as setting parameters for
every CVGAPC function.
436
Base current shall be entered as:
1. rated phase current of the protected object in primary amperes, when the
measured Current Quantity is selected from 1 to 9, as shown in table 240.
2. rated phase current of the protected object in primary amperes multiplied by
√3 (1.732 · Iphase), when the measured Current Quantity is selected from 10
to 15, as shown in table 240.
Base voltage shall be entered as:
1. rated phase-to-earth voltage of the protected object in primary kV, when the
measured Voltage Quantity is selected from 1 to 9, as shown in table 241.
2. rated phase-to-phase voltage of the protected object in primary kV, when the
measured Voltage Quantity is selected from 10 to 15, as shown in table 241.
10.1.2.3 Built-in overcurrent protection steps
Two overcurrent protection steps are available. They are absolutely identical and
therefore only one will be explained here.
Overcurrent step simply compares the magnitude of the measured current quantity
(see table 240) with the set pickup level. Non-directional overcurrent step will
pickup if the magnitude of the measured current quantity is bigger than this set
level. Reset ratio is settable, with default value of 0.96. However depending on
other enabled built-in features this overcurrent pickup might not cause the
overcurrent step start signal. Start signal will only come if all of the enabled built-
in features in the overcurrent step are fulfilled at the same time.
Second harmonic feature

The overcurrent protection step can be restrained by a second harmonic component
in the measured current quantity (see table 240). However it shall be noted that this
feature is not applicable when one of the following measured currents is selected:
• PosSeq (positive sequence current)

• NegSeq (negative sequence current)
• UnbalancePh (unbalance phase current)
• UnbalancePh-Ph (unbalance ph-ph current)
This feature will simple prevent overcurrent step start if the second-to-first
harmonic ratio in the measured current exceeds the set level.
Directional feature
The overcurrent protection step operation can be can be made dependent on the
relevant phase angle between measured current phasor (see table 240) and
measured voltage phasor (see table 241). In protection terminology it means that
the General currrent and voltage protection (CVGAPC) function can be made
directional by enabling this built-in feature. In that case overcurrent protection step
will only operate if the current flow is in accordance with the set direction
437
(Forward, which means towards the protected object, or Reverse, which means
from the protected object). For this feature it is of the outmost importance to
understand that the measured voltage phasor (see table 241) and measured current
phasor (see table 240) will be used for directional decision. Therefore it is the sole
responsibility of the end user to select the appropriate current and voltage signals in
order to get a proper directional decision. CVGAPC function will NOT do this
automatically. It will just simply use the current and voltage phasors selected by
the end user to check for the directional criteria.
Table 243 gives an overview of the typical choices (but not the only possible ones)
for these two quantities for traditional directional relays.
Table 243: Typical current and voltage choices for directional feature
Set value for the Set value for the
parameter parameter Comment
CurrentInput VoltageInput
PosSeq PosSeq Directional positive sequence overcurrent function is
obtained. Typical setting for RCADir is from -45° to
-90° depending on the power
NegSeq -NegSeq Directional negative sequence overcurrent function is
obtained. Typical setting for RCADir is from -45° to
-90° depending on the power system voltage level (X/
R ratio)
3ZeroSeq -3ZeroSeq Directional zero sequence overcurrent function is
obtained. Typical setting for RCADir is from 0° to
-90° depending on the power system earthing (that
is, solidly earthed, earthed via resistor)
Phase1 Phase2-Phase3 Directional overcurrent function for the first phase is
obtained. Typical setting for RCADir is +30° or +45°
Phase2 Phase3-Phase1 Directional overcurrent function for the second phase
is obtained. Typical setting for RCADir is +30° or +45°
Phase3 Phase1-Phase2 Directional overcurrent function for the third phase is
obtained. Typical setting for RCADir is +30° or +45°
Unbalance current or voltage measurement shall not be used when the directional
feature is enabled.
Two types of directional measurement principles are available, I & U and

IcosPhi&U. The first principle, referred to as "I & U" in the parameter setting tool,
checks that:
• the magnitude of the measured current is bigger than the set pick-up level
• the phasor of the measured current is within the operating region (defined by
the relay operate angle, ROADir parameter setting; see figure 219).
438
U=-3U0
RCADir
Ipickup ROADir I=3Io
Operate region
mta line
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Figure 219: I & U directional operating principle for CVGAPC function
where:
RCADir is -75°
ROADir is 50°
The second principle, referred to as "IcosPhi&U" in the parameter setting tool,

checks that:
• that the product I·cos(Φ) is bigger than the set pick-up level, where Φ is angle
between the current phasor and the mta line
• that the phasor of the measured current is within the operating region (defined
by the I·cos(Φ) straight line and the relay operate angle, ROADir parameter
setting; see figure 219).
439
U=-3U0
RCADir
Ipickup ROADir F I=3Io
Operate region
mta line
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IEC05000253 V1 EN
Figure 220: CVGAPC, IcosPhi&U directional operating principle
where:
RCADir is -75°
ROADir is 50°
Note that it is possible to decide by a parameter setting how the directional feature
shall behave when the magnitude of the measured voltage phasor falls below the pre-
set value. User can select one of the following three options:
• Non-directional (operation allowed for low magnitude of the reference voltage)

• Block (operation prevented for low magnitude of the reference voltage)
• Memory (memory voltage shall be used to determine direction of the current)
It shall also be noted that the memory duration is limited in the algorithm to 100
ms. After that time the current direction will be locked to the one determined
during memory time and it will re-set only if the current fails below set pickup
level or voltage goes above set voltage memory limit.
Voltage restraint/control feature

The overcurrent protection step operation can be can be made dependent of a
measured voltage quantity (see table 241). Practically then the pickup level of the
overcurrent step is not constant but instead decreases with the decrease in the
magnitude of the measured voltage quantity. Two different types of dependencies
are available:
• Voltage restraint overcurrent (when setting parameter VDepMode_OC1=Slope)
440
OC1 Stage Pickup Level
StartCurr_OC1
VDepFact_OC1 * StartCurr_OC1
ULowLimit_OC1 UHighLimit_OC1
Selected Voltage
Magnitude
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IEC05000324 V1 EN
Figure 221: Example for OC1 step current pickup level variation as function of
measured voltage magnitude in Slope mode of operation
• Voltage controlled overcurrent (when setting parameter

VDepMode_OC1=Step)
OC1 Stage Pickup Level
StartCurr_OC1
VDepFact_OC1 * StartCurr_OC1
UHighLimit_OC1 Selected Voltage Magnitude
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IEC05000323 V1 EN
Figure 222: Example for OC1 step current pickup level variation as function of
measured voltage magnitude in Step mode of operation
This feature will simply change the set overcurrent pickup level in accordance with
magnitude variations of the measured voltage. It shall be noted that this feature will
as well affect the pickup current value for calculation of operate times for IDMT
441
curves (overcurrent with IDMT curve will operate faster during low voltage
conditions).
Current restraint feature

The overcurrent protection step operation can be made dependent of a restraining
current quantity (see table 242). Practically then the pickup level of the overcurrent
step is not constant but instead increases with the increase in the magnitude of the
restraining current.
IMeasured
ea ain
ar tr
te es
ra ff *I r
pe e
O Co
es tr
I>R
IsetHigh
IsetLow
atan(RestrCoeff)
Restraint
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IEC05000255 V1 EN
Figure 223: Current pickup variation with restraint current magnitude
This feature will simply prevent overcurrent step to start if the magnitude of the
measured current quantity is smaller than the set percentage of the restrain current
magnitude. However this feature will not affect the pickup current value for
calculation of operate times for IDMT curves. This means that the IDMT curve
operate time will not be influenced by the restrain current magnitude.
When set, the start signal will start definite time delay or inverse (IDMT) time
delay in accordance with the end user setting. If the start signal has value one for
longer time than the set time delay, the overcurrent step will set its trip signal to
one. Reset of the start and trip signal can be instantaneous or time delay in
accordance with the end user setting.
10.1.2.4 Built-in undercurrent protection steps
Two undercurrent protection steps are available. They are absolutely identical and
therefore only one will be explained here. Undercurrent step simply compares the
magnitude of the measured current quantity (see table 240) with the set pickup
level. The undercurrent step will pickup and set its start signal to one if the
magnitude of the measured current quantity is smaller than this set level. The start
signal will start definite time delay with set time delay. If the start signal has value
one for longer time than the set time delay the undercurrent step will set its trip
442
signal to one. Reset of the start and trip signal can be instantaneous or time delay in
accordance with the setting.
10.1.2.5 Built-in overvoltage protection steps
Two overvoltage protection steps are available. They are absolutely identical and
Overvoltage step simply compares the magnitude of the measured voltage quantity
(see table 241) with the set pickup level. The overvoltage step will pickup if the
magnitude of the measured voltage quantity is bigger than this set level. Reset ratio
is settable, with default value of 0.99.
The start signal will start definite time delay or inverse (IDMT) time delay in
accordance with the end user setting. If the start signal has value one for longer
time than the set time delay, the overvoltage step will set its trip signal to one.
Reset of the start and trip signal can be instantaneous or time delay in accordance
with the end user setting.
10.1.2.6 Built-in undervoltage protection steps
Two undervoltage protection steps are available. They are absolutely identical and
Undervoltage step simply compares the magnitude of the measured voltage

quantity (see table 241) with the set pickup level. The undervoltage step will
pickup if the magnitude of the measured voltage quantity is smaller than this set
level. Reset ratio is settable, with default value of 1.01.
The start signal will start definite time delay or inverse (IDMT) time delay in
accordance with the end user setting. If the start signal has value one for longer
time than the set time delay, the undervoltage step will set its trip signal to one.
Reset of the start and trip signal can be instantaneous or time delay in accordance
with the end user setting.
10.1.2.7 Inadvertent generator energizing
The inadvertent energizing function is realized by means of the general current and
voltage protection function (CAGVPC). CVGAPC is configured as shown in
figure 224.
443
CVGAPC
3IP
3UP TROC1
TROV1 S Q
TRUV1 R Q
BLKOC1
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IEC08000288 V1 EN
Figure 224: Configuration of the inadvertent energizing function
The setting of the general current and voltage function (typical values) is done as
shown in table 244.
Table 244: The setting of the general current and voltage function
Measured Quantity Pickup in % of generator Time delay in seconds
rating
Undervoltage U< Maximum generator < 70% 10.0 s
Phase to Phase
voltage
Overvoltage U> Maximum generator > 85% 1.0 s
Phase to Phase
voltage
Overcurrent I> Maximum generator > 50% 0.05 s
Phase current
In normal operation the overvoltage trip signal is activated and the undervotage trip
signal is deactivated. This means that the overcurrent function is blocked.
When the generator is taken out of service the generator voltage gets low. The
overvoltage trip signal will be deactivated and the undervoltage trip signal will be
444
activated after the set delay. At this moment the block signal to the overcurrent
function will be deactivated.
It the generator is energized at stand still conditions, that is, when the voltage is
zero, the overcurrent function will operate after the short set delay if the generator
current is larger than the set value.
When the generator is started the overvoltage trip signal will be activated the set
time delay after the moment when the voltage has reached the set value. At this
moment the blocking of the overcurrent function is activated.
The delay of the undervoltage function will prevent false operation at short circuits
in the external power grid.
The simplified internal logics, for CVGAPC function are shown in the following
figures.
IED
ADM CVGAPC function
Current and voltage selection

settings
Phasor calculation of
scaling with CT ratio
individual currents
A/D conversion
Selection of which current Selected current

and voltage shall be given to
Phasors &
samples
the built-in protection Selected voltage

elements
Restraint current selection
Selected restraint current

A/D conversion scaling
Selection of restraint current

Phasor calculation of
individual voltages
with CT ratio
Phasors &
samples
IEC05000169 V2 EN
Figure 225: Treatment of measured currents within IED for CVGAPC function
Figure 225 shows how internal treatment of measured currents is done for
multipurpose protection function
445
The following currents and voltages are inputs to the multipurpose protection
function. They must all be expressed in true power system (primary) Amperes and
kilovolts.
1. Instantaneous values (samples) of currents & voltages from one three-phase

current and one three-phase voltage input.
2. Fundamental frequency phasors from one three-phase current and one three-
phase voltage input calculated by the pre-processing modules.
3. Sequence currents & voltages from one three-phase current and one three-
phase voltage input calculated by the pre-processing modules.
The multipurpose protection function:
1. Selects one current from the three-phase input system (see table 240) for
internally measured current.
2. Selects one voltage from the three-phase input system (see table 241) for
internally measured voltage.
3. Selects one current from the three-phase input system (see table 242) for
internally measured restraint current.
446
CURRENT
UC1
nd TRUC1
2 Harmonic
Selected current restraint
STUC2
UC2
TRUC2
2nd Harmonic
restraint
STOC1
OC1 TROC1
2nd Harmonic BLK2ND

restraint ³1
Selected restraint current
Current restraint
DIROC1
Directionality
Voltage control /
restraint
STOC2
OC2 TROC2
2nd Harmonic
restraint
Current restraint ³1
UDIRLOW
Directionality DIROC2
Voltage control /
restraint
STOV1
OV1 TROV1
STOV2
OV2 TROV2
STUV1
Selected voltage
UV1 TRUV1
STUV2
UV2 TRUV2
VOLTAGE
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Figure 226: CVGAPC function main logic diagram for built-in protection elements
447
Logic in figure 226 can be summarized as follows:
1. The selected currents and voltage are given to built-in protection elements.
Each protection element and step makes independent decision about status of
its START and TRIP output signals.
2. More detailed internal logic for every protection element is given in the
following four figures
3. Common START and TRIP signals from all built-in protection elements &
steps (internal OR logic) are available from multipurpose function as well.
Enable
second
harmonic Second
harmonic check
1 DEF time BLKTROC
selected DEF 1 TROC1
AND
OR
Selected current a
a>b
b
OC1=On STOC1
AND
StartCurr_OC1 BLKOC1
X
Inverse
Voltage Directionality DIR_OK Inverse

control or time
check selected
restraint
feature
Selected voltage
Current
Restraint
Feature
Selected restrain current Imeasured > k Irestraint
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IEC05000831 V1 EN
Figure 227: Simplified internal logic diagram for built-in first overcurrent step that is, OC1 (step OC2 has the
same internal logic)
448
Bin input: BLKUC1TR
Selected current a TRUC1

b>a
DEF AND
b
StartCurr_UC1
AND
Operation_UC1=On
STUC1
Bin input: BLKUC1
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IEC05000750 V1 EN
Figure 228: Simplified internal logic diagram for built-in first undercurrent step that is, UC1 (step UC2 has
the same internal logic)
DEF time BLKTROV1

selected DEF TROV1
AND
OR
Selected voltage a
a>b
b STOV1
StartVolt_OV1
AND
Inverse
Operation_OV1=On
Inverse time
BLKOV1 selected
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Figure 229: Simplified internal logic diagram for built-in first overvoltage step OV1 (step OV2 has the same
internal logic)
449
DEF time BLKTRUV

selected DEF 1 TRUV1
AND
OR
Selected voltage a
b>a
b STUV1
AND
StartVolt_UV1
Inverse
Operation_UV1=On
Inverse time
BLKUV1 selected
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Figure 230: Simplified internal logic diagram for built-in first undervoltage step UV1 (step UV2 has the same
internal logic)

CVGAPC
I3P* TRIP
U3P* TROC1
BLOCK TROC2
BLKOC1 TRUC1
BLKOC1TR TRUC2
ENMLTOC1 TROV1
BLKOC2 TROV2
BLKOC2TR TRUV1
ENMLTOC2 TRUV2
BLKUC1 START
BLKUC1TR STOC1
BLKUC2 STOC2
BLKUC2TR STUC1
BLKOV1 STUC2
BLKOV1TR STOV1
BLKOV2 STOV2
BLKOV2TR STUV1
BLKUV1 STUV2
BLKUV1TR BLK2ND
BLKUV2 DIROC1
BLKUV2TR DIROC2
UDIRLOW
CURRENT
ICOSFI
VOLTAGE
UIANGLE
IEC05000372 V2 EN
Figure 231: CVGAPC function block
450

Table 245: CVGAPC Input signals
SIGNAL
SIGNAL
BLKOC1 BOOLEAN 0 Block of over current function OC1
BLKOC1TR BOOLEAN 0 Block of trip for over current function OC1
ENMLTOC1 BOOLEAN 0 When activated, the current multiplier is in use for
OC1
BLKOC2 BOOLEAN 0 Block of over current function OC2
BLKOC2TR BOOLEAN 0 Block of trip for over current function OC2
ENMLTOC2 BOOLEAN 0 When activated, the current multiplier is in use for
OC2
BLKUC1 BOOLEAN 0 Block of under current function UC1
BLKUC1TR BOOLEAN 0 Block of trip for under current function UC1
BLKUC2 BOOLEAN 0 Block of under current function UC2
BLKUC2TR BOOLEAN 0 Block of trip for under current function UC2
BLKOV1 BOOLEAN 0 Block of over voltage function OV1
BLKOV1TR BOOLEAN 0 Block of trip for over voltage function OV1
BLKOV2 BOOLEAN 0 Block of over voltage function OV2
BLKOV2TR BOOLEAN 0 Block of trip for over voltage function OV2
BLKUV1 BOOLEAN 0 Block of under voltage function UV1
BLKUV1TR BOOLEAN 0 Block of trip for under voltage function UV1
BLKUV2 BOOLEAN 0 Block of under voltage function UV2
BLKUV2TR BOOLEAN 0 Block of trip for under voltage function UV2
Table 246: CVGAPC Output signals

TRIP BOOLEAN General trip signal
TROC1 BOOLEAN Trip signal from overcurrent function OC1
TROC2 BOOLEAN Trip signal from overcurrent function OC2
TRUC1 BOOLEAN Trip signal from undercurrent function UC1
TRUC2 BOOLEAN Trip signal from undercurrent function UC2
TROV1 BOOLEAN Trip signal from overvoltage function OV1
TROV2 BOOLEAN Trip signal from overvoltage function OV2
TRUV1 BOOLEAN Trip signal from undervoltage function UV1
TRUV2 BOOLEAN Trip signal from undervoltage function UV2
451

STOC1 BOOLEAN Start signal from overcurrent function OC1
STOC2 BOOLEAN Start signal from overcurrent function OC2
STUC1 BOOLEAN Start signal from undercurrent function UC1
STUC2 BOOLEAN Start signal from undercurrent function UC2
STOV1 BOOLEAN Start signal from overvoltage function OV1
STOV2 BOOLEAN Start signal from overvoltage function OV2
STUV1 BOOLEAN Start signal from undervoltage function UV1
STUV2 BOOLEAN Start signal from undervoltage function UV2
BLK2ND BOOLEAN Block from second harmonic detection
DIROC1 INTEGER Directional mode of OC1 (nondir, forward,reverse)
DIROC2 INTEGER Directional mode of OC2 (nondir, forward,reverse)
UDIRLOW BOOLEAN Low voltage for directional polarization
CURRENT REAL Measured current value
ICOSFI REAL Measured current multiplied with cos (Phi)
VOLTAGE REAL Measured voltage value
UIANGLE REAL Angle between voltage and current

Table 247: CVGAPC Group settings (basic)
On
CurrentInput phase1 - - MaxPh Select current signal which will be
phase2 measured inside function
phase3
PosSeq
NegSeq
3*ZeroSeq
MaxPh
MinPh
UnbalancePh
phase1-phase2
phase2-phase3
phase3-phase1
MaxPh-Ph
MinPh-Ph
UnbalancePh-Ph
IBase 1 - 99999 A 1 3000 Base Current
452

VoltageInput phase1 - - MaxPh Select voltage signal which will be
phase2 measured inside function
phase3
PosSeq
-NegSeq
-3*ZeroSeq
MaxPh
MinPh
UnbalancePh
phase1-phase2
phase2-phase3
phase3-phase1
MaxPh-Ph
MinPh-Ph
UnbalancePh-Ph
UBase 0.05 - 2000.00 kV 0.05 400.00 Base Voltage
OperHarmRestr Off - - Off Operation of 2nd harmonic restrain Off /
On On
l_2nd/l_fund 10.0 - 50.0 % 1.0 20.0 Ratio of second to fundamental current
harmonic in %
EnRestrainCurr Off - - Off Enable current restrain function On / Off
On
RestrCurrInput PosSeq - - PosSeq Select current signal which will be used
NegSeq for curr restrain
3*ZeroSeq
Max
RestrCurrCoeff 0.00 - 5.00 - 0.01 0.00 Restraining current coefficient
RCADir -180 - 180 Deg 1 -75 Relay Characteristic Angle
ROADir 1 - 90 Deg 1 75 Relay Operate Angle
LowVolt_VM 0.0 - 5.0 %UB 0.1 0.5 Below this level in % of Ubase setting
ActLowVolt takes over
Operation_OC1 Off - - Off Operation OC1 Off / On
On
StartCurr_OC1 2.0 - 5000.0 %IB 1.0 120.0 Operate current level for OC1 in % of
Ibase
CurveType_OC1 ANSI Ext. inv. - - ANSI Def. Time Selection of time delay curve type for OC1
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Programmable
RI type
RD type
tDef_OC1 0.00 - 6000.00 s 0.01 0.50 Independent (definitive) time delay of
OC1
453

k_OC1 0.05 - 999.00 - 0.01 0.30 Time multiplier for the dependent time
delay for OC1
of IBase
tMin_OC1 0.00 - 6000.00 s 0.01 0.05 Minimum operate time for IEC IDMT
curves for OC1
VCntrlMode_OC1 Voltage control - - Off Control mode for voltage controlled OC1
Input control function
Volt/Input control
Off
VDepMode_OC1 Step - - Step Voltage dependent mode OC1 (step,
Slope slope)
VDepFact_OC1 0.02 - 5.00 - 0.01 1.00 Multiplying factor for I pickup when OC1
is U dependent
ULowLimit_OC1 1.0 - 200.0 %UB 0.1 50.0 Voltage low limit setting OC1 in % of
Ubase
UHighLimit_OC1 1.0 - 200.0 %UB 0.1 100.0 Voltage high limit setting OC1 in % of
Ubase
HarmRestr_OC1 Off - - Off Enable block of OC1 by 2nd harmonic
On restrain
DirMode_OC1 Non-directional - - Non-directional Directional mode of OC1 (nondir,
Forward forward,reverse)
Reverse
DirPrinc_OC1 I&U - - I&U Measuring on IandU or IcosPhiandU for
IcosPhi&U OC1
ActLowVolt1_VM Non-directional - - Non-directional Low voltage level action for Dir_OC1
Block (Nodir, Blk, Mem)
Memory
Operation_OC2 Off - - Off Operation OC2 Off / On
On
StartCurr_OC2 2.0 - 5000.0 %IB 1.0 120.0 Operate current level for OC2 in % of
Ibase
CurveType_OC2 ANSI Ext. inv. - - ANSI Def. Time Selection of time delay curve type for OC2
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Programmable
RI type
RD type
tDef_OC2 0.00 - 6000.00 s 0.01 0.50 Independent (definitive) time delay of
OC2
k_OC2 0.05 - 999.00 - 0.01 0.30 Time multiplier for the dependent time
delay for OC2
454

of IBase
tMin_OC2 0.00 - 6000.00 s 0.01 0.05 Minimum operate time for IEC IDMT
curves for OC2
VCntrlMode_OC2 Voltage control - - Off Control mode for voltage controlled OC2
Input control function
Volt/Input control
Off
VDepMode_OC2 Step - - Step Voltage dependent mode OC2 (step,
Slope slope)
VDepFact_OC2 0.02 - 5.00 - 0.01 1.00 Multiplying factor for I pickup when OC2
is U dependent
ULowLimit_OC2 1.0 - 200.0 %UB 0.1 50.0 Voltage low limit setting OC2 in % of
Ubase
UHighLimit_OC2 1.0 - 200.0 %UB 0.1 100.0 Voltage high limit setting OC2 in % of
Ubase
HarmRestr_OC2 Off - - Off Enable block of OC2 by 2nd harmonic
On restrain
DirMode_OC2 Non-directional - - Non-directional Directional mode of OC2 (nondir,
Forward forward,reverse)
Reverse
DirPrinc_OC2 I&U - - I&U Measuring on IandU or IcosPhiandU for
IcosPhi&U OC2
ActLowVolt2_VM Non-directional - - Non-directional Low voltage level action for Dir_OC2
Block (Nodir, Blk, Mem)
Memory
Operation_UC1 Off - - Off Operation UC1 Off / On
On
EnBlkLowI_UC1 Off - - Off Enable internal low current level blocking
On for UC1
BlkLowCurr_UC1 0 - 150 %IB 1 20 Internal low current blocking level for
UC1 in % of Ibase
StartCurr_UC1 2.0 - 150.0 %IB 1.0 70.0 Operate undercurrent level for UC1 in %
of Ibase
tDef_UC1 0.00 - 6000.00 s 0.01 0.50 Independent (definitive) time delay of UC1
tResetDef_UC1 0.00 - 6000.00 s 0.01 0.00 Reset time delay used in IEC Definite
Time curve UC1
HarmRestr_UC1 Off - - Off Enable block of UC1 by 2nd harmonic
On restrain
Operation_UC2 Off - - Off Operation UC2 Off / On
On
EnBlkLowI_UC2 Off - - Off Enable internal low current level blocking
On for UC2
BlkLowCurr_UC2 0 - 150 %IB 1 20 Internal low current blocking level for
UC2 in % of Ibase
StartCurr_UC2 2.0 - 150.0 %IB 1.0 70.0 Operate undercurrent level for UC2 in %
of Ibase
tDef_UC2 0.00 - 6000.00 s 0.01 0.50 Independent (definitive) time delay of UC2
HarmRestr_UC2 Off - - Off Enable block of UC2 by 2nd harmonic
On restrain
455

Operation_OV1 Off - - Off Operation OV1 Off / On
On
StartVolt_OV1 2.0 - 200.0 %UB 0.1 150.0 Operate voltage level for OV1 in % of
Ubase
CurveType_OV1 Definite time - - Definite time Selection of time delay curve type for OV1
Inverse curve A
Inverse curve B
Inverse curve C
Prog. inv. curve
tDef_OV1 0.00 - 6000.00 s 0.01 1.00 Operate time delay in sec for definite
time use of OV1
tMin_OV1 0.00 - 6000.00 s 0.01 0.05 Minimum operate time for IDMT curves
for OV1
k_OV1 0.05 - 999.00 - 0.01 0.30 Time multiplier for the dependent time
delay for OV1
Operation_OV2 Off - - Off Operation OV2 Off / On
On
StartVolt_OV2 2.0 - 200.0 %UB 0.1 150.0 Operate voltage level for OV2 in % of
Ubase
CurveType_OV2 Definite time - - Definite time Selection of time delay curve type for OV2
Inverse curve A
Inverse curve B
Inverse curve C
Prog. inv. curve
tDef_OV2 0.00 - 6000.00 s 0.01 1.00 Operate time delay in sec for definite
time use of OV2
tMin_OV2 0.00 - 6000.00 s 0.01 0.05 Minimum operate time for IDMT curves
for OV2
k_OV2 0.05 - 999.00 - 0.01 0.30 Time multiplier for the dependent time
delay for OV2
Operation_UV1 Off - - Off Operation UV1 Off / On
On
StartVolt_UV1 2.0 - 150.0 %UB 0.1 50.0 Operate undervoltage level for UV1 in %
of Ubase
CurveType_UV1 Definite time - - Definite time Selection of time delay curve type for UV1
Inverse curve A
Inverse curve B
Prog. inv. curve
tDef_UV1 0.00 - 6000.00 s 0.01 1.00 Operate time delay in sec for definite
time use of UV1
tMin_UV1 0.00 - 6000.00 s 0.01 0.05 Minimum operate time for IDMT curves
for UV1
k_UV1 0.05 - 999.00 - 0.01 0.30 Time multiplier for the dependent time
delay for UV1
EnBlkLowV_UV1 Off - - On Enable internal low voltage level
On blocking for UV1
BlkLowVolt_UV1 0.0 - 5.0 %UB 0.1 0.5 Internal low voltage blocking level for
UV1 in % of Ubase
Operation_UV2 Off - - Off Operation UV2 Off / On
On
456

StartVolt_UV2 2.0 - 150.0 %UB 0.1 50.0 Operate undervoltage level for UV2 in %
of Ubase
CurveType_UV2 Definite time - - Definite time Selection of time delay curve type for UV2
Inverse curve A
Inverse curve B
Prog. inv. curve
tDef_UV2 0.00 - 6000.00 s 0.01 1.00 Operate time delay in sec for definite
time use of UV2
tMin_UV2 0.00 - 6000.00 s 0.01 0.05 Minimum operate time for IDMT curves
for UV2
k_UV2 0.05 - 999.00 - 0.01 0.30 Time multiplier for the dependent time
delay for UV2
EnBlkLowV_UV2 Off - - On Enable internal low voltage level
On blocking for UV2
BlkLowVolt_UV2 0.0 - 5.0 %UB 0.1 0.5 Internal low voltage blocking level for
UV2 in % of Ubase
Table 248: CVGAPC Group settings (advanced)

CurrMult_OC1 1.0 - 10.0 - 0.1 2.0 Multiplier for scaling the current setting
value for OC1
ResCrvType_OC1 Instantaneous - - Instantaneous Selection of reset curve type for OC1
IEC Reset
ANSI reset
tResetDef_OC1 0.00 - 6000.00 s 0.01 0.00 Reset time delay used in IEC Definite
Time curve OC1
P_OC1 0.001 - 10.000 - 0.001 0.020 Parameter P for customer programmable
curve for OC1
A_OC1 0.000 - 999.000 - 0.001 0.140 Parameter A for customer programmable
curve for OC1
B_OC1 0.000 - 99.000 - 0.001 0.000 Parameter B for customer programmable
curve for OC1
C_OC1 0.000 - 1.000 - 0.001 1.000 Parameter C for customer
programmable curve for OC1
PR_OC1 0.005 - 3.000 - 0.001 0.500 Parameter PR for customer
TR_OC1 0.005 - 600.000 - 0.001 13.500 Parameter TR for customer
CR_OC1 0.1 - 10.0 - 0.1 1.0 Parameter CR for customer
CurrMult_OC2 1.0 - 10.0 - 0.1 2.0 Multiplier for scaling the current setting
value for OC2
ResCrvType_OC2 Instantaneous - - Instantaneous Selection of reset curve type for OC2
IEC Reset
ANSI reset
tResetDef_OC2 0.00 - 6000.00 s 0.01 0.00 Reset time delay used in IEC Definite
Time curve OC2
P_OC2 0.001 - 10.000 - 0.001 0.020 Parameter P for customer programmable
curve for OC2
457

A_OC2 0.000 - 999.000 - 0.001 0.140 Parameter A for customer programmable
curve for OC2
B_OC2 0.000 - 99.000 - 0.001 0.000 Parameter B for customer programmable
curve for OC2
C_OC2 0.000 - 1.000 - 0.001 1.000 Parameter C for customer
PR_OC2 0.005 - 3.000 - 0.001 0.500 Parameter PR for customer
TR_OC2 0.005 - 600.000 - 0.001 13.500 Parameter TR for customer
CR_OC2 0.1 - 10.0 - 0.1 1.0 Parameter CR for customer
tResetDef_UC2 0.00 - 6000.00 s 0.01 0.00 Reset time delay used in IEC Definite
Time curve UC2
ResCrvType_OV1 Instantaneous - - Instantaneous Selection of reset curve type for OV1
Frozen timer
Linearly decreased
tResetDef_OV1 0.00 - 6000.00 s 0.01 0.00 Reset time delay in sec for definite time
use of OV1
tResetIDMT_OV1 0.00 - 6000.00 s 0.01 0.00 Reset time delay in sec for IDMT curves
for OV1
A_OV1 0.005 - 999.000 - 0.001 0.140 Parameter A for customer programmable
curve for OV1
B_OV1 0.500 - 99.000 - 0.001 1.000 Parameter B for customer programmable
curve for OV1
C_OV1 0.000 - 1.000 - 0.001 1.000 Parameter C for customer
programmable curve for OV1
D_OV1 0.000 - 10.000 - 0.001 0.000 Parameter D for customer
P_OV1 0.001 - 10.000 - 0.001 0.020 Parameter P for customer programmable
curve for OV1
ResCrvType_OV2 Instantaneous - - Instantaneous Selection of reset curve type for OV2
Frozen timer
Linearly decreased
tResetDef_OV2 0.00 - 6000.00 s 0.01 0.00 Reset time delay in sec for definite time
use of OV2
tResetIDMT_OV2 0.00 - 6000.00 s 0.01 0.00 Reset time delay in sec for IDMT curves
for OV2
A_OV2 0.005 - 999.000 - 0.001 0.140 Parameter A for customer programmable
curve for OV2
B_OV2 0.500 - 99.000 - 0.001 1.000 Parameter B for customer programmable
curve for OV2
C_OV2 0.000 - 1.000 - 0.001 1.000 Parameter C for customer
D_OV2 0.000 - 10.000 - 0.001 0.000 Parameter D for customer
P_OV2 0.001 - 10.000 - 0.001 0.020 Parameter P for customer programmable
curve for OV2
458

ResCrvType_UV1 Instantaneous - - Instantaneous Selection of reset curve type for UV1
Frozen timer
Linearly decreased
tResetDef_UV1 0.00 - 6000.00 s 0.01 0.00 Reset time delay in sec for definite time
use of UV1
tResetIDMT_UV1 0.00 - 6000.00 s 0.01 0.00 Reset time delay in sec for IDMT curves
for UV1
A_UV1 0.005 - 999.000 - 0.001 0.140 Parameter A for customer programmable
curve for UV1
B_UV1 0.500 - 99.000 - 0.001 1.000 Parameter B for customer programmable
curve for UV1
C_UV1 0.000 - 1.000 - 0.001 1.000 Parameter C for customer
programmable curve for UV1
D_UV1 0.000 - 10.000 - 0.001 0.000 Parameter D for customer
P_UV1 0.001 - 10.000 - 0.001 0.020 Parameter P for customer programmable
curve for UV1
ResCrvType_UV2 Instantaneous - - Instantaneous Selection of reset curve type for UV2
Frozen timer
Linearly decreased
tResetDef_UV2 0.00 - 6000.00 s 0.01 0.00 Reset time delay in sec for definite time
use of UV2
tResetIDMT_UV2 0.00 - 6000.00 s 0.01 0.00 Reset time delay in sec for IDMT curves
for UV2
A_UV2 0.005 - 999.000 - 0.001 0.140 Parameter A for customer programmable
curve for UV2
B_UV2 0.500 - 99.000 - 0.001 1.000 Parameter B for customer programmable
curve for UV2
C_UV2 0.000 - 1.000 - 0.001 1.000 Parameter C for customer
D_UV2 0.000 - 10.000 - 0.001 0.000 Parameter D for customer
P_UV2 0.001 - 10.000 - 0.001 0.020 Parameter P for customer programmable
curve for UV2
459

Table 249: CVGAPC technical data
Measuring current phase1, phase2, phase3, PosSeq, -
input NegSeq, 3*ZeroSeq, MaxPh, MinPh,
UnbalancePh, phase1-phase2, phase2-
phase3, phase3-phase1, MaxPh-Ph,
MinPh-Ph, UnbalancePh-Ph
Base current (1 - 99999) A -
Measuring voltage phase1, phase2, phase3, PosSeq, - -
input NegSeq, -3*ZeroSeq, MaxPh, MinPh,
UnbalancePh, phase1-phase2, phase2-
phase3, phase3-phase1, MaxPh-Ph,
MinPh-Ph, UnbalancePh-Ph
Base voltage (0.05 - 2000.00) kV -
Start overcurrent, (2 - 5000)% of IBase ± 1.0% of Ir for I<Ir
step 1 and 2 ± 1.0% of I for I>Ir
Start undercurrent, (2 - 150)% of IBase ± 1.0% of Ir for I<Ir

step 1 and 2 ± 1.0% of I for I>Ir
Definite time delay (0.00 - 6000.00) s ± 0.5% ± 10 ms

Operate time start 25 ms typically at 0 to 2 x Iset -
overcurrent
Reset time start 25 ms typically at 2 to 0 x Iset -
overcurrent
Operate time start 25 ms typically at 2 to 0 x Iset -
undercurrent
Reset time start 25 ms typically at 0 to 2 x Iset -
undercurrent
See table 582 and Parameter ranges for customer defined See table 582 and table 583
table 583 characteristic no 17:
k: 0.05 - 999.00
A: 0.0000 - 999.0000
B: 0.0000 - 99.0000
C: 0.0000 - 1.0000
P: 0.0001 - 10.0000
PR: 0.005 - 3.000
TR: 0.005 - 600.000
CR: 0.1 - 10.0
Voltage level where (0.0 - 5.0)% of UBase ± 0.5% of Ur
voltage memory
takes over
Start overvoltage, (2.0 - 200.0)% of UBase ± 0.5% of Ur for U<Ur
step 1 and 2 ± 0.5% of U for U>Ur
Start undervoltage, (2.0 - 150.0)% of UBase ± 0.5% of Ur for U<Ur

step 1 and 2 ± 0.5% of U for U>Ur

overvoltage
overvoltage
Operate time start 25 ms typically 2 to 0 x Uset -
undervoltage
460

Reset time start 25 ms typically at 0 to 2 x Uset -
undervoltage
High and low voltage (1.0 - 200.0)% of UBase ± 1.0% of Ur for U<Ur
limit, voltage ± 1.0% of U for U>Ur
dependent operation
Directional function Settable: NonDir, forward and reverse -
Relay characteristic (-180 to +180) degrees ± 2.0 degrees
angle
Relay operate angle (1 to 90) degrees ± 2.0 degrees
Reset ratio, > 95% -
overcurrent
Reset ratio, < 105% -
undercurrent
Reset ratio, > 95% -
overvoltage
Reset ratio, < 105% -
undervoltage
Overcurrent:

Undercurrent:

Overvoltage:

Undervoltage:
10.2 Rotor earth fault protection
10.2.1 Introduction
The field winding, including the rotor winding and the non-rotating excitation
equipment, is always insulated from the metallic parts of the rotor. The insulation
resistance is high if the rotor is cooled by air or by hydrogen. The insulation
resistance is much lower if the rotor winding is cooled by water. This is true even if
the insulation is intact. A fault in the insulation of the field circuit will result in a
conducting path from the field winding to earth. This means that the fault has
caused a field earth fault.
461
The field circuit of a synchronous generator is normally unearthed. Therefore, a

single earth fault on the field winding will cause only a very small fault current.
Thus the earth fault does not produce any damage in the generator. Furthermore, it
will not affect the operation of a generating unit in any way. However, the
existence of a single earth fault increases the electric stress at other points in the
field circuit. This means that the risk for a second earth fault at another point on the
field winding has increased considerably. A second earth fault will cause a field short-
circuit with severe consequences.
The rotor earth fault protection is based on injection of an AC voltage to the

isolated field circuit. In non-faulted conditions there will be no current flow
associated to this injected voltage. If a rotor earth fault occurs, this condition will
be detected by the rotor earth fault protection. Depending on the generator owner
philosophy this operational state will be alarmed and/or the generator will be
tripped. An injection unit is required for rotor earth fault protection (RXTTE4) and
a protective resistor on plate for correct operation.
Rotor earth fault protection can be integrated in the IED among all
other protection functions typically required for generator
protection. How this is achieved by using COMBIFLEX injection
unit RXTTE4 is described in Instruction 1MRG001910.
10.2.2.1 Rotor earth fault
The protection function uses injection of an ac voltage to the generator field circuit.
The COMBIFLEX voltage injection unit RXTTE4, Part No 1MRK 002 108-AB
contains a voltage transformer with a primary winding for connection to 120 or 230
V, 50 or 60 Hz supply voltage. From the secondary winding of this internal voltage
transformer approximately 40 V AC is injected via series capacitors and resistors
into the rotor circuit. The injected voltage and current are fed to one voltage input
and one current input on the IED.
1A rated current input into REG670 must be used for this function.
The current caused by the injection is fed to a current input on the IED via injection
unit RXTTE4, as shown in figure 232.
462
Generator rotor winding
Connection to be done by
the panel builder / field
contractor Optional
external resistor
RXTTE 4
REG 670 221 222
421
I
428
313
230 V AC
314
120 V AC
315
324 0
U 325
321
en07000185.vsd
IEC07000185 V1 EN
Figure 232: Connection of rotor earth fault protection
By using a two stage directional current measurement in the General current and
voltage protection (CVGAPC), as shown in figure 233, the earth fault current on
the DC side of the excitation is detected. The protection operates when the resistive
component of the measured injected current exceeds the pre-set operate level.
Stage one provides an alarm signal and stage two trips the generator after a short
time delay for fully developed rotor earth faults.
463
Operating Region
IINJECTED
UINJECTED
en06000447.vsd
IEC06000447 V1 EN
Figure 233: Two stage directional current measurement in the general

application multipurpose function
The sensitivity of the rotor earth fault protection is dependent of the rotor winding
capacitance to earth and the set pick-up current level of the General current and
voltage protection (CVGAPC). The sensitivity is shown in figure 234.
464
REG 670 : 50 Hz : Raxle=0
10 0
10
ko hm
0 ,1
0 1 2 3 4 5
uF
3 0 mA 4 0 mA 50 mA 70 mA 10 0 mA 150 mA 2 0 0 mA 3 0 0 mA
en06000445.vsd
IEC06000445 V1 EN
Figure 234: Sensitivity dependence of winding capacitance at different current settings
The undervoltage stage of the General current and voltage protection (CVGAPC)
can be used to monitor the injection voltage and give alarm if the injection voltage
is absent. It shall be set to 80% of the rated value of the rated value of the injected
voltage with a time delay of about 10 s.
An additional instance of the General current and voltage protection (CVGAPC)

can be used to provide a third non-directional overcurrent stage which can be used
to detect earth faults on the AC side of the rectifier in case of a static excitation
system. It shall be set to operate when the magnitude of the injected current into the
rotor circuit exceeds 125 mA and with a delay of 5 s. As the CT in RXTTE4 has a
ratio 10:1 the current measured by the IED will be at least 1.25 A for this fault.

Table 250: Rotor earth fault protection based on General current and voltage protection
(CVGAPC) and RXTTE4
For machines with:
• rated field voltage up to 350 V DC -
• static exciter with rated 700 V 50/60 Hz -

supply voltage up to
465

Supply voltage 120 or 230 V 50/60 Hz -
Operate earth fault resistance Approx. 1–20 kΩ -
value
Influence of harmonics in the Negligible influence of 50 V, 150 -
DC field voltage Hz or 50 V, 300 Hz
Permitted leakage capacitance (1–5) μF
Permitted shaft earthing Maximum 200 Ω -
resistance
Protective resistor 220 Ω, 100 W, plate 135 x 160 -
mm
466
Secondary system supervision
Section 11 Secondary system supervision
About this chapter

This chapter describes functions like Current circuit supervision and Fuse failure
supervision. The way the functions work, their setting parameters, function blocks,
input and output signals and technical data are included for each function.
11.1 Current circuit supervision CCSRDIF

Current circuit supervision CCSRDIF - 87
11.1.1 Introduction
Open or short circuited current transformer cores can cause unwanted operation of
many protection functions such as differential, earth-fault current and negative-
sequence current functions.
It must be remembered that a blocking of protection functions at an occurrence of

open CT circuit will mean that the situation will remain and extremely high
voltages will stress the secondary circuit.
Current circuit supervision (CCSRDIF) compares the residual current from a three
phase set of current transformer cores with the neutral point current on a separate
input taken from another set of cores on the current transformer.
A detection of a difference indicates a fault in the circuit and is used as alarm or to

block protection functions expected to give unwanted tripping.

Current circuit supervision CCSRDIF compares the absolute value of the vectorial
sum of the three phase currents |ΣIphase| and the numerical value of the residual
current |Iref| from another current transformer set, see figure 235.
The FAIL output will be set to a logical one when the following criteria are fulfilled:
467
• The numerical value of the difference |ΣIphase| – |Iref| is higher than 80% of
the numerical value of the sum |ΣIphase| + |Iref|.
• The numerical value of the current |ΣIphase| – |Iref| is equal to or higher than
the set operate value IMinOp.
• No phase current has exceeded Ip>Block during the last 10 ms.
• CCSRDIF is enabled by setting Operation = On.
The FAIL output remains activated 100 ms after the AND-gate resets when being
activated for more than 20 ms. If the FAIL lasts for more than 150 ms an ALARM
will be issued. In this case the FAIL and ALARM will remain activated 1 s after
the AND-gate resets. This prevents unwanted resetting of the blocking function
when phase current supervision element(s) operate, for example, during a fault.
IEC05000463 V1 EN
Figure 235: Simplified logic diagram for Current circuit supervision CCSRDIF
The operate characteristic is percentage restrained, see figure 236.
468
| åI phase | - | I ref |
Slope = 1
Operation
Slope = 0.8
area
I MinOp
| åI phase | + | I ref |
99000068.vsd
IEC99000068 V1 EN
Figure 236: Operate characteristics
Due to the formulas for the axis compared, |SIphase | - |I ref | and |S
I phase | + | I ref | respectively, the slope can not be above 2.

CCSRDIF
I3P* FAIL
IREF* ALARM
BLOCK
IEC05000389 V2 EN
Figure 237: CCSRDIF function block

Table 251: CCSRDIF Input signals
I3P GROUP - Group signal for three phase current input
SIGNAL
IREF GROUP - TBD
SIGNAL
469
Table 252: CCSRDIF Output signals

FAIL BOOLEAN Detection of current circuit failure
ALARM BOOLEAN Alarm for current circuit failure

Table 253: CCSRDIF Group settings (basic)
On
IBase 1 - 99999 A 1 3000 IBase value for current level detectors
IMinOp 5 - 200 %IB 1 20 Minimum operate current differential
level in % of IBase
Table 254: CCSRDIF Group settings (advanced)

Ip>Block 5 - 500 %IB 1 150 Block of the function at high phase
current, in % of IBase

Table 255: CCSRDIF technical data
Operate current (5-200)% of Ir ± 10.0% of Ir at I £ Ir
± 10.0% of I at I > Ir
Block current (5-500)% of Ir ± 5.0% of Ir at I £ Ir

± 5.0% of I at I > Ir
11.2 Fuse failure supervision SDDRFUF

Fuse failure supervision SDDRFUF - -
11.2.1 Introduction
The aim of the fuse failure supervision function (SDDRFUF) is to block voltage
measuring functions at failures in the secondary circuits between the voltage
470
transformer and the IED in order to avoid unwanted operations that otherwise
might occur.
The fuse failure supervision function basically has three different algorithms,
negative sequence and zero sequence based algorithms and an additional delta
voltage and delta current algorithm.
The negative sequence detection algorithm is recommended for IEDs used in

isolated or high-impedance earthed networks. It is based on the negative-sequence
measuring quantities, a high value of voltage 3U2 without the presence of the
negative-sequence current 3I2.
The zero sequence detection algorithm is recommended for IEDs used in directly
or low impedance earthed networks. It is based on the zero sequence measuring
quantities, a high value of voltage 3U0 without the presence of the residual current
3I0.
For better adaptation to system requirements, an operation mode setting has been
introduced which makes it possible to select the operating conditions for negative
sequence and zero sequence based function. The selection of different operation
modes makes it possible to choose different interaction possibilities between the
negative sequence and zero sequence based algorithm.
A criterion based on delta current and delta voltage measurements can be added to
the fuse failure supervision function in order to detect a three phase fuse failure,
which in practice is more associated with voltage transformer switching during
station operations.
11.2.2.1 Zero and negative sequence detection
The zero and negative sequence function continuously measures the currents and
voltages in all three phases and calculates, see figure 238:
• the zero-sequence voltage 3U0

• the zero-sequence current 3I0
• the negative sequence current 3I2
• the negative sequence voltage 3U2
The measured signals are compared with their respective set values 3U0< and
3I0>, 3U2< and 3I2>.
The function enable the internal signal FuseFailDetZeroSeq if the measured zero-
sequence voltage is higher than the set value 3U0> and the measured zero-
sequence current is below the set value 3I0<.
471
The function enable the internal signal FuseFailDetNegSeq if the measured

negative sequence voltage is higher than the set value 3U2> and the measured
negative sequence current is below the set value 3I2<.
A drop off delay of 100 ms for the measured zero-sequence and negative sequence
current will prevent a false fuse failure detection at un-equal breaker opening at the
two line ends.
Sequence Detection
3I0< CurrZeroSeq
IL1
Zero 3I0
sequence
filter 100 ms CurrNegSeq
a
IL2 a>b t
b
Negative 3I2
sequence
IL3 filter FuseFailDetZeroSeq
AND
100 ms
a
a>b t
3I2
VoltZeroSeq
UL1
Zero
sequence a 3U0
a>b
b
filter
UL2 VoltNegSeq
Negative
sequence a 3U2
a>b
UL3 filter b
3U2>
IEC10000036 V1 EN
Figure 238: Simplified logic diagram for sequence detection part
The calculated values 3U0, 3I0, 3I2 and 3U2 are available as service values on local
HMI and monitoring tool in PCM600.
Input and output signals

The output signals 3PH, BLKU and BLKZ can be blocked in the following conditions:
• The input BLOCK is activated

• The input BLKTRIP is activated at the same time as the internal signal
fufailStarted is not present
• The operation mode selector OpMode is set to Off.
• The IED is in TEST status (TEST-ACTIVE is high) and the function has been
blocked from the HMI (BlockFUSE=Yes)
The input BLOCK signal is a general purpose blocking signal of the fuse failure
supervision function. It can be connected to a binary input of the IED in order to
receive a block command from external devices or can be software connected to
other internal functions of the IED itself in order to receive a block command from
472
internal functions. Through OR gate it can be connected to both binary inputs and
internal function outputs.
The input BLKSP is intended to be connected to the trip output at any of the
protection functions included in the IED. When activated for more than 20 ms, the
operation of the fuse failure is blocked during a fixed time of 100 ms. The aim is to
increase the security against unwanted operations during the opening of the
breaker, which might cause unbalance conditions for which the fuse failure might
operate.
The output signal BLKZ will also be blocked if the internal dead line detection is
activated. The block signal has a 200 ms drop-out time delay.
The input signal MCBOP is supposed to be connected via a terminal binary input
to the N.C. auxiliary contact of the miniature circuit breaker protecting the VT
secondary circuit. The MCBOP signal sets the output signals BLKU and BLKZ in
order to block all the voltage related functions when the MCB is open independent
of the setting of OpMode selector. The additional drop-out timer of 150 ms
prolongs the presence of MCBOP signal to prevent the unwanted operation of
voltage dependent function due to non simultaneous closing of the main contacts of
the miniature circuit breaker.
The input signal DISCPOS is supposed to be connected via a terminal binary input
to the N.C. auxiliary contact of the line disconnector. The DISCPOS signal sets the
output signal BLKU in order to block the voltage related functions when the line
disconnector is open. The impedance protection function is not affected by the
position of the line disconnector since there will be no line currents that can cause
malfunction of the distance protection. If DISCPOS=0 it signifies that the line is
connected to the system and when the DISCPOS=1 it signifies that the line is
disconnected from the system and the block signal BLKU is generated.
The output BLKU can be used for blocking the voltage related measuring functions
(undervoltage protection, synchro-check and so on) except for the impedance
protection.
The function output BLKZ shall be used for blocking the impedance protection
function.
473
Fuse failure detection

Main logic
TEST
TEST ACTIVE
AND
BlocFuse = Yes
BLOCK intBlock
OR
BLKTRIP 20 ms 100 ms
AND t t
All UL < USealIn<

OR
AND
3PH
AND
SealIn = On AND
AND
Any UL < UsealIn<
FuseFailDetDUDI
AND 5s
OpDUDI = On
OR t
FuseFailDetZeroSeq
AND
AND
FuseFailDetNegSeq
AND
UNsINs OR
UZsIZs OR
UZsIZs OR UNsINs
OpMode
UZsIZs AND UNsINs
OptimZsNs
OR
CurrZeroSeq
a AND
CurrNegSeq a>b
b
AND
200 ms
DeadLineDet1Ph AND BLKZ
t OR AND
150 ms
MCBOP t
AND BLKU
60 sec
t OR OR
All UL > UsealIn<
AND
VoltZeroSeq 5 sec
VoltNegSeq OR t
AllCurrLow
CBCLOSED
DISCPOS
IEC10000033 V1 EN
Figure 239: Simplified logic diagram for main logic of Fuse failure function
474
11.2.2.2 Delta current and delta voltage detection
A simplified diagram for the functionality is found in figure 240. The calculation of
the change is based on vector change which means that it detects both amplitude
and phase angle changes. The calculated delta quantities are compared with their
respective set values DI< and DU> and the algorithm, detects a fuse failure if a
sufficient change in voltage without a sufficient change in current is detected in
each phase separately. The following quantities are calculated in all three phases:
• The change in voltage DU

• The change in current DI
The internal FuseFailDetDUDI signal is activated if the following conditions are

fulfilled for a phase:
• The magnitude of the phase-ground voltage has been above UPh> for more
than 1.5 cycle
• The magnitude of DU is higher than the corresponding setting DU>
• The magnitude of DI is below the setting DI>
and at least one of the following conditions are fulfilled:
• The magnitude of the phase current in the same phase is higher than the setting
IPh>
• The circuit breaker is closed (CBCLOSED = True)
The first criterion means that detection of failure in one phase together with high
current for the same phase will set the output. The measured phase current is used
to reduce the risk of false fuse failure detection. If the current on the protected line
is low, a voltage drop in the system (not caused by fuse failure) is not by certain
followed by current change and a false fuse failure might occur
The second criterion requires that the delta condition shall be fulfilled in any phase
at the same time as circuit breaker is closed. Opening circuit breaker at one end and
energizing the line from other end onto a fault could lead to wrong start of the fuse
failure function at the end with the open breaker. If this is considering to be an
important disadvantage, connect the CBCLOSED input to FALSE. In this way
only the first criterion can activate the delta function.
475
DUDI Detection
DUDI detection Phase 1
IL1 One cycle
delay
|DI|
a
a>b
DIb AND
DU> b
20 ms 1.5 cycle
a
a>b t t
UPh> b
IL2 DUDI detection Phase 2

UL2
Same logic as for phase 1
IL3 DUDI detection Phase 3

UL3
Same logic as for phase 1
UL1
a
ab
IPh> b AND
OR AND
CBCLOSED AND OR
UL2
a
ab
b AND
OR AND
AND OR
UL3
a
ab
b AND
OR AND FuseFailDetDUDI
AND OR
OR
IEC10000034 V1 EN
Figure 240: Simplified logic diagram for DU/DI detection part
476
11.2.2.3 Dead line detection
A simplified diagram for the functionality is found in figure 241. A dead phase
condition is indicated if both the voltage and the current in one phase is below their
respective setting values UDLD< and IDLD<. If at least one phase is considered to
be dead the output DLD1PH and the internal signal DeadLineDet1Ph is activated.
If all three phases are considered to be dead the output DLD3PH is activated
Dead Line Detection

IL1
a
a<b AllCurrLow
b
AND
IL2
a
a<b
b
IL3
a
a<b
b
IDLD<
DeadLineDet1Ph
UL1
a AND
a<b
b OR DLD1PH
AND
UL2
a AND
a<b
b
AND DLD3PH
UL3 AND
a AND
a<b
b
UDLD<
intBlock
IEC10000035 V1 EN
Figure 241: Simplified logic diagram for Dead Line detection part
11.2.2.4 Main logic
A simplified diagram for the functionality is found in figure 242. The fuse failure
supervision function (SDDRFUF) can be switched on or off by the setting
parameter Operation to On or Off.
For increased flexibility and adaptation to system requirements an operation mode

selector, OpMode, has been introduced to make it possible to select different
operating modes for the negative and zero sequence based algorithms. The
different operation modes are:
• Off; The negative and zero sequence function is switched off

• UNsINs; Negative sequence is selected
• UZsIZs; Zero sequence is selected
477
• UZsIZs OR UNsINs; Both negative and zero sequence is activated and working
in parallel in an OR-condition
• UZsIZs AND UNsINs; Both negative and zero sequence is activated and
working in series (AND-condition for operation)
• OptimZsNs; Optimum of negative and zero sequence (the function that has the
highest magnitude of measured negative and zero sequence current will be
activated)
The delta function can be activated by setting the parameter OpDUDI to On. When
selected it operates in parallel with the sequence based algorithms.
As soon as any fuse failure situation is detected, signals FuseFailDetZeroSeq,

FuseFailDetNegSeq or FuseFailDetDUDI, and the specific functionality is
released, the function will activate the output signal BLKU. The output signal
BLKZ will be activated as well if not the internal dead phase detection,
DeadLineDet1Ph, is activated at the same time. The output BLKU can be used for
blocking voltage related measuring functions (under voltage protection, synchro-
check, and so on). For blocking of impedance protection functions output BLKZ
shall be used.
If the fuse failure situation is present for more than 5 seconds and the setting
parameter SealIn is set to On it will be sealed in as long as at least one phase
voltages is below the set value USealIn<. This will keep the BLKU and BLKZ
signals activated as long as any phase voltage is below the set value USealIn<. If
all three phase voltages drop below the set value USealIn< and the setting
parameter SealIn is set to On also the output signal 3PH will be activated. The
signals 3PH, BLKU and BLKZ signals will now be active as long as any phase
voltage is below the set value USealIn<.
If SealIn is set to On fuse failure condition is stored in the non volatile memory in
the IED. At start-up (due to auxiliary power interruption or re-start due to
configuration change) the IED checks the stored value in its non volatile memory
and re-establishes the conditions present before the shut down. All phase voltages
must became above USealIn< before fuse failure is de-activated and inhibits the
block of different protection functions.
The output signal BLKU will also be active if all phase voltages have been above
the setting USealIn< for more than 60 seconds, the zero or negative sequence
voltage has been above the set value 3U0> and 3U2> for more than 5 seconds, all
phase currents are below the setting IDLD< (operate level for dead line detection)
and the circuit breaker is closed (input CBCLOSED is activated).
The input signal MCBOP is supposed to be connected via a terminal binary input
to the N.C. auxiliary contact of the miniature circuit breaker protecting the VT
secondary circuit. The MCBOP signal sets the output signals BLKU and BLKZ in
order to block all the voltage related functions when the MCB is open independent
of the setting of OpMode or OpDUDI. An additional drop-out timer of 150 ms
prolongs the presence of MCBOP signal to prevent the unwanted operation of
478
voltage dependent function due to non simultaneous closing of the main contacts of
the miniature circuit breaker.
The input signal DISCPOS is supposed to be connected via a terminal binary input
to the N.C. auxiliary contact of the line disconnector. The DISCPOS signal sets the
output signal BLKU in order to block the voltage related functions when the line
disconnector is open. The impedance protection function does not have to be
affected since there will be no line currents that can cause malfunction of the
distance protection.
The output signals 3PH, BLKU and BLKZ as well as the signals DLD1PH and
DLD3PH from dead line detections are blocked if any of the following conditions
occur:
• The operation mode selector OpMode is set to Off

• The input BLOCK is activated
• The input BLKTRIP is activated at the same time as no fuse failure indication
is present
• The IED is in TEST status (TEST-ACTIVE is high) and the function has been
blocked from the HMI (BlockFUSE=Yes)
The input BLOCK is a general purpose blocking signal of the fuse failure
supervision function. It can be connected to a binary input of the IED in order to
receive a block command from external devices or can be software connected to
other internal functions of the IED. Through OR gate it can be connected to both
binary inputs and internal function outputs.
The input BLKTRIP is intended to be connected to the trip output of any of the
protection functions included in the IED and/or trip from external equipments via
binary inputs. When activated for more than 20 ms without any fuse fail detected,
the operation of the fuse failure is blocked during a fixed time of 100 ms. The aim
is to increase the security against unwanted operations during the opening of the
breaker, which might cause unbalance conditions for which the fuse failure might
operate.
479
Fuse failure detection

Main logic
TEST
TEST ACTIVE
AND
BlocFuse = Yes
BLOCK intBlock
OR
BLKTRIP 20 ms 100 ms
AND t t
All UL < USealIn<

OR
AND
3PH
AND
SealIn = On AND
AND
Any UL < UsealIn<
FuseFailDetDUDI
AND 5s
OpDUDI = On
OR t
FuseFailDetZeroSeq
AND
AND
FuseFailDetNegSeq
AND
UNsINs OR
UZsIZs OR
UZsIZs OR UNsINs
OpMode
UZsIZs AND UNsINs
OptimZsNs
OR
CurrZeroSeq
a AND
CurrNegSeq a>b
b
AND
200 ms
DeadLineDet1Ph AND BLKZ
t OR AND
150 ms
MCBOP t
AND BLKU
60 sec
t OR OR
All UL > UsealIn<
AND
VoltZeroSeq 5 sec
VoltNegSeq OR t
AllCurrLow
CBCLOSED
DISCPOS
IEC10000033 V1 EN
Figure 242: Simplified logic diagram for fuse failure supervision function, Main
logic
480

SDDRFUF
I3P* BLKZ
U3P* BLKU
BLOCK 3PH
CBCLOSED DLD1PH
MCBOP DLD3PH
DISCPOS
BLKTRIP
IEC05000700 V3 EN
Figure 243: SDDRFUF function block

Table 256: SDDRFUF Input signals
I3P GROUP - Current connection
SIGNAL
SIGNAL
CBCLOSED BOOLEAN 0 Active when circuit breaker is closed
MCBOP BOOLEAN 0 Active when external MCB opens protected
voltage circuit
DISCPOS BOOLEAN 0 Active when line disconnector is open
BLKTRIP BOOLEAN 0 Blocks operation of function when active
Table 257: SDDRFUF Output signals

BLKZ BOOLEAN Start of current and voltage controlled function
BLKU BOOLEAN General start of function
3PH BOOLEAN Three-phase start of function
DLD1PH BOOLEAN Dead line condition in at least one phase
DLD3PH BOOLEAN Dead line condition in all three phases

Table 258: SDDRFUF Group settings (basic)
Operation Off - - On Operation Off / On
On
481

OpMode Off - - UZsIZs Operating mode selection
UNsINs
UZsIZs
UZsIZs OR UNsINs
UZsIZs AND
UNsINs
OptimZsNs
3U0> 1 - 100 %UB 1 30 Operate level of residual overvoltage
element in % of UBase
3I0< 1 - 100 %IB 1 10 Operate level of residual undercurrent
element in % of IBase
3U2> 1 - 100 %UB 1 30 Operate level of neg seq overvoltage
element in % of UBase
3I2< 1 - 100 %IB 1 10 Operate level of neg seq undercurrent
element in % of IBase
OpDUDI Off - - Off Operation of change based function Off/
On On
DU> 1 - 100 %UB 1 60 Operate level of change in phase voltage
in % of UBase
DI< 1 - 100 %IB 1 15 Operate level of change in phase current
in % of IBase
UPh> 1 - 100 %UB 1 70 Operate level of phase voltage in % of
UBase
IPh> 1 - 100 %IB 1 10 Operate level of phase current in % of
IBase
SealIn Off - - On Seal in functionality Off/On
On
USealln< 1 - 100 %UB 1 70 Operate level of seal-in phase voltage in
% of UBase
IDLD< 1 - 100 %IB 1 5 Operate level for open phase current
detection in % of IBase
UDLD< 1 - 100 %UB 1 60 Operate level for open phase voltage
detection in % of UBase

Table 259: SDDRFUF technical data
Operate voltage, zero sequence (1-100)% of UBase ± 1.0% of Ur
Operate current, zero sequence (1–100)% of IBase ± 1.0% of Ir
Operate voltage, negative sequence (1–100)% of UBase ± 0.5% of Ur
Operate current, negative sequence (1–100)% of IBase ± 1.0% of Ir
Operate voltage change level (1–100)% of UBase ± 5.0% of Ur
Operate current change level (1–100)% of IBase ± 5.0% of Ir
Operate phase voltage (1-100)% of UBase ± 0.5% of Ur
Operate phase current (1-100)% of IBase ± 1.0% of Ir
482

Operate phase dead line voltage (1-100)% of UBase ± 0.5% of Ur
Operate phase dead line current (1-100)% of IBase ± 1.0% of Ir
Operate time, start function 25 ms typically at 1 to 0 Ubase -

Reset time, start function 35 ms typically at 0 to 1 Ubase -
483
484
Control
Section 12 Control
About this chapter

This chapter describes the control functions. The way the functions work, their
setting parameters, function blocks, input and output signals and technical data are
included for each function.
12.1 Synchrocheck, energizing check, and synchronizing

SESRSYN

Synchrocheck, energizing check, and SESRSYN 25
synchronizing
sc/vc
SYMBOL-M V1 EN
12.1.1 Introduction
The Synchronizing function allows closing of asynchronous networks at the correct
moment including the breaker closing time, which improves the network stability.
Synchrocheck, energizing check, and synchronizing (SESRSYN) function checks

that the voltages on both sides of the circuit breaker are in synchronism, or with at
least one side dead to ensure that closing can be done safely.
SESRSYN function includes a built-in voltage selection scheme for double bus and
1½ breaker or ring busbar arrangements.
Manual closing as well as automatic reclosing can be checked by the function and
can have different settings.
For systems which are running asynchronous a synchronizing function is provided.

The main purpose of the synchronizing function is to provide controlled closing of
circuit breakers when two asynchronous systems are going to be connected. It is
used for slip frequencies that are larger than those for synchrocheck and lower than
a set maximum level for the synchronizing function.
However this function can not be used to automatically synchronize the generator
to the network.
485
Control
12.1.2.1 Basic functionality
The synchrocheck function measures the conditions across the circuit breaker and
compares them to set limits. The output is only given when all measured quantities
are simultaneously within their set limits.
The energizing check function measures the bus and line voltages and compares
them to both high and low threshold detectors. The output is given only when the
actual measured quantities match the set conditions.
The synchronizing function measures the conditions across the circuit breaker, and
also determines the angle change occurring during the closing delay of the circuit
breaker, from the measured slip frequency. The output is given only when all
measured conditions are simultaneously within their set limits. The issue of the
output is timed to give closure at the optimal time including the time for the circuit
breaker and the closing circuit.
For single circuit breaker and 1½ breaker circuit breaker arrangements, the
SESRSYN function blocks have the capability to make the necessary voltage
selection. For single circuit breaker arrangements, selection of the correct voltage
is made using auxiliary contacts of the bus disconnectors. For 1½ breaker circuit
breaker arrangements, correct voltage selection is made using auxiliary contacts of
the bus disconnectors as well as the circuit breakers.
The internal logic for each function block as well as, the input and outputs, and the
setting parameters with default setting and setting ranges is described in this
document. For application related information, please refer to the application manual.
12.1.2.2 Logic diagrams
Logic diagrams
The logic diagrams that follow illustrate the main principles of the synchronizing
function components such as Synchrocheck, Energizing check and Voltage
selection, and are intended to simplify the understanding of the function.
Synchrocheck
The voltage difference, frequency difference and phase angle difference values are
measured in the IED centrally and are available for the synchrocheck function for
evaluation. If the bus voltage is connected as phase-phase and the line voltage as
phase-neutral (or the opposite), this need to be compensated. This is done with a
setting, which scales up the line voltage to a level equal to the bus voltage.
When the function is set to OperationSC = On, the measuring will start.
The function will compare the bus and line voltage values with the set values for
UHighBusSC and UHighLineSC.
486
Control
If both sides are higher than the set values, the measured values are compared with
the set values for acceptable frequency, phase angle and voltage difference:
FreqDiff, PhaseDiff and UDiff. If a compensation factor is set due to the use of
different voltages on the bus and line, the factor is deducted from the line voltage
before the comparison of the phase angle values.
The frequency on both sides of the circuit breaker is also measured. The
frequencies must not deviate from the rated frequency more than +/-5Hz. The
frequency difference between the bus frequency and the line frequency is measured
and may not exceed the set value.
Two sets of settings for frequency difference and phase angle difference are
available and used for the manual closing and autoreclose functions respectively, as
required.
The inputs BLOCK and BLKSC are available for total block of the complete
SESRSYN function and block of the Synchrocheck function respectively. Input
TSTSC will allow testing of the function where the fulfilled conditions are
connected to a separate test output.
The outputs MANSYOK and AUTOSYOK are activated when the actual measured
conditions match the set conditions for the respective output. The output signal can
be delayed independently for MANSYOK and AUTOSYOK conditions.
A number of outputs are available as information about fulfilled checking

conditions. UOKSC shows that the voltages are high, UDIFFSC, FRDIFFA,
FRDIFFM, PHDIFFA, PHDIFFM shows when the voltage difference, frequency
difference and phase angle difference conditions are met.
Output INADVCLS, inadvertent circuit breaker closing, indicate that the circuit
breaker has been closed by some other equipment or function than SESRSYN. The
output is activated, if the voltage condition is fulfilled at the same time the phase
angle difference between bus and line is suddenly changed from being larger than
60 degrees to smaller than 5 degrees.
487
Control
Note! Similar logic for Manual Synchrocheck.
OperationSC = On
AND TSTAUTSY
AND
TSTSC
BLKSC AND
BLOCK OR
AUTOSYOK
AND
0-60 s
AND t
tSCA
UDiffSC 50 ms
AND t
UHighBusSC
UOKSC
AND
UHighLineSC
UDIFFSC
1
FRDIFFA
FreqDiffA 1
PHDIFFA
PhaseDiffA 1
UDIFFME
voltageDifferenceValue
FRDIFFME
frequencyDifferenceValue
PHDIFFME
phaseAngleDifferenceValue
32 ms 100 ms
AND t INADVCLS
PhDiff > 60° AND
PhDiff < 5°
IEC07000114 V3 EN
Figure 244: Simplified logic diagram for the Synchrocheck function
Synchronizing
When the function is set to OperationSynch = On the measuring will be performed.
The function will compare the values for the bus and line voltage with the set
values for UHighBusSynch and UHighLineSynch, which is a supervision that the
voltages are both live. If both sides are higher than the set values the measured
values are compared with the set values for acceptable frequency, rate of change of
frequency, phase angle and voltage difference FreqDiffMax, FreqDiffMin and
UDiffSynch.
Measured frequencies between the settings for the maximum and minimum
frequency will initiate the measuring and the evaluation of the angle change to
allow operation to be sent in the right moment including the set tBreaker time.
488
Control
There is a phase angle release internally to block any incorrect closing pulses. At
operation the SYNOK output will be activated with a pulse tClosePulse and the
function reset. The function will also reset if the synchronizing conditions are not
fulfilled within the set tMaxSynch time. This prevents that the functions are, by
mistake, maintained in operation for a long time, waiting for conditions to be fulfilled.
The inputs BLOCK and BLKSYNCH are available for total block of the complete
function respective of the synchronizing part. TSTSYNCH will allow testing of the
function where the fulfilled conditions are connected to a separate output.
SYN1
OPERATION SYNCH
OFF
ON
TEST MODE
OFF
ON
STARTSYN SYNPROGR
AND
AND
S
BLKSYNCH
OR R
UDiffSynch
50 ms SYNOK
AND
UHighBusSynch AND t
UHighLineSynch OR
FreqDiffMax
AND
TSTSYNOK
FreqDiffMin OR
tClose
FreqRateChange Pulse
AND
fBus&fLine ± 5 Hz tMax
AND
Synch
PhaseDiff < 15 deg SYNFAIL
PhaseDiff=closing angle
IEC06000636 V2 EN
Figure 245: Simplified logic diagram for the synchronizing function
Energizing check
Voltage values are measured in the IED centrally and are available for evaluation
by the Energizing check function.
The function measures voltages on the busbar and the line to verify whether they
are live or dead. This is done by comparing with the set values UHighBusEnerg
and ULowBusEnerg for bus energizing and UHighLineEnerg and ULowLineEnerg
for line energizing.
The frequency on both sides of the circuit breaker is also measured. The
frequencies must not deviate from the rated frequency more than +/-5Hz. The
489
Control
frequency difference between the bus frequency and the line frequency is measured
and shall not exceed a set value.
The Energizing direction can be selected individually for the Manual and the
Automatic functions respectively. When the conditions are met the outputs
AUTOENOK and MANENOK respectively will be activated if the fuse
supervision conditions are fulfilled. The output signal can be delayed
independently for MANENOK and AUTOENOK conditions. The Energizing
direction can also be selected by an integer input AENMODE respective
MENMODE, which for example, can be connected to a Binary to Integer function
block (B16I). Integers supplied shall be 1=off, 2=DLLB, 3=DBLL and 4= Both.
Not connected input with connection of INTZERO output from Fixed Signals
(FIXDSIGN) function block will mean that the setting is done from Parameter
Setting tool. The active position can be read on outputs MODEAEN resp
MODEMEN. The modes are 0=OFF, 1=DLLB, 2=DBLL and 3=Both.
The inputs BLOCK and BLKENERG are available for total block of the complete
SESRSYN function respective block of the Energizing check function.
TSTENERG will allow testing of the function where the fulfilled conditions are
connected to a separate test output.
Voltage selection
The voltage selection module including supervision of included voltage
transformer fuses for the different arrangements is a basic part of the SESRSYN
function and determines the parameters fed to the Synchronizing, Synchrocheck
and Energizing check functions. This includes the selection of the appropriate Line
and Bus voltages and fuse supervision.
The voltage selection type to be used is set with the parameter CBConfig.
If No voltage sel. is set the default voltages used will be ULine1 and UBus1. This
is also the case when external voltage selection is provided. Fuse failure
supervision for the used inputs must also be connected.
The voltage selection function, selected voltages, and fuse conditions are the
Synchronizing, Synchrocheck and Energizing check inputs.
For the disconnector positions it is advisable to use (NO) a and (NC) b type
contacts to supply Disconnector Open and Closed positions but, it is also possible
to use an inverter for one of the positions.
Voltage selection for a single circuit breaker with double busbars

This function uses the binary input from the disconnectors auxiliary contacts
B1QOPEN-B1QCLD for Bus 1, and B2QOPEN-B2QCLD for Bus 2 to select
between bus 1 and bus 2 voltages. If the disconnector connected to bus 1 is closed
and the disconnector connected to bus 2 is opened the bus 1 voltage is used. All
other combinations use the bus 2 voltage. The Outputs B1SEL and B2SEL
respectively indicate the selected Bus voltage.
490
Control
The function checks the fuse-failure signals for bus 1, bus 2 and line voltage
transformers. Inputs UB1OK-UB1FF supervise the fuse for Bus 1 and UB2OK-
UB2FF supervises the fuse for Bus 2. ULNOK and ULNFF supervises the fuse for
the Line voltage transformer. The inputs fail (FF) or healthy (OK) can alternatively
be used dependent on the available signal. If a fuse-failure is detected in the
selected voltage source an output signal USELFAIL is set. This output signal is
true if the selected bus or line voltages have a fuse failure. This output as well as
the function can be blocked with the input signal BLOCK. The function logic
diagram is shown in figure 246.
B1QOPEN
B1SEL
B1QCLD AND
B2QOPEN B2SEL
1
B2QCLD AND
AND invalidSelection
bus1Voltage
busVoltage
bus2Voltage
UB1OK AND
UB1FF OR
OR
AND selectedFuseOK
UB2OK AND
UB2FF OR USELFAIL
AND
ULN1OK
ULN1FF OR
BLOCK
en05000779.vsd
IEC05000779 V1 EN
Figure 246: Logic diagram for the voltage selection function of a single circuit breaker with double busbars
Voltage selection for a 1 1/2 circuit breaker arrangement

Note that with 1½ breaker schemes two Synchrocheck functions must be used in
the IED (three for two IEDs in a complete bay). Below, the scheme for one Bus
breaker and the Tie breakers is described.
This voltage selection function uses the binary inputs from the disconnectors and
circuit breakers auxiliary contacts to select the right voltage for the Synchrocheck
(Synchronism and Energizing check) function. For the bus circuit breaker one side
491
Control
of the circuit breaker is connected to the busbar and the other side is connected
either to line 1, line 2 or the other busbar depending on the arrangement.
Inputs LN1QOPEN-LN1QCLD, B1QOPEN-B1QCLD, B2QOPEN-B2QCLD,

LN2QOPEN-LN2QCLD are inputs for the position of the Line disconnectors
respectively the Bus and Tie breakers. The Outputs LN1SEL, LN2SEL and B2SEL
will give indication of the selected Line voltage as a reference to the fixed Bus 1
voltage.
The fuse supervision is connected to ULNOK-ULNFF, and with alternative

Healthy or Failing fuse signals depending on what is available for each of fuse (MCB).
The tie circuit breaker is connected either to bus 1 or line 1 on one side and the
other side is connected either to bus 2 or line 2. Four different output combinations
are possible, bus to bus, bus to line, line to bus and line to line.
• The line 1 voltage is selected if the line 1 disconnector is closed.

• The bus 1 voltage is selected if the line 1 disconnector is open and the bus 1
circuit breaker is closed.
• The line 2 voltage is selected if the line 2 disconnector is closed.
• The bus 2 voltage is selected if the line 2 disconnector is open and the bus 2
Circuit breaker is closed.
The function also checks the fuse-failure signals for bus 1, bus 2, line 1 and line 2.
If a fuse-failure is detected in the selected voltage an output signal USELFAIL is
set. This output signal is true if the selected bus or line voltages have a fuse failure.
This output as well as the function can be blocked with the input signal BLOCK.
The function block diagram for the voltage selection of a bus circuit breaker is
shown in figure 247 and for the tie circuit breaker in figure 248
492
Control
LN1QOPEN
AND
LN1SEL
LN1QCLD
B1QOPEN
LN2SEL
B1QCLD AND AND
OR
B2SEL
LN2QOPEN
LN2QCLD AND
AND invalidSelection
AND
B2QOPEN
B2QCLD AND
line1Voltage
lineVoltage
line2Voltage
bus2Voltage
UB1OK
UB1FF OR
OR
UB2OK AND
AND selectedFuseOK
UB2FF OR
USELFAIL
ULN1OK AND
AND
ULN1FF OR
ULN2OK
AND
ULN2FF OR
BLOCK
en05000780.vsd
IEC05000780 V1 EN
Figure 247: Simplified logic diagram for the voltage selection function for a bus circuit breaker in a 1 1/2
breaker arrangement
493
Control
LN1QOPEN
LN1SEL
LN1QCLD AND
B1SEL
1
B1QOPEN AND
AND
B1QCLD AND
line1Voltage
busVoltage
bus1Voltage
LN2QOPEN
LN2SEL
LN2QCLD AND
B2SEL
1
OR invalidSelection
B2QOPEN AND
AND
B2QCLD AND
line2Voltage
lineVoltage
bus2Voltage
UB1OK AND
UB1FF OR
OR
UB2OK AND selectedFuseOK
AND
UB2FF OR
USELFAIL
ULN1OK AND
AND
ULN1FF OR
ULN2OK
AND
ULN2FF OR
BLOCK
en05000781.vsd
IEC05000781 V1 EN
Figure 248: Simplified logic diagram for the voltage selection function for the tie circuit breaker in 1 1/2
breaker arrangement.
Fuse failure supervision

External fuse failure signals or signals from a tripped fuse switch/MCB are
connected to binary inputs that are configured to the inputs of SESRSYN functions
in the IED. Alternatively, the internal signals from fuse failure supervision can be
used when available. There are two alternative connection possibilities. Inputs
labelled OK must be connected if the available contact indicates that the voltage
circuit is healthy. Inputs labelled FF must be connected if the available contact
indicates that the voltage circuit is faulty.
494
Control
The UB1OK/UB2OK and UB1FF/UB2FF inputs are related to the busbar voltage
and the ULNOK and ULNFF inputs are related to the line voltage. Configure them
to the binary input or function outputs that indicate the status of the external fuse
failure of the busbar and line voltages. In the event of a fuse failure, the energizing
check function is blocked. The synchronizing and the synchrocheck function
requires full voltage on both sides and will be blocked automatically in the event of
fuse failures.

SESRSYN
U3PBB1* SYNOK
U3PBB2* AUTOSYOK
U3PLN1* AUTOENOK
U3PLN2* MANSYOK
BLOCK MANENOK
BLKSYNCH TSTSYNOK
BLKSC TSTAUTSY
BLKENERG TSTMANSY
B1QOPEN TSTENOK
B1QCLD USELFAIL
B2QOPEN B1SEL
B2QCLD B2SEL
LN1QOPEN LN1SEL
LN1QCLD LN2SEL
LN2QOPEN SYNPROGR
LN2QCLD SYNFAIL
UB1OK UOKSYN
UB1FF UDIFFSYN
UB2OK FRDIFSYN
UB2FF FRDIFFOK
ULN1OK FRDERIVA
ULN1FF UOKSC
ULN2OK UDIFFSC
ULN2FF FRDIFFA
STARTSYN PHDIFFA
TSTSYNCH FRDIFFM
TSTSC PHDIFFM
TSTENERG INADVCLS
AENMODE UDIFFME
MENMODE FRDIFFME
PHDIFFME
UBUS
ULINE
MODEAEN
MODEMEN
IEC10000046 V1 EN
Figure 249: SESRSYN function block

Table 260: SESRSYN Input signals
U3PBB1 GROUP - Group signal for phase to earth voltage input L1,
SIGNAL busbar 1
U3PBB2 GROUP - Group signal for phase to earth voltage input L1,
SIGNAL busbar 2
U3PLN1 GROUP - Group signal for phase to earth voltage input L1,
SIGNAL line 1
495
Control

U3PLN2 GROUP - Group signal for phase to earth voltage input L1,
SIGNAL line 2
BLKSYNCH BOOLEAN 0 Block synchronizing
BLKSC BOOLEAN 0 Block synchro check
BLKENERG BOOLEAN 0 Block energizing check
B1QOPEN BOOLEAN 0 Open status for CB or disconnector connected to
bus1
B1QCLD BOOLEAN 0 Close status for CB or disconnector connected to
bus1
B2QOPEN BOOLEAN 0 Open status for CB or disconnector connected to
bus2
B2QCLD BOOLEAN 0 Close status for CB or disconnector connected to
bus2
LN1QOPEN BOOLEAN 0 Open status for CB or disconnector connected to
line1
LN1QCLD BOOLEAN 0 Close status for CB or disconnector connected to
line1
LN2QOPEN BOOLEAN 0 Open status for CB or disconnector connected to
line2
LN2QCLD BOOLEAN 0 Close status for CB or disconnector connected to
line2
UB1OK BOOLEAN 0 Bus1 voltage transformer OK
UB1FF BOOLEAN 0 Bus1 voltage transformer fuse failure
UB2OK BOOLEAN 0 Bus2 voltage transformer OK
UB2FF BOOLEAN 0 Bus2 voltage transformer fuse failure
ULN1OK BOOLEAN 0 Line1 voltage transformer OK
ULN1FF BOOLEAN 0 Line1 voltage transformer fuse failure
ULN2OK BOOLEAN 0 Line2 voltage transformer OK
ULN2FF BOOLEAN 0 Line2 voltage transformer fuse failure
STARTSYN BOOLEAN 0 Start synchronizing
TSTSYNCH BOOLEAN 0 Set synchronizing in test mode
TSTSC BOOLEAN 0 Set synchro check in test mode
TSTENERG BOOLEAN 0 Set energizing check in test mode
AENMODE INTEGER 0 Input for setting of automatic energizing mode
MENMODE INTEGER 0 Input for setting of manual energizing mode
Table 261: SESRSYN Output signals

SYNOK BOOLEAN Synchronizing OK output
AUTOSYOK BOOLEAN Auto synchro check OK
AUTOENOK BOOLEAN Automatic energizing check OK
496
Control

MANSYOK BOOLEAN Manual synchro check OK
MANENOK BOOLEAN Manual energizing check OK
TSTSYNOK BOOLEAN Synchronizing OK test output
TSTAUTSY BOOLEAN Auto synchro check OK test output
TSTMANSY BOOLEAN Manual synchro check OK test output
TSTENOK BOOLEAN Energizing check OK test output
USELFAIL BOOLEAN Selected voltage transformer fuse failed
B1SEL BOOLEAN Bus1 selected
B2SEL BOOLEAN Bus2 selected
LN1SEL BOOLEAN Line1 selected
LN2SEL BOOLEAN Line2 selected
SYNPROGR BOOLEAN Synchronizing in progress
SYNFAIL BOOLEAN Synchronizing failed
UOKSYN BOOLEAN Voltage amplitudes for synchronizing above set
limits
UDIFFSYN BOOLEAN Voltage difference out of limit for synchronizing
FRDIFSYN BOOLEAN Frequency difference out of limit for synchronizing
FRDIFFOK BOOLEAN Frequency difference in band for synchronizing
FRDERIVA BOOLEAN Frequency derivative out of limit for synchronizing
UOKSC BOOLEAN Voltage amplitudes above set limits
UDIFFSC BOOLEAN Voltage difference out of limit
FRDIFFA BOOLEAN Frequency difference out of limit for Auto operation
PHDIFFA BOOLEAN Phase angle difference out of limit for Auto
operation
FRDIFFM BOOLEAN Frequency difference out of limit for Manual
operation
PHDIFFM BOOLEAN Phase angle difference out of limit for Manual
Operation
INADVCLS BOOLEAN Inadvertent circuit breaker closing
UDIFFME REAL Calculated difference of voltage in p.u
FRDIFFME REAL Calculated difference of frequency
PHDIFFME REAL Calculated difference of phase angle
UBUS REAL Bus voltage
ULINE REAL Line voltage
MODEAEN INTEGER Selected mode for automatic energizing
MODEMEN INTEGER Selected mode for manual energizing
497
Control

Table 262: SESRSYN Group settings (basic)
On
CBConfig No voltage sel. - - No voltage sel. Select CB configuration
Double bus
1 1/2 bus CB
1 1/2 bus alt. CB
Tie CB
UBaseBus 0.001 - 9999.999 kV 0.001 400.000 Base value for busbar voltage settings
UBaseLine 0.001 - 9999.999 kV 0.001 400.000 Base value for line voltage settings
PhaseShift -180 - 180 Deg 5 0 Phase shift
URatio 0.040 - 25.000 - 0.001 1.000 Voltage ratio
OperationSynch Off - - Off Operation for synchronizing function Off/
On On
UHighBusSynch 50.0 - 120.0 %UBB 1.0 80.0 Voltage high limit bus for synchronizing
in % of UBaseBus
UHighLineSynch 50.0 - 120.0 %UBL 1.0 80.0 Voltage high limit line for synchronizing
in % of UBaseLine
UDiffSynch 0.02 - 0.50 pu 0.01 0.10 Voltage difference limit for synchronizing
in p.u
FreqDiffMin 0.003 - 0.250 Hz 0.001 0.010 Minimum frequency difference limit for
synchronizing
FreqDiffMax 0.050 - 0.250 Hz 0.001 0.200 Maximum frequency difference limit for
synchronizing
FreqRateChange 0.000 - 0.500 Hz/s 0.001 0.300 Maximum allowed frequency rate of
change
tBreaker 0.000 - 60.000 s 0.001 0.080 Closing time of the breaker
tClosePulse 0.050 - 60.000 s 0.001 0.200 Breaker closing pulse duration
tMaxSynch 0.00 - 6000.00 s 0.01 600.00 Resets synch if no close has been made
before set time
tMinSynch 0.000 - 60.000 s 0.001 2.000 Minimum time to accept synchronizing
conditions
OperationSC Off - - On Operation for synchronism check
On function Off/On
UHighBusSC 50.0 - 120.0 %UBB 1.0 80.0 Voltage high limit bus for synchrocheck
in % of UBaseBus
UHighLineSC 50.0 - 120.0 %UBL 1.0 80.0 Voltage high limit line for synchrocheck
in % of UBaseLine
UDiffSC 0.02 - 0.50 pu 0.01 0.15 Voltage difference limit in p.u
FreqDiffA 0.003 - 1.000 Hz 0.001 0.010 Frequency difference limit between bus
and line Auto
FreqDiffM 0.003 - 1.000 Hz 0.001 0.010 Frequency difference limit between bus
and line Manual
PhaseDiffA 5.0 - 90.0 Deg 1.0 25.0 Phase angle difference limit between
bus and line Auto
498
Control

PhaseDiffM 5.0 - 90.0 Deg 1.0 25.0 Phase angle difference limit between
bus and line Manual
tSCA 0.000 - 60.000 s 0.001 0.100 Time delay output for synchrocheck Auto
tSCM 0.000 - 60.000 s 0.001 0.100 Time delay output for synchrocheck
Manual
AutoEnerg Off - - DBLL Automatic energizing check mode
DLLB
DBLL
Both
ManEnerg Off - - Both Manual energizing check mode
DLLB
DBLL
Both
ManEnergDBDL Off - - Off Manual dead bus, dead line energizing
On
UHighBusEnerg 50.0 - 120.0 %UBB 1.0 80.0 Voltage high limit bus for energizing
check in % of UBaseBus
UHighLineEnerg 50.0 - 120.0 %UBL 1.0 80.0 Voltage high limit line for energizing
check in % of UBaseLine
ULowBusEnerg 10.0 - 80.0 %UBB 1.0 40.0 Voltage low limit bus for energizing
check in % of UBaseBus
ULowLineEnerg 10.0 - 80.0 %UBL 1.0 40.0 Voltage low limit line for energizing
check in % of UBaseLine
UMaxEnerg 50.0 - 180.0 %UB 1.0 115.0 Maximum voltage for energizing in % of
UBase, Line and/or Bus
tAutoEnerg 0.000 - 60.000 s 0.001 0.100 Time delay for automatic energizing
check
tManEnerg 0.000 - 60.000 s 0.001 0.100 Time delay for manual energizing check
499
Control
Table 263: SESRSYN Non group settings (basic)

SelPhaseBus1 Phase L1 for - - Phase L1 for Select phase for busbar1
busbar1 busbar1
Phase L2 for
busbar1
Phase L3 for
busbar1
Phase L1L2 for
busbar1
Phase L2L3 for
busbar1
Phase L3L1 for
busbar1
Pos. sequence for
busbar1
SelPhaseBus2 Phase L1 for - - Phase L1 for Select phase for busbar2
busbar2 busbar2
Phase L2 for
busbar2
Phase L3 for
busbar2
Phase L1L2 for
busbar2
Phase L2L3 for
busbar2
Phase L3L1 for
busbar2
Pos. sequence for
busbar2
SelPhaseLine1 Phase L1 for line1 - - Phase L1 for line1 Select phase for line1
Phase L2 for line1
Phase L3 for line1
Phase L1L2 for
line1
Phase L2L3 for
line1
Phase L3L1 for
line1
Pos. sequence for
line1
SelPhaseLine2 Phase L1 for line2 - - Phase L1 for line2 Select phase for line2
Phase L2 for line2
Phase L3 for line2
Phase L1L2 for
line2
Phase L2L3 for
line2
Phase L3L1 for
line2
Pos. sequence for
line2
500
Control

Table 264: SESRSYN technical data
Phase shift, jline - jbus (-180 to 180) degrees -
Voltage ratio, Ubus/Uline (0.40-25.000) % of UBaseBus -

and UBaseLIne
Voltage high limit for (50.0-120.0)% of UBaseBus and ± 0.5% of Ur at U ≤ Ur
synchronizing and UBaseLIne ± 0.5% of U at U >Ur
synchrocheck
Reset ratio, synchrocheck > 95% -
Frequency difference limit (0.003-1.000) Hz ± 2.0 mHz
between bus and line
Phase angle difference limit (5.0-90.0) degrees ± 2.0 degrees
Voltage difference limit (0.02-0.5) p.u ± 0.5% of Ur
Time delay output for (0.000-60.000) s ± 0.5% ± 10 ms
synchrocheck
Voltage high limit for (50.0-120.0)% of UBaseBus and ± 0.5% of Ur at U ≤ Ur
energizing check UBaseLIne ± 0.5% of U at U >Ur
Reset ratio, voltage high limit > 95% -

Voltage low limit for (10.0-80.0)% of UBase ± 0.5% of Ur
energizing check
Reset ratio, voltage low limit < 105% -
Maximum voltage for (50.0-180.0)% of UBaseBus and/ ± 0.5% of Ur at U ≤ Ur
energizing or UBaseLIne ± 0.5% of U at U >Ur
Time delay for energizing (0.000-60.000) s ± 0.5% ± 10 ms

check
Operate time for 160 ms typically -
synchrocheck function
Operate time for energizing 80 ms typically -
function
12.2 Apparatus control APC
12.2.1 Introduction
The apparatus control functions are used for control and supervision of circuit
breakers, disconnectors and earthing switches within a bay. Permission to operate
is given after evaluation of conditions from other functions such as interlocking,
synchrocheck, operator place selection and external or internal blockings.
501
Control
In normal security, the command is processed and the resulting position is not
supervised. However with enhanced security, the command is processed and the
resulting position is supervised.
12.2.2 Error handling

Depending on the error that occurs during the command sequence the error signal
will be set with a value. Table 265 describes vendor specific cause values in
addition to these specified in IEC 61850-8-1 standard. The list of values of the
“cause” are in order of priority. The values are available over the IEC 61850. An
output L_CAUSE on the function block for Switch controller (SCSWI), Circuit
breaker (SXCBR) and Circuit switch (SXSWI) indicates the latest value of the
error during the command.
Table 265: Values for "cause" signal in priority order

Attribute value Description Supported
Defined in IEC 61850 0 no error X
1 serviceError-type
2 blocked-by-switching- X
hierarchy
3 select-failed X
4 invalid-position X
5 position-reached X
6 parameter-change-in- X
execution
7 step-limit X
8 blocked-by-mode X
9 blocked-by-process X
10 blocked-by-interlocking X
11 blocked-by- X
synchrocheck
12 command-already-in- X
execution
13 blocked-by-health X
14 1-of-n-control X
15 abortion-by-cancel X
16 time-limit-over X
17 abortion-by-trip X
18 object-not-selected X
19 Not in use
502
Control
Attribute value Description Supported

Vendor specific -20 Not in use
-21 Not in use
-23 blocked-for-command X
-24 blocked-for-open- X
command
-25 blocked-for-close- X
command
-26 Not in use
-27 Not in use
-28 Not in use
-29 Not in use
-30 long-operation-time X
-31 switch-not-start-moving X
-32 persisting-intermediate- X
state
-33 switch-returned-to-initial- X
position
-34 switch-in-bad-state X
-35 not-expected-final- X
position
12.2.3 Bay control QCBAY
The Bay control QCBAY function is used together with Local remote and local
remote control functions to handle the selection of the operator place per bay.
QCBAY also provides blocking functions that can be distributed to different
apparatuses within the bay.

QCBAY
LR_OFF PSTO
LR_LOC UPD_BLKD
LR_REM CMD_BLKD
LR_VALID LOC
BL_UPD REM
BL_CMD
IEC10000048 V1 EN
Figure 250: QCBAY function block
503
Control

Table 266: QCBAY Input signals
LR_OFF BOOLEAN 0 External Local/Remote switch is in Off position
LR_LOC BOOLEAN 0 External Local/Remote switch is in Local position
LR_REM BOOLEAN 0 External Local/Remote switch is in Remote
position
LR_VALID BOOLEAN 0 Data representing the L/R switch position is valid
BL_UPD BOOLEAN 0 Steady signal to block the position updates
BL_CMD BOOLEAN 0 Steady signal to block the command
Table 267: QCBAY Output signals

PSTO INTEGER Value for the operator place allocation
UPD_BLKD BOOLEAN Update of position is blocked
CMD_BLKD BOOLEAN Function is blocked for commands
LOC BOOLEAN Local operation allowed
REM BOOLEAN Remote operation allowed

Table 268: QCBAY Non group settings (basic)
AllPSTOValid Priority - - Priority Priority of originators
No priority
12.2.4 Local/Remote switch
The signals from the local HMI or from an external local/remote switch are applied
via the function blocks LOCREM and LOCREMCTRL to the Bay control
(QCBAY) function block. A parameter in function block LOCREM is set to
choose if the switch signals are coming from the local HMI or from an external
hardware switch connected via binary inputs.
The function block Local remote (LOCREM) handles the signals coming from the
local/remote switch. The connections are seen in figure 251, where the inputs on
function block LOCREM are connected to binary inputs if an external switch is
504
Control
used. When a local HMI is used, the inputs are not used and are set to FALSE in
the configuration. The outputs from the LOCREM function block control the
output PSTO (Permitted Source To Operate) on Bay control (QCBAY).
LOCREM QCBAY
CTRLOFF OFF LR_ OFF PSTO
LOCCTRL LOCAL LR_ LOC UPD_ BLKD
REMCTRL REMOTE LR_ REM CMD_ BLKD
LHMICTRL VALID LR_ VALID LOC
BL_ UPD REM
BL_ CMD
LOCREM QCBAY
CTRLOFF OFF LR_ OFF PSTO
LOCCTRL LOCAL LR_ LOC UPD_ BLKD
REMCTRL REMOTE LR_ REM CMD_ BLKD
LHMICTRL VALID LR_ VALID LOC
BL_ UPD REM
BL_ CMD
LOCREMCTRL
PSTO1 HMICTR1
PSTO2 HMICTR2
PSTO3 HMICTR3
PSTO4 HMICTR4
PSTO5 HMICTR5
PSTO6 HMICTR6
PSTO7 HMICTR7
PSTO8 HMICTR8
PSTO9 HMICTR9
PSTO 10 HMICTR 10
PSTO 11 HMICTR 11
PSTO 12 HMICTR 12
IEC10000052 V1 EN
Figure 251: Configuration for the local/remote handling for a local HMI with two
bays and two screen pages
If the IED contains control functions for several bays, the local/remote position can
be different for the included bays. When the local HMI is used the position of the
local/remote switch can be different depending on which single line diagram screen
page that is presented on the local HMI. The function block Local remote control
(LOCREMCTRL) controls the presentation of the LEDs for the local/remote
position to applicable bay and screen page.
The switching of the local/remote switch requires at least system operator level.
The password will be requested at an attempt to operate if authority levels have
been defined in the IED. Otherwise the default authority level, SuperUser, can
handle the control without LogOn. The users and passwords are defined in PCM600.
505
Control

LOCREM
CTRLOFF OFF
LOCCTRL LOCAL
REMCTRL REMOTE
LHMICTRL VALID
IEC05000360 V2 EN
Figure 252: LOCREM function block
LOCREMCTRL
PSTO1 HMICTR1
PSTO2 HMICTR2
PSTO3 HMICTR3
PSTO4 HMICTR4
PSTO5 HMICTR5
PSTO6 HMICTR6
PSTO7 HMICTR7
PSTO8 HMICTR8
PSTO9 HMICTR9
PSTO10 HMICTR10
PSTO11 HMICTR11
PSTO12 HMICTR12
IEC05000361 V2 EN
Figure 253: LOCREMCTRL function block

Table 269: LOCREM Input signals
CTRLOFF BOOLEAN 0 Disable control
LOCCTRL BOOLEAN 0 Local in control
REMCTRL BOOLEAN 0 Remote in control
LHMICTRL INTEGER 0 LHMI control
Table 270: LOCREM Output signals

OFF BOOLEAN Control is disabled
LOCAL BOOLEAN Local control is activated
REMOTE BOOLEAN Remote control is activated
VALID BOOLEAN Outputs are valid
506
Control
Table 271: LOCREMCTRL Input signals

PSTO1 INTEGER 0 PSTO input channel 1
Table 272: LOCREMCTRL Output signals

HMICTR1 INTEGER Bitmask output 1 to local remote LHMI input

Table 273: LOCREM Non group settings (basic)
ControlMode Internal LR-switch - - Internal LR-switch Control mode for internal/external LR-
External LR-switch switch
12.2.5 Switch controller SCSWI
507
Control
The Switch controller (SCSWI) initializes and supervises all functions to properly
select and operate switching primary apparatuses. The Switch controller may
handle and operate on one three-phase device.
The Switch controller (SCSWI) is provided with verification checks for the select -
execute sequence, that is, checks the conditions prior each step of the operation.
The involved functions for these condition verifications are interlocking,
reservation, blockings and synchrocheck.
Control handling
.
Two types of control models can be used. The two control models are "direct with
normal security" and "SBO (Select-Before-Operate) with enhanced security". The
parameter CtlModel defines which one of the two control models is used. The
control model "direct with normal security" does not require a select whereas, the
"SBO with enhanced security" command model requires a select before execution.
Normal security means that only the command is evaluated and the resulting
position is not supervised. Enhanced security means that the command sequence is
supervised in three steps, the selection, command evaluation and the supervision of
position. Each step ends up with a pulsed signal to indicate that the respective step
in the command sequence is finished. If an error occurs in one of the steps in the
command sequence, the sequence is terminated and the error is mapped into the
enumerated variable "cause" attribute belonging to the pulsed response signal for
the IEC 61850 communication. The last cause L_CAUSE can be read from the
function block and used for example at commissioning.
There is no relation between the command direction and the actual

position. For example, if the switch is in close position it is possible
to execute a close command.
Before an execution command, an evaluation of the position is done. If the

parameter PosDependent is true and the position is in intermediate state or in bad
state no execution command is sent. If the parameter is false the execution
command is sent independent of the position value.
Evaluation of position
In the case when there are three one-phase switches connected to the switch control
function, the switch control will "merge" the position of the three switches to the
resulting three-phase position. In the case when the position differ between the one-
phase switches, following principles will be applied:
508
Control
The position output from switch (SXCBR or SXSWI) is connected to SCSWI.

With the group signal connection the SCSWI obtains the position, time stamps and
quality attributes of the position which is used for further evaluation.
All switches in open position: switch control position = open

All switches in close position: switch control position = close
One switch =open, two switches= close (or switch control position = intermediate
inversely):
Any switch in intermediate position: switch control position = intermediate
Any switch in bad state: switch control position = bad state
The time stamp of the output three-phase position from switch control will have the
time stamp of the last changed phase when it goes to end position. When it goes to
intermediate position or bad state, it will get the time stamp of the first changed phase.
In addition, there is also the possibility that one of the one-phase switches will
change position at any time due to a trip. Such situation is here called pole
discordance and is supervised by this function. In case of a pole discordance
situation, that is, the position of the one-phase switches are not equal for a time
longer than the setting tPoleDiscord, an error signal POLEDISC will be set.
In the supervision phase, the switch controller function evaluates the "cause"
values from the switch modules Circuit breaker (SXCBR)/ Circuit switch
(SXSWI). At error the "cause" value with highest priority is shown.
Blocking principles
The blocking signals are normally coming from the bay control function (QCBAY)
and via the IEC 61850 communication from the operator place.
The different blocking possibilities are:
• Block/deblock of command. It is used to block command for operation of

position.
• Blocking of function, BLOCK, signal from DO (Data Object) Behavior (IEC
61850). If DO Behavior is set to "blocked" it means that the function is active,
but no outputs are generated, no reporting, control commands are rejected and
functional and configuration data is visible.
The different block conditions will only affect the operation of this
function, that is, no blocking signals will be "forwarded" to other
functions. The above blocking outputs are stored in a non-volatile
memory.
Interaction with synchrocheck and synchronizing functions

The Switch controller (SCSWI) works in conjunction with the synchrocheck and
the synchronizing function (SESRSYN). It is assumed that the synchrocheck
509
Control
function is continuously in operation and gives the result to SCSWI. The result
from the synchrocheck function is evaluated during the close execution. If the
operator performs an override of the synchrocheck, the evaluation of the
synchrocheck state is omitted. When there is a positive confirmation from the
synchrocheck function, SCSWI will send the close signal EXE_CL to the switch
function Circuit breaker (SXCBR).
When there is no positive confirmation from the synchrocheck function, SCSWI

will send a start signal START_SY to the synchronizing function, which will send
the closing command to SXCBR when the synchronizing conditions are fulfilled,
see figure 254. If no synchronizing function is included, the timer for supervision
of the "synchronizing in progress signal" is set to 0, which means no start of the
synchronizing function. SCSWI will then set the attribute "blocked-by-
synchrocheck" in the "cause" signal. See also the time diagram in figure 258.
SCSWI SXCBR
EXE_CL
OR CLOSE
SYNC_OK
START_SY
SY_INPRO
SESRSYN
CLOSECB
Synchro Synchronizing
check function
IEC09000209 V1 EN
Figure 254: Example of interaction between SCSWI, SESRSYN (synchrocheck

and synchronizing function) and SXCBR function
Time diagrams
The Switch controller (SCSWI) function has timers for evaluating different time
supervision conditions. These timers are explained here.
The timer tSelect is used for supervising the time between the select and the
execute command signal, that is, the time the operator has to perform the command
execution after the selection of the object to operate.
510
Control
select
execute command
tSelect
timer t1 t1>tSelect, then long-
operation-time in 'cause'
is set
en05000092.vsd
IEC05000092 V1 EN
Figure 255: tSelect
The parameter tResResponse is used to set the maximum allowed time to make the
reservation, that is, the time between reservation request and the feedback
reservation granted from all bays involved in the reservation function.
select
reservation request RES_RQ
reservation granted RES_GRT
command termination
tResResponse t1>tResResponse, then
timer 1-of-n-control in 'cause'
t1 is set
en05000093.vsd
IEC05000093 V1 EN
Figure 256: tResResponse
The timer tExecutionFB supervises the time between the execute command and the
command termination, see figure 257.
511
Control
execute command
position L1 open
close
position L2 open
close
position L3 open
close
cmd termination L1
cmd termination L2
cmd termination L3
cmd termination *
position open
close
tExecutionFB t1>tExecutionFB, then

timer long-operation-time in
t1 'cause' is set
* The cmd termination will be delayed one execution sample.

en05000094.vsd
IEC05000094 V1 EN
Figure 257: tExecutionFB
The parameter tSynchrocheck is used to define the maximum allowed time between
the execute command and the input SYNC_OK to become true. If SYNC_OK=true
at the time the execute command signal is received, the timer "tSynchrocheck" will
not start. The start signal for the synchronizing is obtained if the synchrocheck
conditions are not fulfilled.
execute command
SYNC_OK
tSynchrocheck
t1
START_SY
SY_INPRO
tSynchronizing t2>tSynchronizing, then

t2 blocked-by-synchrocheck in
'cause' is set
en05000095.vsd
IEC05000095 V1 EN
Figure 258: tSynchroCheck and tSynchronizing
512
Control

SCSWI
BLOCK EXE_OP
PSTO EXE_CL
L_SEL SELECTED
L_OPEN RES_RQ
L_CLOSE START_SY
AU_OPEN POSITION
AU_CLOSE OPENPOS
BL_CMD CLOSEPOS
RES_GRT POLEDISC
RES_EXT CMD_BLK
SY_INPRO L_CAUSE
SYNC_OK XOUT
EN_OPEN POS_INTR
EN_CLOSE
XPOS1
XPOS2
XPOS3
IEC05000337 V2 EN
Figure 259: SCSWI function block

Table 274: SCSWI Input signals
PSTO INTEGER 2 Operator place selection
L_SEL BOOLEAN 0 Select signal from local panel
L_OPEN BOOLEAN 0 Open signal from local panel
L_CLOSE BOOLEAN 0 Close signal from local panel
AU_OPEN BOOLEAN 0 Used for local automation function
AU_CLOSE BOOLEAN 0 Used for local automation function
BL_CMD BOOLEAN 0 Steady signal for block of the command
RES_GRT BOOLEAN 0 Positive acknowledge that all reservations are
made
RES_EXT BOOLEAN 0 Reservation is made externally
SY_INPRO BOOLEAN 0 Synchronizing function in progress
SYNC_OK BOOLEAN 0 Closing is permitted at set to true by the
synchrocheck
EN_OPEN BOOLEAN 0 Enables open operation
EN_CLOSE BOOLEAN 0 Enables close operation
XPOS1 GROUP - Group signal from XCBR/XSWI per phase
SIGNAL
SIGNAL
SIGNAL
513
Control
Table 275: SCSWI Output signals

EXE_OP BOOLEAN Execute command for open direction
EXE_CL BOOLEAN Execute command for close direction
SELECTED BOOLEAN Select conditions are fulfilled
RES_RQ BOOLEAN Request signal to the reservation function
START_SY BOOLEAN Starts the synchronizing function
POSITION INTEGER Position indication
OPENPOS BOOLEAN Open position indication
CLOSEPOS BOOLEAN Closed position indication
POLEDISC BOOLEAN The positions for poles L1-L3 are not equal after
a set time
CMD_BLK BOOLEAN Commands are blocked
L_CAUSE INTEGER Latest value of the error indication during command
XOUT BOOLEAN Execution information to XCBR/XSWI
POS_INTR BOOLEAN Stopped in intermediate position

Table 276: SCSWI Non group settings (basic)
CtlModel Dir Norm - - SBO Enh Specifies control model type
SBO Enh
PosDependent Always permitted - - Always permitted Permission to operate depending on the
Not perm at 00/11 position
tSelect 0.00 - 600.00 s 0.01 30.00 Maximum time between select and
execute signals
tResResponse 0.000 - 60.000 s 0.001 5.000 Allowed time from reservation request to
reservation granted
tSynchrocheck 0.00 - 600.00 s 0.01 10.00 Allowed time for synchrocheck to fulfil
close conditions
tSynchronizing 0.00 - 600.00 s 0.01 0.00 Supervision time to get the signal
synchronizing in progress
tExecutionFB 0.00 - 600.00 s 0.01 30.00 Maximum time from command execution
to termination
tPoleDiscord 0.000 - 60.000 s 0.001 2.000 Allowed time to have discrepancy
between the poles
12.2.6 Circuit breaker SXCBR
514
Control
The purpose of Circuit breaker (SXCBR) is to provide the actual status of positions
and to perform the control operations, that is, pass all the commands to primary
apparatuses in the form of circuit breakers via output boards and to supervise the
switching operation and position.
The users of the Circuit breaker function (SXCBR) is other functions such as for
example, switch controller, protection functions, autorecloser function or an IEC
61850 client residing in another IED or the operator place. This switch function
executes commands, evaluates block conditions and evaluates different time
supervision conditions. Only if all conditions indicate a switch operation to be
allowed, the function performs the execution command. In case of erroneous
conditions, the function indicates an appropriate "cause" value.
SXCBR has an operation counter for closing and opening commands. The counter
value can be read remotely from the operator place. The value is reset from a
binary input or remotely from the operator place by configuring a signal from the
Single Point Generic Control 8 signals (SPC8GGIO) for example.
Local/Remote switch
One binary input signal LR_SWI is included in SXCBR to indicate the local/
remote switch position from switchyard provided via the I/O board. If this signal is
set to TRUE it means that change of position is allowed only from switchyard
level. If the signal is set to FALSE it means that command from IED or higher
level is permitted. When the signal is set to TRUE all commands (for change of
position) from internal IED clients are rejected, even trip commands from
protection functions are rejected. The functionality of the local/remote switch is
described in figure 260.
Local= Operation at
RU
E switch yard level
T
From I/O switchLR

FAL
SE
Remote= Operation at
IED or higher level
en05000096.vsd
IEC05000096 V1 EN
Figure 260: Local/Remote switch
Blocking principles
SXCBR includes several blocking principles. The basic principle for all blocking
signals is that they will affect commands from all other clients for example,
operators place, protection functions, autoreclosure and so on.
515
Control
The blocking possibilities are:
• Block/deblock for open command. It is used to block operation for open

command. Note that this block signal also affects the input OPEN for
immediate command.
• Block/deblock for close command. It is used to block operation for close
command. Note that this block signal also affects the input CLOSE for
immediate command.
• Update block/deblock of positions. It is used to block the updating of position
values. Other signals related to the position will be reset.
The above blocking outputs are stored in a non-volatile memory.
Substitution
The substitution part in SXCBR is used for manual set of the position for the
switch. The typical use of substitution is that an operator enters a manual value
because that the real process value is erroneous for some reason. SXCBR will then
use the manually entered value instead of the value for positions determined by the
process.
It is always possible to make a substitution, independently of the

position indication and the status information of the I/O board.
When substitution is enabled, the position values are blocked for
updating and other signals related to the position are reset. The
substituted values are stored in a non-volatile memory.
Time diagrams
There are two timers for supervising of the execute phase, tStartMove and
tIntermediate. tStartMove supervises that the primary device starts moving after the
execute output pulse is sent. tIntermediate defines the maximum allowed time for
intermediate position. Figure 261 explains these two timers during the execute phase.
516
Control
EXE_CL AdaptivePulse = TRUE

Close pulse duration
OPENPOS
CLOSEPOS
if t1 > tStartMove then

tStartMove timer "switch-not-start-moving"
t1 attribute in 'cause' is set
tStartMove
if t2 > tIntermediate then

tIntermediate timer "persisting-intermediate-state"
tIntermediate
en05000097.vsd
IEC05000097 V1 EN
Figure 261: The timers tStartMove and tIntermediate
The timers tOpenPulse and tClosePulse are the length of the execute output pulses
to be sent to the primary equipment. Note that the output pulses for open and close
command can have different pulse lengths. The pulses can also be set to be
adaptive with the configuration parameter AdaptivePulse. Figure 262 shows the
principle of the execute output pulse. The AdaptivePulse parameter will have affect
on both execute output pulses.
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
EXE_CL
tClosePulse
AdaptivePulse=TRUE
EXE_CL
tClosePulse
en05000098.vsd
IEC05000098 V1 EN
Figure 262: Execute output pulse
If the pulse is set to be adaptive, it is not possible for the pulse to exceed
tOpenPulse or tClosePulse.
The execute output pulses are reset when:
517
Control
• the new expected final position is reached and the configuration parameter
AdaptivePulse is set to true
• the timer tOpenPulse or tClosePulse has elapsed
• an error occurs due to the switch does not start moving, that is, tStartMove has
elapsed.
There is one exception from the first item above. If the primary device is in open
position and an open command is executed or if the primary device is in closed
position and a close command is executed. In these cases, with the additional
condition that the configuration parameter AdaptivePulse is true, the execute output
pulse is always activated and resets when tStartMove has elapsed. If the
configuration parameter AdaptivePulse is set to false the execution output remains
active until the pulse duration timer has elapsed.
If the start position indicates bad state (OPENPOS=1 and

CLOSEPOS =1) when a command is executed the execute output
pulse resets only when timer tOpenPulse or tClosePulse has elapsed.
An example of when a primary device is open and an open command is executed is

shown in figure 263 .
OPENPOS
CLOSEPOS
EXE_OP AdaptivePulse=FALSE
tOpenPulse
EXE_OP AdaptivePulse=TRUE
tOpenPulse
tStartMove timer
en05000099.vsd
IEC05000099 V1 EN
Figure 263: Open command with open position indication
518
Control

SXCBR
BLOCK XPOS
LR_SWI EXE_OP
OPEN EXE_CL
CLOSE SUBSTED
BL_OPEN OP_BLKD
BL_CLOSE CL_BLKD
BL_UPD UPD_BLKD
POSOPEN POSITION
POSCLOSE OPENPOS
TR_OPEN CLOSEPOS
TR_CLOSE TR_POS
RS_CNT CNT_VAL
XIN L_CAUSE
IEC05000338 V2 EN
Figure 264: SXCBR function block

Table 277: SXCBR Input signals
LR_SWI BOOLEAN 0 Local/Remote switch indication from switchyard
OPEN BOOLEAN 0 Pulsed signal used to immediately open the switch
CLOSE BOOLEAN 0 Pulsed signal used to immediately close the switch
BL_OPEN BOOLEAN 0 Signal to block the open command
BL_CLOSE BOOLEAN 0 Signal to block the close command
BL_UPD BOOLEAN 0 Steady signal for block of the position updating
POSOPEN BOOLEAN 0 Signal for open position of apparatus from I/O
POSCLOSE BOOLEAN 0 Signal for close position of apparatus from I/O
TR_OPEN BOOLEAN 0 Signal for open position of truck from I/O
TR_CLOSE BOOLEAN 0 Signal for close position of truck from I/O
RS_CNT BOOLEAN 0 Resets the operation counter
XIN BOOLEAN 0 Execution information from CSWI
Table 278: SXCBR Output signals

XPOS GROUP SIGNAL Group signal for XCBR output
EXE_OP BOOLEAN Executes the command for open direction
EXE_CL BOOLEAN Executes the command for close direction
SUBSTED BOOLEAN Indication that the position is substituted
OP_BLKD BOOLEAN Indication that the function is blocked for open
commands
CL_BLKD BOOLEAN Indication that the function is blocked for close
commands
519
Control

UPD_BLKD BOOLEAN Update of position indication is blocked
POSITION INTEGER Apparatus position indication
OPENPOS BOOLEAN Apparatus open position
CLOSEPOS BOOLEAN Apparatus closed position
TR_POS INTEGER Truck position indication
CNT_VAL INTEGER Operation counter value

Table 279: SXCBR Non group settings (basic)
tStartMove 0.000 - 60.000 s 0.001 0.100 Supervision time for the apparatus to
move after a command
tIntermediate 0.000 - 60.000 s 0.001 0.150 Allowed time for intermediate position
AdaptivePulse Not adaptive - - Not adaptive Output resets when a new correct end
Adaptive position is reached
tOpenPulse 0.000 - 60.000 s 0.001 0.200 Output pulse length for open command
tClosePulse 0.000 - 60.000 s 0.001 0.200 Output pulse length for close command
SuppressMidPos Off - - On Mid-position is suppressed during the
On time tIntermediate
12.2.7 Circuit switch SXSWI
The purpose of Circuit switch (SXSWI) function is to provide the actual status of
positions and to perform the control operations, that is, pass all the commands to
primary apparatuses in the form of disconnectors or earthing switches via output
boards and to supervise the switching operation and position.
The users of the Circuit switch (SXSWI) is other functions such as for example,
switch controller, protection functions, autorecloser function, or a 61850 client
residing in another IED or the operator place. SXSWI executes commands,
evaluates block conditions and evaluates different time supervision conditions.
Only if all conditions indicate a switch operation to be allowed, SXSWI performs
the execution command. In case of erroneous conditions, the function indicates an
appropriate "cause" value.
520
Control
SXSWI has an operation counter for closing and opening commands. The counter
value can be read remotely from the operator place. The value is reset from a
binary input or remotely from the operator place by configuring a signal from the
Single Point Generic Control 8 signals (SPC8GGIO) for example.
Local/Remote switch
One binary input signal LR_SWI is included in SXSWI to indicate the local/remote
switch position from switchyard provided via the I/O board. If this signal is set to
TRUE it means that change of position is allowed only from switchyard level. If
the signal is set to FALSE it means that command from IED or higher level is
permitted. When the signal is set to TRUE all commands (for change of position)
from internal IED clients are rejected, even trip commands from protection
functions are rejected. The functionality of the local/remote switch is described in
figure 265.
Local= Operation at
RU
E switch yard level
T
From I/O switchLR

FAL
SE
Remote= Operation at
IED or higher level
en05000096.vsd
IEC05000096 V1 EN
Figure 265: Local/Remote switch
Blocking principles
SXSWI includes several blocking principles. The basic principle for all blocking
signals is that they will affect commands from all other clients for example,
operators place, protection functions, autorecloser and so on.
The blocking possibilities are:
• Block/deblock for open command. It is used to block operation for open

command. Note that this block signal also affects the input OPEN for
immediate command.
• Block/deblock for close command. It is used to block operation for close
command. Note that this block signal also affects the input CLOSE for
immediate command.
• Update block/deblock of positions. It is used to block the updating of position
values. Other signals related to the position will be reset.
The above blocking outputs are stored in a non-volatile memory.
521
Control
Substitution
The substitution part in SXSWI is used for manual set of the position for the
switch. The typical use of substitution is that an operator enters a manual value
because the real process value is erroneous of some reason. SXSWI will then use
the manually entered value instead of the value for positions determined by the
process.
It is always possible to make a substitution, independently of the

position indication and the status information of the I/O board.
When substitution is enabled, the position values are blocked for
updating and other signals related to the position are reset. The
substituted values are stored in a non-volatile memory.
Time diagrams
There are two timers for supervising of the execute phase, tStartMove and
tIntermediate. tStartMove supervises that the primary device starts moving after the
execute output pulse is sent. tIntermediate defines the maximum allowed time for
intermediate position. Figure 266 explains these two timers during the execute phase.
EXE_CL AdaptivePulse = TRUE

Close pulse duration
OPENPOS
CLOSEPOS
if t1 > tStartMove then

tStartMove timer "switch-not-start-moving"
tStartMove
if t2 > tIntermediate then

tIntermediate timer "persisting-intermediate-state"
tIntermediate
en05000097.vsd
IEC05000097 V1 EN
Figure 266: The timers tStartMove and tIntermediate
The timers tOpenPulse and tClosePulse are the length of the execute output pulses
to be sent to the primary equipment. Note that the output pulses for open and close
command can have different pulse lengths. The pulses can also be set to be
adaptive with the configuration parameter AdaptivePulse. Figure 267 shows the
principle of the execute output pulse. The AdaptivePulse parameter will have affect
on both execute output pulses.
522
Control
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
EXE_CL
tClosePulse
AdaptivePulse=TRUE
EXE_CL
tClosePulse
en05000098.vsd
IEC05000098 V1 EN
Figure 267: Execute output pulse
If the pulse is set to be adaptive, it is not possible for the pulse to exceed
tOpenPulse or tClosePulse.
The execute output pulses are reset when:
If the start position indicates bad state (OPENPOS=1 and

CLOSEPOS =1) when a command is executed the execute output
pulse resets only when timer tOpenPulse or tClosePulse has elapsed.
• the new expected final position is reached and the configuration parameter
AdaptivePulse is set to true
• the timer tOpenPulse or tClosePulse has elapsed
• an error occurs due to the switch does not start moving, that is, tStartMove has
elapsed.
There is one exception from the first item above. If the primary device is in open
position and an open command is executed or if the primary device is in close
position and a close command is executed. In these cases, with the additional
condition that the configuration parameter AdaptivePulse is true, the execute output
pulse is always activated and resets when tStartMove has elapsed. If the
configuration parameter AdaptivePulse is set to false the execution output remains
active until the pulse duration timer has elapsed.
An example when a primary device is open and an open command is executed is

523
Control
OPENPOS
CLOSEPOS
EXE_OP AdaptivePulse=FALSE
tOpenPulse
EXE_OP AdaptivePulse=TRUE
tOpenPulse
tStartMove timer
en05000099.vsd
IEC05000099 V1 EN
Figure 268: Open command with open position indication

SXSWI
BLOCK XPOS
LR_SWI EXE_OP
OPEN EXE_CL
CLOSE SUBSTED
BL_OPEN OP_BLKD
BL_CLOSE CL_BLKD
BL_UPD UPD_BLKD
POSOPEN POSITION
POSCLOSE OPENPOS
RS_CNT CLOSEPOS
XIN CNT_VAL
L_CAUSE
IEC05000339 V2 EN
Figure 269: SXSWI function block

Table 280: SXSWI Input signals
LR_SWI BOOLEAN 0 Local/Remote switch indication from switchyard
OPEN BOOLEAN 0 Pulsed signal used to immediately open the switch
CLOSE BOOLEAN 0 Pulsed signal used to immediately close the switch
BL_OPEN BOOLEAN 0 Signal to block the open command
BL_CLOSE BOOLEAN 0 Signal to block the close command
BL_UPD BOOLEAN 0 Steady signal for block of the position updating
POSOPEN BOOLEAN 0 Signal for open position of apparatus from I/O
524
Control

POSCLOSE BOOLEAN 0 Signal for close position of apparatus from I/O
RS_CNT BOOLEAN 0 Resets the operation counter
XIN BOOLEAN 0 Execution information from CSWI
Table 281: SXSWI Output signals

XPOS GROUP SIGNAL Group signal for XSWI output
EXE_OP BOOLEAN Executes the command for open direction
EXE_CL BOOLEAN Executes the command for close direction
SUBSTED BOOLEAN Indication that the position is substituted
OP_BLKD BOOLEAN Indication that the function is blocked for open
commands
CL_BLKD BOOLEAN Indication that the function is blocked for close
commands
UPD_BLKD BOOLEAN Update of position indication is blocked
POSITION INTEGER Apparatus position indication
OPENPOS BOOLEAN Apparatus open position
CLOSEPOS BOOLEAN Apparatus closed position
CNT_VAL INTEGER Operation counter value

Table 282: SXSWI Non group settings (basic)
tStartMove 0.000 - 60.000 s 0.001 3.000 Supervision time for the apparatus to
move after a command
tIntermediate 0.000 - 60.000 s 0.001 15.000 Allowed time for intermediate position
AdaptivePulse Not adaptive - - Not adaptive Output resets when a new correct end
Adaptive position is reached
tOpenPulse 0.000 - 60.000 s 0.001 0.200 Output pulse length for open command
tClosePulse 0.000 - 60.000 s 0.001 0.200 Output pulse length for close command
SwitchType Load Break - - Disconnector 1=LoadBreak,2=Disconnector,
Disconnector 3=EarthSw,4=HighSpeedEarthSw
Earthing Switch
HS Earthing Switch
SuppressMidPos Off - - On Mid-position is suppressed during the
On time tIntermediate
12.2.8 Bay reserve QCRSV
525
Control
The purpose of the reservation function is primarily to transfer interlocking

information between IEDs in a safe way and to prevent double operation in a bay,
switchyard part, or complete substation.
The Bay reserve (QCRSV) function handles the reservation. QCRSV function
starts to operate in two ways. It starts when there is a request for reservation of the
own bay or if there is a request for reservation from another bay. It is only possible
to reserve the function if it is not currently reserved. The signal that can reserve the
own bay is the input signal RES_RQx (x=1-8) coming from switch controller
(SCWI). The signals for request from another bay are the outputs RE_RQ_B and
V_RE_RQ from function block RESIN. These signals are included in signal
EXCH_OUT from RESIN and are connected to RES_DATA in QCRSV.
The parameters ParamRequestx (x=1-8) are chosen at reservation of the own bay
only (TRUE) or other bays (FALSE). To reserve the own bay only means that no
reservation request RES_BAYS is created.
Reservation request of own bay

If the reservation request comes from the own bay, the function QCRSV has to
know which apparatus the request comes from. This information is available with
the input signal RES_RQx and parameter ParamRequestx (where x=1-8 is the
number of the requesting apparatus). In order to decide if a reservation request of
the current bay can be permitted QCRSV has to know whether the own bay already
is reserved by itself or another bay. This information is available in the output
signal RESERVED.
If the RESERVED output is not set, the selection is made with the output
RES_GRTx (where x=1-8 is the number of the requesting apparatus), which is
connected to switch controller SCSWI. If the bay already is reserved the command
sequence will be reset and the SCSWI will set the attribute "1-of-n-control" in the
"cause" signal.
Reservation of other bays

When the function QCRSV receives a request from an apparatus in the own bay
that requires other bays to be reserved as well, it checks if it already is reserved. If
not, it will send a request to the other bays that are predefined (to be reserved) and
wait for their response (acknowledge). The request of reserving other bays is done
by activating the output RES_BAYS.
When it receives acknowledge from the bays via the input RES_DATA, it sets the
output RES_GRTx (where x=1-8 is the number of the requesting apparatus). If not
acknowledgement from all bays is received within a certain time defined in SCSWI
(tResResponse), the SCSWI will reset the reservation and set the attribute "1-of-n-
control" in the "cause" signal.
526
Control
Reservation request from another bay

When another bay requests for reservation, the input BAY_RES in corresponding
function block RESIN is activated. The signal for reservation request is grouped
into the output signal EXCH_OUT in RESIN, which is connected to input
RES_DATA in QCRSV. If the bay is not reserved, the bay will be reserved and the
acknowledgment from output ACK_T_B is sent back to the requested bay. If the
bay already is reserved the reservation is kept and no acknowledgment is sent.
Blocking and overriding of reservation

If QCRSV function is blocked (input BLK_RES is set to true) the reservation is
blocked. That is, no reservation can be made from the own bay or any other bay.
This can be set, for example, via a binary input from an external device to prevent
operations from another operator place at the same time.
The reservation function can also be overridden in the own bay with the
OVERRIDE input signal, that is, reserving the own bay without waiting for the
external acknowledge.
Bay with more than eight apparatuses

If only one instance of QCRSV is used for a bay that is, use of up to eight
apparatuses, the input EXCH_IN must be set to FALSE.
If there are more than eight apparatuses in the bay there has to be one additional
QCRSV. The two QCRSV functions have to communicate and this is done through
the input EXCH_IN and EXCH_OUT according to figure 270. If more then one
QCRSV are used, the execution order is very important. The execution order must
be in the way that the first QCRSV has a lower number than the next one.
527
Control
QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_RQ2 RES_GRT3
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6
RES_RQ6 RES_GRT7
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
BLK_RES ACK_TO_B
OVERRIDE RESERVED
RES_DATA EXCH_OUT
QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_BAYS
RES_RQ2 RES_GRT3 ³1
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6 ACK_TO_B
RES_RQ6 RES_GRT7 ³1
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
BLK_RES ACK_TO_B RESERVED
³1
OVERRIDE RESERVED
RES_DATA EXCH_OUT
IEC05000088 V2 EN
Figure 270: Connection of two QCRSV function blocks

QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_RQ2 RES_GRT3
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6
RES_RQ6 RES_GRT7
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
BLK_RES ACK_TO_B
OVERRIDE RESERVED
RES_DATA EXCH_OUT
IEC05000340 V2 EN
Figure 271: QCRSV function block
528
Control

Table 283: QCRSV Input signals
EXCH_IN INTEGER 0 Used for exchange signals between different
BayRes blocks
RES_RQ1 BOOLEAN 0 Signal for app. 1 that requests to do a reservation
BLK_RES BOOLEAN 0 Reservation is not possible and the output signals
are reset
OVERRIDE BOOLEAN 0 Signal to override the reservation
RES_DATA INTEGER 0 Reservation data coming from function block ResIn
Table 284: QCRSV Output signals

RES_GRT1 BOOLEAN Reservation is made and the app. 1 is allowed to
operate
operate
operate
operate
operate
operate
operate
operate
RES_BAYS BOOLEAN Request for reservation of other bays
ACK_TO_B BOOLEAN Acknowledge to other bays that this bay is reserved
RESERVED BOOLEAN Indicates that the bay is reserved
EXCH_OUT INTEGER Used for exchange signals between different
BayRes blocks
529
Control

Table 285: QCRSV Non group settings (basic)
tCancelRes 0.000 - 60.000 s 0.001 10.000 Supervision time for canceling the
reservation
ParamRequest1 Other bays res. - - Only own bay res. Reservation of the own bay only, at
Only own bay res. selection of apparatus 1
12.2.9 Reservation input RESIN
The Reservation input (RESIN) function receives the reservation information from
other bays. The number of instances is the same as the number of involved bays
(up to 60 instances are available).
The reservation input (RESIN) function is based purely on Boolean logic

conditions. The logic diagram in figure 272 shows how the output signals are
created. The inputs of the function block are connected to a receive function block
representing signals transferred over the station bus from another bay.
530
Control
EXCH_IN INT
BIN
ACK_F_B
&
FutureUse
³1
ANY_ACK
BAY_ACK ³1
VALID_TX
&
BAY_VAL ³1
RE_RQ_B
³1
BAY_RES &
V _RE_RQ
³1
BIN
EXCH_OUT
INT
en05000089.vsd
IEC05000089 V1 EN
Figure 272: Logic diagram for RESIN
Figure 273 describes the principle of the data exchange between all RESIN
modules in the current bay. There is one RESIN function block per "other bay"
used in the reservation mechanism. The output signal EXCH_OUT in the last
RESIN functions are connected to the module bay reserve (QCRSV) that handles
the reservation function in the own bay. The value to the input EXCH_IN on the
first RESIN module in the chain has the integer value 5. This is provided by the use
of instance number one of the function block RESIN, where the input EXCH_IN is
set to #5, but is hidden for the user.
531
Control
RESIN
BAY_ACK ACK_F_B
Bay 1 BAY_VAL ANY_ACK
BAY_RES VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
RESIN
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
Bay 2 BAY_VAL VALID_TX
BAY_RES RE_RQ_B
V_RE_RQ
EXCH_OUT
RESIN
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
Bay n BAY_VAL VALID_TX
BAY_RES RE_RQ_B QCRSV
V_RE_RQ
EXCH_OUT RES_DATA
en05000090.vsd
IEC05000090 V2 EN
Figure 273: Diagram of the chaining principle for RESIN

RESIN1
BAY_ACK ACK_F_B
BAY_VAL ANY_ACK
BAY_RES VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
IEC05000341 V2 EN
Figure 274: RESIN1 function block
RESIN2
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
BAY_VAL VALID_TX
BAY_RES RE_RQ_B
V_RE_RQ
EXCH_OUT
IEC09000807 V1 EN
Figure 275: RESIN2 function block
532
Control

Table 286: RESIN1 Input signals
BAY_ACK BOOLEAN 0 Another bay has acknow. the reservation req.
from this bay
BAY_VAL BOOLEAN 0 The reserv. and acknow. signals from another
bay are valid
BAY_RES BOOLEAN 0 Request from other bay to reserve this bay
Table 287: RESIN1 Output signals

ACK_F_B BOOLEAN All other bays have acknow. the reserv. req. from
this bay
ANY_ACK BOOLEAN Any other bay has acknow. the reserv. req. from
this bay
VALID_TX BOOLEAN The reserv. and acknow. signals from other bays
are valid
RE_RQ_B BOOLEAN Request from other bay to reserve this bay
V_RE_RQ BOOLEAN Check if the request of reserving this bay is valid
ResIn blocks
Table 288: RESIN2 Input signals

EXCH_IN INTEGER 5 Used for exchange signals between different
ResIn blocks
BAY_ACK BOOLEAN 0 Another bay has acknow. the reservation req.
from this bay
BAY_VAL BOOLEAN 0 The reserv. and acknow. signals from another
bay are valid
BAY_RES BOOLEAN 0 Request from other bay to reserve this bay
Table 289: RESIN2 Output signals

ACK_F_B BOOLEAN All other bays have acknow. the reserv. req. from
this bay
ANY_ACK BOOLEAN Any other bay has acknow. the reserv. req. from
this bay
VALID_TX BOOLEAN The reserv. and acknow. signals from other bays
are valid
RE_RQ_B BOOLEAN Request from other bay to reserve this bay
V_RE_RQ BOOLEAN Check if the request of reserving this bay is valid
ResIn blocks
533
Control

Table 290: RESIN1 Non group settings (basic)
FutureUse Bay in use - - Bay in use The bay for this ResIn block is for future
Bay future use use
Table 291: RESIN2 Non group settings (basic)

FutureUse Bay in use - - Bay in use The bay for this ResIn block is for future
Bay future use use
12.3 Interlocking
12.3.1 Introduction
The interlocking functionality blocks the possibility to operate high-voltage
switching devices, for instance when a disconnector is under load, in order to
prevent material damage and/or accidental human injury.
Each control IED has interlocking functions for different switchyard arrangements,
each handling the interlocking of one bay. The interlocking functionality in each
IED is not dependent on any central function. For the station-wide interlocking, the
IEDs communicate via the station bus or by using hard wired binary inputs/outputs.
The interlocking conditions depend on the circuit configuration and status of the
system at any given time.

The interlocking function consists of software modules located in each control
IED. The function is distributed and not dependent on any central function.
Communication between modules in different bays is performed via the station bus.
The reservation function (see section "Introduction") is used to ensure that HV

apparatuses that might affect the interlock are blocked during the time gap, which
arises between position updates. This can be done by means of the communication
system, reserving all HV apparatuses that might influence the interlocking
condition of the intended operation. The reservation is maintained until the
operation is performed.
After the selection and reservation of an apparatus, the function has complete data
on the status of all apparatuses in the switchyard that are affected by the selection.
Other operators cannot interfere with the reserved apparatus or the status of
switching devices that may affect it.
534
Control
The open or closed positions of the HV apparatuses are inputs to software modules
distributed in the control IEDs. Each module contains the interlocking logic for a
bay. The interlocking logic in a module is different, depending on the bay function
and the switchyard arrangements, that is, double-breaker or 1 1/2 breaker bays have
different modules. Specific interlocking conditions and connections between
standard interlocking modules are performed with an engineering tool. Bay-level
interlocking signals can include the following kind of information:
• Positions of HV apparatuses (sometimes per phase)

• Valid positions (if evaluated in the control module)
• External release (to add special conditions for release)
• Line voltage (to block operation of line earthing switch)
• Output signals to release the HV apparatus
The interlocking module is connected to the surrounding functions within a bay as

Apparatus control
Interlocking
modules
modules in
SCILO SCSWI
other bays SXSWI
Apparatus control
modules
Interlocking SCILO SCSWI SXCBR
module
Apparatus control
modules
en04000526.vsd SCILO SCSWI SXSWI
IEC04000526 V1 EN
Figure 276: Interlocking module on bay level
Bays communicate via the station bus and can convey information regarding the
following:
• Unearthed busbars
• Busbars connected together
• Other bays connected to a busbar
• Received data from other bays is valid
Figure 277 illustrates the data exchange principle.
535
Control
Station bus
Bay 1 Bay n Bus coupler
Disc QB1 and QB2 closed Disc QB1 and QB2 closed WA1 unearthed
WA1 unearthed
WA1 and WA2 interconn
...
WA1 not earthed WA1 not earthed
WA2 not earthed WA2 not earthed WA1 and WA2 interconn
WA1 and WA2 interconn WA1 and WA2 interconn in other bay
..
WA1
WA2
QB1 QB2 QB1 QB2 QB1 QB2 QC1 QC2
QA1 QA1 QA1
QB9 QB9
en05000494.vsd
IEC05000494 V1 EN
Figure 277: Data exchange between interlocking modules
When invalid data such as intermediate position, loss of a control IED, or input
board error are used as conditions for the interlocking condition in a bay, a release
for execution of the function will not be given.
On the local HMI an override function exists, which can be used to bypass the
interlocking function in cases where not all the data required for the condition is valid.
For all interlocking modules these general rules apply:
• The interlocking conditions for opening or closing of disconnectors and

earthing switches are always identical.
• Earthing switches on the line feeder end, for example, rapid earthing switches,
are normally interlocked only with reference to the conditions in the bay where
they are located, not with reference to switches on the other side of the line. So
a line voltage indication may be included into line interlocking modules. If
there is no line voltage supervision within the bay, then the appropriate inputs
must be set to no voltage, and the operator must consider this when operating.
• Earthing switches can only be operated on isolated sections for example,
without load/voltage. Circuit breaker contacts cannot be used to isolate a
section, that is, the status of the circuit breaker is irrelevant as far as the
earthing switch operation is concerned.
• Disconnectors cannot break power current or connect different voltage
systems. Disconnectors in series with a circuit breaker can only be operated if
the circuit breaker is open, or if the disconnectors operate in parallel with other
closed connections. Other disconnectors can be operated if one side is
completely isolated, or if the disconnectors operate in parallel to other closed
connections, or if they are earthed on both sides.
• Circuit breaker closing is only interlocked against running disconnectors in its
bay or additionally in a transformer bay against the disconnectors and earthing
536
Control
switch on the other side of the transformer, if there is no disconnector between

CB and transformer.
• Circuit breaker opening is only interlocked in a bus-coupler bay, if a bus bar
transfer is in progress.
To make the implementation of the interlocking function easier, a number of

standardized and tested software interlocking modules containing logic for the
interlocking conditions are available:
• Line for double and transfer busbars, ABC_LINE

• Bus for double and transfer busbars, ABC_BC
• Transformer bay for double busbars, AB_TRAFO
• Bus-section breaker for double busbars, A1A2_BS
• Bus-section disconnector for double busbars, A1A2_DC
• Busbar earthing switch, BB_ES
• Double CB Bay, DB_BUS_A, DB_LINE, DB_BUS_B
• 1 1/2-CB diameter, BH_LINE_A, BH_CONN, BH_LINE_B
The interlocking conditions can be altered, to meet the customer specific

requirements, by adding configurable logic by means of the graphical configuration
tool PCM600. The inputs Qx_EXy on the interlocking modules are used to add
these specific conditions.
The input signals EXDU_xx shall be set to true if there is no transmission error at
the transfer of information from other bays. Required signals with designations
ending in TR are intended for transfer to other bays.
12.3.3 Logical node for interlocking SCILO
The Logical node for interlocking SCILO function is used to enable a switching
operation if the interlocking conditions permit. SCILO function itself does not
provide any interlocking functionality. The interlocking conditions are generated in
separate function blocks containing the interlocking logic.
The function contains logic to enable the open and close commands respectively if
the interlocking conditions are fulfilled. That means also, if the switch has a
defined end position for example, open, then the appropriate enable signal (in this
case EN_OPEN) is false. The enable signals EN_OPEN and EN_CLOSE can be
true at the same time only in the intermediate and bad position state and if they are
enabled by the interlocking function. The position inputs come from the logical
nodes Circuit breaker/Circuit switch (SXCBR/SXSWI) and the enable signals
537
Control
come from the interlocking logic. The outputs are connected to the logical node
Switch controller (SCSWI). One instance per switching device is needed.
POSOPEN SCILO
POSCLOSE =1 1
EN_OPEN
&
>1
&
OPEN_EN
CLOSE_EN & EN_CLOSE
>1
&
en04000525.vsd
IEC04000525 V1 EN
Figure 278: SCILO function logic diagram

SCILO
POSOPEN EN_OPEN
POSCLOSE EN_CLOSE
OPEN_EN
CLOSE_EN
IEC05000359 V2 EN
Figure 279: SCILO function block

Table 292: SCILO Input signals
POSOPEN BOOLEAN 0 Open position of switch device
POSCLOSE BOOLEAN 0 Closed position of switch device
OPEN_EN BOOLEAN 0 Open operation from interlocking logic is enabled
CLOSE_EN BOOLEAN 0 Close operation from interlocking logic is enabled
Table 293: SCILO Output signals

EN_OPEN BOOLEAN Open operation at closed or interm. or bad pos. is
enabled
EN_CLOSE BOOLEAN Close operation at open or interm. or bad pos. is
enabled
12.3.4 Interlocking for busbar earthing switch BB_ES
538
Control
The interlocking for busbar earthing switch (BB_ES) function is used for one
busbar earthing switch on any busbar parts according to figure 280.
QC
en04000504.vsd
IEC04000504 V1 EN
Figure 280: Switchyard layout BB_ES

BB_ES
QC_OP QCREL
QC_CL QCITL
BB_DC_OP BBESOPTR
VP_BB_DC BBESCLTR
EXDU_BB
IEC05000347 V2 EN
Figure 281: BB_ES function block

BB_ES
VP_BB_DC QCREL
BB_DC_OP QCITL
EXDU_BB & 1
QC_OP BBESOPTR
QC_CL BBESCLTR
en04000546.vsd
IEC04000546 V1 EN

Table 294: BB_ES Input signals
QC_OP BOOLEAN 0 Busbar earthing switch QC is in open position
QC_CL BOOLEAN 0 Busbar earthing switch QC is in closed position
BB_DC_OP BOOLEAN 0 All disconnectors on this busbar part are open
VP_BB_DC BOOLEAN 0 Status for all disconnectors on this busbar part
are valid
EXDU_BB BOOLEAN 0 No transm error from bays with disc on this
busbar part
539
Control
Table 295: BB_ES Output signals

QCREL BOOLEAN Switching of QC is allowed
QCITL BOOLEAN Switching of QC is forbidden
BBESOPTR BOOLEAN QC on this busbar part is in open position
BBESCLTR BOOLEAN QC on this busbar part is in closed position
12.3.5 Interlocking for bus-section breaker A1A2_BS
The interlocking for bus-section breaker (A1A2_BS) function is used for one bus-
section circuit breaker between section 1 and 2 according to figure 282. The
function can be used for different busbars, which includes a bus-section circuit
breaker.
WA1 (A1) WA2 (A2)
QC1 QB1 QB2 QC2
QA1
QC3 QC4
en04000516.vsd
A1A2_BS
IEC04000516 V1 EN
Figure 282: Switchyard layout A1A2_BS
540
Control

A1A2_BS
QA1_OP QA1OPREL
QA1_CL QA1OPITL
QB1_OP QA1CLREL
QB1_CL QA1CLITL
QB2_OP QB1REL
QB2_CL QB1ITL
QC3_OP QB2REL
QC3_CL QB2ITL
QC4_OP QC3REL
QC4_CL QC3ITL
S1QC1_OP QC4REL
S1QC1_CL QC4ITL
S2QC2_OP S1S2OPTR
S2QC2_CL S1S2CLTR
BBTR_OP QB1OPTR
VP_BBTR QB1CLTR
EXDU_12 QB2OPTR
EXDU_ES QB2CLTR
QA1O_EX1 VPS1S2TR
QA1O_EX2 VPQB1TR
QA1O_EX3 VPQB2TR
QB1_EX1
QB1_EX2
QB2_EX1
QB2_EX2
IEC05000348 V2 EN
Figure 283: A1A2_BS function block
541
Control

A1A2_BS
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB2_OP
QB2_CL =1 VPQB2
QC3_OP
QC3_CL =1 VPQC3
QC4_OP
QC4_CL =1 VPQC4
S1QC1_OP
S1QC1_CL =1 VPS1QC1
S2QC2_OP
S2QC2_CL =1 VPS2QC2
VPQB1
QB1_OP QA1OPREL
& >1
QA1O_EX1 QA1OPITL
1
VPQB2
QB2_OP
&
QA1O_EX2
VP_BBTR
BBTR_OP
&
EXDU_12
QA1O_EX3
VPQB1 QA1CLREL
VPQB2 & QA1CLITL
1
VPQA1
VPQC3 QB1REL
& >1
VPQC4 QB1ITL
1
VPS1QC1
QA1_OP
QC3_OP
QC4_OP
S1QC1_OP
EXDU_ES
QB1_EX1
VPQC3
VPS1QC1
&
QC3_CL
S1QC1_CL
EXDU_ES
QB1_EX2
en04000542.vsd
IEC04000542 V1 EN
542
Control
VPQA1
VPQC3 QB2REL
VPQC4 & >1
QB2ITL
VPS2QC2 1
QA1_OP
QC3_OP
QC4_OP
S2QC2_OP
EXDU_ES
QB2_EX1
VPQC4
VPS2QC2
&
QC4_CL
S2QC2_CL
EXDU_ES
QB2_EX2
VPQB1 QC3REL
VPQB2 QC3ITL
QB1_OP & 1
QC4REL
QB2_OP
QC4ITL
1
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB1_OP S1S2OPTR
QB2_OP >1 S1S2CLTR
QA1_OP 1
VPQB1
VPS1S2TR
VPQB2 &
VPQA1
en04000543.vsd
IEC04000543 V1 EN

Table 296: A1A2_BS Input signals
QA1_OP BOOLEAN 0 QA1 is in open position
QA1_CL BOOLEAN 0 QA1 is in closed position
QB1_OP BOOLEAN 0 QB1 is in open position
QB1_CL BOOLEAN 0 QB1 is in closed position
QC3_OP BOOLEAN 0 QC3 is in open position
QC3_CL BOOLEAN 0 QC3 is in closed position
S1QC1_OP BOOLEAN 0 QC1 on bus section 1 is in open position
S1QC1_CL BOOLEAN 0 QC1 on bus section 1 is in closed position
BBTR_OP BOOLEAN 0 No busbar transfer is in progress
VP_BBTR BOOLEAN 0 Status are valid for app. involved in the busbar
transfer
543
Control

EXDU_12 BOOLEAN 0 No transm error from any bay connected to
busbar 1 and 2
EXDU_ES BOOLEAN 0 No transm error from bays containing earth. sw.
QC1 or QC2
QA1O_EX1 BOOLEAN 0 External open condition for apparatus QA1
QB1_EX1 BOOLEAN 0 External condition for apparatus QB1
Table 297: A1A2_BS Output signals

QA1OPREL BOOLEAN Opening of QA1 is allowed
QA1OPITL BOOLEAN Opening of QA1 is forbidden
QA1CLREL BOOLEAN Closing of QA1 is allowed
QA1CLITL BOOLEAN Closing of QA1 is forbidden
QB1REL BOOLEAN Switching of QB1 is allowed
QB1ITL BOOLEAN Switching of QB1 is forbidden
QC3REL BOOLEAN Switching of QC3 is allowed
QC3ITL BOOLEAN Switching of QC3 is forbidden
S1S2OPTR BOOLEAN No bus section connection between bus section 1
and 2
S1S2CLTR BOOLEAN Bus coupler connection between bus section 1
and 2 exists
QB1OPTR BOOLEAN QB1 is in open position
QB1CLTR BOOLEAN QB1 is in closed position
VPS1S2TR BOOLEAN Status of the app. between bus section 1 and 2
are valid
VPQB1TR BOOLEAN Switch status of QB1 is valid (open or closed)
12.3.6 Interlocking for bus-section disconnector A1A2_DC
544
Control
The interlocking for bus-section disconnector (A1A2_DC) function is used for one
bus-section disconnector between section 1 and 2 according to figure 284.
A1A2_DC function can be used for different busbars, which includes a bus-section
disconnector.
QB
WA1 (A1) WA2 (A2)
QC1 QC2
A1A2_DC en04000492.vsd
IEC04000492 V1 EN
Figure 284: Switchyard layout A1A2_DC

A1A2_DC
QB_OP QBOPREL
QB_CL QBOPITL
S1QC1_OP QBCLREL
S1QC1_CL QBCLITL
S2QC2_OP DCOPTR
S2QC2_CL DCCLTR
S1DC_OP VPDCTR
S2DC_OP
VPS1_DC
VPS2_DC
EXDU_ES
EXDU_BB
QBCL_EX1
QBCL_EX2
QBOP_EX1
QBOP_EX2
QBOP_EX3
IEC05000349 V2 EN
Figure 285: A1A2_DC function block
545
Control

A1A2_DC
QB_OP
VPQB VPDCTR
QB_CL =1
DCOPTR
DCCLTR
S1QC1_OP
VPS1QC1
S1QC1_CL =1
S2QC2_OP
VPS2QC2
S2QC2_CL =1
VPS1QC1
VPS2QC2
VPS1_DC & >1 QBOPREL
S1QC1_OP QBOPITL
1
S2QC2_OP
S1DC_OP
EXDU_ES
EXDU_BB
QBOP_EX1
VPS1QC1
VPS2QC2
VPS2_DC &
S1QC1_OP
S2QC2_OP
S2DC_OP
EXDU_ES
EXDU_BB
QBOP_EX2
VPS1QC1
VPS2QC2
S1QC1_CL &
S2QC2_CL
EXDU_ES
QBOP_EX3
en04000544.vsd
IEC04000544 V1 EN
IEC04000545 V1 EN

Table 298: A1A2_DC Input signals
QB_OP BOOLEAN 0 QB is in open position
QB_CL BOOLEAN 0 QB is in closed position
546
Control

S1DC_OP BOOLEAN 0 All disconnectors on bus section 1 are in open
position
S2DC_OP BOOLEAN 0 All disconnectors on bus section 2 are in open
position
VPS1_DC BOOLEAN 0 Switch status of disconnectors on bus section 1
are valid
VPS2_DC BOOLEAN 0 Switch status of disconnectors on bus section 2
are valid
EXDU_ES BOOLEAN 0 No transm error from bays containing earth. sw.
QC1 or QC2
EXDU_BB BOOLEAN 0 No transm error from bays with disc conn to
section 1 and 2
QBCL_EX1 BOOLEAN 0 External close condition for section disconnector
QB
QBCL_EX2 BOOLEAN 0 External close condition for section disconnector
QB
QBOP_EX1 BOOLEAN 0 External open condition for section disconnector
QB
QB
QB
Table 299: A1A2_DC Output signals

QBOPREL BOOLEAN Opening of QB is allowed
QBOPITL BOOLEAN Opening of QB is forbidden
QBCLREL BOOLEAN Closing of QB is allowed
QBCLITL BOOLEAN Closing of QB is forbidden
DCOPTR BOOLEAN The bus section disconnector is in open position
DCCLTR BOOLEAN The bus section disconnector is in closed position
VPDCTR BOOLEAN Switch status of QB is valid (open or closed)
12.3.7 Interlocking for bus-coupler bay ABC_BC
The interlocking for bus-coupler bay (ABC_BC) function is used for a bus-coupler
bay connected to a double busbar arrangement according to figure 286. The
function can also be used for a single busbar arrangement with transfer busbar or
double busbar arrangement without transfer busbar.
547
Control
WA1 (A)
WA2 (B)
WA7 (C)
QB1 QB2 QB20 QB7
QC1
QA1
QC2
en04000514.vsd
IEC04000514 V1 EN
Figure 286: Switchyard layout ABC_BC

ABC_BC
QA1_OP QA1OPREL
QA1_CL QA1OPITL
QB1_OP QA1CLREL
QB1_CL QA1CLITL
QB2_OP QB1REL
QB2_CL QB1ITL
QB7_OP QB2REL
QB7_CL QB2ITL
QB20_OP QB7REL
QB20_CL QB7ITL
QC1_OP QB20REL
QC1_CL QB20ITL
QC2_OP QC1REL
QC2_CL QC1ITL
QC11_OP QC2REL
QC11_CL QC2ITL
QC21_OP QB1OPTR
QC21_CL QB1CLTR
QC71_OP QB220OTR
QC71_CL QB220CTR
BBTR_OP QB7OPTR
BC_12_CL QB7CLTR
VP_BBTR QB12OPTR
VP_BC_12 QB12CLTR
EXDU_ES BC12OPTR
EXDU_12 BC12CLTR
EXDU_BC BC17OPTR
QA1O_EX1 BC17CLTR
QA1O_EX2 BC27OPTR
QA1O_EX3 BC27CLTR
QB1_EX1 VPQB1TR
QB1_EX2 VQB220TR
QB1_EX3 VPQB7TR
QB2_EX1 VPQB12TR
QB2_EX2 VPBC12TR
QB2_EX3 VPBC17TR
QB20_EX1 VPBC27TR
QB20_EX2
QB7_EX1
QB7_EX2
IEC05000350 V2 EN
Figure 287: ABC_BC function block
548
Control

ABC_BC
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB20_OP
QB20_CL =1 VPQB20
QB7_OP
QB7_CL =1 VPQB7
QB2_OP
QB2_CL =1 VPQB2
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
QC71_OP
QC71_CL =1 VPQC71
VPQB1
QB1_OP QA1OPREL
& >1 QA1OPITL
QA1O_EX1 1
VPQB20
QB20_OP &
QA1O_EX2
VP_BBTR
BBTR_OP &
EXDU_12
QA1O_EX3
VPQB1 QA1CLREL
VPQB2 QA1CLITL
VPQB7 & 1
VPQB20
en04000533.vsd
IEC04000533 V1 EN
VPQA1
VPQB2 QB1REL
& >1
VPQC1 QB1ITL
VPQC2 1
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2
VP_BC_12
&
QB2_CL
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX3
en04000534.vsd
IEC04000534 V1 EN
549
Control
VPQA1
VPQB1 QB2REL
& >1
VPQC1 QB2ITL
VPQC2 1
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1
VP_BC_12
&
QB1_CL
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1
VPQC21
&
QC1_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000535.vsd
IEC04000535 V1 EN
VPQA1
VPQB20 QB7REL
& >1
VPQC1 QB7ITL
VPQC2 1
VPQC71
QA1_OP
QB20_OP
QC1_OP
QC2_OP
QC71_OP
EXDU_ES
QB7_EX1
VPQC2
VPQC71
&
QC2_CL
QC71_CL
EXDU_ES
QB7_EX2
VPQA1
VPQB7 QB20REL
& >1
VPQC1 QB20ITL
VPQC2 1
VPQC21
QA1_OP
QB7_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB20_EX1
VPQC2
VPQC21
&
QC2_CL
QC21_CL
EXDU_ES
QB20_EX2
en04000536.vsd
IEC04000536 V1 EN
550
Control
VPQB1 QC1REL
VPQB20 QC1ITL
& 1
VPQB7
QC2REL
VPQB2
QB1_OP QC2ITL
1
QB20_OP
QB7_OP
QB2_OP
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB20_OP QB220OTR
QB2_OP & QB220CTR
VPQB20 1
VQB220TR
VPQB2 &
QB7_OP QB7OPTR
QB7_CL QB7CLTR
VPQB7 VPQB7TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
QA1_OP BC12OPTR
QB1_OP >1 BC12CLTR
QB20_OP 1
VPQA1
VPBC12TR
VPQB1 &
VPQB20
QA1_OP BC17OPTR
QB1_OP >1 BC17CLTR
QB7_OP 1
VPQA1
VPBC17TR
VPQB1 &
VPQB7
QA1_OP BC27OPTR
QB2_OP >1 BC27CLTR
QB7_OP 1
VPQA1
VPBC27TR
VPQB2 &
VPQB7
en04000537.vsd
IEC04000537 V1 EN

Table 300: ABC_BC Input signals
QC11_OP BOOLEAN 0 Earthing switch QC11 on busbar WA1 is in open
position
551
Control

QC11_CL BOOLEAN 0 Earthing switch QC11 on busbar WA1 is in closed
position
position
position
position
position
BBTR_OP BOOLEAN 0 No busbar transfer is in progress
BC_12_CL BOOLEAN 0 A bus coupler connection exists between busbar
WA1 and WA2
VP_BBTR BOOLEAN 0 Status are valid for app. involved in the busbar
transfer
VP_BC_12 BOOLEAN 0 Status of the bus coupler app. between WA1 and
WA2 are valid
EXDU_ES BOOLEAN 0 No transm error from any bay containing earthing
switches
EXDU_12 BOOLEAN 0 No transm error from any bay connected to WA1/
WA2 busbars
EXDU_BC BOOLEAN 0 No transmission error from any other bus coupler
bay
Table 301: ABC_BC Output signals

QA1OPREL BOOLEAN Opening of QA1 is allowed
QA1OPITL BOOLEAN Opening of QA1 is forbidden
552
Control

QB220OTR BOOLEAN QB2 and QB20 are in open position
QB220CTR BOOLEAN QB2 or QB20 or both are not in open position
QB12OPTR BOOLEAN QB1 or QB2 or both are in open position
QB12CLTR BOOLEAN QB1 and QB2 are not in open position
BC12OPTR BOOLEAN No connection via the own bus coupler between
WA1 and WA2
BC12CLTR BOOLEAN Conn. exists via the own bus coupler between
WA1 and WA2
WA1 and WA7
WA1 and WA7
WA2 and WA7
WA2 and WA7
VQB220TR BOOLEAN Switch status of QB2 and QB20 are valid (open
or closed)
VPQB12TR BOOLEAN Switch status of QB1 and QB2 are valid (open or
closed)
VPBC12TR BOOLEAN Status of the bus coupler app. between WA1 and
WA2 are valid
WA7 are valid
WA7 are valid
553
Control
12.3.8 Interlocking for 1 1/2 CB BH
The interlocking for 1 1/2 breaker diameter (BH_CONN, BH_LINE_A,

BH_LINE_B) functions are used for lines connected to a 1 1/2 breaker diameter
according to figure 288.
WA1 (A)
WA2 (B)
QB1 QB2
QC1 QC1
QA1 QA1
QC2 QC2
QB6 QB6
QC3 QC3
BH_LINE_A BH_LINE_B
QB61 QA1 QB62
QB9 QB9
QC1 QC2
QC9 QC9
BH_CONN
en04000513.vsd
IEC04000513 V1 EN
Figure 288: Switchyard layout 1 1/2 breaker
Three types of interlocking modules per diameter are defined. BH_LINE_A and
BH_LINE_B are the connections from a line to a busbar. BH_CONN is the
connection between the two lines of the diameter in the 1 1/2 breaker switchyard
layout.
554
Control
12.3.8.2 Function blocks

BH_LINE_A
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB6_OP QB6REL
QB6_CL QB6ITL
QB1_OP QB1REL
QB1_CL QB1ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC3_OP QC3REL
QC3_CL QC3ITL
QB9_OP QB9REL
QB9_CL QB9ITL
QC9_OP QC9REL
QC9_CL QC9ITL
CQA1_OP QB1OPTR
CQA1_CL QB1CLTR
CQB61_OP VPQB1TR
CQB61_CL
CQC1_OP
CQC1_CL
CQC2_OP
CQC2_CL
QC11_OP
QC11_CL
VOLT_OFF
VOLT_ON
EXDU_ES
QB6_EX1
QB6_EX2
QB1_EX1
QB1_EX2
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9_EX6
QB9_EX7
IEC05000352 V2 EN
Figure 289: BH_LINE_A function block
555
Control
BH_LINE_B
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB6_OP QB6REL
QB6_CL QB6ITL
QB2_OP QB2REL
QB2_CL QB2ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC3_OP QC3REL
QC3_CL QC3ITL
QB9_OP QB9REL
QB9_CL QB9ITL
QC9_OP QC9REL
QC9_CL QC9ITL
CQA1_OP QB2OPTR
CQA1_CL QB2CLTR
CQB62_OP VPQB2TR
CQB62_CL
CQC1_OP
CQC1_CL
CQC2_OP
CQC2_CL
QC21_OP
QC21_CL
VOLT_OFF
VOLT_ON
EXDU_ES
QB6_EX1
QB6_EX2
QB2_EX1
QB2_EX2
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9_EX6
QB9_EX7
IEC05000353 V2 EN
Figure 290: BH_LINE_B function block
BH_CONN
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB61_OP QB61REL
QB61_CL QB61ITL
QB62_OP QB62REL
QB62_CL QB62ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
1QC3_OP
1QC3_CL
2QC3_OP
2QC3_CL
QB61_EX1
QB61_EX2
QB62_EX1
QB62_EX2
IEC05000351 V2 EN
Figure 291: BH_CONN function block
556
Control

BH_CONN
QA1_OP
QA1_CL =1 VPQA1
QB61_OP
QB61_CL =1 VPQB61
QB62_OP
QB62_CL =1 VPQB62
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
1QC3_OP
1QC3_CL =1 VP1QC3
2QC3_OP
2QC3_CL =1 VP2QC3
VPQB61 QA1CLREL
VPQB62 & QA1CLITL
1
VPQA1
VPQC1 QB61REL
& >1
VPQC2 QB61ITL
1
VP1QC3
QA1_OP
QC1_OP
QC2_OP
1QC3_OP
QB61_EX1
VPQC1
VP1QC3
&
QC1_CL
1QC3_CL
QB61_EX2
VPQA1
VPQC1 QB62REL
& >1
VPQC2 QB62ITL
1
VP2QC3
QA1_OP
QC1_OP
QC2_OP
2QC3_OP
QB62_EX1
VPQC2
VP2QC3
&
QC2_CL
2QC3_CL
QB62_EX2
VPQB61 QC1REL
VPQB62 QC1ITL
& 1
QB61_OP QC2REL
QB62_OP QC2ITL
1
en04000560.vsd
IEC04000560 V1 EN
557
Control
BH_LINE_A
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB6_OP
QB6_CL =1 VPQB6
QC9_OP
QC9_CL =1 VPQC9
QB9_OP
QB9_CL =1 VPQB9
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
CQA1_OP
CQA1_CL =1 VPCQA1
CQC1_OP
CQC1_CL =1 VPCQC1
CQC2_OP
CQC2_CL =1 VPCQC2
CQB61_OP
CQB61_CL =1 VPCQB61
QC11_OP
QC11_CL =1 VPQC11
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQB1 QA1CLREL
VPQB6 QA1CLITL
& 1
VPQB9
VPQA1
VPQC1 QB6REL
VPQC2 & >1
QB6ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB6_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB6_EX2
en04000554.vsd
IEC04000554 V1 EN
558
Control
VPQA1
VPQC1 QB1REL
VPQC2 & >1
QB1ITL
1
VPQC11
QA1_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX2
VPQB1 QC1REL
VPQB6 QC1ITL
QB1_OP & 1
QC2REL
QB6_OP QC2ITL
VPQB6 1
VPQB9 QC3REL
VPCQB61 &
QC3ITL
1
QB6_OP
QB9_OP
CQB61_OP
VPQA1 QB9REL
VPQB6 QB9ITL
VPQC9 & >1 1
VPQC1
VPQC2
VPQC3
VPCQA1
VPCQB61
VPCQC1
VPCQC2
QB9_EX1
QB6_OP
QB9_EX2
>1
QA1_OP
QC1_OP
QC2_OP &
QB9_EX3
en04000555.vsd
IEC04000555 V1 EN
CQB61_OP
QB9_EX4
>1 & >1
CQA1_OP
CQC1_OP
CQC2_OP &
QB9_EX5
QC9_OP
QC3_OP
QB9_EX6
VPQC9
VPQC3
&
QC9_CL
QC3_CL
QB9_EX7
VPQB9 QC9REL
VPVOLT QC9ITL
QB9_OP & 1
VOLT_OFF
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
en04000556.vsd
IEC04000556 V1 EN
559
Control
BH_LINE_B
QA1_OP
QA1_CL =1 VPQA1
QB2_OP
QB2_CL =1 VPQB2
QB6_OP
QB6_CL =1 VPQB6
QC9_OP
QC9_CL =1 VPQC9
QB9_OP
QB9_CL =1 VPQB9
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
CQA1_OP
CQA1_CL =1 VPCQA1
CQC1_OP
CQC1_CL =1 VPCQC1
CQC2_OP
CQC2_CL =1 VPCQC2
CQB62_OP
CQB62_CL =1 VPCQB62
QC21_OP
QC21_CL =1 VPQC21
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQB2 QA1CLREL
VPQB6 QA1CLITL
& 1
VPQB9
VPQA1
VPQC1 QB6REL
VPQC2 & >1
QB6ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB6_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB6_EX2
en04000557.vsd
IEC04000557 V1 EN
560
Control
VPQA1
VPQC1 QB2REL
VPQC2 & >1
QB2ITL
1
VPQC21
QA1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQC1
VPQC21
&
QC1_CL
QC21_CL
EXDU_ES
QB2_EX2
VPQB2 QC1REL
VPQB6 QC1ITL
QB2_OP & 1
QC2REL
QB6_OP QC2ITL
VPQB6 1
VPQB9 QC3REL
VPCQB62 &
QC3ITL
1
QB6_OP
QB9_OP
CQB62_OP
VPQA1 QB9REL
VPQB6 QB9ITL
VPQC9 & >1 1
VPQC1
VPQC2
VPQC3
VPCQA1
VPCQB62
VPCQC1
VPCQC2
QB9_EX1
QB6_OP
QB9_EX2
>1
QA1_OP
QC1_OP
QC2_OP &
QB9_EX3
en04000558.vsd
IEC04000558 V1 EN
CQB62_OP
QB9_EX4
>1 & >1
CQA1_OP
CQC1_OP
CQC2_OP &
QB9_EX5
QC9_OP
QC3_OP
QB9_EX6
VPQC9
VPQC3
&
QC9_CL
QC3_CL
QB9_EX7
VPQB9 QC9REL
VPVOLT QC9ITL
QB9_OP & 1
VOLT_OFF
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
en04000559.vsd
IEC04000559 V1 EN
561
Control

Table 302: BH_LINE_A Input signals
QB6_CL BOOLEAN 0 QB6 is in close position
CQA1_OP BOOLEAN 0 QA1 in module BH_CONN is in open position
CQA1_CL BOOLEAN 0 QA1 in module BH_CONN is in closed position
CQB61_OP BOOLEAN 0 QB61 in module BH_CONN is in open position
CQB61_CL BOOLEAN 0 QB61 in module BH_CONN is in closed position
CQC1_OP BOOLEAN 0 QC1 in module BH_CONN is in open position
CQC1_CL BOOLEAN 0 QC1 in module BH_CONN is in closed position
position
position
VOLT_OFF BOOLEAN 0 There is no voltage on line and not VT (fuse) failure
VOLT_ON BOOLEAN 0 There is voltage on the line or there is a VT (fuse)
failure
EXDU_ES BOOLEAN 0 No transm error from bay containing earthing
switch QC11
562
Control

Table 303: BH_LINE_A Output signals

Table 304: BH_LINE_B Input signals

QB6_CL BOOLEAN 0 QB6 is in close position
563
Control

CQA1_OP BOOLEAN 0 QA1 in module BH_CONN is in open position
CQA1_CL BOOLEAN 0 QA1 in module BH_CONN is in closed position
CQB62_OP BOOLEAN 0 QB62 in module BH_CONN is in open position
CQB62_CL BOOLEAN 0 QB62 in module BH_CONN is in closed position
position
position
VOLT_OFF BOOLEAN 0 There is no voltage on line and not VT (fuse) failure
failure
switch QC21
564
Control
Table 305: BH_LINE_B Output signals

Table 306: BH_CONN Input signals

1QC3_OP BOOLEAN 0 QC3 on line 1 is in open position
1QC3_CL BOOLEAN 0 QC3 on line 1 is in closed position
2QC3_OP BOOLEAN 0 QC3 on line 2 is in open position
2QC3_CL BOOLEAN 0 QC3 on line 2 is in closed position
565
Control

Table 307: BH_CONN Output signals

12.3.9 Interlocking for double CB bay DB
The interlocking for 1 1/2 breaker diameter including DB_BUS_A, DB_BUS_B,

DB_LINEfunctions are used for a line connected to a double circuit breaker
arrangement according to figure 292.
566
Control
WA1 (A)
WA2 (B)
QB1 QB2
QC1 QC4
QA1 QA2
DB_BUS_A DB_BUS_B
QC2 QC5
QB61 QB62
QC3
QB9
DB_LINE
QC9
en04000518.vsd
IEC04000518 V1 EN
Figure 292: Switchyard layout double circuit breaker
Three types of interlocking modules per double circuit breaker bay are defined.
DB_LINE is the connection from the line to the circuit breaker parts that are
connected to the busbars. DB_BUS_A and DB_BUS_B are the connections from
the line to the busbars.

DB_BUS_A
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB1_OP QB61REL
QB1_CL QB61ITL
QB61_OP QB1REL
QB61_CL QB1ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC3_OP QB1OPTR
QC3_CL QB1CLTR
QC11_OP VPQB1TR
QC11_CL
EXDU_ES
QB61_EX1
QB61_EX2
QB1_EX1
QB1_EX2
IEC05000354 V2 EN
Figure 293: DB_BUS_A function block
567
Control
DB_LINE
QA1_OP QB9REL
QA1_CL QB9ITL
QA2_OP QC3REL
QA2_CL QC3ITL
QB61_OP QC9REL
QB61_CL QC9ITL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QB62_OP
QB62_CL
QC4_OP
QC4_CL
QC5_OP
QC5_CL
QB9_OP
QB9_CL
QC3_OP
QC3_CL
QC9_OP
QC9_CL
VOLT_OFF
VOLT_ON
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
IEC05000356 V2 EN
Figure 294: DB_LINE function block
DB_BUS_B
QA2_OP QA2CLREL
QA2_CL QA2CLITL
QB2_OP QB62REL
QB2_CL QB62ITL
QB62_OP QB2REL
QB62_CL QB2ITL
QC4_OP QC4REL
QC4_CL QC4ITL
QC5_OP QC5REL
QC5_CL QC5ITL
QC3_OP QB2OPTR
QC3_CL QB2CLTR
QC21_OP VPQB2TR
QC21_CL
EXDU_ES
QB62_EX1
QB62_EX2
QB2_EX1
QB2_EX2
IEC05000355 V2 EN
Figure 295: DB_BUS_B function block
568
Control

DB_BUS_A
QA1_OP
QA1_CL =1 VPQA1
QB61_OP
QB61_CL =1 VPQB61
QB1_OP
QB1_CL =1 VPQB1
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC3_OP
QC3_CL =1 VPQC3
QC11_OP
QC11_CL =1 VPQC11
VPQB61 QA1CLREL
VPQB1 & QA1CLITL
1
VPQA1
VPQC1 QB61REL
& >1
VPQC2 QB61ITL
1
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB61_EX1
VPQC2
VPQC3
&
QC2_CL
QC3_CL
QB61_EX2
VPQA1
VPQC1 QB1REL
& >1
VPQC2 QB1ITL
1
VPQC11
QA1_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQC1
VPQC11
&
QC1_CL
QC11_CL
EXDU_ES
QB1_EX2
en04000547.vsd
IEC04000547 V1 EN
VPQB61 QC1REL
VPQB1 QC1ITL
& 1
QB61_OP QC2REL
QB1_OP QC2ITL
1
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
en04000548.vsd
IEC04000548 V1 EN
569
Control
DB_BUS_B
QA2_OP
QA2_CL =1 VPQA2
QB62_OP
QB62_CL =1 VPQB62
QB2_OP
QB2_CL =1 VPQB2
QC4_OP
QC4_CL =1 VPQC4
QC5_OP
QC5_CL =1 VPQC5
QC3_OP
QC3_CL =1 VPQC3
QC21_OP
QC21_CL =1 VPQC21
VPQB62 QA2CLREL
VPQB2 & QA2CLITL
1
VPQA2
VPQC4 QB62REL
& >1
VPQC5 QB62ITL
1
VPQC3
QA2_OP
QC4_OP
QC5_OP
QC3_OP
QB62_EX1
VPQC5
VPQC3
&
QC5_CL
QC3_CL
QB62_EX2
VPQA2
VPQC4 QB2REL
& >1
VPQC5 QB2ITL
1
VPQC21
QA2_OP
QC4_OP
QC5_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQC4
VPQC21
&
QC4_CL
QC21_CL
EXDU_ES
QB2_EX2
en04000552.vsd
IEC04000552 V1 EN
VPQB62 QC4REL
VPQB2 QC4ITL
& 1
QB62_OP QC5REL
QB2_OP QC5ITL
1
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
en04000553.vsd
IEC04000553 V1 EN
570
Control
DB_LINE
QA1_OP
QA1_CL =1 VPQA1
QA2_OP
QA2_CL =1 VPQA2
QB61_OP
QB61_CL =1 VPQB61
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QB62_OP
QB62_CL =1 VPQB62
QC4_OP
QC4_CL =1 VPQC4
QC5_OP
QC5_CL =1 VPQC5
QB9_OP
QB9_CL =1 VPQB9
QC3_OP
QC3_CL =1 VPQC3
QC9_OP
QC9_CL =1 VPQC9
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQA1
VPQA2 QB9REL
VPQC1 & >1
QB9ITL
1
VPQC2
VPQC3
VPQC4
VPQC5
VPQC9
QA1_OP
QA2_OP
QC1_OP
QC2_OP
QC3_OP
QC4_OP
QC5_OP
QC9_OP
QB9_EX1
& en04000549.vsd
IEC04000549 V1 EN
VPQA1
VPQC1
VPQC2 & >1
VPQC3
VPQC9
VPQB62
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QC9_OP
QB62_OP
QB9_EX2
VPQA2
VPQB61
&
VPQC3
VPQC4
VPQC5
VPQC9
QA2_OP
QB61_OP
QC3_OP
QC4_OP
QC5_OP
QC9_OP
QB9_EX3
VPQC3
VPQC9
&
VPQB61
VPQB62
QC3_OP
QC9_OP
QB61_OP
QB62_OP
QB9_EX4
VPQC3
VPQC9
&
QC3_CL
QC9_CL
QB9_EX5
en04000550.vsd
IEC04000550 V1 EN
571
Control
VPQB61
VPQB62 QC3REL
VPQB9 &
QC3ITL
1
QB61_OP
QB62_OP
QB9_OP
VPQB9
VPVOLT QC9REL
QB9_OP &
QC9ITL
1
VOLT_OFF
en04000551.vsd
IEC04000551 V1 EN

Table 308: DB_BUS_A Input signals
position
position
switch QC11
Table 309: DB_BUS_A Output signals

572
Control

Table 310: DB_LINE Input signals

VOLT_OFF BOOLEAN 0 There is no voltage on the line and not VT (fuse)
failure
failure
573
Control

Table 311: DB_LINE Output signals

Table 312: DB_BUS_B Input signals

position
position
switch QC21
574
Control
Table 313: DB_BUS_B Output signals

12.3.10 Interlocking for line bay ABC_LINE
The interlocking for line bay (ABC_LINE) function is used for a line connected to
a double busbar arrangement with a transfer busbar according to figure 296. The
function can also be used for a double busbar arrangement without transfer busbar
or a single busbar arrangement with/without transfer busbar.
WA1 (A)
WA2 (B)
WA7 (C)
QB1 QB2 QB7
QC1
QA1
QC2
QB9
QC9
en04000478.vsd
IEC04000478 V1 EN
Figure 296: Switchyard layout ABC_LINE
575
Control

ABC_LINE
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB9_OP QB9REL
QB9_CL QB9ITL
QB1_OP QB1REL
QB1_CL QB1ITL
QB2_OP QB2REL
QB2_CL QB2ITL
QB7_OP QB7REL
QB7_CL QB7ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QC9_OP QC9REL
QC9_CL QC9ITL
QC11_OP QB1OPTR
QC11_CL QB1CLTR
QC21_OP QB2OPTR
QC21_CL QB2CLTR
QC71_OP QB7OPTR
QC71_CL QB7CLTR
BB7_D_OP QB12OPTR
BC_12_CL QB12CLTR
BC_17_OP VPQB1TR
BC_17_CL VPQB2TR
BC_27_OP VPQB7TR
BC_27_CL VPQB12TR
VOLT_OFF
VOLT_ON
VP_BB7_D
VP_BC_12
VP_BC_17
VP_BC_27
EXDU_ES
EXDU_BPB
EXDU_BC
QB9_EX1
QB9_EX2
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
QB7_EX1
QB7_EX2
QB7_EX3
QB7_EX4
IEC05000357 V2 EN
Figure 297: ABC_LINE function block
576
Control
ABC_LINE
QA1_OP
QA1_CL =1 VPQA1
QB9_OP
QB9_CL =1 VPQB9
QA1CLREL
QB1_OP
QB1_CL =1 VPQB1 QA1CLITL
& 1
QB2_OP
QB2_CL =1 VPQB2
QB7_OP
QB7_CL =1 VPQB7
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QC9_OP
QC9_CL =1 VPQC9
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
QC71_OP
QC71_CL =1 VPQC71
VOLT_OFF
VOLT_ON =1 VPVOLT
VPQA1
VPQC1 QB9REL
VPQC2 & >1
QB9ITL
1
VPQC9
QA1_OP
QC1_OP
QC2_OP
QC9_OP
QB9_EX1
VPQC2
VPQC9
&
QC2_CL
QC9_CL
QB9_EX2
en04000527.vsd
IEC04000527 V1 EN
577
Control
VPQA1 QB1REL
& ³1
VPQB2
VPQC1 1 QB1ITL
VPQC2
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2 &
VP_BC_12
QB2_CL
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1 &
VPQC11
QC1_CL
QC11_CL
EXDU_ES
QB1EX3
en04000528.vsd
IEC04000528 V1 EN
578
Control
VPQA1 QB2REL
& ³1
VPQB1
VPQC1 1 QB2ITL
VPQC2
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1 &
VP_BC_12
QB1_CL
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1 &
VPQC21
QC1_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000529.vsd
IEC04000529 V1 EN
579
Control
VPQC9 QB7REL
& >1
VPQC71
VP_BB7_D 1 QB7ITL
VP_BC_17
VP_BC_27
QC9_OP
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_17_OP
BC_27_OP
EXDU_BC
QB7_EX1
VPQA1
VPQB1
VPQC9
&
VPQB9
VPQC71
VP_BB7_D
VP_BC_17
QA1_CL
QB1_CL
QC9_OP
QB9_CL
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_17_CL
EXDU_BC
QB7_EX2
IEC04000530 V1 EN
580
Control
VPQA1
VPQB2
& >1
VPQC9
VPQB9
VPQC71
VP_BB7_D
VP_BC_27
QA1_CL
QB2_CL
QC9_OP
QB9_CL
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_27_CL
EXDU_BC
QB7_EX3
VPQC9
VPQC71
&
QC9_CL
QC71_CL
EXDU_ES
QB7_EX4
VPQB1 QC1REL
VPQB2 QC1ITL
VPQB9 & 1
QC2REL
QB1_OP
QB2_OP QC2ITL
1
QB9_OP
VPQB7
VPQB9 QC9REL
VPVOLT &
QC9ITL
QB7_OP 1
QB9_OP
VOLT_OFF
en04000531.vsd
IEC04000531 V1 EN
581
Control
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB7_OP QB7OPTR
QB7_CL QB7CLTR
VPQB7 VPQB7TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
en04000532.vsd
IEC04000532 V1 EN

Table 314: ABC_LINE Input signals
position
position
position
582
Control

position
position
position
BB7_D_OP BOOLEAN 0 Disconnectors on busbar WA7 except in the own
bay are open
WA1 and WA2
BC_17_OP BOOLEAN 0 No bus coupler connection exists between busbar
WA1 and WA7
WA1 and WA7
BC_27_OP BOOLEAN 0 No bus coupler connection exists between busbar
WA2 and WA7
WA2 and WA7
VOLT_OFF BOOLEAN 0 There is no voltage on the line and not VT (fuse)
failure
failure
VP_BB7_D BOOLEAN 0 Switch status of the disconnectors on busbar
WA7 are valid
WA2 are valid
WA7 are valid
WA7 are valid
switches
EXDU_BPB BOOLEAN 0 No transm error from any bay with disconnectors
on WA7
EXDU_BC BOOLEAN 0 No transmission error from any bus coupler bay
583
Control

Table 315: ABC_LINE Output signals

closed)
12.3.11 Interlocking for transformer bay AB_TRAFO
584
Control
The interlocking for transformer bay (AB_TRAFO) function is used for a

transformer bay connected to a double busbar arrangement according to figure 298.
The function is used when there is no disconnector between circuit breaker and
transformer. Otherwise, the interlocking for line bay (ABC_LINE) function can be
used. This function can also be used in single busbar arrangements.
WA1 (A)
WA2 (B)
QB1 QB2
QC1
QA1
AB_TRAFO
QC2
QC3
QA2
QA2 and QC4 are not
QC4 used in this interlocking
QB3 QB4
en04000515.vsd
IEC04000515 V1 EN
Figure 298: Switchyard layout AB_TRAFO
585
Control

AB_TRAFO
QA1_OP QA1CLREL
QA1_CL QA1CLITL
QB1_OP QB1REL
QB1_CL QB1ITL
QB2_OP QB2REL
QB2_CL QB2ITL
QC1_OP QC1REL
QC1_CL QC1ITL
QC2_OP QC2REL
QC2_CL QC2ITL
QB3_OP QB1OPTR
QB3_CL QB1CLTR
QB4_OP QB2OPTR
QB4_CL QB2CLTR
QC3_OP QB12OPTR
QC3_CL QB12CLTR
QC11_OP VPQB1TR
QC11_CL VPQB2TR
QC21_OP VPQB12TR
QC21_CL
BC_12_CL
VP_BC_12
EXDU_ES
EXDU_BC
QA1_EX1
QA1_EX2
QA1_EX3
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
IEC05000358 V2 EN
Figure 299: AB_TRAFO function block
586
Control

AB_TRAFO
QA1_OP
QA1_CL =1 VPQA1
QB1_OP
QB1_CL =1 VPQB1
QB2_OP
QB2_CL =1 VPQB2
QC1_OP
QC1_CL =1 VPQC1
QC2_OP
QC2_CL =1 VPQC2
QB3_OP
QB3_CL =1 VPQB3
QB4_OP
QB4_CL =1 VPQB4
QC3_OP
QC3_CL =1 VPQC3
QC11_OP
QC11_CL =1 VPQC11
QC21_OP
QC21_CL =1 VPQC21
VPQB1 QA1CLREL
VPQB2 QA1CLITL
VPQC1 & 1
VPQC2
VPQB3
VPQB4
VPQC3
QA1_EX2
QC3_OP
QA1_EX3
QC1_CL >1
QC2_CL
QC3_CL &
QA1_EX1
en04000538.vsd
IEC04000538 V1 EN
VPQA1
VPQB2 QB1REL
& >1
VPQC1 QB1ITL
VPQC2 1
VPQC3
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC3_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2
VPQC3
&
VP_BC_12
QB2_CL
QC3_OP
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1
VPQC2
&
VPQC3
VPQC11
QC1_CL
QC2_CL
QC3_CL
QC11_CL
EXDU_ES
QB1_EX3
en04000539.vsd
IEC04000539 V1 EN
587
Control
VPQA1
VPQB1 QB2REL
& >1
VPQC1 QB2ITL
VPQC2 1
VPQC3
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC3_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1
VPQC3
&
VP_BC_12
QB1_CL
QC3_OP
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1
VPQC2
&
VPQC3
VPQC21
QC1_CL
QC2_CL
QC3_CL
QC21_CL
EXDU_ES
QB2_EX3
en04000540.vsd
IEC04000540 V1 EN
VPQB1 QC1REL
VPQB2 QC1ITL
& 1
VPQB3
QC2REL
VPQB4
QB1_OP QC2ITL
1
QB2_OP
QB3_OP
QB4_OP
QB1_OP QB1OPTR
QB1_CL QB1CLTR
VPQB1 VPQB1TR
QB2_OP QB2OPTR
QB2_CL QB2CLTR
VPQB2 VPQB2TR
QB1_OP QB12OPTR
QB2_OP >1 QB12CLTR
VPQB1 1
VPQB12TR
VPQB2 &
en04000541.vsd
IEC04000541 V1 EN

Table 316: AB_TRAFO Input signals
588
Control

QC11_OP BOOLEAN 0 QC11 on busbar WA1 is in open position
QC11_CL BOOLEAN 0 QC11 on busbar WA1 is in closed position
QC21_OP BOOLEAN 0 QC21 on busbar WA2 is in open position
QC21_CL BOOLEAN 0 QC21 on busbar WA2 is in closed position
WA1 and WA2
WA2 are valid
switches
EXDU_BC BOOLEAN 0 No transmission error from any bus coupler bay
QA1_EX1 BOOLEAN 0 External condition for apparatus QA1
Table 317: AB_TRAFO Output signals

589
Control

closed)
12.3.12 Position evaluation POS_EVAL
Position evaluation (POS_EVAL) function converts the input position data signal
POSITION, consisting of value, time and signal status, to binary signals
OPENPOS or CLOSEPOS.
The output signals are used by other functions in the interlocking scheme.

POS_EVAL
Position including quality POSITION OPENPOS
Open/close position of
CLOSEPOS switch device
IEC08000469-1-EN V1 EN
Only the value, open/close, and status is used in this function. Time information is
not used.
Input position (Value) Signal quality Output OPENPOS Output CLOSEPOS
0 (Breaker Good 0 0
intermediate)
1 (Breaker open) Good 1 0
2 (Breaker closed) Good 0 1
3 (Breaker faulty) Good 0 0
Any Invalid 0 0
Any Oscillatory 0 0
590
Control

POS_EVAL
POSITION OPENPOS
CLOSEPOS
IEC09000079 V1 EN
Figure 300: POS_EVAL function block

Table 318: POS_EVAL Input signals
POSITION INTEGER 0 Position status including quality
Table 319: POS_EVAL Output signals

OPENPOS BOOLEAN Open position
CLOSEPOS BOOLEAN Close position
12.4 Logic rotating switch for function selection and

LHMI presentation SLGGIO

Logic rotating switch for function SLGGIO - -
selection and LHMI presentation
12.4.1 Introduction
The logic rotating switch for function selection and LHMI presentation function
(SLGGIO) (or the selector switch function block) is used to get a selector switch
functionality similar to the one provided by a hardware selector switch. Hardware
selector switches are used extensively by utilities, in order to have different
functions operating on pre-set values. Hardware switches are however sources for
maintenance issues, lower system reliability and an extended purchase portfolio.
The logic selector switches eliminate all these problems.

The logic rotating switch for function selection and LHMI presentation (SLGGIO)
function has two operating inputs – UP and DOWN. When a signal is received on
the UP input, the block will activate the output next to the present activated output,
591
Control
in ascending order (if the present activated output is 3 – for example and one
operates the UP input, then the output 4 will be activated). When a signal is
received on the DOWN input, the block will activate the output next to the present
activated output, in descending order (if the present activated output is 3 – for
example and one operates the DOWN input, then the output 2 will be activated).
Depending on the output settings the output signals can be steady or pulsed. In case
of steady signals, in case of UP or DOWN operation, the previously active output
will be deactivated. Also, depending on the settings one can have a time delay
between the UP or DOWN activation signal positive front and the output activation.
Besides the inputs visible in the application configuration in the Application

Configuration tool, there are other possibilities that will allow an user to set the
desired position directly (without activating the intermediate positions), either
locally or remotely, using a “select before execute” dialog. One can block the
function operation, by activating the BLOCK input. In this case, the present
position will be kept and further operation will be blocked. The operator place
(local or remote) is specified through the PSTO input. If any operation is allowed
the signal INTONE from the Fixed signal function block can be connected.
SLGGIO function block has also an integer value output, that generates the actual
position number. The positions and the block names are fully settable by the user.
These names will appear in the menu, so the user can see the position names
instead of a number.
592
Control
12.4.2.1 Functionality and behaviour
Control
Control Single Line Diagram Ctrl/Com
Measurements Commands Single Command
Events Selector Switch (GGIO)
Disturbance records
Settings
Diagnostics
Test
Reset
Authorization
Language
1 2 3
../Com/Sel Sw/ ../Com/Sel Sw/
../Ctrl/Com/Sel Sw SLGGIO3
SLGGIO1 SLGGIO3
Damage ctrl 4 Damage ctrl 4
SLGGIO2
..
..
SLGGIO15
P:Disc All N: Disc Fe
OK Cancel
4
5
The dialog window that appears
../Com/Sel Sw/ shows the present position (P:)
DmgCtrl 7
and the new position (N:), both
Damage ctrl: in clear names, given by the
user (max. 13 characters).
E
Modify the position with arrows.
The pos will not be modified (outputs
will not be activated) until you press
the E-button for O.K. IEC06000420-2-en.vsd
IEC06000420 V2 EN
Figure 301: Example 1 on handling the switch from the local HMI.
From the local HMI:
1 SLGGIO instances in the ACT application configuration

2 Switch name given by the user (max 13 characters)
3 Position number, up to 32 positions
4 Change position
5 New position
12.4.2.2 Graphical display
There are two possibilities for SLGGIO
593
Control
• if it is used just for the monitoring, the switches will be listed with their actual
position names, as defined by the user (max. 13 characters).
• if it is used for control, the switches will be listed with their actual positions,
but only the first three letters of the name will be used.
In both cases, the switch full name will be shown, but the user has to redefine it
when building the Graphical Display Editor, under the "Caption". If used for the
control, the following sequence of commands will ensure:
From the graphical display:
Control
Control Single Line Diagram
Measurements Commands
Events
Disturbance records
Settings
Diagnostics
Test
Change to the "Switches" page Reset
of the SLD by left-right arrows. Authorization
Select switch by up-down Language
arrows
../Control/SLD/Switch
O I ../Control/SLD/Switch
SMBRREC control SMBRREC control
WFM Select switch. Press the
WFM
I or O key. A dialog box
Pilot setup appears.
Pilot setup
OFF OFF
Damage control E P: Disc N: Disc Fe
DAL
The pos will not be modified
(outputs will not be activated) until OK Cancel
you press the E-button for O.K.
../Control/SLD/Switch
SMBRREC control
WFM
Pilot setup
OFF
Damage control
DFW
IEC06000421 V2 EN
Figure 302: Example 2 on handling the switch from the local HMI.
From the single line diagram on local HMI.
594
Control

SLGGIO
BLOCK ^SWPOS01
PSTO ^SWPOS02
UP ^SWPOS03
DOWN ^SWPOS04
^SWPOS05
^SWPOS06
^SWPOS07
^SWPOS08
^SWPOS09
^SWPOS10
^SWPOS11
^SWPOS12
^SWPOS13
^SWPOS14
^SWPOS15
^SWPOS16
^SWPOS17
^SWPOS18
^SWPOS19
^SWPOS20
^SWPOS21
^SWPOS22
^SWPOS23
^SWPOS24
^SWPOS25
^SWPOS26
^SWPOS27
^SWPOS28
^SWPOS29
^SWPOS30
^SWPOS31
^SWPOS32
SWPOSN
IEC05000658 V2 EN
Figure 303: SLGGIO function block

Table 320: SLGGIO Input signals
UP BOOLEAN 0 Binary "UP" command
DOWN BOOLEAN 0 Binary "DOWN" command
Table 321: SLGGIO Output signals

SWPOS01 BOOLEAN Selector switch position 1
595
Control

SWPOSN INTEGER Switch position (integer)

Table 322: SLGGIO Non group settings (basic)
On
NrPos 2 - 32 - 1 32 Number of positions in the switch
OutType Pulsed - - Steady Output type, steady or pulse
Steady
596
Control

tPulse 0.000 - 60.000 s 0.001 0.200 Operate pulse duration, in [s]
tDelay 0.000 - 60000.000 s 0.010 0.000 Time delay on the output, in [s]
StopAtExtremes Disabled - - Disabled Stop when min or max position is reached
Enabled
12.5 Selector mini switch VSGGIO

Selector mini switch VSGGIO - -
12.5.1 Introduction
The Selector mini switch VSGGIO function block is a multipurpose function used
for a variety of applications, as a general purpose switch.
VSGGIO can be controlled from the menu or from a symbol on the single line
diagram (SLD) on the local HMI.

Selector mini switch (VSGGIO) function can be used for double purpose, in the
same way as switch controller (SCSWI) functions are used:
• for indication on the single line diagram (SLD). Position is received through
the IPOS1 and IPOS2 inputs and distributed in the configuration through the
POS1 and POS2 outputs, or to IEC 61850 through reporting, or GOOSE.
• for commands that are received via the local HMI or IEC 61850 and
distributed in the configuration through outputs CMDPOS12 and CMDPOS21.
The output CMDPOS12 is set when the function receives a CLOSE command
from the local HMI when the SLD is displayed and the object is chosen.
The output CMDPOS21 is set when the function receives an OPEN command
from the local HMI when the SLD is displayed and the object is chosen.
It is important for indication in the SLD that the a symbol is

associated with a controllable object, otherwise the symbol won't be
displayed on the screen. A symbol is created and configured in
GDE tool in PCM600.
The PSTO input is connected to the Local remote switch to have a selection of
operators place , operation from local HMI (Local) or through IEC 61850
597
Control
(Remote). An INTONE connection from Fixed signal function block (FXDSIGN)

will allow operation from local HMI.
As it can be seen, both indications and commands are done in double-bit

representation, where a combination of signals on both inputs/outputs generate the
desired result.
The following table shows the relationship between IPOS1/IPOS2 inputs and the
name of the string that is shown on the SLD. The value of the strings are set in PST.
IPOS1 IPOS2 Name of displayed string Default string value
0 0 PosUndefined P00
1 0 Position1 P01
0 1 Position2 P10
1 1 PosBadState P11

VSGGIO
BLOCK BLOCKED
PSTO POSITION
IPOS1 POS1
IPOS2 POS2
CMDPOS12
CMDPOS21
IEC06000508 V3 EN
Figure 304: VSGGIO function block

Table 323: VSGGIO Input signals
IPOS1 BOOLEAN 0 Position 1 indicating input
IPOS2 BOOLEAN 0 Position 2 indicating input
Table 324: VSGGIO Output signals

BLOCKED BOOLEAN The function is active but the functionality is
blocked
POSITION INTEGER Position indication, integer
POS1 BOOLEAN Position 1 indication, logical signal
598
Control

POS2 BOOLEAN Position 2 indication, logical signal
CMDPOS12 BOOLEAN Execute command from position 1 to position 2
CMDPOS21 BOOLEAN Execute command from position 2 to position 1

Table 325: VSGGIO Non group settings (basic)
On
CtlModel Dir Norm - - Dir Norm Specifies the type for control model
SBO Enh according to IEC 61850
Mode Steady - - Pulsed Operation mode
Pulsed
tSelect 0.000 - 60.000 s 0.001 30.000 Max time between select and execute
signals
tPulse 0.000 - 60.000 s 0.001 0.200 Command pulse lenght
12.6 Generic double point function block DPGGIO

IEC 61850 generic communication I/O DPGGIO - -
functions
12.6.1 Introduction
The IEC 61850 generic communication I/O functions (DPGGIO) function block is
used to send double indications to other systems or equipment in the substation. It
is especially used in the interlocking and reservation station-wide logics.

Upon receiving the input signals, the IEC 61850 generic communication I/O
functions (DPGGIO) function block will send the signals over IEC 61850-8-1 to
the equipment or system that requests these signals. To be able to get the signals,
other tools must be used, as described in the application manual, to PCM600 must
be used to define which function block in which equipment or system should
receive this information.
599
Control

DPGGIO
OPEN POSITION
CLOSE
VALID
IEC07000200 V2 EN
Figure 305: DPGGIO function block

Table 326: DPGGIO Input signals
OPEN BOOLEAN 0 Open indication
CLOSE BOOLEAN 0 Close indication
VALID BOOLEAN 0 Valid indication
Table 327: DPGGIO Output signals

POSITION INTEGER Double point indication
12.6.5 Settings
12.7 Single point generic control 8 signals SPC8GGIO

Single point generic control 8 signals SPC8GGIO - -
12.7.1 Introduction
The Single point generic control 8 signals (SPC8GGIO) function block is a
collection of 8 single point commands, designed to bring in commands from
REMOTE (SCADA) to those parts of the logic configuration that do not need
extensive command receiving functionality (for example, SCSWI). In this way,
simple commands can be sent directly to the IED outputs, without confirmation.
Confirmation (status) of the result of the commands is supposed to be achieved by
600
Control
other means, such as binary inputs and SPGGIO function blocks. The commands
can be pulsed or steady.

The PSTO input will determine which the allowed position for the operator
(LOCAL, REMOTE, ALL) is. Upon sending a command from an allowed operator
position, one of the 8 outputs will be activated. The settings Latchedx and tPulsex
(where x is the respective output) will determine if the signal will be pulsed (and
how long the pulse is) or latched (steady). BLOCK will block the operation of the
function – in case a command is sent, no output will be activated.
PSTO is the universal operator place selector for all control

functions. Even if PSTO can be configured to allow LOCAL or
ALL operator positions, the only functional position usable with the
SPC8GGIO function block is REMOTE.

SPC8GGIO
BLOCK ÔUT1
PSTO ÔUT2
ÔUT3
ÔUT4
ÔUT5
ÔUT6
ÔUT7
ÔUT8
IEC07000143 V2 EN
Figure 306: SPC8GGIO function block

Table 328: SPC8GGIO Input signals
BLOCK BOOLEAN 0 Blocks the function operation
Table 329: SPC8GGIO Output signals

OUT1 BOOLEAN Output 1
OUT2 BOOLEAN Output2
601
Control


Table 330: SPC8GGIO Non group settings (basic)
On
Latched1 Pulsed - - Pulsed Setting for pulsed/latched mode for
Latched output 1
tPulse1 0.01 - 6000.00 s 0.01 0.10 Output1 Pulse Time
Latched output 2
Latched output 3
Latched output 4
Latched output 5
Latched output 6
Latched output 7
Latched output 8
tPulse8 0.01 - 6000.00 s 0.01 0.10 Output8 pulse time
12.8 AutomationBits, command function for DNP3.0

AUTOBITS
602
Control

AutomationBits, command function for
AUTOBITS - -
DNP3
12.8.1 Introduction
AutomationBits function for DNP3 (AUTOBITS) is used within PCM600 to get
into the configuration of the commands coming through the DNP3 protocol. The
AUTOBITS function plays the same role as functions GOOSEBINRCV (for IEC
61850) and MULTICMDRCV (for LON).

AutomationBits function (AUTOBITS) has 32 individual outputs which each can
be mapped as a Binary Output point in DNP3. The output is operated by a "Object
12" in DNP3. This object contains parameters for control-code, count, on-time and
off-time. To operate an AUTOBITS output point, send a control-code of latch-On,
latch-Off, pulse-On, pulse-Off, Trip or Close. The remaining parameters will be
regarded were appropriate. ex: pulse-On, on-time=100, off-time=300, count=5
would give 5 positive 100 ms pulses, 300 ms apart.
There is a BLOCK input signal, which will disable the operation of the function, in
the same way the setting Operation: On/Off does. That means that, upon activation
of the BLOCK input, all 32 CMDBITxx outputs will be set to 0. The BLOCK acts
like an overriding, the function still receives data from the DNP3 master. Upon
deactivation of BLOCK, all the 32 CMDBITxx outputs will be set by the DNP3
master again, momentarily. For AUTOBITS , the PSTO input determines the
operator place. The command can be written to the block while in “Remote”. If
PSTO is in “Local” then no change is applied to the outputs.
603
Control

AUTOBITS
BLOCK ^CMDBIT1
PSTO ^CMDBIT2
^CMDBIT3
^CMDBIT4
^CMDBIT5
^CMDBIT6
^CMDBIT7
^CMDBIT8
^CMDBIT9
^CMDBIT10
^CMDBIT11
^CMDBIT12
^CMDBIT13
^CMDBIT14
^CMDBIT15
^CMDBIT16
^CMDBIT17
^CMDBIT18
^CMDBIT19
^CMDBIT20
^CMDBIT21
^CMDBIT22
^CMDBIT23
^CMDBIT24
^CMDBIT25
^CMDBIT26
^CMDBIT27
^CMDBIT28
^CMDBIT29
^CMDBIT30
^CMDBIT31
^CMDBIT32
IEC09000925 V1 EN
Figure 307: AUTOBITS function block

Table 331: AUTOBITS Input signals
Table 332: AUTOBITS Output signals

CMDBIT1 BOOLEAN Command out bit 1
604
Control


Table 333: AUTOBITS Non group settings (basic)
On
Table 334: DNPGEN Non group settings (basic)

Operation Off - - Off Operation mode Off / On
On
605
Control
Table 335: CHSERRS485 Non group settings (basic)

Operation Off - - Off Operation mode
Serial-Mode
BaudRate 300 Bd - - 9600 Bd Baud-rate for serial port
600 Bd
1200 Bd
2400 Bd
4800 Bd
9600 Bd
19200 Bd
WireMode Four-wire - - Two-wire RS485 wire mode
Two-wire
Table 336: CHSERRS485 Non group settings (advanced)

DLinkConfirm Never - - Never Data-link confirm
Sometimes
Always
tDLinkTimeout 0.000 - 60.000 s 0.001 2.000 Data-link confirm timeout in s
DLinkRetries 0 - 255 - 1 3 Data-link maximum retries
tRxToTxMinDel 0.000 - 60.000 s 0.001 0.000 Rx to Tx minimum delay in s
ApLayMaxRxSize 20 - 2048 - 1 2048 Application layer maximum Rx fragment
size
ApLayMaxTxSize 20 - 2048 - 1 2048 Application layer maximum Tx fragment
size
StopBits 1-2 - 1 1 Stop bits
Parity No - - Even Parity
Even
Odd
tRTSWarmUp 0.000 - 60.000 s 0.001 0.000 RTS warm-up in s
tRTSWarmDown 0.000 - 60.000 s 0.001 0.000 RTS warm-down in s
tBackOffDelay 0.000 - 60.000 s 0.001 0.050 RS485 back-off delay in s
tMaxRndDelBkOf 0.000 - 60.000 s 0.001 0.100 RS485 maximum back-off random delay
in s
Table 337: CH2TCP Non group settings (basic)

TCP/IP
UDP-Only
TCPIPLisPort 1 - 65535 - 1 20000 TCP/IP listen port
UDPPortAccData 1 - 65535 - 1 20000 UDP port to accept UDP datagrams from
master
UDPPortInitNUL 1 - 65535 - 1 20000 UDP port for initial NULL response
UDPPortCliMast 0 - 65535 - 1 0 UDP port to remote client/master
606
Control
Table 338: CH2TCP Non group settings (advanced)

size
size

TCP/IP
UDP-Only
master

size
size

TCP/IP
UDP-Only
master

size
size
607
Control

TCP/IP
UDP-Only
master

size
size
Table 345: MSTRS485 Non group settings (basic)

On
SlaveAddress 0 - 65519 - 1 1 Slave address
MasterAddres 0 - 65519 - 1 1 Master address
Obj1DefVar 1:BISingleBit - - 1:BISingleBit Object 1, default variation
2:BIWithStatus
Obj2DefVar 1:BIChWithoutTim - - 3:BIChWithRelTim Object 2, default variation
e e
2:BIChWithTime
3:BIChWithRelTim
e
Obj4DefVar 1:DIChWithoutTim - - 3:DIChWithRelTim Object 4, default variation
e e
2:DIChWithTime
3:DIChWithRelTim
e
Obj10DefVar 1:BO - - 2:BOStatus Object 10, default variation
2:BOStatus
Obj20DefVar 1:BinCnt32 - - 5:BinCnt32WoutF Object 20, default variation
2:BinCnt16
5:BinCnt32WoutF
6:BinCnt16WoutF
608
Control

Obj22DefVar 1:BinCnt32EvWout - - 1:BinCnt32EvWou Object 22, default variation
T tT
2:BinCnt16EvWout
T
5:BinCnt32EvWith
T
6:BinCnt16EvWith
T
Obj30DefVar 1:AI32Int - - 3:AI32IntWithoutF Object 30, default variation
2:AI16Int
3:AI32IntWithoutF
4:AI16IntWithoutF
5:AI32FltWithF
6:AI64FltWithF
Obj32DefVar 1:AI32IntEvWoutF - - 1:AI32IntEvWoutF Object 32, default variation
2:AI16IntEvWoutF
3:AI32IntEvWithFT
4:AI16IntEvWithFT
5:AI32FltEvWithF
6:AI64FltEvWithF
7:AI32FltEvWithFT
8:AI64FltEvWithFT
Table 346: MSTRS485 Non group settings (advanced)

ValMasterAddr No - - Yes Validate source (master) address
Yes
AddrQueryEnbl No - - Yes Address query enable
Yes
tApplConfTout 0.00 - 300.00 s 0.01 10.00 Application layer confim timeout
ApplMultFrgRes No - - Yes Enable application for multiple fragment
Yes response
ConfMultFrag No - - Yes Confirm each multiple fragment
Yes
UREnable No - - Yes Unsolicited response enabled
Yes
URSendOnline No - - No Unsolicited response sends when on-line
Yes
UREvClassMask Off - - Off Unsolicited response, event class mask
Class 1
Class 2
Class 1 and 2
Class 3
Class 1 and 3
Class 2 and 3
Class 1, 2 and 3
UROfflineRetry 0 - 10 - 1 5 Unsolicited response retries before off-
line retry mode
tURRetryDelay 0.00 - 60.00 s 0.01 5.00 Unsolicited response retry delay in s
tUROfflRtryDel 0.00 - 60.00 s 0.01 30.00 Unsolicited response off-line retry delay
in s
UREvCntThold1 1 - 100 - 1 5 Unsolicited response class 1 event count
report treshold
609
Control

tUREvBufTout1 0.00 - 60.00 s 0.01 5.00 Unsolicited response class 1 event
buffer timeout
report treshold
buffer timeout
report treshold
buffer timeout
DelOldBufFull No - - No Delete oldest event when buffer is full
Yes
tSynchTimeout 30 - 3600 s 1 1800 Time synch timeout before error status is
generated
TSyncReqAfTout No - - No Time synchronization request after
Yes timeout
DNPToSetTime No - - Yes Allow DNP to set time in IED
Yes
Averag3TimeReq No - - No Use average of 3 time requests
Yes
PairedPoint No - - Yes Enable paired point
Yes
tSelectTimeout 1.0 - 60.0 s 0.1 30.0 Select timeout
Table 347: MST1TCP Non group settings (basic)

On
Yes
MasterIP-Addr 0 - 18 IP 1 0.0.0.0 Master IP-address
Address
MasterIPNetMsk 0 - 18 IP 1 255.255.255.255 Master IP net mask
Address
2:BIWithStatus
e e
2:BIChWithTime
3:BIChWithRelTim
e
Obj3DefVar 1:DIWithoutFlag - - 1:DIWithoutFlag Object 3, default variation
2:DIWithFlag
610
Control

e e
2:DIChWithTime
3:DIChWithRelTim
e
2:BOStatus
2:BinCnt16
5:BinCnt32WoutF
6:BinCnt16WoutF
T tT
2:BinCnt16EvWout
T
5:BinCnt32EvWith
T
6:BinCnt16EvWith
T
2:AI16Int
3:AI32IntWithoutF
4:AI16IntWithoutF
5:AI32FltWithF
6:AI64FltWithF
2:AI16IntEvWoutF
3:AI32IntEvWithFT
4:AI16IntEvWithFT
5:AI32FltEvWithF
6:AI64FltEvWithF
7:AI32FltEvWithFT
8:AI64FltEvWithFT
Table 348: MST1TCP Non group settings (advanced)

Yes
Yes response
Yes
Yes
Class 1
Class 2
Class 1 and 2
Class 3
Class 1 and 3
Class 2 and 3
Class 1, 2 and 3
611
Control

line retry mode
in s
report treshold
buffer timeout
report treshold
buffer timeout
report treshold
buffer timeout
Yes
ExtTimeFormat LocalTime - - UTC External time format
UTC
DNPToSetTime No - - No Allow DNP to set time in IED
Yes
generated
Yes timeout
Yes
Yes
tBrokenConTout 0 - 3600 s 1 0 Broken connection timeout
tKeepAliveT 0 - 3600 s 1 10 Keep-Alive timer

On
Yes
Address
612
Control

Address
2:BIWithStatus
e e
2:BIChWithTime
3:BIChWithRelTim
e
2:DIWithFlag
e e
2:DIChWithTime
3:DIChWithRelTim
e
2:BOStatus
2:BinCnt16
5:BinCnt32WoutF
6:BinCnt16WoutF
T tT
2:BinCnt16EvWout
T
5:BinCnt32EvWith
T
6:BinCnt16EvWith
T
2:AI16Int
3:AI32IntWithoutF
4:AI16IntWithoutF
5:AI32FltWithF
6:AI64FltWithF
2:AI16IntEvWoutF
3:AI32IntEvWithFT
4:AI16IntEvWithFT
5:AI32FltEvWithF
6:AI64FltEvWithF
7:AI32FltEvWithFT
8:AI64FltEvWithFT

Yes
Yes response
613
Control

Yes
Yes
Class 1
Class 2
Class 1 and 2
Class 3
Class 1 and 3
Class 2 and 3
Class 1, 2 and 3
line retry mode
in s
report treshold
buffer timeout
report treshold
buffer timeout
report treshold
buffer timeout
Yes
UTC
Yes
generated
Yes timeout
Yes
Yes
614
Control

On
Yes
Address
Address
2:BIWithStatus
e e
2:BIChWithTime
3:BIChWithRelTim
e
2:DIWithFlag
e e
2:DIChWithTime
3:DIChWithRelTim
e
2:BOStatus
2:BinCnt16
5:BinCnt32WoutF
6:BinCnt16WoutF
T tT
2:BinCnt16EvWout
T
5:BinCnt32EvWith
T
6:BinCnt16EvWith
T
2:AI16Int
3:AI32IntWithoutF
4:AI16IntWithoutF
5:AI32FltWithF
6:AI64FltWithF
2:AI16IntEvWoutF
3:AI32IntEvWithFT
4:AI16IntEvWithFT
5:AI32FltEvWithF
6:AI64FltEvWithF
7:AI32FltEvWithFT
8:AI64FltEvWithFT
615
Control

Yes
Yes response
Yes
Yes
Class 1
Class 2
Class 1 and 2
Class 3
Class 1 and 3
Class 2 and 3
Class 1, 2 and 3
line retry mode
in s
report treshold
buffer timeout
report treshold
buffer timeout
report treshold
buffer timeout
Yes
UTC
Yes
generated
Yes timeout
Yes
Yes
616
Control


On
Yes
Address
Address
2:BIWithStatus
e e
2:BIChWithTime
3:BIChWithRelTim
e
2:DIWithFlag
e e
2:DIChWithTime
3:DIChWithRelTim
e
2:BOStatus
2:BinCnt16
5:BinCnt32WoutF
6:BinCnt16WoutF
617
Control

T tT
2:BinCnt16EvWout
T
5:BinCnt32EvWith
T
6:BinCnt16EvWith
T
2:AI16Int
3:AI32IntWithoutF
4:AI16IntWithoutF
5:AI32FltWithF
6:AI64FltWithF
2:AI16IntEvWoutF
3:AI32IntEvWithFT
4:AI16IntEvWithFT
5:AI32FltEvWithF
6:AI64FltEvWithF
7:AI32FltEvWithFT
8:AI64FltEvWithFT

Yes
Yes response
Yes
Yes
Class 1
Class 2
Class 1 and 2
Class 3
Class 1 and 3
Class 2 and 3
Class 1, 2 and 3
line retry mode
in s
report treshold
buffer timeout
report treshold
618
Control

buffer timeout
report treshold
buffer timeout
Yes
UTC
Yes
generated
Yes timeout
Yes
Yes
12.9 Single command, 16 signals SINGLECMD

Single command, 16 signals SINGLECMD - -
12.9.1 Introduction
The IEDs can receive commands either from a substation automation system or
from the local HMI. The command function block has outputs that can be used, for
example, to control high voltage apparatuses or for other user defined functionality.

Single command, 16 signals (SINGLECMD) function has 16 binary output signals.
The outputs can be individually controlled from a substation automation system or
from the local HMI. Each output signal can be given a name with a maximum of
13 characters in PCM600.
619
Control
The output signals can be of the types Off, Steady, or Pulse. This configuration
setting is done via the local HMI or PCM600 and is common for the whole
function block. The length of the output pulses are 100 ms. In steady mode,
SINGLECMD function has a memory to remember the output values at power
interruption of the IED. Also a BLOCK input is available used to block the
updating of the outputs.
The output signals, OUT1 to OUT16, are available for configuration to built-in
functions or via the configuration logic circuits to the binary outputs of the IED.

SINGLECMD
BLOCK ÔUT1
ÔUT2
ÔUT3
ÔUT4
ÔUT5
ÔUT6
ÔUT7
ÔUT8
ÔUT9
ÔUT10
ÔUT11
ÔUT12
ÔUT13
ÔUT14
ÔUT15
ÔUT16
IEC05000698 V3 EN
Figure 308: SINGLECMD function block

Table 355: SINGLECMD Input signals
BLOCK BOOLEAN 0 Block single command function
Table 356: SINGLECMD Output signals

OUT1 BOOLEAN Single command output 1
620
Control


Table 357: SINGLECMD Non group settings (basic)
Mode Off - - Off Operation mode
Steady
Pulsed
621
622
Logic
Section 13 Logic
About this chapter

This chapter describes primarily tripping and trip logic functions. The way the
functions work, their setting parameters, function blocks, input and output signals
and technical data are included for each function.
13.1 Tripping logic SMPPTRC

Tripping logic SMPPTRC 94
I->O
SYMBOL-K V1 EN
13.1.1 Introduction
A function block for protection tripping is provided for each circuit breaker
involved in the tripping of the fault. It provides pulse prolongation to ensure a trip
pulse of sufficient length, as well as all functionality necessary for correct co-
operation with autoreclosing functions.
The trip function block includes functionality for evolving faults and breaker lock-
out.

The duration of a trip output signal from tripping logic SMPPTRC is settable
(tTripMin). The pulse length should be long enough to secure the breaker opening.
For three-phase tripping, SMPPTRC has a single input (TRIN) through which all
trip output signals from the protection functions within the IED, or from external
protection functions via one or more of the IEDs binary inputs, are routed. It has a
single trip output (TRIP) for connection to one or more of the IEDs binary outputs,
as well as to other functions within the IED requiring this signal.
623
Logic
BLOCK
tTripMin TRIP
TRIN OR
AND t
Operation Mode = On
Program = 3Ph
en05000789.vsd
IEC05000789 V1 EN
Figure 309: Simplified logic diagram for three phase trip
SMPPTRC function for single-phase and two-phase tripping has additional phase
segregated inputs for this, as well as inputs for faulted phase selection. The latter
inputs enable single- phase and two-phase tripping for those functions which do not
have their own phase selection capability, and therefore which have just a single
trip output and not phase segregated trip outputs for routing through the phase
segregated trip inputs of the expanded SMPPTRC function. Examples of such
protection functions are the residual overcurrent protections. The expanded
SMPPTRC function has two inputs for these functions, one for impedance tripping
(for example, carrier-aided tripping commands from the scheme communication
logic), and one for earth fault tripping (for example, tripping output from a residual
overcurrent protection).
Additional logic, including a timer tWaitForPHS, secures a three-phase trip

command for these protection functions in the absence of the required phase
selection signals.
The expanded SMPPTRC function has three trip outputs TRL1, TRL2, TRL3
(besides the trip output TRIP), one per phase, for connection to one or more of the
IEDs binary outputs, as well as to other functions within the IED requiring these
signals. There are also separate output signals indicating single-phase, two-phase or
three-phase trip. These signals are important for cooperation with the autorecloser
SMBRREC function.
The expanded SMPPTRC function is equipped with logic which secures correct
operation for evolving faults as well as for reclosing on to persistent faults. A
special input is also provided which disables single- phase and two-phase tripping,
forcing all tripping to be three-phase.
In multi-breaker arrangements, one SMPPTRC function block is used for each

breaker. This can be the case if single pole tripping and autoreclosing is used.
The breaker close lockout function can be activated from an external trip signal
from another protection function via input (SETLKOUT) or internally at a three-
phase trip, if desired.
It is possible to lockout seal in the tripping output signals or use blocking of

closing only the choice is by setting TripLockout.
624
Logic
TRINL1
TRINL2
OR
TRINL3
1PTRZ OR
1PTREF
OR
TRIN RSTTRIP - cont.
AND
Program = 3ph
en05000517.vsd
IEC05000517 V1 EN
Figure 310: Three-phase front logic — simplified logic diagram
TRINP_3P
TRINP_A
PS_A ATRIP
OR
AND
TRINP_B
PS_B BTRIP
OR
AND
TRINP_C
PS_C CTRIP
OR
AND
OR
OR OR
-loop
-loop
OR
AND AND AND
1PTRGF AND tWaitForPHS

1PTRZ OR t
IEC10000056 V1 EN
Figure 311: Phase segregated front logic
625
Logic
150 ms
L1TRIP OR
t RTRIP
OR
2000 ms
t
OR
AND
150 ms
L2TRIP OR
t STRIP
OR
2000 ms
t
OR
AND
150 ms
L3TRIP OR
t TTRIP
OR
2000 ms
t
OR
AND
OR
OR AND
P3PTR
OR
-loop
en05000519.vsd
Figure 312: Additional logic for the 1ph/3ph operating mode
626
Logic
150 ms
L1TRIP - cont.
t OR RTRIP
OR
2000 ms
t
AND
150 ms
L2TRIP
t OR STRIP
OR
2000 ms
t AND
AND
150 ms
L3TRIP
t OR TTRIP
OR
2000 ms
t
AND
OR
AND
TRIP OR
OR
-loop
en05000520.vsd
Figure 313: Additional logic for the 1ph/2ph/3ph operating mode
627
Logic
BLOCK
RTRIP TRL1
AND
OR
STRIP TRL2
AND
OR
TTRIP TRL3
AND
OR
RSTTRIP
TRIP
OR
TR3P
AND AND
OR
-loop
AND 10 ms
TR1P
AND t
AND 5 ms
TR2P
AND t
OR
AND
-loop
en05000521.vsd
Figure 314: Final tripping circuits

SMPPTRC
BLOCK TRIP
BLKLKOUT TRL1
TRIN TRL2
TRINL1 TRL3
TRINL2 TR1P
TRINL3 TR2P
PSL1 TR3P
PSL2 CLLKOUT
PSL3
1PTRZ
1PTREF
P3PTR
SETLKOUT
RSTLKOUT
IEC05000707 V2 EN
Figure 315: SMPPTRC function block

Table 358: SMPPTRC Input signals
BLKLKOUT BOOLEAN 0 Blocks circuit breaker lockout output (CLLKOUT)
TRIN BOOLEAN 0 Trip all phases
628
Logic

TRINL1 BOOLEAN 0 Trip phase 1
PSL1 BOOLEAN 0 Functional input for phase selection in phase L1
1PTRZ BOOLEAN 0 Zone Trip with a separate phase selection
1PTREF BOOLEAN 0 Single phase DEF Trip for separate phase
selection
P3PTR BOOLEAN 0 Prepare all tripping to be three-phase
SETLKOUT BOOLEAN 0 Input for setting the circuit breaker lockout function
RSTLKOUT BOOLEAN 0 Input for resetting the circuit breaker lockout
function
Table 359: SMPPTRC Output signals

TRIP BOOLEAN General trip output signal
TR1P BOOLEAN Tripping single-pole
TR2P BOOLEAN Tripping two-pole
TR3P BOOLEAN Tripping three-pole
CLLKOUT BOOLEAN Circuit breaker lockout output (set until reset)

Table 360: SMPPTRC Group settings (basic)
On
Program 3 phase - - 1ph/3ph Three ph; single or three ph; single, two
1ph/3ph or three ph trip
1ph/2ph/3ph
tTripMin 0.000 - 60.000 s 0.001 0.150 Minimum duration of trip output signal
tWaitForPHS 0.020 - 0.500 s 0.001 0.050 Secures 3-pole trip when phase
selection failed
629
Logic
Table 361: SMPPTRC Group settings (advanced)

TripLockout Off - - Off On: activate output (CLLKOUT) and trip
On latch, Off: only outp
AutoLock Off - - Off On: lockout from input (SETLKOUT) and
On trip, Off: only inp

Table 362: SMPPTRC technical data
Trip action 3-ph, 1/3-ph, 1/2/3-ph -
Minimum trip pulse length (0.000-60.000) s ± 0.5% ± 10 ms
Timers (0.000-60.000) s ± 0.5% ± 10 ms
13.2 Trip matrix logic TMAGGIO

Trip matrix logic TMAGGIO - -
13.2.1 Introduction
Trip matrix logic TMAGGIO function is used to route trip signals and other logical
output signals to different output contacts on the IED.
TMAGGIO output signals and the physical outputs allows the user to adapt the
signals to the physical tripping outputs according to the specific application needs.

Trip matrix logic (TMAGGIO) block is provided with 32 input signals and 3
output signals. The function block incorporates internal logic OR gates in order to
provide the necessary grouping of connected input signals (for example, for
tripping and alarming purposes) to the three output signals from the function block.
Internal built-in OR logic is made in accordance with the following three rules:
630
Logic
1. when any one of first 16 inputs signals (INPUT1 to INPUT16) has logical
value 1 (TRUE) the first output signal (OUTPUT1) will get logical value 1
(TRUE).
2. when any one of second 16 inputs signals (INPUT17 to INPUT32) has logical
value 1 (TRUE) the second output signal (OUTPUT2) will get logical value 1
(TRUE).
3. when any one of all 32 input signals (INPUT1 to INPUT32) has logical value
1 (TRUE) the third output signal (OUTPUT3) will get logical value 1 (TRUE).
By use of the settings ModeOutput1, ModeOutput2, ModeOutput3, PulseTime,

OnDelay and OffDelay the behavior of each output can be customized. The
OnDelay is always active and will delay the input to output transition by the set
time. The ModeOutput for respective output decides wether the output shall be
steady with an drop-off delay as set by OffDelay or if it shall give a pulse with
duration set by PulseTime. Note that for pulsed operation since the inputs are
connected in an OR-function a new pulse will only be given on the output if all
related inputs are reset and then one is activated again. And for steady operation
the of delay will start when all related inputs have reset. Detailed logical diagram is
shown in figure 316
PulseTime
t
&
ModeOutput1
Input 1
Output 1
Ondelay Offdelay
&
³1
³1 t t
Input 16
PulseTime
t
&
ModeOutput2
Input 17
Output 2
Ondelay Offdelay
&
³1
³1 t t
Input 32
PulseTime
t
&
ModeOutput3
Output 3
Ondelay Offdelay
&
³1
³1 t t
IEC09000612 V1 EN
Figure 316: Trip matrix internal logic
Output signals from TMAGGIO are typically connected to other logic blocks or
directly to output contacts in the IED. When used for direct tripping of the circuit
breaker(s) the pulse time delay shall be set to approximately 0.150 seconds in order
to obtain satisfactory minimum duration of the trip pulse to the circuit breaker trip
coils.
631
Logic

TMAGGIO
INPUT1 OUTPUT1
INPUT2 OUTPUT2
INPUT3 OUTPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
INPUT17
INPUT18
INPUT19
INPUT20
INPUT21
INPUT22
INPUT23
INPUT24
INPUT25
INPUT26
INPUT27
INPUT28
INPUT29
INPUT30
INPUT31
INPUT32
IEC09000830 V1 EN
Figure 317: TMAGGIO function block

Table 363: TMAGGIO Input signals
INPUT1 BOOLEAN 0 Binary input 1
632
Logic

Table 364: TMAGGIO Output signals

OUTPUT1 BOOLEAN OR function betweeen inputs 1 to 16
OUTPUT2 BOOLEAN OR function between inputs 17 to 32
OUTPUT3 BOOLEAN OR function between inputs 1 to 32

Table 365: TMAGGIO Group settings (basic)
On
PulseTime 0.050 - 60.000 s 0.001 0.150 Output pulse time
OnDelay 0.000 - 60.000 s 0.001 0.000 Output on delay time
OffDelay 0.000 - 60.000 s 0.001 0.000 Output off delay time
ModeOutput1 Steady - - Steady Mode for output ,1 steady or pulsed
Pulsed
ModeOutput2 Steady - - Steady Mode for output 2, steady or pulsed
Pulsed
ModeOutput3 Steady - - Steady Mode for output 3, steady or pulsed
Pulsed
633
Logic
13.3 Configurable logic blocks
13.3.1 Introduction
A number of logic blocks and timers are available for the user to adapt the
configuration to the specific application needs.
• OR function block.
• INVERTER function blocks that inverts the input signal.
• PULSETIMER function block can be used, for example, for pulse extensions
or limiting of operation of outputs.
• GATE function block is used for whether or not a signal should be able to
pass from the input to the output.
• XOR function block.
• LOOPDELAY function block used to delay the output signal one execution
cycle.
• TIMERSET function has pick-up and drop-out delayed outputs related to the
input signal. The timer has a settable time delay.
• AND function block.
• SRMEMORY function block is a flip-flop that can set or reset an output from
two inputs respectively. Each block has two outputs where one is inverted. The
memory setting controls if the block's output should reset or return to the state
it was, after a power interruption. Set input has priority.
• RSMEMORY function block is a flip-flop that can reset or set an output from
two inputs respectively. Each block has two outputs where one is inverted. The
memory setting controls if the block's output should reset or return to the state
it was, after a power interruption. Reset input has priority.
13.3.2 Inverter function block INV

INV
INPUT OUT
IEC04000404 V2 EN
Figure 318: INV function block
634
Logic
Table 366: INV Input signals

INPUT BOOLEAN 0 Input
Table 367: INV Output signals

OUT BOOLEAN Output
13.3.3 OR function block OR

The OR function is used to form general combinatory expressions with boolean
variables. The OR function block has six inputs and two outputs. One of the
outputs is inverted.
OR
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
INPUT5
INPUT6
IEC04000405 V2 EN
Figure 319: OR function block
Table 368: OR Input signals

INPUT1 BOOLEAN 0 Input 1 to OR gate
Table 369: OR Output signals

OUT BOOLEAN Output from OR gate
NOUT BOOLEAN Inverted output from OR gate
635
Logic
13.3.4 AND function block AND

The AND function is used to form general combinatory expressions with boolean
variables. The AND function block has four inputs and two outputs. One of the
outputs are inverted.
AND
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4N
IEC04000406 V2 EN
Figure 320: AND function block
Table 370: AND Input signals

INPUT1 BOOLEAN 1 Input 1
INPUT4N BOOLEAN 0 Input 4 inverted
Table 371: AND Output signals

OUT BOOLEAN Output
NOUT BOOLEAN Output inverted
13.3.5 Timer function block TIMER

The function block TIMER has drop-out and pick-up delayed outputs related to the
input signal. The timer has a settable time delay (T).
TIMER
INPUT ON
T OFF
IEC04000378 V2 EN
Figure 321: TIMER function block
Table 372: TIMER Input signals

INPUT BOOLEAN 0 Input to timer
636
Logic
Table 373: TIMER Output signals

ON BOOLEAN Output from timer , pick-up delayed
OFF BOOLEAN Output from timer, drop-out delayed
Table 374: TIMER Non group settings (basic)

T 0.000 - 90000.000 s 0.001 0.000 Time delay of function
13.3.6 Pulse timer function block PULSETIMER

The pulse (PULSETIMER) function can be used, for example, for pulse extensions
or limiting of operation of outputs. The pulse timer TP has a settable length.
PULSETIMER
INPUT OUT
T
IEC04000407 V2 EN
Figure 322: PULSETIMER function block
Table 375: PULSETIMER Input signals

INPUT BOOLEAN 0 Input to pulse timer
Table 376: PULSETIMER Output signals

OUT BOOLEAN Output from pulse timer
Table 377: PULSETIMER Non group settings (basic)

T 0.000 - 90000.000 s 0.001 0.010 Time delay of function
13.3.7 Exclusive OR function block XOR

The exclusive OR function (XOR) is used to generate combinatory expressions
with boolean variables. XOR has two inputs and two outputs. One of the outputs is
inverted. The output signal is 1 if the input signals are different and 0 if they are equal.
637
Logic
XOR
INPUT1 OUT
INPUT2 NOUT
IEC04000409 V2 EN
Figure 323: XOR function block
Table 378: XOR Input signals

INPUT1 BOOLEAN 0 Input 1 to XOR gate
INPUT2 BOOLEAN 0 Input 2 to XOR gate
Table 379: XOR Output signals

OUT BOOLEAN Output from XOR gate
NOUT BOOLEAN Inverted output from XOR gate
13.3.8 Loop delay function block LOOPDELAY

The Logic loop delay function block (LOOPDELAY) function is used to delay the
output signal one execution cycle.
LOOPDELAY
INPUT OUT
IEC09000296 V1 EN
Figure 324: LOOPDELAY function block
Table 380: LOOPDELAY Input signals

INPUT BOOLEAN 0 Input signal
Table 381: LOOPDELAY Output signals

OUT BOOLEAN Output signal, signal is delayed one execution
cycle
13.3.9 Set-reset with memory function block SRMEMORY

The Set-reset with memory function block (SRMEMORY) is a flip-flop with
memory that can set or reset an output from two inputs respectively. Each
SRMEMORY function block has two outputs, where one is inverted. The memory
638
Logic
setting controls if the flip-flop after a power interruption will return the state it had
before or if it will be reset.
Table 382: Truth table for SRMEMORY function block

SET RESET OUT NOUT
0 0 Last Inverted
value last value
0 1 0 1
1 0 1 0
1 1 1 0
SRMEMORY
SET OUT
RESET NOUT
IEC04000408 V2 EN
Figure 325: SRMEMORY function block
Table 383: SRMEMORY Input signals

SET BOOLEAN 0 Input signal to set
RESET BOOLEAN 0 Input signal to reset
Table 384: SRMEMORY Output signals

OUT BOOLEAN Output signal
NOUT BOOLEAN Inverted output signal
Table 385: SRMEMORY Group settings (basic)

Memory Off - - On Operating mode of the memory function
On
13.3.10 Reset-set with memory function block RSMEMORY
The Reset-set with memory function block (RSMEMORY) is a flip-flop with

memory that can reset or set an output from two inputs respectively. Each
RSMEMORY function block has two outputs, where one is inverted. The memory
setting controls if the flip-flop after a power interruption will return the state it had
before or if it will be reset. For a Reset-Set flip-flop, RESET input has higher
priority over SET input.
639
Logic
Table 386: Truth table for RSMEMORY function block

RESET SET OUT NOUT
0 0 Last Inverted last
value value
0 1 1 0
1 0 0 1
1 1 0 1
RSMEMORY
SET OUT
RESET NOUT
IEC09000294 V1 EN
Figure 326: RSMEMORY function block
Table 387: RSMEMORY Input signals

SET BOOLEAN 0 Input signal to set
RESET BOOLEAN 0 Input signal to reset
Table 388: RSMEMORY Output signals

OUT BOOLEAN Output signal
NOUT BOOLEAN Inverted output signal
Table 389: RSMEMORY Group settings (basic)

Memory Off - - On Operating mode of the memory function
On
13.3.11 Controllable gate function block GATE

The Controllable gate function block (GATE) is used for controlling if a signal
should be able to pass from the input to the output or not depending on a setting.
GATE
INPUT OUT
IEC04000410 V2 EN
Figure 327: GATE function block
640
Logic
Table 390: GATE Input signals

INPUT BOOLEAN 0 Input to gate
Table 391: GATE Output signals

OUT BOOLEAN Output from gate
Table 392: GATE Group settings (basic)

On
13.3.12 Settable timer function block TIMERSET

The Settable timer function block (TIMERSET) timer has outputs for delayed input
signal at drop-out and at pick-up. The timer has a settable time delay. It also has an
Operation setting On/, Off/ that controls the operation of the timer.
TIMERSET
INPUT ON
OFF
IEC04000411 V2 EN
Figure 328: TIMERSET function block
Table 393: TIMERSET Input signals

INPUT BOOLEAN 0 Input to timer
Table 394: TIMERSET Output signals

ON BOOLEAN Output from timer, pick-up delayed
OFF BOOLEAN Output from timer, drop-out delayed
Table 395: TIMERSET Group settings (basic)

On
t 0.000 - 90000.000 s 0.001 0.000 Delay for settable timer n
641
Logic

Table 396: Configurable logic blocks
Logic block Quantity with cycle time Range or Accuracy
fast medium normal value
LogicAND 60 60 160 - -
LogicOR 60 60 160 - -
LogicXOR 10 10 20 - -
LogicInverter 30 30 80 - -
LogicSRMemory 10 10 20 - -
LogicRSMemory 10 10 20 - -
LogicGate 10 10 20 - -
LogicTimer 10 10 20 (0.000– ± 0.5% ± 10 ms
90000.000) s
LogicPulseTimer 10 10 20 (0.000– ± 0.5% ± 10 ms
90000.000) s
LogicTimerSet 10 10 20 (0.000– ± 0.5% ± 10 ms
90000.000) s
LogicLoopDelay 10 10 20 (0.000– ± 0.5% ± 10 ms
90000.000) s
Trip Matrix Logic 6 6 - - -
Boolean 16 to Integer 4 4 8 - -
Boolean 16 to 4 4 8 - -
integer with Logic
Node
Integer to Boolean 16 4 4 8 - -
Integer to Boolean 4 4 8 - -
16 with Logic Node
13.4 Fixed signal function block FXDSIGN

Fixed signals FXDSIGN - -
The Fixed signals function (FXDSIGN) generates a number of pre-set (fixed)

signals that can be used in the configuration of an IED, either for forcing the
unused inputs in other function blocks to a certain level/value, or for creating
certain logic.

There are eight outputs from FXDSIGN function block:
642
Logic
• OFF is a boolean signal, fixed to OFF (boolean 0) value

• ON is a boolean signal, fixed to ON (boolean 1) value
• INTZERO is an integer number, fixed to integer value 0
• INTONE is an integer number, fixed to integer value 1
• INTALONE is an integer value FFFF (hex)
• REALZERO is a floating point real number, fixed to 0.0 value
• STRNULL is a string, fixed to an empty string (null) value
• ZEROSMPL is a channel index, fixed to 0 value
• GRP_OFF is a group signal, fixed to 0 value

FXDSIGN
OFF
ON
INTZERO
INTONE
REALZERO
STRNULL
ZEROSMPL
GRP_OFF
IEC05000445 V2 EN
Figure 329: FXDSIGN function block

Table 397: FXDSIGN Output signals
OFF BOOLEAN Boolean signal fixed off
ON BOOLEAN Boolean signal fixed on
INTZERO INTEGER Integer signal fixed zero
INTONE INTEGER Integer signal fixed one
INTALONE INTEGER Integer signal fixed all ones
REALZERO REAL Real signal fixed zero
STRNULL STRING String signal with no characters
ZEROSMPL GROUP SIGNAL Channel id for zero sample
GRP_OFF GROUP SIGNAL Group signal fixed off

643
Logic
13.5 Boolean 16 to Integer conversion B16I

Boolean 16 to integer conversion B16I - -
13.5.1 Introduction
Boolean 16 to integer conversion function (B16I) is used to transform a set of 16
binary (logical) signals into an integer.

Boolean 16 to integer conversion function (B16I) is used to transform a set of 16
binary (logical) signals into an integer. The BLOCK input will freeze the output at
the last value.

B16I
BLOCK OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IEC07000128 V2 EN
Figure 330: B16I function block

Table 398: B16I Input signals
IN1 BOOLEAN 0 Input 1
644
Logic

Table 399: B16I Output signals

OUT INTEGER Output value

13.6 Boolean 16 to Integer conversion with logic node

representation B16IFCVI

Boolean 16 to integer conversion with B16IFCVI - -
logic node representation
13.6.1 Introduction
Boolean 16 to integer conversion with logic node representation function
(B16IFCVI) is used to transform a set of 16 binary (logical) signals into an integer.
B16IFCVI can receive remote values via IEC 61850 depending on the operator
position input (PSTO).
645
Logic

Boolean 16 to integer conversion with logic node representation function
(B16IFCVI) is used to transform a set of 16 binary (logical) signals into an integer.
The BLOCK input will freeze the output at the last value.

B16IFCVI
BLOCK OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IEC09000624 V1 EN
Figure 331: B16IFCVI function block

Table 400: B16IFCVI Input signals
646
Logic

Table 401: B16IFCVI Output signals

OUT INTEGER Output value

13.7 Integer to Boolean 16 conversion IB16

Integer to boolean 16 conversion IB16 - -
13.7.1 Introduction
Integer to boolean 16 conversion function (IB16) is used to transform an integer
into a set of 16 binary (logical) signals.

Integer to boolean 16 conversion function (IB16) is used to transform an integer
into a set of 16 binary (logical) signals. IB16 function is designed for receiving the
integer input locally. The BLOCK input will freeze the logical outputs at the last
value.
647
Logic

IB16
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
IEC06000501 V2 EN
Figure 332: IB16 function block

Table 402: IB16 Input signals
INP INTEGER 0 Integer Input
Table 403: IB16 Output signals

648
Logic

13.8 Integer to Boolean 16 conversion with logic node

representation IB16FCVB

Integer to boolean 16 conversion with IB16FCVB - -
logic node representation
13.8.1 Introduction
Integer to boolean conversion with logic node representation function (IB16FCVB)
is used to transform an integer to 16 binary (logic) signals.
IB16FCVB function can receive remote values over IEC61850 depending on the
operator position input (PSTO).

Integer to boolean conversion with logic node representation function (IB16FCVB)
is used to transform an integer into a set of 16 binary (logical) signals. IB16FCVB
function can receive an integer from a station computer – for example, over IEC
61850. The BLOCK input will freeze the logical outputs at the last value.
The operator position input (PSTO) determines the operator place. The integer
number can be written to the block while in “Remote”. If PSTO is in ”Off”
or ”Local”, then no change is applied to the outputs.
649
Logic

IB16FCVB
BLOCK OUT1
PSTO OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
IEC09000399 V1 EN
Figure 333: IB16FCVB function block

Table 404: IB16FCVB Input signals
Table 405: IB16FCVB Output signals

650
Logic

This function does not have any setting parameters.
651
652
Monitoring
Section 14 Monitoring
About this chapter

This chapter describes the functions that handle measurements, events and
disturbances. The way the functions work, their setting parameters, function
blocks, input and output signals, and technical data are included for each function.
14.1 Measurements

Measurements CVMMXN -
P, Q, S, I, U, f
SYMBOL-RR V1 EN
Phase current measurement CMMXU -

I
SYMBOL-SS V1 EN
Phase-phase voltage measurement VMMXU -

U
SYMBOL-UU V1 EN
Current sequence component CMSQI -

measurement
I1, I2, I0
SYMBOL-VV V1 EN
Voltage sequence measurement VMSQI -

U1, U2, U0
SYMBOL-TT V1 EN
Phase-neutral voltage measurement VNMMXU -

U
SYMBOL-UU V1 EN
653
Monitoring
14.1.1 Introduction
Measurement functions is used for power system measurement, supervision and
reporting to the local HMI, monitoring tool within PCM600 or to station level for
example, via IEC 61850. The possibility to continuously monitor measured values
of active power, reactive power, currents, voltages, frequency, power factor etc. is
vital for efficient production, transmission and distribution of electrical energy. It
provides to the system operator fast and easy overview of the present status of the
power system. Additionally, it can be used during testing and commissioning of
protection and control IEDs in order to verify proper operation and connection of
instrument transformers (CTs and VTs). During normal service by periodic
comparison of the measured value from the IED with other independent meters the
proper operation of the IED analog measurement chain can be verified. Finally, it
can be used to verify proper direction orientation for distance or directional
overcurrent protection function.
The available measured values of an IED are depending on the

actual hardware (TRM) and the logic configuration made in PCM600.
All measured values can be supervised with four settable limits that is, low-low
limit, low limit, high limit and high-high limit. A zero clamping reduction is also
supported, that is, the measured value below a settable limit is forced to zero which
reduces the impact of noise in the inputs.
Dead-band supervision can be used to report measured signal value to station level
when change in measured value is above set threshold limit or time integral of all
changes since the last time value updating exceeds the threshold limit. Measure
value can also be based on periodic reporting.
The measurement function, CVMMXN, provides the following power system

quantities:
• P, Q and S: three phase active, reactive and apparent power

• PF: power factor
• U: phase-to-phase voltage amplitude
• I: phase current amplitude
• F: power system frequency
Main menu/Measurement/Monitoring/Service values/CVMMXN
The measuring functions CMMXU, VNMMXU and VMMXU provide physical

quantities:
• I: phase currents (amplitude and angle) (CMMXU)

• U: voltages (phase-to-earth and phase-to-phase voltage, amplitude and angle)
(VMMXU, VNMMXU)
654
Monitoring
It is possible to calibrate the measuring function above to get better then class 0.5
presentation. This is accomplished by angle and amplitude compensation at 5, 30
and 100% of rated current and at 100% of rated voltage.
The power system quantities provided, depends on the actual

hardware, (TRM) and the logic configuration made in PCM600.
The measuring functions CMSQI and VMSQI provide sequential quantities:
• I: sequence currents (positive, zero, negative sequence, amplitude and angle)

• U: sequence voltages (positive, zero and negative sequence, amplitude and
angle).
The CVMMXN function calculates three-phase power quantities by using

fundamental frequency phasors (DFT values) of the measured current respectively
voltage signals. The measured power quantities are available either, as
instantaneously calculated quantities or, averaged values over a period of time (low
pass filtered) depending on the selected settings.
14.1.2.1 Measurement supervision
The protection, control, and monitoring IEDs have functionality to measure and
further process information for currents and voltages obtained from the pre-
processing blocks. The number of processed alternate measuring quantities
depends on the type of IED and built-in options.
The information on measured quantities is available for the user at different locations:
• Locally by means of the local HMI

• Remotely using the monitoring tool within PCM600 or over the station bus
• Internally by connecting the analogue output signals to the Disturbance Report
function
Phase angle reference

All phase angles are presented in relation to a defined reference channel. The
General setting parameter PhaseAngleRef defines the reference.
Zero point clamping

Measured value below zero point clamping limit is forced to zero. This allows the
noise in the input signal to be ignored. The zero point clamping limit is a general
setting (XZeroDb where X equals S, P, Q, PF, U, I, F, IL1-3, UL1-3, UL12-31, I1,
I2, 3I0, U1, U2 or 3U0). Observe that this measurement supervision zero point
clamping might be overridden by the zero point clamping used for the
measurement values within CVMMXU.
655
Monitoring
Continuous monitoring of the measured quantity

Users can continuously monitor the measured quantity available in each function
block by means of four defined operating thresholds, see figure 334. The
monitoring has two different modes of operating:
• Overfunction, when the measured current exceeds the High limit (XHiLim) or
High-high limit (XHiHiLim) pre-set values
• Underfunction, when the measured current decreases under the Low limit
(XLowLim) or Low-low limit (XLowLowLim) pre-set values.
X_RANGE is illustrated in figure 334.
X_RANGE = 3
High-high limit
X_RANGE= 1 Hysteresis
High limit
X_RANGE=0
X_RANGE=0 t
Low limit
X_RANGE=2
Low-low limit
X_RANGE=4
en05000657.vsd
IEC05000657 V1 EN
Figure 334: Presentation of operating limits
Each analogue output has one corresponding supervision level output

(X_RANGE). The output signal is an integer in the interval 0-4 (0: Normal, 1:
High limit exceeded, 3: High-high limit exceeded, 2: below Low limit and 4: below
Low-low limit). The output may be connected to a measurement expander block
(XP (RANGE_XP)) to get measurement supervision as binary signals.
The logical value of the functional output signals changes according to figure 334.
The user can set the hysteresis (XLimHyst), which determines the difference
between the operating and reset value at each operating point, in wide range for
each measuring channel separately. The hysteresis is common for all operating
values within one channel.
Actual value of the measured quantity

The actual value of the measured quantity is available locally and remotely. The
measurement is continuous for each measured quantity separately, but the reporting
of the value to the higher levels depends on the selected reporting mode. The
following basic reporting modes are available:
656
Monitoring
• Cyclic reporting (Cyclic)

• Amplitude dead-band supervision (Dead band)
• Integral dead-band supervision (Int deadband)
Cyclic reporting
The cyclic reporting of measured value is performed according to chosen setting
(XRepTyp). The measuring channel reports the value independent of amplitude or
integral dead-band reporting.
In addition to the normal cyclic reporting the IED also report spontaneously when
measured value passes any of the defined threshold limits.
Y
Value Reported Value Reported
(1st)
Y3 Value Reported
Y2 Y4
Y1 Y5
t (*) t (*) t (*) t (*)
t
Value 1
Value 2
Value 3
Value 4
Value 5
en05000500.vsd
(*)Set value for t: XDbRepInt
IEC05000500 V1 EN
Figure 335: Periodic reporting
Amplitude dead-band supervision

If a measuring value is changed, compared to the last reported value, and the
change is larger than the ±ΔY pre-defined limits that are set by user (XZeroDb),
then the measuring channel reports the new value to a higher level, if this is
detected by a new measured value. This limits the information flow to a minimum
necessary. Figure 336 shows an example with the amplitude dead-band
supervision. The picture is simplified: the process is not continuous but the values
are evaluated with a time interval of one execution cycle from each other.
657
Monitoring
Value Reported
Y

Value Reported
(1st)
Y3 DY
DY
Y2 DY
DY
DY
DY
Y1
99000529.vsd
IEC99000529 V1 EN
Figure 336: Amplitude dead-band supervision reporting
After the new value is reported, the ±ΔY limits for dead-band are automatically set
around it. The new value is reported only if the measured quantity changes more
than defined by the ±ΔY set limits. Even if amplitude dead-band reporting is
selected, there will be a 30 s "back-ground" cyclic reporting as well.
Integral dead-band reporting

The measured value is reported if the time integral of all changes exceeds the pre-
set limit (XZeroDb), figure 337, where an example of reporting with integral dead-
band supervision is shown. The picture is simplified: the process is not continuous
but the values are evaluated with a time interval of one execution cycle from each
other.
The last value reported, Y1 in figure 337 serves as a basic value for further
measurement. A difference is calculated between the last reported and the newly
measured value and is multiplied by the time increment (discrete integral). The
absolute values of these integral values are added until the pre-set value is
exceeded. This occurs with the value Y2 that is reported and set as a new base for
the following measurements (as well as for the values Y3, Y4 and Y5).
The integral dead-band supervision is particularly suitable for monitoring signals

with small variations that can last for relatively long periods. Even if integral dead-
band reporting is selected, there will be a 30 s "back-ground" cyclic reporting as well.
658
Monitoring
Y A1 >=
A >= pre-set value
A2 >=
pre-set value pre-set value
Y3 A3 + A4 + A5 + A6 + A7 >=
pre-set value
Y2 A1 A2
A4 A6
Value Reported Y4 A3 A5 A7
(1st) Value
Value Reported Y5
A Reported Value
Reported Value
Y1 Reported
t
99000530.vsd
IEC99000530 V1 EN
Figure 337: Reporting with integral dead-band supervision
14.1.2.2 Measurements CVMMXN
Mode of operation
The measurement function must be connected to three-phase current and three-
phase voltage input in the configuration tool (group signals), but it is capable to
measure and calculate above mentioned quantities in nine different ways depending
on the available VT inputs connected to the IED. The end user can freely select by
a parameter setting, which one of the nine available measuring modes shall be used
within the function. Available options are summarized in the following table:
Set value for Formula used for complex, three- Formula used for voltage and Comment
parameter phase power calculation current magnitude calculation
“Mode”
1 L1, L2, L3 Used when
* * *
S = U L1 × I L1 + U L 2 × I L 2 + U L 3 × I L 3 U = ( U L1 + U L 2 + U L 3 ) / 3
three phase-
EQUATION1385 V1 EN
to-earth
I = ( I L1 + I L 2 + I L 3 ) / 3
voltages are
EQUATION1386 V1 EN available
2 Arone Used when
S = U L1 L 2 × I L1 - U L 2 L 3 × I L 3
* *
U = ( U L1 L 2 + U L 2 L 3 ) / 2 three two
phase-to-
(Equation 128)
I = ( I L1 + I L 3 ) / 2 phase
EQUATION1387 V1 EN
voltages are
EQUATION1388 V1 EN (Equation 129) available
3 PosSeq Used when
S = 3 × U PosSeq × I PosSeq
*
U = 3 × U PosSeq only
symmetrical
(Equation 130) three phase
EQUATION1389 V1 EN
I = I PosSeq
power shall
EQUATION1390 V1 EN (Equation 131) be measured
659
Monitoring
Set value for Formula used for complex, three- Formula used for voltage and Comment
parameter phase power calculation current magnitude calculation
“Mode”
4 L1L2 Used when
S = U L1 L 2 × ( I L*1 - I L* 2 ) U = U L1 L 2 only UL1L2
phase-to-
(Equation 132)
I = ( I L1 + I L 2 ) / 2
EQUATION1391 V1 EN
phase
voltage is
5 L2L3 Used when
S = U L 2 L3 × ( I L 2 - I L3 )
* *
U = U L2 L3 only UL2L3
phase-to-
(Equation 134)
I = ( I L2 + I L3 ) / 2
EQUATION1393 V1 EN
phase
voltage is
6 L3L1 Used when
S = U L 3 L1 × ( I L 3 - I L1 )
* *
U = U L 3 L1 only UL3L1
phase-to-
(Equation 136)
I = ( I L 3 + I L1 ) / 2
EQUATION1395 V1 EN
phase
voltage is
7 L1 Used when
S = 3 × U L1 × I L1
*
U = 3 × U L1 only UL1
phase-to-
(Equation 138) earth voltage
I = I L1
EQUATION1397 V1 EN
is available
8 L2 Used when
S = 3 ×U L2 × I L2
*
phase-to-
(Equation 140) earth voltage
I = IL2
EQUATION1399 V1 EN
is available
9 L3 Used when
S = 3 ×U L3 × I L3
*
phase-to-
(Equation 142)
I = I L3 earth voltage
EQUATION1401 V1 EN
is available
* means complex conjugated value
It shall be noted that only in the first two operating modes that is, 1 & 2 the
measurement function calculates exact three-phase power. In other operating
modes that is, from 3 to 9 it calculates the three-phase power under assumption that
the power system is fully symmetrical. Once the complex apparent power is
calculated then the P, Q, S, & PF are calculated in accordance with the following
formulas:
P = Re( S )
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Monitoring
Q = Im( S )
S = S = P +Q
2 2
PF = cosj = P
S
Additionally to the power factor value the two binary output signals from the
function are provided which indicates the angular relationship between current and
voltage phasors. Binary output signal ILAG is set to one when current phasor is
lagging behind voltage phasor. Binary output signal ILEAD is set to one when
current phasor is leading the voltage phasor.
Each analogue output has a corresponding supervision level output (X_RANGE).

The output signal is an integer in the interval 0-4, see section "Measurement
supervision".
Calibration of analog inputs

Measured currents and voltages used in the CVMMXN function can be calibrated
to get class 0.5 measuring accuracy. This is achieved by amplitude and angle
below 5% and above 100% is constant and linear in between, see example in
figure 338.
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IEC05000652 V2 EN
Low pass filtering

possible to introduce the recursive, low pass filtering of the measured values for P,
Q, S, U, I and power factor. This will make slower measurement response to the
step changes in the measured quantity. Filtering is performed in accordance with
the following recursive formula:
X = k × X Old + (1 - k ) × X Calculated
where:
X is a new measured value (that is P, Q, S, U, I or PF) to be given out from the function
XOld is the measured value given from the measurement function in previous execution cycle
XCalculated is the new calculated value in the present execution cycle
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Monitoring
immediately given out without any filtering (that is, without any additional delay).
When k is set to value bigger than 0, the filtering is enabled. Appropriate value of k
shall be determined separately for every application. Some typical value for k =0.14.
Zero point clamping

In order to avoid erroneous measurements when either current or voltage signal is
not present, it is possible for the end user to set the amplitudeIGenZeroDb level for
current and voltage measurement UGenZeroDb is forced to zero. When either
current or voltage measurement is forced to zero automatically the measured values
for power (P, Q and S) and power factor are forced to zero as well. Since the
measurement supervision functionality, included in CVMMXN, is using these
values the zero clamping will influence the subsequent supervision (observe the
possibility to do zero point clamping within measurement supervision, see section
"Measurement supervision").
Compensation facility
In order to compensate for small amplitude and angular errors in the complete
measurement chain (CT error, VT error, IED input transformer errors and so on.) it
is possible to perform on site calibration of the power measurement. This is
achieved by setting the complex constant which is then internally used within the
function to multiply the calculated complex apparent power S. This constant is set
as amplitude (setting parameter PowAmpFact, default value 1.000) and angle
(setting parameter PowAngComp, default value 0.0 degrees). Default values for
these two parameters are done in such way that they do not influence internally
calculated value (complex constant has default value 1). In this way calibration, for
specific operating range (for example, around rated power) can be done at site.
However, to perform this calibration it is necessary to have an external power
meter with high accuracy class available.
Directionality
If CT earthing parameter is set as described in section "Analog inputs", active and
reactive power will be measured always towards the protected object. This is
shown in the following figure 339.
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Monitoring
Busbar
IED
P Q
Protected
Object
IEC09000038-1-EN V1 EN
Figure 339: Internal IED directionality convention for P & Q measurements
Practically, it means that active and reactive power will have positive values when
they flow from the busbar towards the protected object and they will have negative
values when they flow from the protected object towards the busbar.
In some application, for example, when power is measured on the secondary side
of the power transformer it might be desirable, from the end client point of view, to
have actually opposite directional convention for active and reactive power
measurements. This can be easily achieved by setting parameter PowAngComp to
value of 180.0 degrees. With such setting the active and reactive power will have
positive values when they flow from the protected object towards the busbar.
Frequency
Frequency is actually not calculated within measurement block. It is simply
obtained from the pre-processing block and then just given out from the
measurement block as an output.
14.1.2.3 Phase current measurement CMMXU
The Phase current measurement (CMMXU) function must be connected to three-

phase current input in the configuration tool to be operable. Currents handled in the
function can be calibrated to get better then class 0.5 measuring accuracy for
internal use, on the outputs and IEC 61850. This is achieved by amplitude and
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Monitoring
angle compensation at 5, 30 and 100% of rated current. The compensation below

5% and above 100% is constant and linear in between, see figure 338.
Phase currents (amplitude and angle) are available on the outputs and each
amplitude output has a corresponding supervision level output (ILx_RANG). The
supervision output signal is an integer in the interval 0-4, see section
"Measurement supervision".
14.1.2.4 Phase-phase and phase-neutral voltage measurements VMMXU,

VNMMXU
The voltage function must be connected to three-phase voltage input in the

configuration tool to be operable. Voltages are handled in the same way as currents
when it comes to class 0.5 calibrations, see above.
The voltages (phase or phase-phase voltage, amplitude and angle) are available on
the outputs and each amplitude output has a corresponding supervision level output
(ULxy_RANG). The supervision output signal is an integer in the interval 0-4, see
section "Measurement supervision".
14.1.2.5 Voltage and current sequence measurements VMSQI, CMSQI
The measurement functions must be connected to three-phase current (CMSQI) or

voltage (VMSQI) input in the configuration tool to be operable. No outputs, but
XRANG, are calculated within the measuring block and it is not possible to
calibrate the signals. Input signals are obtained from the pre-processing block and
transferred to corresponding output.
Positive, negative and three times zero sequence quantities are available on the
outputs (voltage and current, amplitude and angle). Each amplitude output has a
corresponding supervision level output (X_RANGE). The output signal is an
integer in the interval 0-4, see section "Measurement supervision".

The available function blocks of an IED are depending on the actual hardware
(TRM) and the logic configuration made in PCM600.
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Monitoring
CVMMXN
I3P* S
U3P* S_RANGE
P_INST
P
P_RANGE
Q_INST
Q
Q_RANGE
PF
PF_RANGE
ILAG
ILEAD
U
U_RANGE
I
I_RANGE
F
F_RANGE
IEC10000016 V1 EN
Figure 340: CVMMXN function block
CMMXU
I3P* IL1
IL1RANG
IL1ANGL
IL2
IL2RANG
IL2ANGL
IL3
IL3RANG
IL3ANGL
IEC05000699 V2 EN
Figure 341: CMMXU function block
VNMMXU
U3P* UL1
UL1RANG
UL1ANGL
UL2
UL2RANG
UL2ANGL
UL3
UL3RANG
UL3ANGL
IEC09000850 V1 EN
Figure 342: VNMMXU function block
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Monitoring
VMMXU
U3P* UL12
UL12RANG
UL12ANGL
UL23
UL23RANG
UL23ANGL
UL31
UL31RANG
UL31ANGL
IEC05000701 V2 EN
Figure 343: VMMXU function block
CMSQI
I3P* 3I0
3I0RANG
3I0ANGL
I1
I1RANG
I1ANGL
I2
I2RANG
I2ANGL
IEC05000703 V2 EN
Figure 344: CMSQI function block
VMSQI
U3P* 3U0
3U0RANG
3U0ANGL
U1
U1RANG
U1ANGL
U2
U2RANG
U2ANGL
IEC05000704 V2 EN
Figure 345: VMSQI function block

Table 406: CVMMXN Input signals
SIGNAL
SIGNAL
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Table 407: CVMMXN Output signals

S REAL Apparent Power magnitude of deadband value
S_RANGE INTEGER Apparent Power range
P_INST REAL Active Power
P REAL Active Power magnitude of deadband value
P_RANGE INTEGER Active Power range
Q_INST REAL Reactive Power
Q REAL Reactive Power magnitude of deadband value
Q_RANGE INTEGER Reactive Power range
PF REAL Power Factor magnitude of deadband value
PF_RANGE INTEGER Power Factor range
ILAG BOOLEAN Current is lagging voltage
ILEAD BOOLEAN Current is leading voltage
U REAL Calculate voltage magnitude of deadband value
U_RANGE INTEGER Calcuate voltage range
I REAL Calculated current magnitude of deadband value
I_RANGE INTEGER Calculated current range
F REAL System frequency magnitude of deadband value
F_RANGE INTEGER System frequency range
Table 408: CMMXU Input signals

I3P GROUP - Group connection abstract block 1
SIGNAL
Table 409: CMMXU Output signals

IL1 REAL IL1 Amplitude, magnitude of reported value
IL1RANG INTEGER IL1 Amplitude range
IL1ANGL REAL IL1 Angle, magnitude of reported value
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Table 410: VNMMXU Input signals

U3P GROUP - Group connection abstract block 5
SIGNAL
Table 411: VNMMXU Output signals

UL1 REAL UL1 Amplitude, magnitude of reported value
UL1RANG INTEGER UL1 Amplitude range
UL1ANGL REAL UL1 Angle, magnitude of reported value
Table 412: VMMXU Input signals

SIGNAL
Table 413: VMMXU Output signals

Table 414: CMSQI Input signals

I3P GROUP - Group connection abstract block 3
SIGNAL
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Table 415: CMSQI Output signals

3I0 REAL 3I0 Amplitude, magnitude of reported value
3I0RANG INTEGER 3I0 Amplitude range
3I0ANGL REAL 3I0 Angle, magnitude of reported value
I1 REAL I1 Amplitude, magnitude of reported value
I1RANG INTEGER I1 Amplitude range
I1ANGL REAL I1 Angle, magnitude of reported value
I2 REAL I2 Amplitude, magnitude of reported value
I2RANG INTEGER I2 Amplitude range
I2ANGL REAL I2 Angle, magnitude of reported value
Table 416: VMSQI Input signals

SIGNAL
Table 417: VMSQI Output signals

3U0 REAL 3U0 Amplitude, magnitude of reported value
3U0RANG INTEGER 3U0 Amplitude range
3U0ANGL REAL 3U0 Angle, magnitude of reported value
U1 REAL U1 Amplitude, magnitude of reported value
U1RANG INTEGER U1 Amplitude range
U1ANGL REAL U1 Angle, magnitude of reported value
U2 REAL U2 Amplitude, magnitude of reported value
U2RANG INTEGER U2 Amplitude range
U2ANGL REAL U2 Angle, magnitude of reported value

The available setting parameters of the measurement function (MMXU, MSQI) are
depending on the actual hardware (TRM) and the logic configuration made in
PCM600.
Table 418: CVMMXN Non group settings (basic)

SLowLim 0.0 - 2000.0 %SB 0.1 80.0 Low limit in % of SBase
SLowLowLim 0.0 - 2000.0 %SB 0.1 60.0 Low Low limit in % of SBase
SMin 0.0 - 2000.0 %SB 0.1 50.0 Minimum value in % of SBase
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Monitoring

SMax 0.0 - 2000.0 %SB 0.1 200.0 Maximum value in % of SBase
SRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
PMin -2000.0 - 2000.0 %SB 0.1 -200.0 Minimum value in % of SBase
PMax -2000.0 - 2000.0 %SB 0.1 200.0 Maximum value in % of SBase
PRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
QMin -2000.0 - 2000.0 %SB 0.1 -200.0 Minimum value in % of SBase
QMax -2000.0 - 2000.0 %SB 0.1 200.0 Maximum value in % of SBase
QRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
PFMin -1.000 - 1.000 - 0.001 -1.000 Minimum value
PFMax -1.000 - 1.000 - 0.001 1.000 Maximum value
PFRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
UMin 0.0 - 200.0 %UB 0.1 50.0 Minimum value in % of UBase
UMax 0.0 - 200.0 %UB 0.1 200.0 Maximum value in % of UBase
URepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
IMin 0.0 - 500.0 %IB 0.1 50.0 Minimum value in % of IBase
IMax 0.0 - 500.0 %IB 0.1 200.0 Maximum value in % of IBase
IRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
FrMin 0.000 - 100.000 Hz 0.001 0.000 Minimum value
FrMax 0.000 - 100.000 Hz 0.001 70.000 Maximum value
FrRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
On
IBase 1 - 99999 A 1 3000 Base setting for current values in A
UBase 0.05 - 2000.00 kV 0.05 400.00 Base setting for voltage value in kV
SBase 0.05 - 200000.00 MVA 0.05 2080.00 Base setting for power values in MVA
Mode L1, L2, L3 - - L1, L2, L3 Selection of measured current and
Arone voltage
Pos Seq
L1L2
L2L3
L3L1
L1
L2
L3
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PowAmpFact 0.000 - 6.000 - 0.001 1.000 Amplitude factor to scale power
calculations
PowAngComp -180.0 - 180.0 Deg 0.1 0.0 Angle compensation for phase shift
between measured I & U
measurement, U and I
Table 419: CVMMXN Non group settings (advanced)

SDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
range, Int Db: In %s
SZeroDb 0 - 100000 m% 1 500 Zero point clamping in 0,001% of range
SHiHiLim 0.0 - 2000.0 %SB 0.1 150.0 High High limit in % of SBase
SHiLim 0.0 - 2000.0 %SB 0.1 120.0 High limit in % of SBase
SLimHyst 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range (common
for all limits)
PDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
PZeroDb 0 - 100000 m% 1 500 Zero point clamping in 0,001% of range
PHiHiLim -2000.0 - 2000.0 %SB 0.1 150.0 High High limit in % of SBase
PHiLim -2000.0 - 2000.0 %SB 0.1 120.0 High limit in % of SBase
PLowLim -2000.0 - 2000.0 %SB 0.1 -120.0 Low limit in % of SBase
PLowLowLim -2000.0 - 2000.0 %SB 0.1 -150.0 Low Low limit in % of SBase
PLimHyst 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range (common
for all limits)
QDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
QZeroDb 0 - 100000 m% 1 500 Zero point clamping in 0,001% of range
QHiHiLim -2000.0 - 2000.0 %SB 0.1 150.0 High High limit in % of SBase
QHiLim -2000.0 - 2000.0 %SB 0.1 120.0 High limit in % of SBase
QLowLim -2000.0 - 2000.0 %SB 0.1 -120.0 Low limit in % of SBase
QLowLowLim -2000.0 - 2000.0 %SB 0.1 -150.0 Low Low limit in % of SBase
QLimHyst 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range (common
for all limits)
PFDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
PFZeroDb 0 - 100000 m% 1 500 Zero point clamping in 0,001% of range
PFHiHiLim -1.000 - 1.000 - 0.001 1.000 High High limit (physical value)
PFHiLim -1.000 - 1.000 - 0.001 0.800 High limit (physical value)
PFLowLim -1.000 - 1.000 - 0.001 -0.800 Low limit (physical value)
PFLowLowLim -1.000 - 1.000 - 0.001 -1.000 Low Low limit (physical value)
PFLimHyst 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range (common
for all limits)
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UDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
UZeroDb 0 - 100000 m% 1 500 Zero point clamping in 0,001% of range
UHiHiLim 0.0 - 200.0 %UB 0.1 150.0 High High limit in % of UBase
UHiLim 0.0 - 200.0 %UB 0.1 120.0 High limit in % of UBase
ULowLim 0.0 - 200.0 %UB 0.1 80.0 Low limit in % of UBase
ULowLowLim 0.0 - 200.0 %UB 0.1 60.0 Low Low limit in % of UBase
ULimHyst 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range (common
for all limits)
IDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
IZeroDb 0 - 100000 m% 1 500 Zero point clamping in 0,001% of range
IHiHiLim 0.0 - 500.0 %IB 0.1 150.0 High High limit in % of IBase
IHiLim 0.0 - 500.0 %IB 0.1 120.0 High limit in % of IBase
ILowLim 0.0 - 500.0 %IB 0.1 80.0 Low limit in % of IBase
ILowLowLim 0.0 - 500.0 %IB 0.1 60.0 Low Low limit in % of IBase
ILimHyst 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range (common
for all limits)
FrDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
FrZeroDb 0 - 100000 m% 1 500 Zero point clamping in 0,001% of range
FrHiHiLim 0.000 - 100.000 Hz 0.001 65.000 High High limit (physical value)
FrHiLim 0.000 - 100.000 Hz 0.001 63.000 High limit (physical value)
FrLowLim 0.000 - 100.000 Hz 0.001 47.000 Low limit (physical value)
FrLowLowLim 0.000 - 100.000 Hz 0.001 45.000 Low Low limit (physical value)
FrLimHyst 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range (common
for all limits)
UGenZeroDb 1 - 100 %UB 1 5 Zero point clamping in % of Ubase
IGenZeroDb 1 - 100 %IB 1 5 Zero point clamping in % of Ibase
5% of Ur
30% of Ur
100% of Ur
5% of Ir
30% of Ir
100% of Ir
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Monitoring
Table 420: CMMXU Non group settings (basic)

IL1DbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
Operation Off - - Off Operation Mode On / Off
On
IBase 1 - 99999 A 1 3000 Base setting for current level in A
IL1Max 0.000 - A 0.001 1000.000 Maximum value
10000000000.000
IL1RepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
IL1AngDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
10000000000.000
Dead band
Int deadband
10000000000.000
Dead band
Int deadband
Table 421: CMMXU Non group settings (advanced)

IL1ZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
IL1HiHiLim 0.000 - A 0.001 900.000 High High limit (physical value)
10000000000.000
IL1HiLim 0.000 - A 0.001 800.000 High limit (physical value)
10000000000.000
5% of Ir
30% of Ir
IL1LowLim 0.000 - A 0.001 0.000 Low limit (physical value)
10000000000.000
IL1LowLowLim 0.000 - A 0.001 0.000 Low Low limit (physical value)
10000000000.000
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Monitoring

100% of Ir
IL1Min 0.000 - A 0.001 0.000 Minimum value
10000000000.000
IL1LimHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range and is
common for all limits
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
Table 422: VNMMXU Non group settings (basic)

UL1DbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
On
UBase 0.05 - 2000.00 kV 0.05 400.00 Base setting for voltage level in kV
UL1Max 0.000 - V 0.001 300000.000 Maximum value
10000000000.000
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Monitoring

UL1RepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
UL1LimHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range and is
UL1AnDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
10000000000.000
Dead band
Int deadband
10000000000.000
Dead band
Int deadband
Table 423: VNMMXU Non group settings (advanced)

UL1ZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
UL1HiHiLim 0.000 - V 0.001 260000.000 High High limit (physical value)
10000000000.000
UL1HiLim 0.000 - V 0.001 240000.000 High limit (physical value)
10000000000.000
UL1LowLim 0.000 - V 0.001 220000.000 Low limit (physical value)
10000000000.000
UL1LowLowLim 0.000 - V 0.001 200000.000 Low Low limit (physical value)
10000000000.000
100% of Ur
UL1Min 0.000 - V 0.001 0.000 Minimum value
10000000000.000
10000000000.000
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10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
Table 424: VMMXU Non group settings (basic)

On
UBase 0.05 - 2000.00 kV 0.05 400.00 Base setting for voltage level in kV
10000000000.000
Dead band
Int deadband
10000000000.000
Dead band
Int deadband
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Monitoring

10000000000.000
Dead band
Int deadband
Table 425: VMMXU Non group settings (advanced)

10000000000.000
10000000000.000
10000000000.000
10000000000.000
100% of Ur
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
10000000000.000
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Monitoring

10000000000.000
10000000000.000
Table 426: CMSQI Non group settings (basic)

3I0DbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
3I0Min 0.000 - A 0.001 0.000 Minimum value
10000000000.000
3I0Max 0.000 - A 0.001 1000.000 Maximum value
10000000000.000
3I0RepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
3I0LimHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range and is
3I0AngDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
On
3I0AngMin -180.000 - 180.000 Deg 0.001 -180.000 Minimum value
3I0AngMax -180.000 - 180.000 Deg 0.001 180.000 Maximum value
3I0AngRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
I1DbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
I1Min 0.000 - A 0.001 0.000 Minimum value
10000000000.000
I1Max 0.000 - A 0.001 1000.000 Maximum value
10000000000.000
I1RepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
I1AngDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
I1AngMax -180.000 - 180.000 Deg 0.001 180.000 Maximum value
I1AngRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
I2DbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
I2Min 0.000 - A 0.001 0.000 Minimum value
10000000000.000
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I2Max 0.000 - A 0.001 1000.000 Maximum value
10000000000.000
I2RepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
I2LimHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range and is
I2AngDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
I2AngMin -180.000 - 180.000 Deg 0.001 -180.000 Minimum value
I2AngRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
Table 427: CMSQI Non group settings (advanced)

3I0ZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
3I0HiHiLim 0.000 - A 0.001 900.000 High High limit (physical value)
10000000000.000
3I0HiLim 0.000 - A 0.001 800.000 High limit (physical value)
10000000000.000
3I0LowLim 0.000 - A 0.001 0.000 Low limit (physical value)
10000000000.000
3I0LowLowLim 0.000 - A 0.001 0.000 Low Low limit (physical value)
10000000000.000
3I0AngZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
I1ZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
I1HiHiLim 0.000 - A 0.001 900.000 High High limit (physical value)
10000000000.000
I1HiLim 0.000 - A 0.001 800.000 High limit (physical value)
10000000000.000
I1LowLim 0.000 - A 0.001 0.000 Low limit (physical value)
10000000000.000
I1LowLowLim 0.000 - A 0.001 0.000 Low Low limit (physical value)
10000000000.000
I1LimHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range and is
I1AngZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
I1AngMin -180.000 - 180.000 Deg 0.001 -180.000 Minimum value
I2ZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
I2HiHiLim 0.000 - A 0.001 900.000 High High limit (physical value)
10000000000.000
I2HiLim 0.000 - A 0.001 800.000 High limit (physical value)
10000000000.000
I2LowLim 0.000 - A 0.001 0.000 Low limit (physical value)
10000000000.000
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Monitoring

I2LowLowLim 0.000 - A 0.001 0.000 Low Low limit (physical value)
10000000000.000
I2AngZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
I2AngMax -180.000 - 180.000 Deg 0.001 180.000 Maximum value
Table 428: VMSQI Non group settings (basic)

3U0DbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
3U0Min 0.000 - V 0.001 0.000 Minimum value
10000000000.000
3U0Max 0.000 - V 0.001 300000.000 Maximum value
10000000000.000
3U0RepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
3U0LimHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range and is
3U0AngDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
On
3U0AngZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
3U0AngMin -180.000 - 180.000 Deg 0.001 -180.000 Minimum value
3U0AngMax -180.000 - 180.000 Deg 0.001 180.000 Maximum value
3U0AngRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
U1DbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
U1Min 0.000 - V 0.001 0.000 Minimum value
10000000000.000
U1Max 0.000 - V 0.001 300000.000 Maximum value
10000000000.000
U1RepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
U1LimHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range and is
U1AngDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
U2DbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
U2Min 0.000 - V 0.001 0.000 Minimum value
10000000000.000
U2Max 0.000 - V 0.001 300000.000 Maximum value
10000000000.000
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U2RepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
U2LimHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range and is
U2AngDbRepInt 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
U2AngMin -180.000 - 180.000 Deg 0.001 -180.000 Minimum value
U2AngMax -180.000 - 180.000 Deg 0.001 180.000 Maximum value
U2AngRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
UAmpPreComp5 -10.000 - 10.000 % 0.001 0.000 Amplitude factor to pre-calibrate voltage
at 5% of Ir
at 30% of Ir
at 100% of Ir
Table 429: VMSQI Non group settings (advanced)

3U0ZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
3U0HiHiLim 0.000 - V 0.001 260000.000 High High limit (physical value)
10000000000.000
3U0HiLim 0.000 - V 0.001 240000.000 High limit (physical value)
10000000000.000
3U0LowLim 0.000 - V 0.001 220000.000 Low limit (physical value)
10000000000.000
3U0LowLowLim 0.000 - V 0.001 200000.000 Low Low limit (physical value)
10000000000.000
U1ZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
U1HiHiLim 0.000 - V 0.001 260000.000 High High limit (physical value)
10000000000.000
U1HiLim 0.000 - V 0.001 240000.000 High limit (physical value)
10000000000.000
U1LowLim 0.000 - V 0.001 220000.000 Low limit (physical value)
10000000000.000
U1LowLowLim 0.000 - V 0.001 200000.000 Low Low limit (physical value)
10000000000.000
U1AngZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
U1AngMin -180.000 - 180.000 Deg 0.001 -180.000 Minimum value
U1AngMax -180.000 - 180.000 Deg 0.001 180.000 Maximum value
U1AngRepTyp Cyclic - - Cyclic Reporting type
Dead band
Int deadband
U2ZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range
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U2HiHiLim 0.000 - V 0.001 260000.000 High High limit (physical value)
10000000000.000
U2HiLim 0.000 - V 0.001 240000.000 High limit (physical value)
10000000000.000
U2LowLim 0.000 - V 0.001 220000.000 Low limit (physical value)
10000000000.000
U2LowLowLim 0.000 - V 0.001 200000.000 Low Low limit (physical value)
10000000000.000
U2AngZeroDb 0 - 100000 m% 1 0 Zero point clamping in 0,001% of range

Table 430: CVMMXN technical data
Frequency (0.95-1.05) × fr ± 2.0 mHz
Voltage (0.1-1.5) ×Ur ± 0.5% of Ur at U£Ur

± 0.5% of U at U > Ur
Connected current (0.2-4.0) × Ir ± 0.5% of Ir at I £ Ir

± 0.5% of I at I > Ir
Active power, P 0.1 x Ur Sr
Conditions:
Reactive power, Q 0.1 x Ur< U < 1.5 x Ur 0.8 x Ur < U < 1.2 Ur
0.2 x Ir < I < 4.0 x Ir 0.2 x Ir < I < 1.2 Ir
Apparent power, S 0.1 x Ur < U < 1.5 x Ur
0.2 x Ir< I < 4.0 x Ir
Power factor, cos (φ) 0.1 x Ur < U < 1.5 x Ur ± 0.02

0.2 x Ir< I < 4.0 x Ir
14.2 Event counter CNTGGIO
14.2.1 Identification
Event counter CNTGGIO -
S00946 V1 EN
14.2.2 Introduction
Event counter (CNTGGIO) has six counters which are used for storing the number
of times each counter input has been activated.
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Event counter (CNTGGIO) has six counter inputs. CNTGGIO stores how many
times each of the inputs has been activated. The counter memory for each of the six
inputs is updated, giving the total number of times the input has been activated, as
soon as an input is activated. The maximum count up speed is 10 pulses per
second. The maximum counter value is 10 000. For counts above 10 000 the
counter will stop at 10 000 and no restart will take place.
To not risk that the flash memory is worn out due to too many writings, a
mechanism for limiting the number of writings per time period is included in the
product. This however gives as a result that it can take long time, up to several
minutes, before a new value is stored in the flash memory. And if a new
CNTGGIO value is not stored before auxiliary power interruption, it will be lost.
CNTGGIO stored values in flash memory will however not be lost at an auxiliary
power interruption.
The function block also has an input BLOCK. At activation of this input all six
counters are blocked. The input can for example, be used for blocking the counters
at testing.The function block has an input RESET. At activation of this input all six
counters are set to 0.
All inputs are configured via PCM600.
14.2.3.1 Reporting
The content of the counters can be read in the local HMI.
Reset of counters can be performed in the local HMI and a binary input.
Reading of content can also be performed remotely, for example from a IEC 61850
client. The value can also be presented as a measuring value on the local HMI
graphical display.
14.2.3.2 Design
The function block has six inputs for increasing the counter values for each of the
six counters respectively. The content of the counters are stepped one step for each
positive edge of the input respectively.
The function block also has an input BLOCK. At activation of this input all six
counters are blocked and are not updated. Valid number is held.
The function block has an input RESET. At activation of this input all six counters
are set to 0.
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Monitoring

CNTGGIO
BLOCK VALUE1
COUNTER1 VALUE2
COUNTER2 VALUE3
COUNTER3 VALUE4
COUNTER4 VALUE5
COUNTER5 VALUE6
COUNTER6
RESET
IEC05000345 V2 EN
Figure 346: CNTGGIO function block
14.2.5 Input signals

Table 431: CNTGGIO Input signals
COUNTER1 BOOLEAN 0 Input for counter1
RESET BOOLEAN 0 Reset of function
Table 432: CNTGGIO Output signals

VALUE1 INTEGER Output of counter1

Table 433: CNTGGIO Group settings (basic)
On
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Table 434: CNTGGIO technical data
Counter value 0-10000 -
Max. count up speed 10 pulses/s -
14.3 Event function EVENT

Event function EVENT -
S00946 V1 EN
14.3.1 Introduction
When using a Substation Automation system with LON or SPA communication,
time-tagged events can be sent at change or cyclically from the IED to the station
level. These events are created from any available signal in the IED that is
connected to the Event function (EVENT). The event function block is used for
LON and SPA communication.
Analog and double indication values are also transferred through EVENT function.

The main purpose of the event function (EVENT) is to generate events when the
state or value of any of the connected input signals is in a state, or is undergoing a
state transition, for which event generation is enabled.
Each EVENT function has 16 inputs INPUT1 - INPUT16. Each input can be given
a name from the Application Configuration tool. The inputs are normally used to
create single events, but are also intended for double indication events.
EVENT function also has an input BLOCK to block the generation of events.
The events that are sent from the IED can originate from both internal logical
signals and binary input channels. The internal signals are time-tagged in the main
processing module, while the binary input channels are time-tagged directly on the
input module. The time-tagging of the events that are originated from internal
logical signals have a resolution corresponding to the execution cyclicity of
EVENT function. The time-tagging of the events that are originated from binary
input signals have a resolution of 1 ms.
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Monitoring
The outputs from EVENT function are formed by the reading of status, events and
alarms by the station level on every single input. The user-defined name for each
input is intended to be used by the station level.
All events according to the event mask are stored in a buffer, which contains up to
1000 events. If new events appear before the oldest event in the buffer is read, the
oldest event is overwritten and an overflow alarm appears.
The events are produced according to the set-event masks. The event masks are
treated commonly for both the LON and SPA communication. The EventMask can
be set individually for each input channel. These settings are available:
• NoEvents
• OnSet
• OnReset
• OnChange
• AutoDetect
It is possible to define which part of EVENT function generates the events. This
can be performed individually for the SPAChannelMask and LONChannelMask
respectively. For each communication type these settings are available:
• Off
• Channel 1-8
• Channel 9-16
• Channel 1-16
For LON communication the events normally are sent to station level at change. It
is possibly also to set a time for cyclic sending of the events individually for each
input channel.
To protect the SA system from signals with a high change rate that can easily
saturate the event system or the communication subsystems behind it, a quota
limiter is implemented. If an input creates events at a rate that completely consume
the granted quota then further events from the channel will be blocked. This block
will be removed when the input calms down and the accumulated quota reach 66%
of the maximum burst quota. The maximum burst quota per input channel is 45
events per second.
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EVENT
BLOCK
ÎNPUT1
ÎNPUT2
ÎNPUT3
ÎNPUT4
ÎNPUT5
ÎNPUT6
ÎNPUT7
ÎNPUT8
ÎNPUT9
ÎNPUT10
ÎNPUT11
ÎNPUT12
ÎNPUT13
ÎNPUT14
ÎNPUT15
ÎNPUT16
IEC05000697 V2 EN
Figure 347: EVENT function block

Table 435: EVENT Input signals
INPUT1 GROUP 0 Input 1
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
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SIGNAL
SIGNAL
SIGNAL
SIGNAL

Table 436: EVENT Non group settings (basic)
SPAChannelMask Off - - Off SPA channel mask
Channel 1-8
Channel 9-16
Channel 1-16
LONChannelMask Off - - Off LON channel mask
Channel 1-8
Channel 9-16
Channel 1-16
EventMask1 NoEvents - - AutoDetect Reporting criteria for input 1
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
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OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
OnSet
OnReset
OnChange
AutoDetect
MinRepIntVal1 0 - 3600 s 1 2 Minimum reporting interval input 1
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14.4 Logical signal status report BINSTATREP

Logical signal status report BINSTATREP - -
14.4.1 Introduction
The Logical signal status report (BINSTATREP) function makes it possible for a
SPA master to poll signals from various other functions.

The Logical signal status report (BINSTATREP) function has 16 inputs and 16
outputs. The output status follows the inputs and can be read from the local HMI or
via SPA communication.
When an input is set, the respective output is set for a user defined time. If the
input signal remains set for a longer period, the output will remain set until the
input signal resets.
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INPUTn
OUTPUTn
t t
IEC09000732 V1 EN
Figure 348: BINSTATREP logical diagram

BINSTATREP
BLOCK OUTPUT1
ÎNPUT1 OUTPUT2
ÎNPUT2 OUTPUT3
ÎNPUT3 OUTPUT4
ÎNPUT4 OUTPUT5
ÎNPUT5 OUTPUT6
ÎNPUT6 OUTPUT7
ÎNPUT7 OUTPUT8
ÎNPUT8 OUTPUT9
ÎNPUT9 OUTPUT10
ÎNPUT10 OUTPUT11
ÎNPUT11 OUTPUT12
ÎNPUT12 OUTPUT13
ÎNPUT13 OUTPUT14
ÎNPUT14 OUTPUT15
ÎNPUT15 OUTPUT16
ÎNPUT16
IEC09000730 V1 EN
Figure 349: BINSTATREP function block

Table 437: BINSTATREP Input signals
INPUT1 BOOLEAN 0 Single status report input 1
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Table 438: BINSTATREP Output signals

OUTPUT1 BOOLEAN Logical status report output 1

Table 439: BINSTATREP Non group settings (basic)
t 0.000 - 60000.000 s 0.001 10.000 Time delay of function
14.5 Measured value expander block RANGE_XP

Measured value expander block RANGE_XP - -
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Monitoring
14.5.1 Introduction
The current and voltage measurements functions (CVMMXN, CMMXU, VMMXU
and VNMMXU), current and voltage sequence measurement functions (CMSQI
and VMSQI) and IEC 61850 generic communication I/O functions (MVGGIO) are
provided with measurement supervision functionality. All measured values can be
supervised with four settable limits: low-low limit, low limit, high limit and high-
high limit. The measure value expander block (RANGE_XP) has been introduced
to enable translating the integer output signal from the measuring functions to 5
binary signals: below low-low limit, below low limit, normal, above high-high
limit or above high limit. The output signals can be used as conditions in the
configurable logic or for alarming purpose.

The input signal must be connected to a range output of a measuring function block
(CVMMXN, CMMXU, VMMXU, VNMMXU, CMSQI, VMSQ or MVGGIO).
The function block converts the input integer value to five binary output signals
according to table 440.
Table 440: Input integer value converted to binary output signals

Measured supervised below low-low between low‐ between low between high- above high-
value is: limit low and low and high limit high and high high limit
Output: limit limit
LOWLOW High
LOW High
NORMAL High
HIGH High
HIGHHIGH High

RANGE_XP
RANGE* HIGHHIGH
HIGH
NORMAL
LOW
LOWLOW
IEC05000346 V2 EN
Figure 350: RANGE_XP function block

Table 441: RANGE_XP Input signals
RANGE INTEGER 0 Measured value range
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Table 442: RANGE_XP Output signals

HIGHHIGH BOOLEAN Measured value is above high-high limit
HIGH BOOLEAN Measured value is between high and high-high limit
NORMAL BOOLEAN Measured value is between high and low limit
LOW BOOLEAN Measured value is between low and low-low limit
LOWLOW BOOLEAN Measured value is below low-low limit
14.6 Disturbance report DRPRDRE

Analog input signals A41RADR - -
Disturbance report DRPRDRE - -
Disturbance report A1RADR - -
Disturbance report A4RADR - -
Disturbance report B1RBDR - -
14.6.1 Introduction
Complete and reliable information about disturbances in the primary and/or in the
secondary system together with continuous event-logging is accomplished by the
disturbance report functionality.
Disturbance report DRPRDRE, always included in the IED, acquires sampled data
of all selected analog input and binary signals connected to the function block with
a, maximum of 40 analog and 96 binary signals.
The Disturbance report functionality is a common name for several functions:
• Event list
• Indications
• Event recorder
• Trip value recorder
• Disturbance recorder
The Disturbance report function is characterized by great flexibility regarding

configuration, starting conditions, recording times, and large storage capacity.
A disturbance is defined as an activation of an input to the AxRADR or BxRBDR

function blocks, which are set to trigger the disturbance recorder. All signals from
start of pre-fault time to the end of post-fault time will be included in the recording.
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Every disturbance report recording is saved in the IED in the standard Comtrade
format. The same applies to all events, which are continuously saved in a ring-
buffer. The local HMI is used to get information about the recordings. The
disturbance report files may be uploaded to PCM600 for further analysis using the
disturbance handling tool.

Disturbance report DRPRDRE is a common name for several functions to supply
the operator, analysis engineer, and so on, with sufficient information about events
in the system.
The functions included in the disturbance report are:
• Event list (EL)

• Indications (IND)
• Event recorder (ER)
• Trip value recorder(TVR)
• Disturbance recorder (DR)
Figure 351 shows the relations between Disturbance Report, included functions
and function blocks. Event list (EL), Event recorder (ER) and Indications (IND)
uses information from the binary input function blocks (BxRBDR). Trip value
recorder (TVR) uses analog information from the analog input function blocks
(AxRADR). Disturbance recorder DRPRDRE acquires information from both
AxRADR and BxRBDR.
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A1-4RADR Disturbance Report
A4RADR DRPRDRE
Analog signals
Trip value rec
B1-6RBDR Disturbance
recorder
Binary signals B6RBDR

Event list
Event recorder
Indications
IEC09000337 V2 EN
Figure 351: Disturbance report functions and related function blocks
The whole disturbance report can contain information for a number of recordings,
each with the data coming from all the parts mentioned above. The event list
function is working continuously, independent of disturbance triggering, recording
time, and so on. All information in the disturbance report is stored in non-volatile
flash memories. This implies that no information is lost in case of loss of auxiliary
power. Each report will get an identification number in the interval from 0-999.
Disturbance report
Record no. N Record no. N+1 Record no. N+100
General dist. Trip Event Disturbance

Indications Event list
information values recordings recording
en05000161.vsd
IEC05000161 V1 EN
Figure 352: Disturbance report structure
Up to 100 disturbance reports can be stored. If a new disturbance is to be recorded

when the memory is full, the oldest disturbance report is overwritten by the new
one. The total recording capacity for the disturbance recorder is depending of
sampling frequency, number of analog and binary channels and recording time.
Figure 353 shows the number of recordings versus the total recording time tested
for a typical configuration, that is, in a 50 Hz system it is possible to record 100
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where the average recording time is 3.4 seconds. The memory limit does not affect
the rest of the disturbance report (Event list (EL), Event recorder (ER), Indications
(IND) and Trip value recorder (TVR)).
Number of recordings
100
3,4 s
80 3,4 s 20 analog
96 binary
40 analog
96 binary
60 6,3 s
6,3 s
6,3 s 50 Hz
40
60 Hz
Total recording time
250 300 350 400 s
en05000488.vsd
IEC05000488 V1 EN
Figure 353: Example of number of recordings versus the total recording time
The maximum number of recordings depend on each recordings

total recording time. Long recording time will reduce the number of
recordings to less than 100.
The IED flash disk should NOT be used to store any user files. This
might cause disturbance recordings to be deleted due to lack of disk
space.
Disturbance information
Date and time of the disturbance, the indications, events, fault location and the trip
values are available on the local HMI. To acquire a complete disturbance report the
user must use a PC and - either the PCM600 Disturbance handling tool - or a FTP
or MMS (over 61850) client. The PC can be connected to the IED front, rear or
remotely via the station bus (Ethernet ports).
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Indications (IND)
Indications is a list of signals that were activated during the total recording time of
the disturbance (not time-tagged), see section "Indications" for more detailed
information.
Event recorder (ER)

The event recorder may contain a list of up to 150 time-tagged events, which have
occurred during the disturbance. The information is available via the local HMI or
PCM600, see section "Event recorder" for more detailed information.
Event list (EL)

The event list may contain a list of totally 1000 time-tagged events. The list
information is continuously updated when selected binary signals change state. The
oldest data is overwritten. The logged signals may be presented via local HMI or
PCM600, see section "Event list" for more detailed information.
Trip value recorder (TVR)

The recorded trip values include phasors of selected analog signals before the fault
and during the fault, see section "Trip value recorder" for more detailed information.
Disturbance recorder (DR)

Disturbance recorder records analog and binary signal data before, during and after
the fault, see section "Disturbance recorder" for more detailed information.
Time tagging
The IED has a built-in real-time calendar and clock. This function is used for all
time tagging within the disturbance report
Recording times
Disturbance report DRPRDRE records information about a disturbance during a
settable time frame. The recording times are valid for the whole disturbance report.
Disturbance recorder (DR), event recorder (ER) and indication function register
disturbance data and events during tRecording, the total recording time.
The total recording time, tRecording, of a recorded disturbance is:
tRecording = PreFaultrecT + tFault + PostFaultrecT or PreFaultrecT + TimeLimit, depending on

which criterion stops the current disturbance recording
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Trig point
TimeLimit
PreFaultRecT PostFaultRecT
1 2 3
en05000487.vsd
IEC05000487 V1 EN
Figure 354: The recording times definition
PreFaultRecT, 1 Pre-fault or pre-trigger recording time. The time before the fault including the
operate time of the trigger. Use the setting PreFaultRecT to set this time.
tFault, 2 Fault time of the recording. The fault time cannot be set. It continues as long as
any valid trigger condition, binary or analog, persists (unless limited by TimeLimit
the limit time).
PostFaultRecT, 3 Post fault recording time. The time the disturbance recording continues after all
activated triggers are reset. Use the setting PostFaultRecT to set this time.
TimeLimit Limit time. The maximum allowed recording time after the disturbance recording
was triggered. The limit time is used to eliminate the consequences of a trigger
that does not reset within a reasonable time interval. It limits the maximum
recording time of a recording and prevents subsequent overwriting of already
stored disturbances. Use the setting TimeLimit to set this time.
Analog signals
Up to 40 analog signals can be selected for recording by the Disturbance recorder
and triggering of the Disturbance report function. Out of these 40, 30 are reserved
for external analog signals from analog input modules (TRM) and line data
communication module (LDCM) via preprocessing function blocks (SMAI) and
summation block (3PHSUM). The last 10 channels may be connected to internally
calculated analog signals available as function block output signals (mA input
signals, phase differential currents, bias currents and so on).
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SMAI A1RADR
Block AI3P A2RADR
^GRP2L1 AI1 INPUT1 A3RADR
External
analogue ^GRP2L2 AI2 INPUT2
signals ^GRP2L3 AI3 INPUT3
^GRP2N AI4 INPUT4
Type AIN INPUT5
INPUT6
...
A4RADR
INPUT31
INPUT32
INPUT33
Internal analogue signals INPUT34
INPUT35
INPUT36
...
INPUT40
IEC10000029 V1 EN
Figure 355: Analog input function blocks
The external input signals will be acquired, filtered and skewed and (after
configuration) available as an input signal on the AxRADR function block via the
SMAI function block. The information is saved at the Disturbance report base
sampling rate (1000 or 1200 Hz). Internally calculated signals are updated
according to the cycle time of the specific function. If a function is running at
lower speed than the base sampling rate, Disturbance recorder will use the latest
updated sample until a new updated sample is available.
If the IED is preconfigured the only tool needed for analog configuration of the
Disturbance report is the Signal Matrix Tool (SMT, external signal configuration).
In case of modification of a preconfigured IED or general internal configuration the
Application Configuration tool within PCM600 is used.
The preprocessor function block (SMAI) calculates the residual quantities in cases
where only the three phases are connected (AI4-input not used).SMAI makes the
information available as a group signal output, phase outputs and calculated
residual output (AIN-output). In situations where AI4-input is used as an input
signal the corresponding information is available on the non-calculated output
(AI4) on the SMAI function block. Connect the signals to the AxRADR accordingly.
For each of the analog signals, Operation = On means that it is recorded by the
disturbance recorder. The trigger is independent of the setting of Operation, and
triggers even if operation is set to Off. Both undervoltage and overvoltage can be
used as trigger conditions. The same applies for the current signals.
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If Operation = Off, no waveform (samples) will be recorded and reported in graph.

However, Trip value, pre-fault and fault value will be recorded and reported. The
input channel can still be used to trig the disturbance recorder.
If Operation = On, waveform (samples) will also be recorded and reported in graph.
The analog signals are presented only in the disturbance recording, but they affect
the entire disturbance report when being used as triggers.
Binary signals
Up to 96 binary signals can be selected to be handled by disturbance report. The
signals can be selected from internal logical and binary input signals. A binary
signal is selected to be recorded when:
• the corresponding function block is included in the configuration

• the signal is connected to the input of the function block
Each of the 96 signals can be selected as a trigger of the disturbance report

(Operation = Off). A binary signal can be selected to activate the red LED on the
local HMI (SetLED = On/Off).
The selected signals are presented in the event recorder, event list and the
disturbance recording. But they affect the whole disturbance report when they are
used as triggers. The indications are also selected from these 96 signals with local
HMI IndicationMask=Show/Hide.
Trigger signals
The trigger conditions affect the entire disturbance report, except the event list,
which runs continuously. As soon as at least one trigger condition is fulfilled, a
complete disturbance report is recorded. On the other hand, if no trigger condition
is fulfilled, there is no disturbance report, no indications, and so on. This implies
the importance of choosing the right signals as trigger conditions.
A trigger can be of type:
• Manual trigger
• Binary-signal trigger
• Analog-signal trigger (over/under function)
Manual trigger
A disturbance report can be manually triggered from the local HMI, PCM600 or
via station bus (IEC 61850). When the trigger is activated, the manual trigger
signal is generated. This feature is especially useful for testing. Refer to the
operator's manual for procedure.
Binary-signal trigger
Any binary signal state (logic one or a logic zero) can be selected to generate a
trigger (Triglevel = Trig on 0/Trig on 1). When a binary signal is selected to
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generate a trigger from a logic zero, the selected signal will not be listed in the
indications list of the disturbance report.
Analog-signal trigger
All analog signals are available for trigger purposes, no matter if they are recorded
in the disturbance recorder or not. The settings are OverTrigOp, UnderTrigOp,
OverTrigLe and UnderTrigLe.
The check of the trigger condition is based on peak-to-peak values. When this is
found, the absolute average value of these two peak values is calculated. If the
average value is above the threshold level for an overvoltage or overcurrent trigger,
this trigger is indicated with a greater than (>) sign with the user-defined name.
If the average value is below the set threshold level for an undervoltage or
undercurrent trigger, this trigger is indicated with a less than (<) sign with its name.
The procedure is separately performed for each channel.
This method of checking the analog start conditions gives a function which is
insensitive to DC offset in the signal. The operate time for this start is typically in
the range of one cycle, 20 ms for a 50 Hz network.
All under/over trig signal information is available on the local HMI and PCM600.
Post Retrigger
Disturbance report function does not respond to any new trig condition, during a
recording. Under certain circumstances the fault condition may reoccur during the
post-fault recording, for instance by automatic reclosing to a still faulty power line.
In order to capture the new disturbance it is possible to allow retriggering

(PostRetrig = On) during the post-fault time. In this case a new, complete
recording will start and, during a period, run in parallel with the initial recording.
When the retrig parameter is disabled (PostRetrig = Off), a new recording will not
start until the post-fault (PostFaultrecT or TimeLimit) period is terminated. If a
new trig occurs during the post-fault period and lasts longer than the proceeding
recording a new complete recording will be fetched.
Disturbance report function can handle maximum 3 simultaneous disturbance

recordings.

DRPRDRE
DRPOFF
RECSTART
RECMADE
CLEARED
MEMUSED
IEC05000406 V3 EN
Figure 356: DRPRDRE function block
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A1RADR
ÎNPUT1
ÎNPUT2
ÎNPUT3
ÎNPUT4
ÎNPUT5
ÎNPUT6
ÎNPUT7
ÎNPUT8
ÎNPUT9
ÎNPUT10
IEC05000430 V3 EN
Figure 357: A1RADR function block
A4RADR
ÎNPUT31
ÎNPUT32
ÎNPUT33
ÎNPUT34
ÎNPUT35
ÎNPUT36
ÎNPUT37
ÎNPUT38
ÎNPUT39
ÎNPUT40
IEC05000431 V3 EN
Figure 358: A4RADR function block, derived analog inputs
B1RBDR
ÎNPUT1
ÎNPUT2
ÎNPUT3
ÎNPUT4
ÎNPUT5
ÎNPUT6
ÎNPUT7
ÎNPUT8
ÎNPUT9
ÎNPUT10
ÎNPUT11
ÎNPUT12
ÎNPUT13
ÎNPUT14
ÎNPUT15
ÎNPUT16
IEC05000432 V3 EN
Figure 359: B1RBDR function block, binary inputs, example for B1RBDR -
B6RBDR
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Table 443: DRPRDRE Output signals
DRPOFF BOOLEAN Disturbance report function turned off
RECSTART BOOLEAN Disturbance recording started
RECMADE BOOLEAN Disturbance recording made
CLEARED BOOLEAN All disturbances in the disturbance report cleared
MEMUSED BOOLEAN More than 80% of memory used
Table 444: A1RADR Input signals

INPUT1 GROUP - Group signal for input 1
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
Table 445: A4RADR Input signals

INPUT31 REAL 0 Analogue channel 31
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Table 446: B1RBDR Input signals

INPUT1 BOOLEAN 0 Binary channel 1

Table 447: DRPRDRE Non group settings (basic)
On
PreFaultRecT 0.05 - 9.90 s 0.01 0.10 Pre-fault recording time
PostFaultRecT 0.1 - 10.0 s 0.1 0.5 Post-fault recording time
TimeLimit 0.5 - 10.0 s 0.1 1.0 Fault recording time limit
PostRetrig Off - - Off Post-fault retrig enabled (On) or not (Off)
On
ZeroAngleRef 1 - 30 Ch 1 1 Reference channel (voltage), phasors,
frequency measurement
OpModeTest Off - - Off Operation mode during test mode
On
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Table 448: A1RADR Non group settings (basic)

Operation01 Off - - Off Operation On/Off
On
NomValue01 0.0 - 999999.9 - 0.1 0.0 Nominal value for analogue channel 1
UnderTrigOp01 Off - - Off Use under level trig for analogue cha 1
On (on) or not (off)
UnderTrigLe01 0 - 200 % 1 50 Under trigger level for analogue cha 1 in
% of signal
OverTrigOp01 Off - - Off Use over level trig for analogue cha 1
OverTrigLe01 0 - 5000 % 1 200 Over trigger level for analogue cha 1 in
% of signal
On
% of signal
% of signal
On
% of signal
OverTrigLe03 0 - 5000 % 1 200 Overtrigger level for analogue cha 3 in %
of signal
On
% of signal
% of signal
On
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% of signal
% of signal
On
% of signal
% of signal
On
% of signal
% of signal
On
% of signal
% of signal
On
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% of signal
% of signal
On
UnderTrigLe10 0 - 200 % 1 50 Under trigger level for analogue cha 10
in % of signal
% of signal
Table 449: A4RADR Non group settings (basic)

Operation31 Off - - Off Operation On/off
On
in % of signal
% of signal
On
in % of signal
% of signal
On
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in % of signal
OverTrigLe33 0 - 5000 % 1 200 Overtrigger level for analogue cha 33 in
% of signal
On
in % of signal
% of signal
On
in % of signal
% of signal
On
in % of signal
% of signal
On
in % of signal
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% of signal
On
in % of signal
% of signal
On
in % of signal
% of signal
On
in % of signal
% of signal
Table 450: B1RBDR Non group settings (basic)

Operation01 Off - - Off Trigger operation On/Off
On
TrigLevel01 Trig on 0 - - Trig on 1 Trig on positiv (1) or negative (0) slope
Trig on 1 for binary inp 1
IndicationMa01 Hide - - Hide Indication mask for binary channel 1
Show
SetLED01 Off - - Off Set red-LED on HMI for binary channel 1
On
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On
Show
On
On
Show
On
On
Show
On
On
Show
On
On
Show
On
On
Show
On
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On
Show
On
On
Show
On
On
Show
On
On
Show
On
On
Show
SetLED12 Off - - Off Set red-LED on HMI for binary input 12
On
On
Show
On
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On
Show
On
On
Show
On
On
Show
On
FUNT1 0 - 255 FunT 1 0 Function type for binary channel 1 (IEC
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
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-60870-5-103)
-60870-5-103)
-60870-5-103)
-60870-5-103)
INFNO1 0 - 255 InfNo 1 0 Information number for binary channel 1
(IEC -60870-5-103)
(IEC -60870-5-103)
(IEC -60870-5-103)
(IEC -60870-5-103)
(IEC -60870-5-103)
(IEC -60870-5-103)
(IEC -60870-5-103)
(IEC -60870-5-103)
(IEC -60870-5-103)
INFNO10 0 - 255 InfNo 1 0 Information number for binary channel
10 (IEC -60870-5-103)
11 (IEC -60870-5-103)
12 (IEC -60870-5-103)
13 (IEC -60870-5-103)
14 (IEC -60870-5-103)
15 (IEC -60870-5-103)
16 (IEC -60870-5-103)
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Table 451: DRPRDRE technical data
Pre-fault time (0.05–9.90) s -
Post-fault time (0.1–10.0) s -
Limit time (0.5–10.0) s -
Maximum number of recordings 100, first in - first out -
Time tagging resolution 1 ms See table 28
Maximum number of analog inputs 30 + 10 (external + internally -
derived)
Maximum number of binary inputs 96 -
Maximum number of phasors in the 30 -
Trip Value recorder per recording
Maximum number of indications in a 96 -
disturbance report
Maximum number of events in the 150 -
Event recording per recording
Maximum number of events in the 1000, first in - first out -
Event list
Maximum total recording time (3.4 s 340 seconds (100 recordings) -
recording time and maximum number at 50 Hz, 280 seconds (80
of channels, typical value) recordings) at 60 Hz
Sampling rate 1 kHz at 50 Hz -
1.2 kHz at 60 Hz
Recording bandwidth (5-300) Hz -
14.7 Event list
14.7.1 Introduction
Continuous event-logging is useful for monitoring the system from an overview
perspective and is a complement to specific disturbance recorder functions.
The event list logs all binary input signals connected to the Disturbance report
function. The list may contain up to 1000 time-tagged events stored in a ring-buffer.

When a binary signal, connected to the disturbance report function, changes status,
the event list function stores input name, status and time in the event list in
chronological order. The list can contain up to 1000 events from both internal logic
signals and binary input channels. If the list is full, the oldest event is overwritten
when a new event arrives.
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The list can be configured to show oldest or newest events first with a setting on
the local HMI.
The event list function runs continuously, in contrast to the event recorder function,
which is only active during a disturbance.
The name of the binary input signal that appears in the event recording is the user-
defined name assigned when the IED is configured. The same name is used in the
disturbance recorder function (DR), indications (IND)and the event recorder
function (ER).
The event list is stored and managed separate from the disturbance report
information (ER, DR, IND, TVR and FL).

The Event list has no function block of it’s own.It is included in the DRPRDRE
block and uses information from the BxRBDR block.

The Event list logs the same binary input signals as configured for the Disturbance
report function.

Table 452: technical data
Function Value
Buffer capacity Maximum number of events in the list 1000
Resolution 1 ms
Accuracy Depending on time
synchronizing
14.8 Indications
14.8.1 Introduction
To get fast, condensed and reliable information about disturbances in the primary
and/or in the secondary system it is important to know, for example binary signals
that have changed status during a disturbance. This information is used in the short
perspective to get information via the local HMI in a straightforward way.
There are three LEDs on the local HMI (green, yellow and red), which will display
status information about the IED and the Disturbance report function (trigged).
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The Indication list function shows all selected binary input signals connected to the
Disturbance report function that have changed status during a disturbance.

The LED indications display this information:
Green LED:
Steady light In Service

Flashing light Internal fail
Dark No power supply
Yellow LED:
Steady light A disturbance report is triggered

Flashing light The IED is in test mode or in configuration mode
Red LED:
Steady light Trigged on binary signal N with SetLEDN=On
Indication list:
The possible indicated signals are the same as the ones chosen for the disturbance
report function and disturbance recorder.
The indication function tracks 0 to 1 changes of binary signals during the recording
period of the collection window. This means that constant logic zero, constant logic
one or state changes from logic one to logic zero will not be visible in the list of
indications. Signals are not time tagged. In order to be recorded in the list of
indications the:
• the signal must be connected to binary input(DRB1-6)

• the DRPparameter Operation must be set On
• the DRP must be trigged (binary or analog)
Indications are selected with the indication mask (IndicationMask) when

configuring the binary inputs.
The name of the binary input signal that appears in the Indication function is the user-
defined name assigned at configuration of the IED. The same name is used in
disturbance recorder function (DR), indications (IND) and event recorder function
(ER).
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The Indications function has no function block of it’s own. It is included in the
DRPRDRE block and uses information from the BxRBDR block.

The Indications function may log the same binary input signals as the Disturbance
report function.

Function Value
Buffer capacity Maximum number of indications 96
presented for single disturbance
Maximum number of recorded 100
disturbances
14.9 Event recorder
14.9.1 Introduction
Quick, complete and reliable information about disturbances in the primary and/or
in the secondary system is vital, for example, time-tagged events logged during
disturbances. This information is used for different purposes in the short term (for
example corrective actions) and in the long term (for example functional analysis).
The event recorder logs all selected binary input signals connected to the
Disturbance report function. Each recording can contain up to 150 time-tagged events.
The event recorder information is available for the disturbances locally in the IED.
The event recording information is an integrated part of the disturbance record

(Comtrade file).

When one of the trig conditions for the disturbance report is activated, the event
recorder logs every status change in the 96 selected binary signals. The events can
be generated by both internal logical signals and binary input channels. The
internal signals are time-tagged in the main processor module, while the binary
input channels are time-tagged directly in each I/O module. The events are
collected during the total recording time (pre-, post-fault and limit time), and are
stored in the disturbance report flash memory at the end of each recording.
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In case of overlapping recordings, due to PostRetrig = On and a new trig signal

appears during post-fault time, events will be saved in both recording files.
The name of the binary input signal that appears in the event recording is the user-
defined name assigned when configuring the IED. The same name is used in the
disturbance recorder function (DR), indications (IND) and event recorder
function(ER).
The event record is stored as a part of the disturbance report information (ER, DR,
IND, TVR and FL) and managed via the local HMI or PCM600.
Events can not be read from the IED if more than one user is
accessing the IED simultaneously.

The Event recorder has no function block of it’s own. It is included in the

The Event recorder function logs the same binary input signals as the Disturbance
report function.

Function Value
Buffer capacity Maximum number of events in disturbance 150
report
Maximum number of disturbance reports 100
Resolution 1 ms
Accuracy Depending on time
synchronizing
14.10 Trip value recorder
14.10.1 Introduction
Information about the pre-fault and fault values for currents and voltages are vital
for the disturbance evaluation.
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The Trip value recorder calculates the values of all selected analog input signals
connected to the Disturbance report function. The result is magnitude and phase
angle before and during the fault for each analog input signal.
The trip value recorder information is available for the disturbances locally in the
IED.
The trip value recorder information is an integrated part of the disturbance record
(Comtrade file).

Trip value recorder (TVR)calculates and presents both fault and pre-fault
amplitudes as well as the phase angles of all the selected analog input signals. The
parameter ZeroAngleRef points out which input signal is used as the angle reference.
When the disturbance report function is triggered the sample for the fault
interception is searched for, by checking the non-periodic changes in the analog
input signals. The channel search order is consecutive, starting with the analog
input with the lowest number.
When a starting point is found, the Fourier estimation of the pre-fault values of the
complex values of the analog signals starts 1.5 cycle before the fault sample. The
estimation uses samples during one period. The post-fault values are calculated
using the Recursive Least Squares (RLS) method. The calculation starts a few
samples after the fault sample and uses samples during 1/2 - 2 cycles depending on
the shape of the signals.
If no starting point is found in the recording, the disturbance report trig sample is
used as the start sample for the Fourier estimation. The estimation uses samples
during one cycle before the trig sample. In this case the calculated values are used
both as pre-fault and fault values.
The name of the analog input signal that appears in the Trip value recorder function
is the user-defined name assigned when the IED is configured. The same name is
used in the Disturbance recorder function (DR).
The trip value record is stored as a part of the disturbance report information (ER,
DR, IND, TVR and fault locator) and managed in via the local HMI or PCM600.

The Trip value recorder has no function block of it’s own. It is included in the

The trip value recorder function uses analog input signals connected to A1RADR
to A3RADR (not A4RADR).
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Function Value
Buffer capacity Maximum number of analog inputs 30
14.11 Disturbance recorder
14.11.1 Introduction
The Disturbance recorder function supplies fast, complete and reliable information
about disturbances in the power system. It facilitates understanding system
behavior and related primary and secondary equipment during and after a
disturbance. Recorded information is used for different purposes in the short
perspective (for example corrective actions) and long perspective (for example
functional analysis).
The Disturbance recorder acquires sampled data from selected analog- and binary
signals connected to the Disturbance report function (maximum 40 analog and 96
binary signals). The binary signals available are the same as for the event recorder
function.
The function is characterized by great flexibility and is not dependent on the

operation of protection functions. It can record disturbances not detected by
protection functions. Up to ten seconds of data before the trigger instant can be
saved in the disturbance file.
The disturbance recorder information for up to 100 disturbances are saved in the
IED and the local HMI is used to view the list of recordings.

Disturbance recording (DR) is based on the acquisition of binary and analog
signals. The binary signals can be either true binary input signals or internal logical
signals generated by the functions in the IED. The analog signals to be recorded are
input channels from the Transformer Input Module (TRM), Line Differential
communication Module (LDCM) through the Signal Matrix Analog Input (SMAI)
and possible summation (Sum3Ph) function blocks and some internally derived
analog signals.For details, refer to section "Disturbance report DRPRDRE".
Disturbance recorder collects analog values and binary signals continuously, in a

cyclic buffer. The pre-fault buffer operates according to the FIFO principle; old
data will continuously be overwritten as new data arrives when the buffer is full.
The size of this buffer is determined by the set pre-fault recording time.
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Upon detection of a fault condition (triggering), the disturbance is time tagged and
the data storage continues in a post-fault buffer. The storage process continues as
long as the fault condition prevails - plus a certain additional time. This is called
the post-fault time and it can be set in the disturbance report.
The above mentioned two parts form a disturbance recording. The whole memory,
intended for disturbance recordings, acts as a cyclic buffer and when it is full, the
oldest recording is overwritten. The last 100 recordings are stored in the IED.
The time tagging refers to the activation of the trigger that starts the disturbance
recording. A recording can be trigged by, manual start, binary input and/or from
analog inputs (over-/underlevel trig).
A user-defined name for each of the signals can be set. These names are common
for all functions within the disturbance report functionality.
14.11.2.1 Memory and storage
The maximum number of recordings depend on each recordings

total recording time. Long recording time will reduce the number of
recordings to less than 100.
The IED flash disk should NOT be used to store any user files. This
might cause disturbance recordings to be deleted due to lack of disk
space.
When a recording is completed, a post recording processing occurs.
This post-recording processing comprises:
• Saving the data for analog channels with corresponding data for binary signals
• Add relevant data to be used by the Disturbance handling tool (part of PCM 600)
• Compression of the data, which is performed without losing any data accuracy
• Storing the compressed data in a non-volatile memory (flash memory)
The recorded disturbance is now ready for retrieval and evaluation.
The recording files comply with the Comtrade standard IEC 60255-24 and are
divided into three files; a header file (HDR), a configuration file (CFG) and a data
file (DAT).
The header file (optional in the standard) contains basic information about the
disturbance, that is, information from the Disturbance report sub-functions (ER,
TVR). The Disturbance handling tool use this information and present the
recording in a user-friendly way.
General:
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• Station name, object name and unit name

• Date and time for the trig of the disturbance
• Record number
• Sampling rate
• Time synchronization source
• Recording times
• Activated trig signal
• Active setting group
Analog:
• Signal names for selected analog channels

• Information e.g. trig on analog inputs
• Primary and secondary instrument transformer rating
• Over- or Undertrig: level and operation
• Over- or Undertrig status at time of trig
• CT direction
Binary:
• Signal names
• Status of binary input signals
The configuration file is a mandatory file containing information needed to

interpret the data file. For example sampling rate, number of channels, system
frequency, channel info etc.
The data file, which also is mandatory, containing values for each input channel for
each sample in the record (scaled value). The data file also contains a sequence
number and time stamp for each set of samples.
14.11.2.2 IEC 60870-5-103
The communication protocol IEC 60870-5-103 may be used to poll disturbance

recordings from the IED to a master (station HSI). The standard describes how to
handle 8 disturbance recordings, 8 analog channels (4 currents and 4 voltages)
using the public range and binary signals.
The last 8 recordings, out of maximum 100, are available for transfer to the master.
When the last one is transferred and acknowledged new recordings in the IED will
appear, in the master points of view (even if they already where stored in the IED).
To be able to report 40 analog channels from the IED using IEC 60870-5-103 the
first 8 channels are placed in the public range and the next 32 are placed in the
private range. To comply the standard the first 8 must be configured according to
table 456.
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Table 456: Configuration of analog channels

Signal Disturbance recorder
IL1 A1RADR INPUT1
IL2 A1RADR INPUT2
IL3 A1RADR INPUT3
IN A1RADR INPUT4
UL1 A1RADR INPUT5
UL2 A1RADR INPUT6
UL3 A1RADR INPUT7
UN A1RADR INPUT8
The binary signals connected to BxRBDR are reported by polling. The function
blocks include function type and information number.

The Disturbance recorder has no function block of it’s own. It is included in the
DRPRDRE, AxRADR and BxRBDR block.

For signals see section, in Disturbance report, "Input and output signals".

For Setting parameters see section "Disturbance report DRPRDRE".

Function Value
Buffer capacity Maximum number of analog inputs 40
Maximum number of binary inputs 96
Maximum total recording time (3.4 s recording time and maximum number 340 seconds (100
of channels, typical value) recordings) at 50 Hz
280 seconds (80
recordings) at 60 Hz
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Section 15 Metering
About this chapter

This chapter describes among others, Pulse counter logic which is a function used
to meter externally generated binary pulses. The way the functions work, their
setting parameters, function blocks, input and output signals, and technical data are
15.1 Pulse-counter logic PCGGIO

Pulse-counter logic PCGGIO -
S00947 V1 EN
15.1.1 Introduction
Pulse counter (PCGGIO) function counts externally generated binary pulses, for
instance pulses coming from an external energy meter, for calculation of energy
consumption values. The pulses are captured by the binary input module and then
read by the function. A scaled service value is available over the station bus. The
special Binary input module with enhanced pulse counting capabilities must be
ordered to achieve this functionality.

The registration of pulses is done for positive transitions (0->1) on one of the 16
binary input channels located on the Binary Input Module (BIM). Pulse counter
values are sent to the station HMI with predefined cyclicity without reset.
The reporting time period can be set in the range from 1 second to 60 minutes and
is synchronized with absolute system time. Interrogation of additional pulse
counter values can be done with a command (intermediate reading) for a single
counter. All active counters can also be read by the LON General Interrogation
command (GI) or IEC 61850.
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Pulse counter (PCGGIO) function in the IED supports unidirectional incremental

counters. That means only positive values are possible. The counter uses a 32 bit
format, that is, the reported value is a 32-bit, signed integer with a range
0...+2147483647. The counter is reset at initialization of the IED.
The reported value to station HMI over the station bus contains Identity, Scaled
Value (pulse count x scale), Time, and Pulse Counter Quality. The Pulse Counter
Quality consists of:
• Invalid (board hardware error or configuration error)

• Wrapped around
• Blocked
• Adjusted
The transmission of the counter value by SPA can be done as a service value, that
is, the value frozen in the last integration cycle is read by the station HMI from the
database. PCGGIO updates the value in the database when an integration cycle is
finished and activates the NEW_VAL signal in the function block. This signal can
be connected to an Event function block, be time tagged, and transmitted to the
station HMI. This time corresponds to the time when the value was frozen by the
function.
The pulse counter function requires a binary input card, BIMp, that
is specially adapted to the pulse counter function.
Figure 360 shows the pulse counter function block with connections of the inputs
and outputs.
SingleCmdFunc PulseCounter EVENT

OUTx BLOCK
INVALID INPUT1
SingleCmdFunc Pulse RESTART INPUT2
OUTx INPUT OUT READ_VAL
Pulse length >1s BLOCKED INPUT3
I/O-module NEW_VAL INPUT4
BI_PULSE
”Reset counter” RS_CNT
NAME
SCAL_VAL IEC EVENT
SMS settings Database

1.Operation = Off/On Pulse counter value:
2.tReporting = 0s...60min 0...2147483647
3.Event Mask = No Events/Report Events
4.Scale = 1-90000
en05000744.vsd
IEC05000744 V1 EN
Figure 360: Overview of the pulse counter function
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Metering
The BLOCK and READ_VAL inputs can be connected to Single Command

blocks, which are intended to be controlled either from the station HMI or/and the
local HMI. As long as the BLOCK signal is set, the pulse counter is blocked. The
signal connected to READ_VAL performs one additional reading per positive
flank. The signal must be a pulse with a length >1 second.
The BI_PULSE input is connected to the used input of the function block for the
Binary Input Module (BIM).
The RS_CNT input is used for resetting the counter.
Each pulse counter function block has four binary output signals that can be
connected to an Event function block for event recording: INVALID, RESTART,
BLOCKED and NEW_VAL. The SCAL_VAL signal can be connected to the IEC
Event function block.
The INVALID signal is a steady signal and is set if the Binary Input Module,
where the pulse counter input is located, fails or has wrong configuration.
The RESTART signal is a steady signal and is set when the reported value does not
comprise a complete integration cycle. That is, in the first message after IED start-
up, in the first message after deblocking, and after the counter has wrapped around
during last integration cycle.
The BLOCKED signal is a steady signal and is set when the counter is blocked.
There are two reasons why the counter is blocked:
• The BLOCK input is set, or

• The Binary Input Module, where the counter input is situated, is inoperative.
The NEW_VAL signal is a pulse signal. The signal is set if the counter value was
updated since last report.
The SCAL_VAL signal consists of scaled value (according to parameter Scale),

time and status information.

PCGGIO
BLOCK INVALID
READ_VAL RESTART
BI_PULSE* BLOCKED
RS_CNT NEW_VAL
SCAL_VAL
IEC05000709 V3 EN
Figure 361: PCGGIO function block
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Metering

Table 458: PCGGIO Input signals
READ_VAL BOOLEAN 0 Initiates an additional pulse counter reading
BI_PULSE BOOLEAN 0 Connect binary input channel for metering
RS_CNT BOOLEAN 0 Resets pulse counter value
Table 459: PCGGIO Output signals

INVALID BOOLEAN The pulse counter value is invalid
RESTART BOOLEAN The reported value does not comprise a complete
integration cycle
BLOCKED BOOLEAN The pulse counter function is blocked
NEW_VAL BOOLEAN A new pulse counter value is generated
SCAL_VAL REAL Scaled value with time and status information

Table 460: PCGGIO Non group settings (basic)
On
EventMask NoEvents - - NoEvents Report mask for analog events from
ReportEvents pulse counter
CountCriteria Off - - RisingEdge Pulse counter criteria
RisingEdge
Falling edge
OnChange
Scale 1.000 - 90000.000 - 0.001 1.000 Scaling value for SCAL_VAL output to
unit per counted value
Quantity Count - - Count Measured quantity for SCAL_VAL output
ActivePower
ApparentPower
ReactivePower
ActiveEnergy
ApparentEnergy
ReactiveEnergy
tReporting 0 - 3600 s 1 60 Cycle time for reporting of counter value
730
Metering

Table 461: PCGGIO technical data
Input frequency See Binary Input Module (BIM) -
Cycle time for report of (1–3600) s -
counter value
15.2 Function for energy calculation and demand

handling ETPMMTR

Energy calculation and demand ETPMMTR -
handling
15.2.1 Introduction
Outputs from the Measurements (CVMMXN) function can be used to calculate
energy consumption. Active as well as reactive values are calculated in import and
export direction. Values can be read or generated as pulses. Maximum demand
power values are also calculated by the function.

The instantaneous output values of active and reactive power from the
Measurements (CVMMXN) function block are used and integrated over a selected
time tEnergy to measure the integrated energy. The energy values (in MWh and
MVarh) are available as output signals and also as pulsed output which can be
connected to a pulse counter. Outputs are available for forward as well as reverse
direction. The accumulated energy values can be reset from the local HMI reset
menu or with input signal RSTACC.
The maximum demand values for active and reactive power are calculated for the
set time tEnergy and the maximum value is stored in a register available over
communication and from outputs MAXPAFD, MAXPARD, MAXPRFD,
MAXPRRD for the active and reactive power forward and reverse direction until
reset with input signal RSTDMD or from the local HMI reset menu.
731
Metering
CVMMXN ETPMMTR
P_INST P
Q_INST Q
STACC
TRUE
RSTACC
FALSE
RSTDMD
FALSE
IEC09000106.vsd
IEC09000106 V1 EN
Figure 362: Connection of Energy calculation and demand handling function

(ETPMMTR) to the Measurements function (CVMMXN)

ETPMMTR
P ACCST
Q EAFPULSE
STACC EARPULSE
RSTACC ERFPULSE
RSTDMD ERRPULSE
EAFALM
EARALM
ERFALM
ERRALM
EAFACC
EARACC
ERFACC
ERRACC
MAXPAFD
MAXPARD
MAXPRFD
MAXPRRD
IEC07000120 V2 EN
Figure 363: ETPMMTR function block

Table 462: ETPMMTR Input signals
P REAL 0 Measured active power
Q REAL 0 Measured reactive power
STACC BOOLEAN 0 Start to accumulate energy values
RSTACC BOOLEAN 0 Reset of accumulated enery reading
RSTDMD BOOLEAN 0 Reset of maximum demand reading
Table 463: ETPMMTR Output signals

ACCST BOOLEAN Start of accumulating energy values.
EAFPULSE BOOLEAN Accumulated forward active energy pulse
EARPULSE BOOLEAN Accumulated reverse active energy pulse
732
Metering

ERFPULSE BOOLEAN Accumulated forward reactive energy pulse
ERRPULSE BOOLEAN Accumulated reverse reactive energy pulse
EAFALM BOOLEAN Alarm for active forward energy exceed limit in
set interval
EARALM BOOLEAN Alarm for active reverse energy exceed limit in
set interval
ERFALM BOOLEAN Alarm for reactive forward energy exceed limit in
set interval
ERRALM BOOLEAN Alarm for reactive reverse energy exceed limit in
set interval
EAFACC REAL Accumulated forward active energy value in Ws
EARACC REAL Accumulated reverse active energy value in Ws
ERFACC REAL Accumulated forward reactive energy value in
VArS
ERRACC REAL Accumulated reverse reactive energy value in
VArS
MAXPAFD REAL Maximum forward active power demand value for
set interval
MAXPARD REAL Maximum reverse active power demand value for
set interval
MAXPRFD REAL Maximum forward reactive power demand value
for set interval
MAXPRRD REAL Maximum reactive power demand value in
reverse direction

Table 464: ETPMMTR Non group settings (basic)
On
StartAcc Off - - Off Activate the accumulation of energy
On values
tEnergy 1 Minute - - 1 Minute Time interval for energy calculation
5 Minutes
10 Minutes
15 Minutes
30 Minutes
60 Minutes
180 Minutes
tEnergyOnPls 0.000 - 60.000 s 0.001 1.000 Energy accumulated pulse ON time in
secs
tEnergyOffPls 0.000 - 60.000 s 0.001 0.500 Energy accumulated pulse OFF time in
secs
EAFAccPlsQty 0.001 - 10000.000 MWh 0.001 100.000 Pulse quantity for active forward
accumulated energy value
733
Metering

EARAccPlsQty 0.001 - 10000.000 MWh 0.001 100.000 Pulse quantity for active reverse
ERFAccPlsQty 0.001 - 10000.000 MVArh 0.001 100.000 Pulse quantity for reactive forward
ERVAccPlsQty 0.001 - 10000.000 MVArh 0.001 100.000 Pulse quantity for reactive reverse
Table 465: ETPMMTR Non group settings (advanced)

EALim 0.001 - MWh 0.001 1000000.000 Active energy limit
10000000000.000
ERLim 0.001 - MVArh 0.001 1000.000 Reactive energy limit
10000000000.000
DirEnergyAct Forward - - Forward Direction of active energy flow Forward/
Reverse Reverse
DirEnergyReac Forward - - Forward Direction of reactive energy flow Forward/
Reverse Reverse
EnZeroClamp Off - - On Enable of zero point clamping detection
On function
LevZeroClampP 0.001 - 10000.000 MW 0.001 10.000 Zero point clamping level at active Power
LevZeroClampQ 0.001 - 10000.000 MVAr 0.001 10.000 Zero point clamping level at reactive
Power
EAFPrestVal 0.000 - 10000.000 MWh 0.001 0.000 Preset Initial value for forward active
energy
EARPrestVal 0.000 - 10000.000 MWh 0.001 0.000 Preset Initial value for reverse active
energy
ERFPresetVal 0.000 - 10000.000 MVArh 0.001 0.000 Preset Initial value for forward reactive
energy
ERVPresetVal 0.000 - 10000.000 MVArh 0.001 0.000 Preset Initial value for reverse reactive
energy
734
Station communication
Section 16 Station communication
About this chapter

This chapter describes the functions and protocols used on the interfaces to the
substation automation and substation monitoring buses. The way these work, their
setting parameters, function blocks, input and output signals and technical data are
16.1 Overview
Each IED is provided with a communication interface, enabling it to connect to one

or many substation level systems or equipment, either on the Substation
Automation (SA) bus or Substation Monitoring (SM) bus.
Following communication protocols are available:
• IEC 61850-8-1 communication protocol

• LON communication protocol
• SPA or IEC 60870-5-103 communication protocol
• DNP3.0 communication protocol
Theoretically, several protocols can be combined in the same IED.
16.2 IEC 61850-8-1 communication protocol

Table 466: IEC61850-8-1 Non group settings (basic)
On
GOOSE Front - - OEM311_AB Port for GOOSE communication
OEM311_AB
OEM311_CD
735

Table 467: IEC 61850-8-1 communication protocol
Function Value
Protocol IEC 61850-8-1
Communication speed for the IEDs 100BASE-FX
16.2.3 IEC 61850 generic communication I/O functions SPGGIO,

SP16GGIO
IEC61850 generic communication I/O functions (SPGGIO) is used to send one

single logical signal to other systems or equipment in the substation.
Upon receiving a signal at its input, IEC61850 generic communication I/O

functions (SPGGIO) function sends the signal over IEC 61850-8-1 to the
equipment or system that requests this signal. To get the signal, PCM600 must be
used to define which function block in which equipment or system should receive
this information.

SPGGIO
BLOCK
ÎN
IEC07000124 V2 EN
Figure 364: SPGGIO function block
736
SP16GGIO
BLOCK
ÎN1
ÎN2
ÎN3
ÎN4
ÎN5
ÎN6
ÎN7
ÎN8
ÎN9
ÎN10
ÎN11
ÎN12
ÎN13
ÎN14
ÎN15
ÎN16
IEC07000125 V2 EN
Figure 365: SP16GGIO function block

Table 468: SPGGIO Input signals
IN BOOLEAN 0 Input status
Table 469: SP16GGIO Input signals

IN1 BOOLEAN 0 Input 1 status
737
16.2.4 IEC 61850 generic communication I/O functions MVGGIO
IEC61850 generic communication I/O functions (MVGGIO) function is used to

send the instantaneous value of an analog output to other systems or equipment in
the substation. It can also be used inside the same IED, to attach a RANGE aspect
to an analog value and to permit measurement supervision on that value.
Upon receiving an analog signal at its input, IEC61850 generic communication I/O
functions (MVGGIO) will give the instantaneous value of the signal and the range,
as output values. In the same time, it will send over IEC 61850-8-1 the value, to
other IEC 61850 clients in the substation.

MVGGIO
BLOCK ^VALUE
ÎN RANGE
IEC05000408 V2 EN
Figure 366: MVGGIO function block

Table 470: MVGGIO Input signals
IN REAL 0 Analogue input value
Table 471: MVGGIO Output signals

VALUE REAL Magnitude of deadband value
RANGE INTEGER Range
738

Table 472: MVGGIO Non group settings (basic)
MV db 1 - 300 Type 1 10 Cycl: Report interval (s), Db: In % of
MV zeroDb 0 - 100000 m% 1 500 Zero point clamping in 0,001% of range
MV hhLim -10000000000.000 - 0.001 90.000 High High limit
- 10000000000.000
MV hLim -10000000000.000 - 0.001 80.000 High limit
- 10000000000.000
MV lLim -10000000000.000 - 0.001 -80.000 Low limit
- 10000000000.000
MV llLim -10000000000.000 - 0.001 -90.000 Low Low limit
- 10000000000.000
MV min -10000000000.000 - 0.001 -100.000 Minimum value
- 10000000000.000
MV max -10000000000.000 - 0.001 100.000 Maximum value
- 10000000000.000
MV dbType Cyclic - - Dead band Reporting type
Dead band
Int deadband
MV limHys 0.000 - 100.000 % 0.001 5.000 Hysteresis value in % of range (common
for all limits)
16.2.5 IEC 61850-8-1 redundant station bus communication

Parallel Redundancy Protocol Status PRPSTATUS - -
Duo driver configuration DUODRV - -
Redundant station bus communication is used to assure communication, even

though one communication channels might not be available for some reason.
Redundant communication over station bus running IEC 61850-8-1 use both port
AB and CD on OEM module and IEC 62439-PRP protocol.
The redundant station bus communication (DUODRV) is configured using the

local HMI. The settings for DUODRV are also visible in PST in PCM600.
The communication is performed in parallel, that is the same data package is

transmitted on both channels simultaneously. The received package identity from
739
one channel is compared with data package identity from the other channel, if the
same, the last package is discarded.
PRPSTATUS function block supervise the redundant communication on the two

channels. If no data package has been received on one (or both) channels within the
last 10 s, the output LAN-A-STATUS and/or LAN-B-STATUS is set to indicate error.
Station Control System
Redundancy
Supervision
Duo
Data Data
Switch A Switch B
1 2 1 2
Data
Data
AB CD IED
Configuration OEM
DUODRV PRPSTATUS
IEC09000758 V2 EN
Figure 367: Redundant station bus
740

PRPSTATUS
LAN-A-Status
LAN-B-Status
IEC09000757 V1 EN
Figure 368: PRPSTATUS function block
16.2.5.4 Output signals

Table 473: PRPSTATUS Output signals
LAN-A-Status BOOLEAN Channel A status
LAN-B-Status BOOLEAN Channel B status

Table 474: DUODRV Non group settings (basic)
On
IPAddress 0 - 18 IP 1 192.168.7.10 IP-Address
Address
IPMask 0 - 18 IP 1 255.255.255.0 IP-Mask
Address
16.3 LON communication protocol
16.3.1 Introduction
An optical network can be used within the substation automation system. This
enables communication with the IED through the LON bus from the operator’s
workplace, from the control center and also from other terminals.
LON communication protocol is specified in LonTalkProtocol Specification

Version 3 from Echelon Corporation and is designed for communication in control
networks. These networks are characterized by high speed for data transfer, short
messages (few bytes), peer-to-peer communication, multiple communication
media, low maintenance, multivendor equipment, and low support costs. LonTalk
supports the needs of applications that cover a range of requirements. The protocol
follows the reference model for open system interconnection (OSI) designed by the
International Standardization Organization (ISO).
741
In this document the most common addresses for commands and events are
available. For other addresses, refer to section "Related documents".
It is assumed that the reader is familiar with LON communication protocol in general.

The speed of the network depends on the medium and transceiver design. With
protection and control devices, fibre optic media is used, which enables the use of
the maximum speed of 1.25 Mbits/s. The protocol is a peer-to-peer protocol where
all the devices connected to the network can communicate with each other. The
own subnet and node number are identifying the nodes (max. 255 subnets, 127
nodes per one subnet).
The LON bus links the different parts of the protection and control system. The
measured values, status information, and event information are spontaneously sent
to the higher-level devices. The higher-level devices can read and write memorized
values, setting values, and other parameter data when required. The LON bus also
enables the bay level devices to communicate with each other to deliver, for
example, interlocking information among the terminals without the need of a bus
master.
The LonTalk protocol supports two types of application layer objects: network
variables and explicit messages. Network variables are used to deliver short
messages, such as measuring values, status information, and interlocking/blocking
signals. Explicit messages are used to transfer longer pieces of information, such as
events and explicit read and write messages to access device data.
The benefits achieved from using the LON bus in protection and control systems
include direct communication among all terminals in the system and support for
multi-master implementations. The LON bus also has an open concept, so that the
terminals can communicate with external devices using the same standard of
network variables.
Introduction of LON protocol

For more information, refer to LON bus, LonWorks Network in Protection and
Control, User’s manual and Technical description.
LON protocol
Configuration of LON
Lon Network Tool (LNT 505) is a multi-purpose tool for LonWorks network
configuration. All the functions required for setting up and configuring a
LonWorks network, is easily accessible on a single tool program. For more
information, refer to the operator's manual.
742
Activate LON Communication

Activate LON communication in the Parameter Setting tool under Main menu/
Communication/ SLM configuration/ Rear optical LON port/ Horizontal
communication, where Operation must be set to ON.
Add LON Device Types LNT

A new device is added to LON Network Tool from the Device menu or by
installing the device from the ABB LON Device Types package for LNT 505, with
the SLDT 670 series package version 1p2 r03.
LON net address

To establish a LON connection with the 670 series IEDs, the IED has to be given a
unique net address. The net address consists of a subnet and node number. This is
accomplished with the LON Network Tool by creating one device for each IED.
Vertical communication
Vertical communication describes communication between the monitoring devices
and protection and control IEDs. This communication includes sending of changed
process data to monitoring devices as events and transfer of commands, parameter
data and disturbance recorder files. This communication is implemented using
explicit messages.
Events and indications

Events sent to the monitoring devices are using explicit messages (message code
44H) with unacknowledged transport service of the LonTalk protocol. When a
signal is changed in the IED, one message with the value, quality and time is
transmitted from terminal.
Binary events
Binary events are generated in event function blocks EVENT:1 to EVENT:20 in
the 670 series IEDs. The event function blocks have predefined LON addresses.
table 475 shows the LON addresses to the first input on the event function blocks.
The addresses to the other inputs on the event function block are consecutive after
the first input. For example, input 15 on event block EVENT:17 has the address
1280 + 14 (15-1) = 1294.
For double indications only the first eight inputs 1–8 must be used. Inputs 9–16 can
be used for other type of events at the same event block.
As basic, three event function blocks EVENT:1 to EVENT:3 running with a fast
loop time (3 ms) is available in the 670 series IEDs. The remaining event function
blocks EVENT:4 to EVENT:9 runs with a loop time on 8 ms and EVENT:10 to
EVENT:20 runs with a loop time on 100 ms. The event blocks are used to send
binary signals, integers, real time values like analogue data from measuring
functions and mA input modules as well as pulse counter signals.
16 pulse counter value function blocks PCGGIO:1 to PCGGIO:16 and 24 mA input

service values function blocks SMMI1_In1 to 6 – SMMI4_In1 to 6 are available in
the 670 series IEDs.
743
The first LON address in every event function block is found in table 475
Table 475: LON adresses for Event functions

Function block First LON address in
function block
EVENT:1 1024
EVENT:2 1040
EVENT:3 1056
EVENT:4 1072
EVENT:5 1088
EVENT:6 1104
EVENT:7 1120
EVENT:8 1136
EVENT:9 1152
EVENT:10 1168
EVENT:11 1184
EVENT:12 1200
EVENT:13 1216
EVENT:14 1232
EVENT:15 1248
EVENT:16 1264
EVENT:17 1280
EVENT:18 1296
EVENT:19 1312
EVENT:20 1328
Event masks
The event mask for each input can be set individually from Parameter Setting Tool
(PST) under: Settings/ General Settings/ Monitoring / EventFunction as follows:
• No events
• OnSet, at pick-up of the signal
• OnReset, at drop-out of the signal
• OnChange, at both pick-up and drop-out of the signal
• AutoDetect, event system itself make the reporting decision, (reporting criteria
for integers has no semantic, prefer to be set by the user)
The following type of signals from application functions can be connected to the
event function block.
Single indication
Directly connected binary IO signal via binary input function block (SMBI) is
always reported on change, no changed detection is done in the event function
744
block. Other Boolean signals, for example a start or a trip signal from a protection
function is event masked in the event function block.
Double indications
Double indications can only be reported via switch-control (SCSWI) functions, the
event reporting is based on information from switch-control, no change detection is
done in the event function block.
Directly connected binary IO signal via binary input function block (SMBI) is not
possible to handle as double indication. Double indications can only be reported for
the first 8 inputs on an event function block.
• 00 generates an intermediate event with the read status 0

• 01 generates an open event with the read status 1
• 10 generates a close event with the read status 2
• 11 generates an undefined event with the read status 3
Analog value
All analog values are reported cyclic, the reporting interval is taken from the
connected function if there is a limit supervised signal, otherwise it is taken from
the event function block.
Command handling
Commands are transferred using transparent SPA-bus messages. The transparent
SPA-bus message is an explicit LON message, which contains an ASCII character
message following the coding rules of the SPA-bus protocol. The message is sent
using explicit messages with message code 41H and using acknowledged transport
service.
Both the SPA-bus command messages (R or W) and the reply messages (D, A or
N) are sent using the same message code. It is mandatory that one device sends out
only one SPA-bus message at a time to one node and waits for the reply before
sending the next message.
For commands from the operator workplace to the IED for apparatus control, That
is, the function blocks type SCSWI 1 to 32, SXCBR 1 to 18 and SXSWI 1 to 28;
the SPA addresses are according to table 476.
Horizontal communication
Network variables are used for communication between 500 series and 670 series
IEDs. The supported network variable type is SNVT_state (NV type 83).
SNVT_state is used to communicate the state of a set of 1 to 16 Boolean values.
Multiple command send function block (MULTICMDSND) is used to pack the

information to one value. This value is transmitted to the receiving node and
presented for the application by a multiple command function block
(MULTICMDRCV). At horizontal communication the input BOUND on the event
function block (MULTICMDSND) must be set to 1. There are 10
MULTICMDSND and 60 MULTICMDRCV function blocks available. The
745
MULTICMDSND and MULTICMDRCV function blocks are connected using Lon

Network Tool (LNT 505). This tool also defines the service and addressing on LON.
This is an overview for configuring the network variables for 670 series IEDs.
Configuration of LON network variables

Configure the Network variables according to the specific application using the
LON network Tool. For more information, refer to LNT 505 in Operation manual.
The following is an example of how to configure network variables concerning, for
example, interlocking between two IEDs.
LON
BAY E1 BAY E3 BAY E4

MULTICMDSND: 7 MULTICMDSND: 9 MULTICMDSND: 9
en05000718.vsd
IEC05000718 V2 EN
Figure 369: Examples connections between MULTICMDSND and

MULTICMDRCV function blocks in three IEDs
The network variable connections are done from the NV Connection window.
From LNT window select Connections/ NVConnections/ New.
746
en05000719.vsd
IEC05000719 V1 EN
Figure 370: The network variables window in LNT
There are two ways of downloading NV connections. Either the users can use the
drag-and-drop method where they can select all nodes in the device window, drag
them to the Download area in the bottom of the program window and drop them
there; or, they can perform it by selecting the traditional menu, Configuration/
Download.
747
en05000720.vsd
IEC05000720 V1 EN
Figure 371: The download configuration window in LNT
Communication ports
The serial communication module (SLM) is used for SPA/IEC60870-5-103/DNP
and LON communication. This module is a mezzanine module, and can be placed
on the Main Processing Module (NUM). The serial communication module can
have connectors for two plastic fibre cables (snap-in) or two glass fibre cables (ST,
bayonet) or a combination of plastic and glass fibre. Three different types are
available depending on type of fibre. The incoming optical fibre is connected to the
RX receiver input, and the outgoing optical fibre to the TX transmitter output.
When the fibre optic cables are laid out, pay special attention to the instructions
concerning the handling and connection of the optical fibres. The module is
identified with a number on the label on the module.
Table 476: SPA addresses for commands from the operator workplace to the IED for apparatus
control
Name Function SPA Description
block address
BL_CMD SCSWI01 1 I 5115 SPA parameters for block
command
command
command
command
command
command
748

block address
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
749

block address
command
command
CANCEL SCSWI01 1 I 5107 SPA parameters for cancel
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
750

block address
command
command
command
command
command
command
command
command
command
command
SELECTOpen=00, SCSWI01 1 I 5105 SPA parameters for select (Open/
SELECTClose=01, Close) command
SELOpen+ILO=10, Note: Send select command
SELClose+ILO=11, before operate command
SELOpen+SCO=20,
SELClose+SCO=21,
SELOpen+ILO+SCO=30,
SELClose+ILO+SCO=31
SELECTClose=01, so on. Close) command
751

block address
ExcOpen=00, SCSWI01 1 I 5106 SPA parameters for operate (Open/
ExcClose=01, Close) command
ExcOpen+ILO=10, Note: Send select command
ExcClose+ILO=11, before operate command
ExcOpen+SCO=20,
ExcClose+SCO=21,
ExcOpen+ILO+SCO=30,
ExcClose+ILO+SCO=31
ExcClose=01, so on. Close) command
752

block address
753

block address
Sub Value SXCBR01 2 I 7854 SPA parameter for position to be
substituted
Note: Send the value before Enable
substituted
substituted
substituted
substituted
substituted
substituted
substituted
Sub Value SXCBR09 3I7 SPA parameter for position to be
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
754

block address
Sub Value SXSWI01 3 I 196 SPA parameter for position to be
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
substituted
755

block address
substituted
substituted
substituted
substituted
Sub Enable SXCBR01 2 I 7855 SPA parameter for substitute
enable command
Note: Send the Value before
Enable
enable command
enable command
enable command
enable command
enable command
enable command
enable command
Sub Enable SXCBR09 3I8 SPA parameter for substitute
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
Sub Enable SXSWI01 3 I 197 SPA parameter for substitute
enable command
756

block address
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
Sub Enable SXSWI11 3I 379 SPA parameter for substitute
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
enable command
757

block address
enable command
enable command
enable command
Update Block SXCBR01 2 I 7853 SPA parameter for update block
command
command
command
command
command
command
command
command
Update Block SXCBR09 3I6 SPA parameter for update block
command
command
command
command
command
command
command
command
command
command
Update Block SXSWI01 3 I 198 SPA parameter for update block
command
command
command
758

block address
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
command
759

block address
command
command
command

Table 477: HORZCOMM Non group settings (basic)
Operation Off - - Off Operation
On
Table 478: ADE Non group settings (basic)

On
TimerClass Slow - - Slow Timer class
Normal
Fast

Table 479: LON communication protocol
Function Value
Protocol LON
Communication speed 1.25 Mbit/s
16.4 SPA communication protocol
16.4.1 Introduction
In this section the most common addresses for commands and events are available.
For other addresses, refer to section "Related documents".
It is assumed that the reader is familiar with the SPA communication protocol in
general.
760

The SPA bus uses an asynchronous serial communications protocol (1 start bit, 7
data bits + even parity, 1 stop bit) with data transfer rate up to 38400 bit/s. For
more information on recommended baud rate for each type of IED, refer to
Technical reference manual. Messages on the bus consist of ASCII characters.
Introduction of SPA protocol

The basic construction of the protocol assumes that the slave has no self-initiated
need to talk to the master but the master is aware of the data contained in the slaves
and, consequently, can request required data. In addition, the master can send data
to the slave. Requesting by the master can be performed either by sequenced
polling (for example, for event information) or only on demand.
The master requests slave information using request messages and sends
information to the slave in write messages. Furthermore, the master can send all
slaves in common a broadcast message containing time or other data. The inactive
state of bus transmit and receive lines is a logical "1".
SPA protocol
The tables below specify the SPA addresses for reading data from and writing data
to an IED with the SPA communication protocol implemented.
The SPA addresses for the mA input service values (MIM3 to MIM16) are found
in table 480.
Table 480: SPA addresses for the MIM function

Function block SPA address
MIM3-CH1 4-O-6508
MIM3-CH2 4-O-6511
MIM3-CH3 4-O-6512
MIM3-CH4 4-O-6515
MIM3-CH5 4-O-6516
MIM3-CH6 4-O-6519
MIM4-CH1 4-O-6527
MIM4-CH2 4-O-6530
MIM4-CH3 4-O-6531
MIM4-CH4 4-O-6534
MIM4-CH5 4-O-6535
MIM4-CH6 4-O-6538
MIM5-CH1 4-O-6546
MIM5-CH2 4-O-6549
MIM5-CH3 4-O-6550
MIM5-CH4 4-O-6553
MIM5-CH5 4-O-6554
761

MIM5-CH6 4-O-6557
MIM6-CH1 4-O-6565
MIM6-CH2 4-O-6568
MIM6-CH3 4-O-6569
MIM6-CH4 4-O-6572
MIM6-CH5 4-O-6573
MIM6-CH6 4-O-6576
MIM7-CH1 4-O-6584
MIM7-CH2 4-O-6587
MIM7-CH3 4-O-6588
MIM7-CH4 4-O-6591
MIM7-CH5 4-O-6592
MIM7-CH6 4-O-6595
MIM8-CH1 4-O-6603
MIM8-CH2 4-O-6606
MIM8-CH3 4-O-6607
MIM8-CH4 4-O-6610
MIM8-CH5 4-O-6611
MIM8-CH6 4-O-6614
MIM9-CH1 4-O-6622
MIM9-CH2 4-O-6625
MIM9-CH3 4-O-6626
MIM9-CH4 4-O-6629
MIM9-CH5 4-O-6630
MIM9-CH6 4-O-6633
MIM10-CH1 4-O-6641
MIM10-CH2 4-O-6644
MIM10-CH3 4-O-6645
MIM10-CH4 4-O-6648
MIM10-CH5 4-O-6649
MIM10-CH6 4-O-6652
MIM11-CH1 4-O-6660
MIM11-CH2 4-O-6663
MIM11-CH3 4-O-6664
MIM11-CH4 4-O-6667
MIM11-CH5 4-O-6668
MIM11-CH6 4-O-6671
MIM12-CH1 4-O-6679
MIM12-CH2 4-O-6682
762

MIM12-CH3 4-O-6683
MIM12-CH4 4-O-6686
MIM12-CH5 4-O-6687
MIM12-CH6 4-O-6690
MIM13-CH1 4-O-6698
MIM13-CH2 4-O-6701
MIM13-CH3 4-O-6702
MIM13-CH4 4-O-6705
MIM13-CH5 4-O-6706
MIM13-CH6 4-O-6709
MIM14-CH1 4-O-6717
MIM14-CH2 4-O-6720
MIM14-CH3 4-O-6721
MIM14-CH4 4-O-6724
MIM14-CH5 4-O-6725
MIM14-CH6 4-O-6728
MIM15-CH1 4-O-6736
MIM15-CH2 4-O-6739
MIM15-CH3 4-O-6740
MIM15-CH4 4-O-6743
MIM15-CH5 4-O-6744
MIM15-CH6 4-O-6747
MIM16-CH1 4-O-6755
MIM16-CH2 4-O-6758
MIM16-CH3 4-O-6759
MIM16-CH4 4-O-6762
MIM16-CH5 4-O-6763
MIM16-CH6 4-O-6766
The SPA addresses for the pulse counter values PCGGIO:1 to PCGGIO:16 are
found in table 481.
Table 481: SPA addresses for the PCGGIO function

Function block SPA address CNT_VAL SPA address NEW_VAL
PCGGIO:1 3-O-5834 3-O-5833
PCGGIO:2 3-O-5840 3-O-5839
PCGGIO:3 3-O-5846 3-O-5845
PCGGIO:4 3-O-5852 3-O-5851
PCGGIO:5 3-O-5858 3-O-5857
PCGGIO:6 3-O-5864 3-O-5863
763
Function block SPA address CNT_VAL SPA address NEW_VAL

PCGGIO:7 3-O-5870 3-O-5869
PCGGIO:8 3-O-5876 3-O-5875
PCGGIO:9 3-O-5882 3-O-5881
PCGGIO:10 3-O-5888 3-O-5887
PCGGIO:11 3-O-5894 3-O-5893
PCGGIO:12 3-O-5900 3-O-5899
PCGGIO:13 3-O-5906 3-O-5905
PCGGIO:14 3-O-5912 3-O-5911
PCGGIO:15 3-O-5918 3-O-5917
PCGGIO:16 3-O-5924 3-O-5923
I/O modules
To read binary inputs, the SPA-addresses for the outputs of the I/O-module
function block are used, that is, the addresses for BI1 – BI16. For SPA addresses,
refer to section "Related documents".
Single command, 16 signals

The IEDs can be provided with a function to receive signals either from a
substation automation system or from the local HMI. That receiving function block
has 16 outputs that can be used, for example, to control high voltage apparatuses in
switchyards. For local control functions, the local HMI can also be used.
Single command, 16 signals function consists of three function blocks;

SINGLECMD:1 to SINGLECMD:3 for 16 binary output signals each.
The signals can be individually controlled from the operator station, remote-control
gateway, or from the local HMI on the IED. For Single command, 16 signals
function block, SINGLECMD:1 to SINGLECMD:3, the address is for the first
output. The other outputs follow consecutively after the first one. For example,
output 7 on the SINGLECMD:2 function block has the 5O533 address.
The SPA addresses for Single command, 16 signals functions SINGLECMD:1 to

SINGLECMD:3 are found in table 482.
Table 482: SPA addresses for SINGLECMD function

Function block SPA address CMD Input SPA address CMD output
SINGLECMD1-Cmd1 4-S-4639 5-O-511
764
SINGLECMD1-Cmdt13 4-S-4651 5-O-523
SINGLECMD2-Cmdt3 4-S-4674 5-O-529
765
Figure 372 shows an application example of how the user can, in a simplified way,
connect the command function via the configuration logic circuit in a protection
IED for control of a circuit breaker.
A pulse via the binary outputs of the IED normally performs this type of command
control. The SPA addresses to control the outputs OUT1 – OUT16 in SINGLECMD:
1 are shown in table 482.
SINGLECMD PULSETIMER
BLOCK ÔUT1 INPUT OUT To output board, CLOSE
ÔUT2 #1.000 T
ÔUT3
ÔUT4
ÔUT5
ÔUT6
ÔUT7 AND PULSETIMER
ÔUT8 INPUT1 OUT INPUT OUT To output board, OPEN
INPUT2 NOUT T
ÔUT9 #1.000
INPUT3
ÔUT10
INPUT4N
ÔUT11
ÔUT12
ÔUT13
ÔUT14
ÔUT15
ÔUT16
SYNCH OK
IEC05000717 V2 EN
Figure 372: Application example showing a simplified logic diagram for control
of a circuit breaker
The MODE input defines if the output signals from SINGLECMD:1 is off, steady
or pulsed signals. This is set in Parameter Setting Tool (PST) under: Setting /
General Settings / Control / Commands / Single Command.
Event function
Event function is intended to send time-tagged events to the station level (for
example, operator workplace) over the station bus. The events are there presented
in an event list. The events can be created from both internal logical signals and
binary input channels. All the internal signals are time tagged in the main
processing module, while the binary input channels are time tagged directly on
each I/O module. The events are produced according to the set event masks. The
event masks are treated commonly for both the LON and SPA channels. All events
according to the event mask are stored in a buffer, which contains up to 1000
events. If new events appear before the oldest event in the buffer is read, the oldest
event is overwritten and an overflow alarm appears.
Two special signals for event registration purposes are available in the IED,
Terminal Restarted (0E50) and Event buffer overflow (0E51).
766
The input parameters can be set individually from the Parameter Setting Tool
(PST) under: Setting / General Setting / Monitoring / Event Function as follows:
• No events
• OnSet, at pick-up of the signal
• OnReset, at drop-out of the signal
• OnChange, at both pick-up and drop-out of the signal
• AutoDetect, event system itself make the reporting decision, (reporting criteria
for integers has no semantic, prefer to be set by the user)
The Status and event codes for the Event functions are found in table 483.
Table 483: Status and event codes
Single indication1) Double indication

Event block Status Set event Reset Intermedi Closed 10 Open 01 Undefined
event ate 00 11
EVENT:1
Input 1 22O1 22E33 22E32 22E0 22E1 22E2 22E3
Input 2 22O2 22E35 22E34 22E4 22E5 22E6 22E7
Input 3 22O3 22E37 22E36 22E8 22E9 22E10 22E11
Input 4 22O4 22E39 22E38 22E12 22E13 22E14 22E15
Input 5 22O5 22E41 22E40 22E16 22E17 22E18 22E19
Input 6 22O6 22E43 22E42 22E20 22E21 22E22 22E23
Input 7 22O7 22E45 22E44 22E24 22E25 22E26 22E27
Input 8 22O8 22E47 22E46 22E28 22E29 22E30 22E31
Input 9 22O9 22E49 22E48 - - - -
Input 10 22O10 22E51 22E50 - - - -
Input 11 22O11 22E53 22E52 - - - -
Input 12 22O12 22E55 22E54 - - - -
Input 13 22O13 22E57 22E56 - - - -
Input 14 22O14 22E59 22E58 - - - -
Input 15 22O15 22E61 22E60 - - - -
Input 16 22O16 22E63 22E62 - - - -
EVENT:2 230.. 23E.. 23E.. 23E.. 23E.. 23E.. 23E..

EVENT:3 240.. 24E.. 24E.. 24E.. 23E.. 24E.. 24E..
- - - - - - - -
- - - - - - - -
- - - - - - - -
EVENT:20 410.. 41E.. 41E.. 41E.. 41E.. 41E.. 41E..
These values are only applicable if the Event mask is masked ≠ OFF.
Connection of signals as events

Signals coming from different protection and control functions and must be sent as
events to the station level over the SPA-bus (or LON-bus) are connected to the
Event function block according to figure 373.
767
EVENT
Block BLOCK
ILRANG ÎNPUT1
PSTO ÎNPUT2
UL12RANG ÎNPUT3
UL23RANG ÎNPUT4
UL31RANG ÎNPUT5
3I0RANG ÎNPUT6
3U0RANG ÎNPUT7
FALSE ÎNPUT8
ÎNPUT9
ÎNPUT10
ÎNPUT11
ÎNPUT12
ÎNPUT13
ÎNPUT14
ÎNPUT15
ÎNPUT16
IEC07000065 V2 EN
Figure 373: Connection of protection signals for event handling
16.4.2.1 Communication ports
The serial communication module (SLM) is used for SPA /IEC 60870-5-103/DNP
on the Analog/Digital conversion module (ADM). The serial communication
module can have connectors for two plastic fibre cables (snap-in) or two glass fibre
cables (ST, bayonet) or a combination of plastic and glass fibre. Three different
types are available depending on type of fibre.
The incoming optical fibre is connected to the RX receiver input, and the outgoing
optical fibre to the TX transmitter output. When the fibre optic cables are laid out,
pay special attention to the instructions concerning the handling and connection of
the optical fibres. The module is identified with a number on the label on the module.
The procedure to set the transfer rate and slave number can be found in the
Installation and commissioning manual for respective IEDs.
16.4.3 Design
When communicating locally with a computer (PC) in the station, using the rear
SPA port, the only hardware needed for a station monitoring system is:
• Optical fibres
• Opto/electrical converter for the PC
• PC
When communicating remotely with a PC using the rear SPA port, the same
hardware and telephone modems are needed.
The software needed in the PC, either local or remote, is PCM600.
When communicating between the local HMI and a PC, the only hardware required
is a front-connection cable.
768

Table 484: SPA Non group settings (basic)
BaudRate 300 Bd - - 9600 Bd Baudrate on serial line
1200 Bd
2400 Bd
4800 Bd
9600 Bd
19200 Bd
38400 Bd
Table 485: LONSPA Non group settings (basic)

On

Table 486: SPA communication protocol
Function Value
Protocol SPA
Communication speed 300, 1200, 2400, 4800, 9600, 19200 or 38400
Bd
Slave number 1 to 899
16.5 IEC 60870-5-103 communication protocol
16.5.1 Introduction
IEC 60870-5-103 communication protocol is mainly used when a protection IED
communicates with a third party control or monitoring system. This system must
have software that can interpret the IEC 60870-5-103 communication messages.
16.5.2.1 General
IEC 60870-5-103 is an unbalanced (master-slave) protocol for coded-bit serial

communication exchanging information with a control system, and with a data
transfer rate up to 38400 bit/s. In IEC terminology, a primary station is a master
769
and a secondary station is a slave. The communication is based on a point-to-point

principle. The master must have software that can interpret IEC 60870-5-103
communication messages.
Introduction to IEC 60870–5–103 protocol

IEC 60870-5-103 protocol functionality consists of the following functions:
• Event handling
• Report of analog service values (measurements)
• Fault location
• Command handling
• Autorecloser ON/OFF
• Teleprotection ON/OFF
• Protection ON/OFF
• LED reset
• Characteristics 1 - 4 (Setting groups)
• File transfer (disturbance files)
• Time synchronization
For detailed information about IEC 60870-5-103, refer to the IEC 60870 standard
part 5: Transmission protocols, and to the section 103: Companion standard for the
informative interface of protection equipment.
IEC 60870-5-103 vendor specific implementation

The signal and setting tables specify the information types supported by the IEDs
with the communication protocol IEC 60870-5-103 implemented.
The information types are supported when corresponding functions are included in
the protection and control IED.
Commands in control direction

Commands in control direction, I103IEDCMD
Command block in control direction with defined output signals.
Number of instances: 1
Function type is selected with parameter FunctionType.
Information number is defined for each output signals.

Info. no Message Supported
19 LED Reset Yes
23 Activate setting group 1 Yes
770
Function commands in control direction, pre-defined I103CMD

Function command block in control direction with defined output signals.
Information number is defined for each output signals.

Info. no. Message Supported
16 Auto-recloser on/off Yes
17 Teleprotection on/off Yes
18 Protection on/off Yes
Function commands in control direction, user-defined, I103UserCMD

Function command blocks in control direction with user-defined output signals.
Function type for each function block instance in private range is selected with
parameter FunctionType. Default values are defined in private range 1 - 4. One for
each instance.
Information number must be selected for each output signal. Default values are 1 - 8.
1 Output signal 01 Yes
Status
Terminal status indications in monitor direction, I103IED
Indication block for status in monitor direction with defined IED functions.
Information number is defined for each input signals.
771

19 LED reset Yes
20 Monitor direction blocked No
21 TestMode
22 Local Parameter setting
23 Setting group 1 active Yes
Function status indications in monitor direction, user-defined, I103UserDef

Function indication blocks in monitor direction with user-defined input signals.
Function type is selected with parameter FunctionType for each function block
instance in private range. Default values are defined in private range 5 - 24. One
for each instance.
Information number is required for each input signal. Default values are defined in
range 1 - 8.
Supervision indications in monitor direction, I103Superv

Indication block for supervision in monitor direction with defined functions.
Information number is defined for output signals.
Earth fault indications in monitor direction, I103EF

Indication block for earth fault in monitor direction with defined functions.
Information number is defined for each output signal.

48 Earth fault L1 No
51 Earth fault forward Yes
52 Earth fault reverse Yes
Fault indications in monitor direction, type 1, I103FltDis

772
Fault indication block for faults in monitor direction with defined functions.
The instance type is suitable for distance protection function.
FUNCTION TYPE parameter for each block.
INFORMATION NUMBER is defined for each input signal.
64 Start L1 Yes
65 Start L2 Yes
66 Start L3 Yes
67 Start IN Yes
84 General start Yes
69 Trip L1 Yes
70 Trip L2 Yes
71 Trip L3 Yes
68 General trip Yes
74 Fault forward/line Yes
75 Fault reverse/busbar Yes
78 Zone 1 Yes
79 Zone 2 Yes
80 Zone 3 Yes
81 Zone 4 Yes
82 Zone 5 Yes
76 Signal transmitted Yes
77 Signal received Yes
73 SCL, Fault location in ohm Yes
Fault indications in monitor direction, type 2, I103FltStd

Fault indication block for faults in monitor direction with defined functions.
The instance type is suitable for line differential, transformer differential,

overcurrent and earth fault protection functions.
FUNCTION TYPE setting for each block.
INFORMATION NUMBER is defined for each input signal.
773

64 Start L1 Yes
65 Start L2 Yes
66 Start L3 Yes
67 Start IN Yes
84 General start Yes
69 Trip L1 Yes
70 Trip L2 Yes
71 Trip L3 Yes
68 General trip Yes
74 Fault forward/line Yes
75 Fault reverse/busbar Yes
85 Breaker failure Yes
86 Trip measuring system L1 Yes
89 Trip measuring system N Yes
90 Over current trip I> Yes
91 Over current trip I>> Yes
92 Earth fault trip IN> Yes
93 Earth fault trip IN>> Yes
Autorecloser indications in monitor direction, I103AR

Indication block for autorecloser in monitor direction with defined functions.
Information number is defined for each output signal.

16 Autorecloser active Yes
17 Teleprotection active No
18 Protection active No
128 CB on by Autorecloser Yes
129 CB ‘on’ by long-time AR No
130 Autorecloser blocked Yes
Measurands
Function blocks in monitor direction for input measurands. Typically connected to
monitoring function, for example to power measurement CVMMXN.
774
Measurands in public range, I103Meas

The IED reports all valid measuring types depending on connected signals.
Upper limit for measured currents, active/reactive-power is 2.4 times rated value.
Upper limit for measured voltages and frequency is 1.2 times rated value.
148 IL1 Yes
144, 145, IL2 Yes
148
148 IL3 Yes
147 IN, Neutral current Yes
148 UL1 Yes
148 UL2 Yes
148 UL3 Yes
145, 146 UL1-UL2 Yes
147 UN, Neutral voltage Yes
146, 148 P, active power Yes
146, 148 Q, reactive power Yes
148 f, frequency Yes
Measurands in private range, I103MeasUsr

Function type parameter for each block in private range. Default values are defined
in private range 25 – 27. One for each instance.
Information number must be selected for measurands.

Info. Message Supported
*1) Meas1 Yes
* Meas2 Yes
* Meas3 Yes
* Meas4 Yes
* Meas5 Yes
* Meas6 Yes
* Meas7 Yes
* Meas8 Yes
* Meas9 Yes
1) * User defined information number
775
Disturbance recordings
The following elements are used in the ASDUs (Application Service Data Units)
defined in the standard.
Analog signals, 40-channels: the channel number for each channel has to be
specified. Channels used in the public range are 1 to 8 and with:
• IL1 connected to channel 1 on disturbance function block A1RADR

• IN connected to channel 4 on disturbance function block A1RADR
• VL1E connected to channel 5 on disturbance function block A1RADR
• VEN connected to channel 8 on disturbance function block A1RADR
Channel number used for the remaining 32 analog signals are numbers in the
private range 64 to 95.
Binary signals, 96-channels: for each channel the user can specify a FUNCTION
TYPE and an INFORMATION NUMBER.
Disturbance upload
All analog and binary signals that are recorded with disturbance recorder can be
reported to the master. The last eight disturbances that are recorded are available
for transfer to the master. A successfully transferred disturbance (acknowledged by
the master) will not be reported to the master again.
When a new disturbance is recorded by the IED a list of available recorded

disturbances will be sent to the master, an updated list of available disturbances can
be sent whenever something has happened to disturbances in this list. For example,
when a disturbance is deteceted (by other client, for example, SPA) or when a new
disturbance has been recorded or when the master has uploaded a disturbance.
Deviations from the standard
Information sent in the disturbance upload is specified by the standard; however,

some of the information are adapted to information available in disturbance
recorder in 670 series.
This section describes all data that is not exactly as specified in the standard.
ASDU23
In ‘list of recorded disturbances’ (ASDU23) an information element named SOF

(status of fault) exists. This information element consists of 4 bits and indicates
whether:
776
• Bit TP: the protection equipment has tripped during the fault
• Bit TM: the disturbance data are currently being transmitted
• Bit TEST: the disturbance data have been recorded during normal operation or
test mode.
• Bit OTEV: the disturbance data recording has been initiated by another event
than start
The only information that is easily available is test-mode status. The other
information is always set (hard coded) to:
TP Recorded fault with trip. [1]

TM Disturbance data waiting for transmission [0]
OTEV Disturbance data initiated by other events [1]
Another information element in ASDU23 is the FAN (fault number). According to

the standard this is a number that is incremented when a protection function takes
action. In 670 series FAN is equal to disturbance number, which is incremented for
each disturbance.
ASDU26
When a disturbance has been selected by the master; (by sending ASDU24), the
protection equipment answers by sending ASDU26, which contains an information
element named NOF (number of grid faults). This number must indicate fault
number in the power system,that is, a fault in the power system with several trip
and auto-reclosing has the same NOF (while the FAN must be incremented). NOF
is in 670 series, just as FAN, equal to disturbance number.
To get INF and FUN for the recorded binary signals there are parameters on the
disturbance recorder for each input. The user must set these parameters to whatever
he connects to the corresponding input.
Interoperability, physical layer

Supported
Electrical Interface
EIA RS-485 No
number of loads No
Optical interface
glass fibre Yes
plastic fibre
Transmission speed
9600 bit/s Yes
19200 bit/s Yes
Link Layer
DFC-bit used Yes
777
Supported
Connectors
connector F-SMA No
connector BFOC/2.5 Yes
Interoperability, application layer

Supported
Selection of standard ASDUs in monitoring direction
ASDU Yes
1 Time-tagged message Yes
2 Time-tagged message with rel. time Yes
3 Measurands I Yes
4 Time-tagged message with rel. time Yes
5 Identification Yes
6 Time synchronization Yes
8 End of general interrogation Yes
9 Measurands II Yes
10 Generic data No
11 Generic identification No
23 List of recorded disturbances Yes
26 Ready for transm. of disturbance data Yes
27 Ready for transm. of a channel Yes
28 Ready for transm of tags Yes
29 Transmission of tags Yes
30 Transmission fo disturbance data Yes
31 End of transmission Yes
Selection of standard ASDUs in control direction
ASDU Yes
6 Time synchronization Yes
7 General interrogation Yes
10 Generic data No
20 General command Yes
21 Generic command No
24 Order for disturbance data transmission Yes
25 Acknowledgement for distance data transmission Yes
Selection of basic application functions
Test mode No
Blocking of monitoring direction Yes
778
Supported
Disturbance data Yes
Private data Yes
Generic services No
16.5.2.2 Communication ports
The serial communication module (SLM) is used for SPA/IEC 60870-5-103/DNP

on the Analog/Digital conversion module (ADM). The serial communication
module can have connectors for two plastic fibre cables (snap-in) or two glass fibre
cables (ST, bayonet) or a combination of plastic and glass fibre. Three different
types are available depending on type of fibre.
The incoming optical fibre is connected to the RX receiver input, and the outgoing
optical fibre to the TX transmitter output. When the fibre optic cables are laid out,
pay special attention to the instructions concerning the handling and connection of
the optical fibres. The module is identified with a number on the label on the module.

I103IEDCMD
BLOCK 19-LEDRS
FUNTYPE 23-GRP1
24-GRP2
25-GRP3
26-GRP4
IEC05000689 V2 EN
I103CMD
BLOCK 16-AR
FUNTYPE 17-DIFF
18-PROT
IEC05000684 V2 EN
I103USRCMD
BLOCK OUTPUT1
PULSEMOD OUTPUT2
T OUTPUT3
FUNTYPE OUTPUT4
INFNO_1 OUTPUT5
INFNO_2 OUTPUT6
INFNO_3 OUTPUT7
INFNO_4 OUTPUT8
INFNO_5
INFNO_6
INFNO_7
INFNO_8
IEC05000693 V2 EN
779
I103IED
BLOCK
19_LEDRS
23_GRP1
24_GRP2
25_GRP3
26_GRP4
21_TESTM
FUNTYPE
IEC05000688 V2 EN
I103USRDEF
BLOCK
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
FUNTYPE
INFNO_1
INFNO_2
INFNO_3
INFNO_4
INFNO_5
INFNO_6
INFNO_7
INFNO_8
IEC05000694 V2 EN
I103SUPERV
BLOCK
32_MEASI
33_MEASU
37_IBKUP
38_VTFF
46_GRWA
47_GRAL
FUNTYPE
IEC05000692 V2 EN
I103EF
BLOCK
51_EFFW
52_EFREV
FUNTYPE
IEC05000685 V2 EN
780
I103FLTDIS
BLOCK
64_STL1
65_STL2
66_STL3
67_STIN
84_STGEN
69_TRL1
70_TRL2
71_TRL3
68_TRGEN
74_FW
75_REV
78_ZONE1
79_ZONE2
80_ZONE3
81_ZONE4
82_ZONE5
76_TRANS
77_RECEV
73_SCL
FLTLOC
ARINPROG
FUNTYPE
IEC05000686 V2 EN
I103FLTSTD
BLOCK
64_STL1
65_STL2
66_STL3
67_STIN
84_STGEN
69_TRL1
70_TRL2
71_TRL3
68_TRGEN
74_FW
75_REV
85_BFP
86_MTRL1
87_MTRL2
88_MTRL3
89_MTRN
90_IOC
91_IOC
92_IEF
93_IEF
ARINPROG
FUNTYPE
IEC05000687 V2 EN
I103AR
BLOCK
16_ARACT
128_CBON
130_UNSU
FUNTYPE
IEC05000683 V2 EN
781
I103MEAS
BLOCK
IL1
IL2
IL3
IN
UL1
UL2
UL3
UL1L2
UN
P
Q
F
FUNTYPE
IEC05000690 V2 EN
I103MEASUSR
BLOCK
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
FUNTYPE
INFNO
IEC05000691 V2 EN

Table 487: I103IEDCMD Input signals
BLOCK BOOLEAN 0 Block of commands
Table 488: I103IEDCMD Output signals

19-LEDRS BOOLEAN Information number 19, reset LEDs
23-GRP1 BOOLEAN Information number 23, activate setting group 1
Table 489: I103CMD Input signals

782
Table 490: I103CMD Output signals

16-AR BOOLEAN Information number 16, block of autorecloser
17-DIFF BOOLEAN Information number 17, block of differential
protection
18-PROT BOOLEAN Information number 18, block of protection
Table 491: I103USRCMD Input signals

Table 492: I103USRCMD Output signals

OUTPUT1 BOOLEAN Command output 1
Table 493: I103IED Input signals

BLOCK BOOLEAN 0 Block of status reporting
19_LEDRS BOOLEAN 0 Information number 19, reset LEDs
23_GRP1 BOOLEAN 0 Information number 23, setting group 1 is active
21_TESTM BOOLEAN 0 Information number 21, test mode is active
Table 494: I103USRDEF Input signals

INPUT1 BOOLEAN 0 Binary signal Input 1
INPUT2 BOOLEAN 0 Binary signal input 2
783

Table 495: I103SUPERV Input signals

32_MEASI BOOLEAN 0 Information number 32, measurand supervision of
I
33_MEASU BOOLEAN 0 Information number 33, measurand supervision of
U
37_IBKUP BOOLEAN 0 Information number 37, I high-high back-up
protection
38_VTFF BOOLEAN 0 Information number 38, fuse failure VT
46_GRWA BOOLEAN 0 Information number 46, group warning
47_GRAL BOOLEAN 0 Information number 47, group alarm
Table 496: I103EF Input signals

51_EFFW BOOLEAN 0 Information number 51, earth-fault forward
52_EFREV BOOLEAN 0 Information number 52, earth-fault reverse
Table 497: I103FLTDIS Input signals

64_STL1 BOOLEAN 0 Information number 64, start phase L1
67_STIN BOOLEAN 0 Information number 67, start residual current IN
84_STGEN BOOLEAN 0 Information number 84, start general
69_TRL1 BOOLEAN 0 Information number 69, trip phase L1
68_TRGEN BOOLEAN 0 Information number 68, trip general
74_FW BOOLEAN 0 Information number 74, forward/line
75_REV BOOLEAN 0 Information number 75, reverse/bus
784

78_ZONE1 BOOLEAN 0 Information number 78, zone 1
76_TRANS BOOLEAN 0 Information number 76, signal transmitted
77_RECEV BOOLEAN 0 Information number 77, signal recevied
73_SCL REAL 0 Information number 73, fault location in ohm
FLTLOC BOOLEAN 0 Faultlocator faultlocation valid (LMBRFLO-
CALCMADE)
ARINPROG BOOLEAN 0 Autorecloser in progress (SMBRREC- INPROGR)
Table 498: I103FLTSTD Input signals

67_STIN BOOLEAN 0 Information number 67, start residual curent IN
84_STGEN BOOLEAN 0 Information number 84, start general
68_TRGEN BOOLEAN 0 Information number 68, trip general
74_FW BOOLEAN 0 Information number 74, forward/line
75_REV BOOLEAN 0 Information number 75, reverse/bus
85_BFP BOOLEAN 0 Information number 85, breaker failure
86_MTRL1 BOOLEAN 0 Information number 86, trip measuring system
phase L1
phase L2
phase L3
89_MTRN BOOLEAN 0 Information number 89, trip measuring system
neutral N
90_IOC BOOLEAN 0 Information number 90, over current trip, stage low
91_IOC BOOLEAN 0 Information number 91, over current trip, stage high
92_IEF BOOLEAN 0 Information number 92, earth-fault trip, stage low
93_IEF BOOLEAN 0 Information number 93, earth-fault trip, stage high
ARINPROG BOOLEAN 0 Autorecloser in progress (SMBRREC- INPROGR)
785
Table 499: I103AR Input signals

16_ARACT BOOLEAN 0 Information number 16, auto-recloser active
128_CBON BOOLEAN 0 Information number 128, circuit breaker on by auto-
recloser
130_UNSU BOOLEAN 0 Information number 130, unsuccessful reclosing
Table 500: I103MEAS Input signals

BLOCK BOOLEAN 0 Block of service value reporting
IL1 REAL 0.0 Service value for current phase L1
IN REAL 0.0 Service value for residual current IN
UL1 REAL 0.0 Service value for voltage phase L1
UL1L2 REAL 0.0 Service value for voltage phase-phase L1-L2
UN REAL 0.0 Service value for residual voltage UN
P REAL 0.0 Service value for active power
Q REAL 0.0 Service value for reactive power
F REAL 0.0 Service value for system frequency
Table 501: I103MEASUSR Input signals

BLOCK BOOLEAN 0 Block of service value reporting
INPUT1 REAL 0.0 Service value for measurement on input 1
786

Table 502: IEC60870-5-103 Non group settings (basic)
BaudRate 9600 Bd - - 9600 Bd Baudrate on serial line
19200 Bd
RevPolarity Off - - On Invert polarity
On
CycMeasRepTime 1.0 - 3600.0 - 0.1 5.0 Cyclic reporting time of measurments
Table 503: I103IEDCMD Non group settings (basic)

FUNTYPE 1 - 255 FunT 1 255 Function type (1-255)
Table 504: I103CMD Non group settings (basic)

Table 505: I103USRCMD Non group settings (basic)

PULSEMOD 0-1 Mode 1 1 Pulse mode 0=Steady, 1=Pulsed
T 0.200 - 60.000 s 0.001 0.400 Pulse length
INFNO_1 1 - 255 InfNo 1 1 Information number for output 1 (1-255)
Table 506: I103IED Non group settings (basic)

787
Table 507: I103USRDEF Non group settings (basic)

INFNO_1 1 - 255 InfNo 1 1 Information number for binary input 1
(1-255)
(1-255)
(1-255)
(1-255)
(1-255)
(1-255)
(1-255)
(1-255)
Table 508: I103SUPERV Non group settings (basic)

Table 509: I103EF Non group settings (basic)

Table 510: I103FLTDIS Non group settings (basic)

Table 511: I103FLTSTD Non group settings (basic)

Table 512: I103AR Non group settings (basic)

788
Table 513: I103MEAS Non group settings (basic)

RatedIL1 1 - 99999 A 1 3000 Rated current phase L1
RatedIN 1 - 99999 A 1 3000 Rated residual current IN
RatedUL1 0.05 - 2000.00 kV 0.05 230.00 Rated voltage for phase L1
RatedUL1-UL2 0.05 - 2000.00 kV 0.05 400.00 Rated voltage for phase-phase L1-L2
RatedUN 0.05 - 2000.00 kV 0.05 230.00 Rated residual voltage UN
RatedP 0.00 - 2000.00 MW 0.05 1200.00 Rated value for active power
RatedQ 0.00 - 2000.00 MVA 0.05 1200.00 Rated value for reactive power
RatedF 50.0 - 60.0 Hz 10.0 50.0 Rated system frequency
Table 514: I103MEASUSR Non group settings (basic)

INFNO 1 - 255 InfNo 1 1 Information number for measurands
(1-255)
RatedMeasur1 0.05 - - 0.05 1000.00 Rated value for measurement on input 1
10000000000.00
10000000000.00
10000000000.00
10000000000.00
10000000000.00
10000000000.00
10000000000.00
10000000000.00
10000000000.00
789

Table 515: IEC60870-5-103 communication protocol
Function Value
Protocol IEC 60870-5-103
Communication speed 9600, 19200 Bd
16.6 Horizontal communication via GOOSE for

interlocking GOOSEINTLKRCV

GOOSEINTLKRCV
BLOCK ^RESREQ
^RESGRANT
ÂPP1_OP
ÂPP1_CL
APP1VAL
ÂPP2_OP
ÂPP2_CL
APP2VAL
ÂPP3_OP
ÂPP3_CL
APP3VAL
ÂPP4_OP
ÂPP4_CL
APP4VAL
ÂPP5_OP
ÂPP5_CL
APP5VAL
ÂPP6_OP
ÂPP6_CL
APP6VAL
ÂPP7_OP
ÂPP7_CL
APP7VAL
ÂPP8_OP
ÂPP8_CL
APP8VAL
ÂPP9_OP
ÂPP9_CL
APP9VAL
ÂPP10_OP
ÂPP10_CL
APP10VAL
ÂPP11_OP
ÂPP11_CL
APP11VAL
ÂPP12_OP
ÂPP12_CL
APP12VAL
ÂPP13_OP
ÂPP13_CL
APP13VAL
ÂPP14_OP
ÂPP14_CL
APP14VAL
ÂPP15_OP
ÂPP15_CL
APP15VAL
COM_VAL
IEC07000048 V2 EN
Figure 374: GOOSEINTLKRCV function block
790

Table 516: GOOSEINTLKRCV Input signals
BLOCK BOOLEAN 0 Block of output signals
Table 517: GOOSEINTLKRCV Output signals

RESREQ BOOLEAN Reservation request
RESGRANT BOOLEAN Reservation granted
APP1_OP BOOLEAN Apparatus 1 position is open
APP1_CL BOOLEAN Apparatus 1 position is closed
APP1VAL BOOLEAN Apparatus 1 position is valid
791

COM_VAL BOOLEAN Receive communication status is valid

Table 518: GOOSEINTLKRCV Non group settings (basic)
On
792
16.7 Goose binary receive GOOSEBINRCV

GOOSEBINRCV
BLOCK ÔUT1
OUT1VAL
ÔUT2
OUT2VAL
ÔUT3
OUT3VAL
ÔUT4
OUT4VAL
ÔUT5
OUT5VAL
ÔUT6
OUT6VAL
ÔUT7
OUT7VAL
ÔUT8
OUT8VAL
ÔUT9
OUT9VAL
ÔUT10
OUT10VAL
ÔUT11
OUT11VAL
ÔUT12
OUT12VAL
ÔUT13
OUT13VAL
ÔUT14
OUT14VAL
ÔUT15
OUT15VAL
ÔUT16
OUT16VAL
IEC07000047 V2 EN
Figure 375: GOOSEBINRCV function block

Table 519: GOOSEBINRCV Input signals
BLOCK BOOLEAN 0 Block of output signals
Table 520: GOOSEBINRCV Output signals

OUT1 BOOLEAN Binary output 1
OUT1VAL BOOLEAN Valid data on binary output 1
793


Table 521: GOOSEBINRCV Non group settings (basic)
On
16.8 Multiple command and transmit MULTICMDRCV,

MULTICMDSND
794

Multiple command and transmit MULTICMDRCV - -
Multiple command and transmit MULTICMDSND - -
16.8.1 Introduction
The IED can be provided with a function to send and receive signals to and from
other IEDs via the interbay bus. The send and receive function blocks has 16 outputs/
inputs that can be used, together with the configuration logic circuits, for control
purposes within the IED or via binary outputs. When it is used to communicate
with other IEDs, these IEDs have a corresponding Multiple transmit function block
with 16 outputs to send the information received by the command block.

Two multiple transmit function blocks MULTICMDSND:1 and MULTICMDSND:
2 and 8 slow multiple transmit function blocks MULTICMDSND:3 to
MULTICMDSND:10 are available in the IED.
Sixteen signals can be connected and they will then be sent to the multiple
command block in the other IED. The connections are set with the LON Network
Tool (LNT).
Twelve multiple command function blocks MULTICMDRCV:1 to

MULTICMDRCV:12 with fast execution time and 48 multiple command function
blocks MULTICMDRCV:13 to MULTICMDRCV:60 with slower execution time
are available in the IED.
Multiple command function block MULTICMDRCV has 16 outputs combined in

one block, which can be controlled from other IEDs.
The output signals, here OUTPUT1 to OUTPUT16, are then available for
configuration to built-in functions or via the configuration logic circuits to the
binary outputs of the IED.
MULTICMDRCV also has a supervision function, which sets the output VALID to
0 if the block does not receive data within set maximum time.
16.8.3 Design
16.8.3.1 General
The output signals can be of the types Off, Steady, or Pulse. The setting is done on
the MODE settings, common for the whole block, from PCM600.
795
• 0 = Off sets all outputs to 0, independent of the values sent from the station
level, that is, the operator station or remote-control gateway.
• 1 = Steady sets the outputs to a steady signal 0 or 1, depending on the values
sent from the station level.
• 2 = Pulse gives a pulse with one execution cycle duration, if a value sent from
the station level is changed from 0 to 1. That means that the configured logic
connected to the command function blocks may not have a cycle time longer
than the execution cycle time for the command function block.

MULTICMDRCV
BLOCK ERROR
NEWDATA
OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
OUTPUT9
OUTPUT10
OUTPUT11
OUTPUT12
OUTPUT13
OUTPUT14
OUTPUT15
OUTPUT16
VALID
IEC06000007 V2 EN
Figure 376: MULTICMDRCV function block
MULTICMDSND
BLOCK ERROR
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
IEC06000008 V2 EN
Figure 377: MULTICMDSND function block
796

Table 522: MULTICMDRCV Input signals
Table 523: MULTICMDSND Input signals

Table 524: MULTICMDRCV Output signals

ERROR BOOLEAN MultiReceive error
NEWDATA BOOLEAN New data is received
OUTPUT1 BOOLEAN Output 1
797

VALID BOOLEAN Output data is valid
Table 525: MULTICMDSND Output signals

ERROR BOOLEAN MultiSend error

Table 526: MULTICMDRCV Non group settings (basic)
tMaxCycleTime 0.050 - 200.000 s 0.001 11.000 Maximum cycle time between receptions
of input data
tMinCycleTime 0.000 - 200.000 s 0.001 0.000 Minimum cycle time between receptions
of input data
Mode Steady - - Steady Mode for output signals
Pulsed
tPulseTime 0.000 - 60.000 s 0.001 0.200 Pulse length for multi command outputs
Table 527: MULTICMDSND Non group settings (basic)

tMaxCycleTime 0.000 - 200.000 s 0.001 5.000 Maximum time interval between
transmission of output data
tMinCycleTime 0.000 - 200.000 s 0.001 0.000 Minimum time interval between
transmission of output data
798
Remote communication
Section 17 Remote communication
About this chapter

This chapter describes the Binary signal transfer function and associated hardware
functionality. The way the functions work, their setting parameters, function
blocks, input and output signals, and technical data are included for each function.
17.1 Binary signal transfer

Binary signal transfer BinSignReceive - -
Binary signal transfer BinSignTransm - -
17.1.1 Introduction
The remote end data communication is used either for the transmission of current
values together with maximum 8 binary signals in the line differential protection,
or for transmission of only binary signals, up to 192 signals, in the other 670 series
IEDs. The binary signals are freely configurable and can, thus, be used for any
purpose, for example, communication scheme related signals, transfer trip and/or
other binary signals between IEDs.
Communication between two IEDs requires that each IED is equipped with an
LDCM (Line Data Communication Module). The LDCMs are then interfaces to a
64 kbit/s communication channel for duplex communication between the IEDs.
The IED can be equipped with up to two short range or medium range LDCM.

The communication is made on standard ITU (CCITT) PCM digital 64 kbit/s
channels. It is a two-way communication where telegrams are sent every 5 ms
(same in 50 Hz and 60 Hz), exchanging information between two IEDs. The format
used is C37.94 and one telegram consists of start and stop flags, address, data to be
transmitted, Cyclic Redundancy Check (CRC) and Yellow bit (which is associated
with C37.94).
799
Start Stop
Information CRC
flag flag
8 bits n x 16 bits 16 bits 8 bits

en01000134.vsd
IEC01000134 V1 EN
Figure 378: Data message structure
The start and stop flags are the 0111 1110 sequence (7E hexadecimal), defined in
the HDLC standard. The CRC is designed according to the standard CRC16
definition. The optional address field in the HDLC frame is not used instead a
separate addressing is included in the data field.
The address field is used for checking that the received message originates from
the correct equipment. There is always a risk that multiplexers occasionally mix the
messages up. Each terminal in the system is given a number. The terminal is then
programmed to accept messages from a specific terminal number. If the CRC
function detects a faulty message, the message is thrown away and not used in the
evaluation.
When the communication is used for line differential purpose, the transmitted data
consists of three currents, clock information, trip-, block- and alarm-signals and
eight binary signals which can be used for any purpose. The three currents are
represented as sampled values.
When the communication is used exclusively for binary signals, the full data
capacity of the communication channel is used for the binary signal purpose which
gives the capacity of 192 signals.

Table 528: LDCMRecBinStat1 Non group settings (basic)
ChannelMode Off - - On Channel mode of LDCM, 0=OFF, 1=ON,
On 2=OutOfService
OutOfService
TerminalNo 0 - 255 - 1 0 Terminal number used for line differential
communication
RemoteTermNo 0 - 255 - 1 0 Terminal number on remote terminal
CommSync Slave - - Slave Com Synchronization mode of LDCM,
Master 0=Slave, 1=Master
OptoPower LowPower - - LowPower Transmission power for LDCM, 0=Low,
HighPower 1=High
ComFailAlrmDel 5 - 500 ms 5 100 Time delay before communication error
signal is activated
ComFailResDel 5 - 500 ms 5 100 Reset delay before communication error
signal is reset
InvertPolX21 Off - - Off Invert polarization for X21 communication
On
800

On 2=OutOfService
OutOfService
NAMECH1 0 - 13 - 1 LDCM#-CH1 User define string for analogue input 1
communication
DiffSync Echo - - Echo Diff Synchronization mode of LDCM,
GPS 0=ECHO, 1=GPS
GPSSyncErr Block - - Block Operation mode when GPS
Echo synchroniation signal is lost
HighPower 1=High
TransmCurr CT-GRP1 - - CT-GRP1 Summation mode for transmitted current
CT-GRP2 values
CT-SUM
CT-DIFF1
CT-DIFF2
signal is activated
signal is reset
RedChSwTime 5 - 500 ms 5 5 Time delay before switching in
redundant channel
RedChRturnTime 5 - 500 ms 5 100 Time delay before switching back from
redundant channel
AsymDelay -20.00 - 20.00 ms 0.01 0.00 Asymmetric delay when communication
use echo synch.
AnalogLatency 2 - 20 - 1 2 Latency between local analogue data
and transmitted
remAinLatency 2 - 20 - 1 2 Analog latency of remote terminal
MaxTransmDelay 0 - 40 ms 1 20 Max allowed transmission delay
CompRange 0-10kA - - 0-25kA Compression range
0-25kA
0-50kA
0-150kA
MaxtDiffLevel 200 - 2000 us 1 600 Maximum time diff for ECHO back-up
DeadbandtDiff 200 - 1000 us 1 300 Deadband for t Diff
On
801

On 2=OutOfService
OutOfService
communication
DiffSync Echo - - Echo Diff Synchronization mode of LDCM,
GPS 0=ECHO, 1=GPS
GPSSyncErr Block - - Block Operation mode when GPS
Echo synchroniation signal is lost
HighPower 1=High
TransmCurr CT-GRP1 - - CT-GRP1 Summation mode for transmitted current
CT-GRP2 values
CT-SUM
CT-DIFF1
CT-DIFF2
RedundantChannel
signal is activated
signal is reset
RedChSwTime 5 - 500 ms 5 5 Time delay before switching in
redundant channel
RedChRturnTime 5 - 500 ms 5 100 Time delay before switching back from
redundant channel
AsymDelay -20.00 - 20.00 ms 0.01 0.00 Asymmetric delay when communication
use echo synch.
AnalogLatency 2 - 20 - 1 2 Latency between local analogue data
and transmitted
remAinLatency 2 - 20 - 1 2 Analog latency of remote terminal
MaxTransmDelay 0 - 40 ms 1 20 Max allowed transmission delay
CompRange 0-10kA - - 0-25kA Compression range
0-25kA
0-50kA
0-150kA
MaxtDiffLevel 200 - 2000 us 1 600 Maximum time diff for ECHO back-up
DeadbandtDiff 200 - 1000 us 1 300 Deadband for t Diff
On
802
17.2 Transmission of analog data from LDCM

LDCMTransmit

LDCMTRN
^CT1L1
^CT1L2
^CT1L3
^CT1N
^CT2L1
^CT2L2
^CT2L3
^CT2N
IEC10000017 V1 EN
Figure 379: LDCMTransmit function block
The function blocks are not represented in the Application

Configuration tool except for the LDCMTRN function block that is
visible in ACT. The signals appear only in the Signal Matrix tool
when a LDCM is included in the configuration with the function
selector tool.

Table 531: LDCMTRN Input signals
CT1L1 STRING 0 Input to be used for transmit CT-group1 line L1 to
remote end
remote end
remote end
CT1N STRING 0 Input to be used for transmit CT-group1 neutral N
to remote end
remote end
remote end
remote end
CT2N STRING 0 Input to be used for transmit CT-group2 neutral N
to remote end
803
804
IED hardware
Section 18 IED hardware
About this chapter

This chapter describes the different hardware modules available in the IED. The
descriptions includes diagrams from different elevations indicating the location of
connection terminals and modules.
18.1 Overview
18.1.1 Variants of case and local HMI display size
xx04000458.ep
IEC04000458 V1 EN
Figure 380: 1/2 19” case with medium local HMI display.
805
IED hardware
xx04000459.ep
IEC04000459 V1 EN
Figure 381: 1/2 19” case with small local HMI display.
IEC05000762 V1 EN
xx05000763.eps
IEC05000763 V1 EN
806
IED hardware
xx04000460.ep
IEC04000460 V1 EN
xx04000461.eps
IEC04000461 V1 EN
807
IED hardware
18.1.2 Case from the rear side

Table 532: Designations for 1/2 x 19” casing with 1 TRM slot
Module Rear Positions

PSM X11
BIM, BOM, SOM, IOM or X31 and X32 etc. to X51
MIM and X52
SLM X301:A, B, C, D
LDCM, IRIG-B or RS485 X302
LDCM or RS485 X303
OEM X311:A, B, C, D
LDCM, RS485 or GTM X312, 313
TRM X401
1MRK002801-AC 2 670 1.2 PG V1 EN
808
IED hardware

PSM X11
BIM, BOM, SOM, IOM or X31 and X32 etc. to
MIM X101 and X102
SLM X301:A, B, C, D
LDCM or RS485 X303
OEM X311:A, B, C, D
LDCM, RS485 or GTM X312, X313
TRM X401
1MRK002801-AC 3 670 1.2 PG V1 EN
809
IED hardware

PSM X11
BIM, BOM, SOM, IOM or X31 and X32 etc. to X71 and
MIM X72
SLM X301:A, B, C, D
LDCM or RS485 X303
OEM X311:A, B, C, D
LDCM, RS485 or GTM X312, X313, X322, X323
TRM 1 X401
TRM 2 X411
1MRK002801-AC 4 670 1.2 PG V1 EN
810
IED hardware

PSM X11
BIM, BOM, X31 and X32 etc. to X161
SOM, IOM or and X162
MIM
SLM X301:A, B, C, D
LDCM, IRIG-B or X302
RS485
LDCM or RS485 X303
OEM X311:A, B, C, D
LDCM,RS485 or X312, X313
GTM
TRM X401
1MRK002801-AC 5 670 1.2 PG V1 EN
811
IED hardware
Table 536: Designations for 1/1 x 19” casing with 2 TRM slots

PSM X11
BIM, BOM, X31 and X32 etc. to X131
SOM, IOM or and X132
MIM
SLM X301:A, B, C, D
LDCM, IRIG-B or X302
RS485
LDCM or RS485 X303
OEM X311:A, B, C, D
LDCM, RS485 or X312, X313, X322, X323
GTM
TRM 1 X401
TRM 2 X411
1MRK002801-AC 6 670 1.2 PG V1 EN
18.2 Hardware modules
18.2.1 Overview
Table 537: Basic modules
Module Description
Combined backplane module (CBM) A backplane PCB that carries all internal signals
between modules in an IED. Only the TRM (when
included) is not connected directly to this board.
Universal backplane module (UBM) A backplane PCB that forms part of the IED
backplane with connectors for TRM (when
included), ADM etc.
Power supply module (PSM) Including a regulated DC/DC converter that
supplies auxiliary voltage to all static circuits.
• An internal fail alarm output is available.
Numerical module (NUM) Module for overall application control. All

information is processed or passed through this
module, such as configuration, settings and
communication.
812
IED hardware
Module Description
Local Human machine interface (LHMI) The module consists of LED:s, an LCD, a push
button keyboard and an ethernet connector used
to connect a PC to the IED.
Transformer input module (TRM) Transformer module that galvanically separates
the internal circuits from the VT and CT circuits. It
has 12 analog inputs.
Analog digital conversion module (ADM) Slot mounted PCB with A/D conversion.
Table 538: Application specific modules

Module Description
Binary input module (BIM) Module with 16 optically isolated binary inputs
Binary output module (BOM) Module with 24 single outputs or 12 double-pole
command outputs including supervision function
Binary I/O module (IOM) Module with 8 optically isolated binary inputs, 10
outputs and 2 fast signalling outputs.
Line data communication modules (LDCM), Modules used for digital communication to remote
short range, medium range, long range, X21 terminal.
Serial SPA/LON/IEC 60870-5-103/DNP3 Used for SPA/LON/IEC 60870–5–103/DNP3
communication modules (SLM) communication
Optical ethernet module (OEM) PMC board for IEC 61850 based communication.
mA input module (MIM) Analog input module with 6 independent,
galvanically separated channels.
IRIG-B Time synchronization module (IRIG-B) Module with 2 inputs. One is used for handling
both pulse-width modulated signals and
amplitude modulated signals and one is used for
optical input type ST for PPS time synchronization.
18.2.2 Combined backplane module (CBM)
The combined backplane module (CBM) carries signals between modules in an IED.
18.2.2.2 Functionality
The Compact PCI makes 3.3V or 5V signaling in the backplane possible. The
CBM backplane and connected modules are 5V PCI-compatible.
Some pins on the Compact PCI connector are connected to the CAN bus, to be able
to communicate with CAN based modules.
If a modules self test discovers an error it informs other modules using the Internal
Fail signal IRF.
813
IED hardware
18.2.2.3 Design
There are two basic versions of the CBM:
• with 3 Compact PCI connectors and a number of euro connectors depending

on the IED case size. One Compact PCI connector is used by NUM and two
are used by other PCI modules, for example two ADMs in IEDs with two
TRMs. See figure 387
• with 2 Compact PCI connectors and a number of euro connectors depending
on the IED case size. One Compact PCI connector is used by NUM and one is
used by for example an ADM in IEDs with one TRM. See figure 386
Each PCI connector consists of 2 compact PCI receptacles. The euro connectors
are connected to the CAN bus and used for I/O modules and power supply.
1 2
en05000516.vsd
IEC05000516 V1 EN
Figure 386: CBM for 1 TRM.
Pos Description
1 CAN slots
2 CPCI slots
814
IED hardware
1 2
en05000755.vsd
IEC05000755 V1 EN
Figure 387: CBM for 2 TRM.
Pos Description
1 CAN slots
2 CPCI slots
en05000756.vsd
IEC05000756 V1 EN
Figure 388: CBM position, rear view.
Pos Description
1 CBM
815
IED hardware
18.2.3 Universal backplane module (UBM)
The Universal Backplane Module (UBM) is part of the IED backplane and is
mounted above the CBM. It connects the Transformer input module (TRM) to the
Analog digital conversion module (ADM) and the Numerical module (NUM).
The Universal Backplane Module connects the CT and VT analog signals from the
transformer input module to the analog digital converter module. The Numerical
processing module (NUM) is also connected to the UBM. The ethernet contact on
the front panel as well as the internal ethernet contacts are connected to the UBM
which provides the signal path to the NUM board.
18.2.3.3 Design
It connects the Transformer input module (TRM) to the Analog digital conversion
module (ADM) and the Numerical module (NUM).
The UBM exists in 2 versions.
• for IEDs with two TRM and two ADM. It has four 48 pin euro connectors and
one 96 pin euro connector, see figure 390
• for IEDs with one TRM and one ADM. It has two 48 pin euro connectors and
one 96 pin euro connector, see figure 391.
The 96 pin euro connector is used to connect the NUM board to the backplane. The
48 pin connectors are used to connect the TRM and ADM.
816
IED hardware
TRM ADM
NUM
AD Data
X1 X2
X3 X4
RS485
X10 X10
Front Ethernet
LHMI connection
port
Ethernet X5
en05000489.vsd
IEC05000489 V1 EN
Figure 389: UBM block diagram.
en05000757.vsd
IEC05000757 V1 EN
Figure 390: UBM for 1 TRM.
en05000758.vsd
IEC05000758 V1 EN
Figure 391: UBM for 2 TRM.
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en05000759.vsd
IEC05000759 V1 EN
Figure 392: UBM position, rear view.
Pos Description
1 UBM
18.2.4 Numeric processing module (NUM)
The Numeric processing module (NUM), is a CPU-module that handles all

protection functions and logic.
For communication with high speed modules, e.g. analog input modules and high
speed serial interfaces, the NUM is equipped with a Compact PCI bus. The NUM
is the compact PCI system card i.e. it controls bus mastering, clock distribution and
receives interrupts.
The NUM, Numeric processing module is a high performance, standard off-the-

shelf compact-PCI CPU module. It is 6U high and occupies one slot. Contact with
the backplane is via two compact PCI connectors and an euro connector.
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The NUM has one PMC slot (32-bit IEEE P1386.1 compliant) and two PC-MIP
slots onto which mezzanine cards such as SLM or LDCM can be mounted.
To reduce bus loading of the compact PCI bus in the backplane the NUM has one
internal PCI bus for internal resources and the PMC/PC-MIP slots and external PCI
accesses through the backplane are buffered in a PCI/PCI bridge.
The application code and configuration data are stored in flash memory using a
flash file system.
The NUM is equipped with a real time clock. It uses a capacitor for power backup
of the real time clock.
No forced cooling is used on this standard module because of the low power
dissipation.
18.2.4.3 Block diagram
Compact
Flash Logic
PMC
connector
PC-MIP
connector
UBM
Memory Ethernet
North
bridge
Backplane
PCI-PCI-
connector
bridge
CPU
en04000473.vsd
IEC04000473 V1 EN
Figure 393: Numeric processing module block diagram
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18.2.5 Power supply module (PSM)
The power supply module is used to provide the correct internal voltages and full
isolation between the terminal and the battery system. An internal fail alarm output
is available.
18.2.5.2 Design
There are two types of the power supply module. They are designed for different
DC input voltage ranges see table 539. The power supply module contains a built-
in, self-regulated DC/DC converter that provides full isolation between the
terminal and the external battery system.
Block diagram
Input connector
Power
Filter supply
Backplane connector
Supervision
99000516.vsd
IEC99000516 V1 EN
Figure 394: PSM Block diagram.

Table 539: PSM - Power supply module
Quantity Rated value Nominal range
Auxiliary dc voltage, EL (input) EL = (24 - 60) V EL ± 20%
EL = (90 - 250) V EL ± 20%
Power consumption 50 W typically -
Auxiliary DC power in-rush < 5 A during 0.1 s -
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18.2.6 Local human-machine interface (Local HMI)

Refer to section "Local HMI" for information.
18.2.7 Transformer input module (TRM)
The transformer input module is used to galvanically separate and transform the
secondary currents and voltages generated by the measuring transformers. The
module has twelve inputs in different combinations of currents and voltage inputs.
Either protection class or metering class CT inputs are available.
Alternative connectors of Ring lug or Compression type can be ordered.
18.2.7.2 Design
The transformer module has 12 input transformers. There are several versions of
the module, each with a different combination of voltage and current input
transformers.
Basic versions:
• 6 current channels and 6 voltage channels

• 12 current channels
• 6 current channels
The rated values and channel type, measurement or protection, of the current inputs
are selected at order.
Transformer input module for measuring should not be used with

current transformers intended for protection purposes, due to
limitations in overload characteristics.
The TRM is connected to the ADM and NUM via the UBM.
For configuration of the input and output signals, refer to section "Signal matrix
for analog inputs SMAI".
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Table 540: TRM - Energizing quantities, rated values and limits for protection transformer
modules
Current Ir = 1 or 5 A (0.2-40) × Ir
Operative range (0-100) x Ir
Permissive overload 4 × Ir cont.

100 × Ir for 1 s *)
Burden < 150 mVA at Ir = 5 A

< 20 mVA at Ir = 1 A
Ac voltage Ur = 110 V 0.5–288 V
Operative range (0–340) V

Permissive overload 420 V cont.
450 V 10 s
Burden < 20 mVA at 110 V
Frequency fr = 50/60 Hz ± 5%
*) max. 350 A for 1 s when COMBITEST test switch is included.
Table 541: TRM - Energizing quantities, rated values and limits for measuring transformer
modules
Current Ir = 1 or 5 A (0-1.8) × Irat Ir = 1 A
(0-1.6) × Irat Ir = 5 A
Permissive overload 1.1 × Ir cont.

1.8 × Ir for 30 min at Ir = 1 A
1.6 × Ir for 30 min at Ir = 5 A
Burden < 350 mVA at Ir = 5 A

< 200 mVA at Ir = 1 A
Ac voltage Ur = 110 V 0.5–288 V
Operative range (0–340) V

Permissive overload 420 V cont.
450 V 10 s
Burden < 20 mVA at 110 V
Frequency fr = 50/60 Hz ± 5%
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18.2.8 Analog digital conversion module, with time

synchronization (ADM)
The Analog/Digital module has twelve analog inputs, 2 PC-MIP slots and 1 PMC
slot. The PC-MIP slot is used for PC-MIP cards and the PMC slot for PMC cards
according to table 542. The OEM card should always be mounted on the ADM
board. The UBM connects the ADM to the transformer input module (TRM).
Table 542: PC-MIP cards and PMC cards

PC-MIP cards PMC cards
LDCM SLM
LR-LDCM OEM 1 ch
MR-LDCM OEM 2 ch
X21-LDCM
IRIG-B
RS485
18.2.8.2 Design
The Analog digital conversion module input signals are voltage and current from
the transformer module. Shunts are used to adapt the current signals to the
electronic voltage level. To gain dynamic range for the current inputs, two shunts
with separate A\D channels are used for each input current. In this way a 20 bit
dynamic range is obtained with a 16 bit A\D converter.
Input signals are sampled with a sampling freqency of 5 kHz at 50 Hz system

frequency and 6 kHz at 60 Hz system frequency.
The A\D converted signals goes through a filter with a cut off frequency of 500 Hz
and are reported to the numerical module (NUM) with 1 kHz at 50 Hz system
frequency and 1,2 kHz at 60 Hz system frequency.
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Channel 1
AD1 Channel 2
Channel 3
Channel 4
AD2
Channel 5
1.2v Channel 6
AD3 Channel 7
Channel 8
Channel 9
AD4 Channel 10
Channel 11
Channel 12
PMC
level shift
PC-MIP
2.5v
PCI to PCI
PC-MIP
en05000474.vsd
IEC05000474 V1 EN
Figure 395: The ADM layout
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18.2.9 Binary input module (BIM)
The binary input module has 16 optically isolated inputs and is available in two
versions, one standard and one with enhanced pulse counting capabilities on the
inputs to be used with the pulse counter function. The binary inputs are freely
programmable and can be used for the input of logical signals to any of the
functions. They can also be included in the disturbance recording and event-
recording functions. This enables extensive monitoring and evaluation of operation
of the IED and for all associated electrical circuits.
18.2.9.2 Design
The Binary input module contains 16 optical isolated binary inputs. The voltage
level of the binary input is selected at order.
For configuration of the input signals, refer to section "Signal matrix for binary
inputs SMBI".
A signal discriminator detects and blocks oscillating signals. When blocked, a

hysteresis function may be set to release the input at a chosen frequency, making it
possible to use the input for pulse counting. The blocking frequency may also be set.
Figure 396 shows the operating characteristics of the binary inputs of the four
voltage levels.
The standard version of binary inputs gives an improved capability to withstand

disturbances and should generally be used when pulse counting is not required.
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[V]
300
176
144
88
72
38
32
19
18
24/30V 48/60V 110/125V 220/250V
xx06000391.vsd
IEC06000391 V1 EN
Figure 396: Voltage dependence for the binary inputs
Guaranteed operation
Operation uncertain
No operation
IEC99000517-ABC V1 EN
This binary input module communicates with the Numerical module (NUM) via
the CAN-bus on the backplane.
The design of all binary inputs enables the burn off of the oxide of the relay contact
connected to the input, despite the low, steady-state power consumption, which is
shown in figure 397 and 398.
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[mA]
30 / 50
1
35 70 [ms]
en07000104-2.vsd
IEC07000104 V2 EN
Figure 397: Approximate binary input inrush current for the two standard
versions of BIM.
[mA]
30
1
3.5 7.0 [ms]
en07000105.vsd
IEC07000105 V1 EN
Figure 398: Approximate binary input inrush current for the BIM version with
enhanced pulse counting capabilities.
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Opto isolated input
Opto isolated input
Process connector Opto isolated input
Opto isolated input
Opto isolated input
Opto isolated input
Opto isolated input

Micro-
Opto isolated input controller
Opto isolated input
Opto isolated input

Memory
Opto isolated input
Backplane connector
Process connector
Opto isolated input
Opto isolated input CAN
Opto isolated input
Opto isolated input
Opto isolated input
99000503.vsd
IEC99000503 V1 EN
Figure 399: Block diagram of the Binary input module.
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Table 543: BIM - Binary input module
Binary inputs 16 -
DC voltage, RL 24/30 V RL ± 20%
48/60 V RL ± 20%
110/125 V RL ± 20%
220/250 V RL ± 20%
Power consumption
24/30 V max. 0.05 W/input -
48/60 V max. 0.1 W/input
110/125 V max. 0.2 W/input
220/250 V max. 0.4 W/input
Counter input frequency 10 pulses/s max -
Oscillating signal discriminator Blocking settable 1–40 Hz
Release settable 1–30 Hz
Table 544: BIM - Binary input module with enhanced pulse counting capabilities
Binary inputs 16 -
48/60 V RL ± 20%
110/125 V RL ± 20%
220/250 V RL ± 20%
Power consumption
24/30 V max. 0.05 W/input -
110/125 V max. 0.2 W/input
220/250 V max. 0.4 W/input
Counter input frequency 10 pulses/s max -
Balanced counter input frequency 40 pulses/s max -
Oscillating signal discriminator Blocking settable 1–40 Hz
Release settable 1–30 Hz
18.2.10 Binary output modules (BOM)
The binary output module has 24 independent output relays and is used for trip
output or any signaling purpose.
18.2.10.2 Design
The binary output module (BOM) has 24 software supervised output relays. Each
pair of relays have a common power source input to the contacts, see figure 400.
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This should be considered when connecting the wiring to the connection terminal
on the back of the IED.
The high closing and carrying current capability allows connection directly to
breaker trip and closing coils. If breaking capability is required to manage fail of
the breaker auxiliary contacts normally breaking the trip coil current, a parallel
reinforcement is required.
For configuration of the output signals, refer to section "Signal matrix for binary
outputs SMBO".
Output module
xx00000299.vsd
IEC00000299 V1 EN
Figure 400: Relay pair example
1 Output connection from relay 1

2 Output signal power source connection
3 Output connection from relay 2
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Relay
Relay
Relay
Relay
Relay
Process connector
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Relay
Backplane connector
Process connector
Relay Micro-
controller
Relay
Relay
CAN
Relay
Relay Memory
Relay
Relay
99000505.vsd
IEC99000505 V1 EN
Figure 401: Block diagram of the Binary Output Module

Table 545: BOM - Binary output module contact data (reference standard: IEC 61810-2)
Function or quantity Trip and Signal relays
Binary outputs 24
Max system voltage 250 V AC, DC
Test voltage across open contact, 1 min 1000 V rms
Current carrying capacity
Continuous 8A
1s 10 A
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Function or quantity Trip and Signal relays

Making capacity at inductive load with L/R>10 ms
0.2 s 30 A
1.0 s 10 A
Breaking capacity for AC, cos j>0.4 250 V/8.0 A
Breaking capacity for DC with L/R < 40 ms 48 V/1 A
110 V/0.4 A
125 V/0.35 A
220 V/0.2 A
250 V/0.15 A
18.2.11 Binary input/output module (IOM)
The binary input/output module is used when only a few input and output channels
are needed. The ten standard output channels are used for trip output or any
signaling purpose. The two high speed signal output channels are used for
applications where short operating time is essential. Eight optically isolated binary
inputs cater for required binary input information.
18.2.11.2 Design
The binary input/output module is available in two basic versions, one with
unprotected contacts and one with MOV (Metal Oxide Varistor) protected contacts.
Inputs are designed to allow oxide burn-off from connected contacts, and increase
the disturbance immunity during normal protection operate times. This is achieved
with a high peak inrush current while having a low steady-state current, see figure
397. Inputs are debounced by software.
Well defined input high and input low voltages ensures normal operation at battery
supply earth faults, see figure 396.
The voltage level of the inputs is selected when ordering.
I/O events are time stamped locally on each module for minimum time deviance
and stored by the event recorder if present.
The binary I/O module, IOM, has eight optically isolated inputs and ten output
relays. One of the outputs has a change-over contact. The nine remaining output
contacts are connected in two groups. One group has five contacts with a common
and the other group has four contacts with a common, to be used as single-output
channels, see figure 402.
The binary I/O module also has two high speed output channels where a reed relay
is connected in parallel to the standard output relay.
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For configuration of the input and output signals, refer to sections "Signal matrix
for binary inputs SMBI" and "Signal matrix for binary outputs SMBO".
The making capacity of the reed relays are limited.
IEC1MRK002801-AA11-UTAN-RAM V1 EN
Figure 402: Binary in/out module (IOM), input contacts named XA corresponds
to rear position X31, X41, and so on, and output contacts named
XB to rear position X32, X42, and so on
The binary input/output module version with MOV protected contacts can for
example be used in applications where breaking high inductive load would cause
excessive wear of the contacts.
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The test voltage across open contact is lower for this version of the
binary input/output module.
xx04000069.vsd
IEC04000069 V1 EN
Figure 403: IOM with MOV protection, relay example

Table 546: IOM - Binary input/output module
Binary inputs 8 -
48/60 V RL ± 20%
110/125 V RL ± 20%
220/250 V RL ± 20%
Power consumption -
110/125 V max. 0.2 W/input
220/250 V max. 0.4 W/input
Table 547: IOM - Binary input/output module contact data (reference standard: IEC 61810-2)
Function or quantity Trip and signal relays Fast signal relays (parallel reed
relay)
Binary outputs 10 2
Max system voltage 250 V AC, DC 250 V AC, DC
Test voltage across open contact, 1000 V rms 800 V DC
1 min
Continuous 8A 8A
1s 10 A 10 A
Making capacity at inductive load
with L/R>10 ms
0.2 s 30 A 0.4 A
1.0 s 10 A 0.4 A
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Function or quantity Trip and signal relays Fast signal relays (parallel reed
relay)
Breaking capacity for AC, cos φ > 250 V/8.0 A 250 V/8.0 A
0.4
Breaking capacity for DC with L/R 48 V/1 A 48 V/1 A
< 40 ms 110 V/0.4 A 110 V/0.4 A
125 V/0.35 A 125 V/0.35 A
220 V/0.2 A 220 V/0.2 A
250 V/0.15 A 250 V/0.15 A
Maximum capacitive load - 10 nF
Table 548: IOM with MOV - contact data (reference standard: IEC 60255-23)
Function or quantity Trip and Signal relays Fast signal relays (parallel
reed relay)
Binary outputs IOM: 10 IOM: 2
Max system voltage 250 V AC, DC 250 V AC, DC
Test voltage across open 250 V rms 250 V DC
contact, 1 min
Continuous 8A 8A
1s 10 A 10 A
Making capacity at inductive
loadwith L/R>10 ms
0.2 s 30 A 0.4 A
1.0 s 10 A 0.4 A
Breaking capacity for AC, cos 250 V/8.0 A 250 V/8.0 A
j>0.4
Breaking capacity for DC with L/ 48 V/1 A 48 V/1 A
R < 40 ms 110 V/0.4 A 110 V/0.4 A
220 V/0.2 A 220 V/0.2 A
250 V/0.15 A 250 V/0.15 A
Maximum capacitive load - 10 nF
18.2.12 mA input module (MIM)
The milli-ampere input module is used to interface transducer signals in the –20 to
+20 mA range from for example OLTC position, temperature or pressure
transducers. The module has six independent, galvanically separated channels.
18.2.12.2 Design
The Milliampere Input Module has six independent analog channels with separated
protection, filtering, reference, A/D-conversion and optical isolation for each input
making them galvanically isolated from each other and from the rest of the module.
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For configuration of the input signals, refer to section "Signal matrix for mA
inputs SMMI".
The analog inputs measure DC current in the range of +/- 20 mA. The A/D
converter has a digital filter with selectable filter frequency. All inputs are
calibrated separately The filter parameters and the calibration factors are stored in a
non-volatile memory on the module.
The calibration circuitry monitors the module temperature and starts an automatical
calibration procedure if the temperature drift is outside the allowed range. The
module communicates, like the other I/O-modules on the serial CAN-bus.
A/D Converter Opto-

Protection isolation
& filter
Volt-ref DC/DC
Process connector
A/D Converter Opto-

& filter
Volt-ref DC/DC
A/D Converter Opto-

& filter
Volt-ref DC/DC
A/D Converter Opto-

& filter
Volt-ref DC/DC
A/D Converter Opto-

& filter
Volt-ref DC/DC
Backplane connector
A/D Converter Opto-

& filter
Volt-ref DC/DC
CAN
Memory Micro-
controller
99000504.vsd
IEC99000504 V1 EN
Figure 404: MIM block diagram
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Table 549: MIM - mA input module
Quantity: Rated value: Nominal range:
Input resistance Rin = 194 Ohm -
Input range ± 5, ± 10, ± 20mA -

0-5, 0-10, 0-20, 4-20mA
Power consumption -
each mA-board £2W
each mA input £ 0.1 W
18.2.13 Serial and LON communication module (SLM)
The serial and LON communication module (SLM) is used for SPA, IEC
60870-5-103, DNP3 and LON communication. The module has two optical
communication ports for plastic/plastic, plastic/glass or glass/glass. One port is
used for serial communication (SPA, IEC 60870-5-103 and DNP3 port or
dedicated IEC 60870-5-103 port depending on ordered SLM module) and one port
is dedicated for LON communication.
18.2.13.2 Design
The SLM is a PMC card and it is factory mounted as a mezzanine card on the
NUM module. Three variants of the SLM is available with different combinations
of optical fiber connectors, see figure 405. The plastic fiber connectors are of snap-
in type and the glass fiber connectors are of ST type.
837
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IEC05000760 V1 EN
Figure 405: The SLM variants, component side view
A Snap in connector for plastic fiber

B ST connector for glass fiber
1 LON port
2 SPA/IEC 60870-5-103/DNP3 port or dedicated IEC 60870-5-103 port depending on
ordered SLM module
IEC05000761 V1 EN
Figure 406: The SLM layout overview, component side view
1 Receiver, LON
2 Transmitter, LON
3 Receiver, SPA/IEC 60870-5-103/DNP3
4 Transmitter, SPA/IEC 60870-5-103/DNP3
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Observe that when the SLM connectors are viewed from the rear
side of the IED, contact 4 above is in the uppermost position and
contact 1 in the lowest position.

Table 550: SLM – LON port
Quantity Range or value
Optical connector Glass fibre: type ST
Plastic fibre: type HFBR snap-in
Fibre, optical budget Glass fibre: 11 dB (1000 m typically *)
Plastic fibre: 7 dB (10 m typically *)
Fibre diameter Glass fibre: 62.5/125 mm
Plastic fibre: 1 mm
*) depending on optical budget calculation
Table 551: SLM – SPA/IEC 60870-5-103/DNP3 port

Quantity Range or value
Optical connector Glass fibre: type ST
Plastic fibre: type HFBR snap-in
Fibre, optical budget Glass fibre: 11 dB (3000ft/1000 m typically *)
Plastic fibre: 7 dB (80ft/25 m typically *)
Fibre diameter Glass fibre: 62.5/125 mm
Plastic fibre: 1 mm
18.2.14 Optical ethernet module (OEM)
The optical fast-ethernet module is used to connect an IED to the communication

buses (like the station bus) that use the IEC 61850-8-1 protocol (port A, B). The
module has one or two optical ports with ST connectors.
The Optical Ethernet module (OEM) is used when communication systems

according to IEC61850–8–1 have been implemented.
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18.2.14.3 Design
The Optical Ethernet module (OEM) is a PMC card and mounted as a mezzanine
card on the ADM. The OEM is a 100base Fx module and available as a single
channel or double channel unit.
PCI - bus Connector
100Base-FX
EEPROM
Transmitter ST fiber optic
Ethernet Controller connectors
100Base-FX
Receiver
PCI - PCI Bridge
100Base-FX
Transmitter
ID chip ST fiber optic
Ethernet Controller
connectors
100Base-FX
EEPROM
IO - bus Connector Receiver
en04000472.vsd
IEC04000472 V1 EN
Figure 407: OEM block diagram.
ID chip
Receiver
IO bus
LED
Ethernet cont.
25MHz oscillator
Transmitter
Receiver
LED
PCI bus
Ethernet cont. PCI to PCI
bridge
25MHz oscillator
Transmitter
en05000472.vsd
IEC05000472 V1 EN
Figure 408: OEM layout, standard PMC format 2 channels

Table 552: OEM - Optical ethernet module
Quantity Rated value
Number of channels 1 or 2
Standard IEEE 802.3u 100BASE-FX
Type of fiber 62.5/125 mm multimode fibre
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Wave length 1300 nm
Optical connector Type ST
Communication speed Fast Ethernet 100 MB
18.2.15 Line data communication module (LDCM)
The line data communication module (LDCM) is used for communication between
the IEDs situated at distances <110 km or from the IED to optical to electrical
converter with G.703 interface located on a distances <3 km away. The LDCM
module sends and rereceives data, to and from another LDCM module. The IEEE/
ANSI standard format is used.
The line data communication module is used for binary signal transfer. The module
has one optical port with ST connectors see figure 409.
Line data communication module LDCM

Each module has one optical port, one for each remote end to which the IED
communicates.
Alternative cards for Medium range (1310 nm single mode) and Short range (850
nm multi mode) are available.
Class 1 laser product. Take adequate measures to protect the eyes.

Never look into the laser beam.
18.2.15.2 Design
The LDCM is a PCMIP type II single width format module. The LDCM can be
mounted on:
• the ADM
• the NUM
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ID
ST
16.000
IO-connector
MHz
32,768
MHz
ST
en07000087.vsd
IEC07000087 V1 EN
Figure 409: The SR-LDCM layout. PCMIP type II single width format with two
PCI connectors and one I/O ST type connector
X1
C
ADN 2.5V
ID
2841
PCI9054
FPGA TQ176
DS DS
256 FBGA
3904 3904
MAX
3645
3
2
en06000393.vsd
IEC06000393 V1 EN
Figure 410: The MR-LDCM and LR-LDCM layout. PCMIP type II single width
format with two PCI connectors and one I/O FC/PC type connector
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Table 553: Line data communication module

Characteristic Range or value
Type of LDCM Short range (SR) Medium range (MR) Long range (LR)
Type of fibre Graded-index Singlemode 9/125 Singlemode 9/125 µm
multimode µm
62.5/125 µm or
50/125 µm
Wave length 850 nm 1310 nm 1550 nm
Optical budget 13 dB (typical 22 dB (typical 26 dB (typical distance 110 km *)
Graded-index distance about 3 distance 80 km *)
multimode 62.5/125 km *)
mm, 9 dB (typical
distance about 2
km *)
Graded-index
multimode 50/125
mm
Optical connector Type ST Type FC/PC Type FC/PC

Protocol C37.94 C37.94 C37.94 implementation **)
implementation **)
Data transmission Synchronous Synchronous Synchronous
Transmission rate / 2 Mb/s / 64 kbit/s 2 Mb/s / 64 kbit/s 2 Mb/s / 64 kbit/s
Data rate
Clock source Internal or Internal or derived Internal or derived from received
derived from from received signal signal
received signal
**) C37.94 originally defined just for multimode; using same header, configuration and data format as
C37.94
18.2.16 GPS antenna
In order to receive GPS signals from the satellites orbiting the earth a GPS antenna
with applicable cable must be used.
18.2.16.2 Design
The antenna with a console for mounting on a horizontal or vertical flat surface or
on an antenna mast. See figure 411
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1 6
4 7
xx04000155.vsd
IEC04000155 V2 EN
Figure 411: Antenna with console
where:
1 GPS antenna
2 TNC connector
3 Console, 78x150 mm
4 Mounting holes 5.5 mm
5 Tab for securing of antenna cable
6 Vertical mounting position
7 Horizontal mounting position
Always position the antenna and its console so that a continuous clear line-of-sight
visibility to all directions is obtained, preferably more than 75%. A minimum of
50% clear line-of-sight visibility is required for un-interrupted operation.
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99001046.vsd
IEC99001046 V1 EN
Figure 412: Antenna line-of-sight
Antenna cable
Use a 50 ohm coaxial cable with a male TNC connector in the antenna end and a
male SMA connector in the receiver end to connect the antenna to GTM. Choose
cable type and length so that the total attenuation is max. 26 dB at 1.6 GHz.
Make sure that the antenna cable is not charged when connected to
the antenna or to the receiver. Short-circuit the end of the antenna
cable with some metal device, when first connected to the antenna.
When the antenna is connected to the cable, connect the cable to the
receiver. REx670 must be switched off when the antenna cable is
connected.

Table 554: GPS – Antenna and cable
Function Value
Max antenna cable attenuation 26 db @ 1.6 GHz
Antenna cable impedance 50 ohm
Lightning protection Must be provided externally
Antenna cable connector SMA in receiver end
TNC in antenna end
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18.2.17 IRIG-B time synchronization module IRIG-B
The IRIG-B time synchronizing module is used for accurate time synchronizing of
the IED from a station clock.
Electrical (BNC) and optical connection (ST) for 0XX and 12X IRIG-B support.
18.2.17.2 Design
The IRIG-B module have two inputs. One input is for the IRIG-B that can handle
both a pulse-width modulated signal (also called unmodulated) and an amplitude
modulated signal (also called sine wave modulated). The other is an optical input
type ST for PPS to synchronize the time between several protections.
32 MHz FPGA
connector
PCI-con
OPTO_INPUT
ST-
PCI-bus
Registers
PCI-Controller
PCI-con
4 mm barrier
IRIG- IRIG_INPUT
connector
Amplitude
ID-chip Decoder
BNC-
modulator
Capture1 Isolated
ZXING
receiver
Zero-cross
Capture2 detector
MPPS
IO-con
PPS
TSU Isolated
DC/DC
CMPPS 5 to +- 12V
en06000303.vsd
IEC06000303 V1 EN
Figure 413: IRIG-B block diagram
846
IED hardware
A1
DC//DC
ST
C
Y2
C
C
A1
C
O
T
3
2
O
en06000304.vsd
IEC06000304 V1 EN
Figure 414: IRIG-B PC-MIP board with top left ST connector for PPS 820 nm
multimode fibre optic signal input and lower left BNC connector for
IRIG-B signal input

Table 555: IRIG-B
Number of channels IRIG-B 1
Number of channels PPS 1
Electrical connector IRIG-B BNC
Optical connector PPS and IRIG-B Type ST
Type of fibre 62.5/125 μm multimode fibre
Pulse-width modulated 5 Vpp
Amplitude modulated
– low level 1-3 Vpp
– high level 3 x low level, max 9 Vpp
847
IED hardware
18.3 Dimensions
18.3.1 Case without rear cover
A
D
B C
xx08000164.vsd
IEC08000164 V1 EN
Figure 415: Case without rear cover
848
IED hardware
K
F
G
H J
xx08000166.vsd
IEC08000166 V1 EN
Figure 416: Case without rear cover with 19” rack mounting kit
Case size (mm) A B C D E F G H J K

6U, 1/2 x 19” 265.9 223.7 201.1 252.9 205.7 190.5 203.7 - 187.6 -
6U, 3/4 x 19” 265.9 336.0 201.1 252.9 318.0 190.5 316.0 - 187.6 -
6U, 1/1 x 19” 265.9 448.3 201.1 252.9 430.3 190.5 428.3 465.1 187.6 482.6
The H and K dimensions are defined by the 19” rack mounting kit
849
IED hardware
18.3.2 Case with rear cover
A
D
B
C
xx08000163.vsd
IEC08000163 V1 EN
Figure 417: Case with rear cover
850
IED hardware
K
F
G
J
H
xx08000165.vsd
IEC08000165 V1 EN
Figure 418: Case with rear cover and 19” rack mounting kit
xx05000503.vsd
IEC05000503 V1 EN
Figure 419: Rear cover case with details
Case size (mm) A B C D E F G H J K

6U, 1/2 x 19” 265.9 223.7 242.1 255.8 205.7 190.5 203.7 - 228.6 -
6U, 3/4 x 19” 265.9 336.0 242.1 255.8 318.0 190.5 316.0 - 228.6 -
6U, 1/1 x 19” 265.9 448.3 242.1 255.8 430.3 190.5 428.3 465.1 228.6 482.6
The H and K dimensions are defined by the 19” rack mounting kit.
851
IED hardware
18.3.3 Flush mounting dimensions
A C
B
E
D
xx08000162.vsd
IEC08000162 V1 EN
Figure 420: Flush mounting
Cut-out dimensions (mm)

Case size
Tolerance A B C D
+/-1 +/-1
6U, 1/2 x 19" 210.1 254.3 4.0-10.0 12.5
6U, 3/4 x 19" 322.4 254.3 4.0-10.0 12.5
6U, 1/1 x 19" 434.7 254.3 4.0-10.0 12.5
E = 188.6 mm without rear protection cover, 229.6 mm with rear protection cover
852
IED hardware
18.3.4 Side-by-side flush mounting dimensions
xx06000182.vsd
IEC06000182 V1 EN
Figure 421: A 1/2 x 19” size 670 series IED side-by-side with RHGS6.
G
D
B
E
F
C
xx05000505.vsd
IEC05000505 V1 EN
Figure 422: Panel-cut out dimensions for side-by-side flush mounting
Case size (mm) A B C D E F G

Tolerance ±1 ±1 ±1 ±1 ±1 ±1 ±1
6U, 1/2 x 19” 214.0 259.3 240.4 190.5 34.4 13.2 6.4 diam
6U, 3/4 x 19” 326.4 259.3 352.8 190.5 34.4 13.2 6.4 diam
6U, 1/1 x 19” 438.7 259.3 465.1 190.5 34.4 13.2 6.4 diam
853
IED hardware
18.3.5 Wall mounting dimensions
B
E
C
D
en04000471.vsd
IEC04000471 V1 EN
Figure 423: Wall mounting
Case size (mm) A B C D E

6U, 1/2 x 19” 292.0 267.1 272.8 390.0 243.0
6U, 3/4 x 19” 404.3 379.4 272.8 390.0 243.0
6U, 1/1 x 19” 516.0 491.1 272.8 390.0 243.0
18.3.6 External resistor unit for high impedance differential

protection
WARNING! - USE EXTREME CAUTION!Dangerously high

voltages might be present on this equipment, especially on the plate
with resistors. Do any maintenance ONLY if the primary object
protected with this equipment is de-energized. If required by
national low/standard enclose the plate with resistors with a
protective cover or in a separate box!
854
IED hardware
[1.48
[6.97]
[4.02] [18.31]
[0.33] [0.79] [7.68]
[18.98]
Dimension
mm [inches] xx06000232.eps
IEC06000232 V1 EN
Figure 424: Dimension drawing of a one phase impedance resistor unit

[1.50]
[10.47]
[7.50]
[0.33] [18.31] [0.79] [7.68]

[18.98]
en06000234.eps
[inches]
IEC06000234 V1 EN
Figure 425: Dimension drawing of a three phase high impedance resistor unit
18.3.7 External current transformer unit

482.6 [19]
89 [3.5]
57 [2.24]
Dimension
mm [inches]
xx06000233.vsd
IEC06000233 V1 EN
Figure 426: Dimension drawing of summation current transformers
855
IED hardware
18.4 Mounting alternatives
18.4.1 Flush mounting
18.4.1.1 Overview
The flush mounting kit are utilized for case sizes:
• 1/2 x 19”
• 3/4 x 19”
• 1/1 x 19”
• 1/4 x 19” (RHGS6 6U)
Only a single case can be mounted in each cut-out on the cubicle panel, for class
IP54 protection.
Flush mounting cannot be used for side-by-side mounted IEDs

when IP54 class must be fulfilled. Only IP20 class can be obtained
when mounting two cases side-by-side in one (1) cut-out.
To obtain IP54 class protection, an additional factory mounted

sealing must be ordered when ordering the IED.
856
IED hardware
18.4.1.2 Mounting procedure for flush mounting
xx08000161.vsd
IEC08000161 V1 EN
Figure 427: Flush mounting details.
PosNo Description Quantity Type

1 Sealing strip, used to obtain IP54 class. The sealing strip is factory - -
mounted between the case and front plate.
2 Fastener 4 -
3 Groove - -
4 Screw, self tapping 4 2.9x9.5 mm
5 Joining point of sealing strip - -
6 Panel - -
857
IED hardware
18.4.2 19” panel rack mounting
18.4.2.1 Overview
All IED sizes can be mounted in a standard 19” cubicle rack by using the for each
size suited mounting kit which consists of two mounting angles and fastening
screws for the angles.
The mounting angles are reversible which enables mounting of IED size 1/2 x 19”
or 3/4 x 19” either to the left or right side of the cubicle.
Please note that the separately ordered rack mounting kit for side-by-
side mounted IEDs, or IEDs together with RHGS cases, is to be
selected so that the total size equals 19”.
When mounting the mounting angles, be sure to use screws that

follows the recommended dimensions. Using screws with other
dimensions than the original may damage the PCBs inside the IED.
858
IED hardware
18.4.2.2 Mounting procedure for 19” panel rack mounting
1a
1b
xx08000160.vsd
IEC08000160 V1 EN
Figure 428: 19” panel rack mounting details
Pos Description Quantity Type

1a, 1b Mounting angels, which can be mounted, either to 2 -
the left or right side of the case.
2 Screw 8 M4x6
18.4.3 Wall mounting
18.4.3.1 Overview
All case sizes, 1/2 x 19”, 3/4 x 19” and 1/1 x 19”, can be wall mounted. It is also
possible to mount the IED on a panel or in a cubicle.
859
IED hardware
When mounting the side plates, be sure to use screws that follows
the recommended dimensions. Using screws with other dimensions
than the original may damage the PCBs inside the IED.
If fiber cables are bent too much, the signal can be weakened. Wall
mounting is therefore not recommended for communication
modules with fiber connection; Serial SPA/IEC 60870-5-103,
DNP3 and LON communication module (SLM), Optical Ethernet
module (OEM) and Line data communication module (LDCM).
18.4.3.2 Mounting procedure for wall mounting
3
4
2
6
xx04000453.vs d
DOCUMENT127716-IMG2265 V1 EN
Figure 429: Wall mounting details.

1 Bushing 4 -
2 Screw 8 M4x10
3 Screw 4 M6x12 or
corresponding
860
IED hardware
4 Mounting bar 2 -
5 Screw 6 M5x8
6 Side plate 2 -
18.4.3.3 How to reach the rear side of the IED
The IED can be equipped with a rear protection cover, which is recommended to
use with this type of mounting. See figure 430.
To reach the rear side of the IED, a free space of 80 mmis required on the unhinged
side.
View from above
3
1
80 mm 2
en06000135.vsd
IEC06000135 V1 EN
Figure 430: How to reach the connectors on the rear side of the IED.
PosNo Description Type

1 Screw M4x10
2 Screw M5x8
3 Rear protection cover -
18.4.4 Side-by-side 19” rack mounting
18.4.4.1 Overview
IED case sizes, 1/2 x 19” or 3/4 x 19” and RHGS cases, can be mounted side-by-
side up to a maximum size of 19”. For side-by-side rack mounting, the side-by-side
mounting kit together with the 19” rack panel mounting kit must be used. The
mounting kit has to be ordered separately.
861
IED hardware
When mounting the plates and the angles on the IED, be sure to use
screws that follows the recommended dimensions. Using screws
with other dimensions than the original may damage the PCBs
inside the IED.
18.4.4.2 Mounting procedure for side-by-side rack mounting
2
1
xx04000456.vsd
IEC04000456 V1 EN
Figure 431: Side-by-side rack mounting details.

1 Mounting plate 2 -
2, 3 Screw 16 M4x6
4 Mounting angle 2 -
18.4.4.3 IED in the 670 series mounted with a RHGS6 case
An 1/2 x 19” or 3/4 x 19” size IED can be mounted with a RHGS (6 or 12
depending on IED size) case. The RHGS case can be used for mounting a test
switch of type RTXP 24. It also has enough space for a terminal base of RX 2 type
for mounting of, for example, a DC-switch or two trip IEDs.
862
IED hardware
1 2
1 2 1 2
1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
5 5 5 5
6 6 6 6
7 7 7 7
8 8 8 8
xx06000180.vsd
IEC06000180 V1 EN
Figure 432: IED in the 670 series (1/2 x 19”) mounted with a RHGS6 case
containing a test switch module equipped with only a test switch
and a RX2 terminal base
18.4.5 Side-by-side flush mounting
18.4.5.1 Overview
It is not recommended to flush mount side by side mounted cases if IP54 is

required. If your application demands side-by-side flush mounting, the side-by-side
mounting details kit and the 19” panel rack mounting kit must be used. The
mounting kit has to be ordered separately. The maximum size of the panel cut out
is 19”.
With side-by-side flush mounting installation, only IP class 20 is

obtained. To reach IP class 54, it is recommended to mount the
IEDs separately. For cut out dimensions of separately mounted
IEDs, see section "Flush mounting".
When mounting the plates and the angles on the IED, be sure to use
screws that follows the recommended dimensions. Using screws
with other dimensions than the original may damage the PCBs
inside the IED.
863
IED hardware
Please contact factory for special add on plates for mounting FT

switches on the side (for 1/2 19" case) or bottom of the relay.
18.4.5.2 Mounting procedure for side-by-side flush mounting
1 2
xx06000181.vsd
IEC06000181 V1 EN
Figure 433: Side-by-side flush mounting details (RHGS6 side-by-side with 1/2 x
19” IED).

1 Mounting plate 2 -
2, 3 Screw 16 M4x6
4 Mounting angle 2 -
18.5 Technical data
18.5.1 Enclosure
Table 556: Case
Material Steel sheet
Front plate Steel sheet profile with cut-out for HMI
Surface treatment Aluzink preplated steel
Finish Light grey (RAL 7035)
864
IED hardware
Table 557: Water and dust protection level according to IEC 60529
Front IP40 (IP54 with sealing strip)

Rear, sides, top and IP20
bottom
Table 558: Weight

Case size Weight
6U, 1/2 x 19” £ 10 kg
6U, 3/4 x 19” £ 15 kg
6U, 1/1 x 19” £ 18 kg
18.5.2 Connection system

Table 559: CT and VT circuit connectors
Connector type Rated voltage and current Maximum conductor area
Screw compression type 250 V AC, 20 A 4 mm2 (AWG12)
2 x 2.5 mm2 (2 x AWG14)
Terminal blocks suitable for 250 V AC, 20 A 4 mm2 (AWG12)
ring lug terminals
Table 560: Binary I/O connection system

Connector type Rated voltage Maximum conductor area
Screw compression type 250 V AC 2.5 mm2 (AWG14)
2 × 1 mm2 (2 x AWG18)
Terminal blocks suitable for 300 V AC 3 mm2 (AWG14)
ring lug terminals
Because of limitations of space, when ring lug terminal is ordered

for Binary I/O connections, one blank slot is necessary between two
adjacent IO cards. Please refer to the ordering particulars for details.
18.5.3 Influencing factors

Table 561: Temperature and humidity influence
Parameter Reference value Nominal range Influence
Ambient temperature, +20 °C -10 °C to +55 °C 0.02% /°C
operate value
Relative humidity 10%-90% 10%-90% -
Operative range 0%-95%
Storage temperature -40 °C to +70 °C - -
865
IED hardware
Table 562: Auxiliary DC supply voltage influence on functionality during operation

Dependence on Reference value Within nominal range Influence
Ripple, in DC auxiliary voltage max. 2% 15% of EL 0.01% /%
Operative range Full wave rectified
Auxiliary voltage dependence, operate ± 20% of EL 0.01% /%
value
Interrupted auxiliary DC voltage 24-60 V DC ± 20%
90-250 V DC ± 20%
Interruption
interval
0–50 ms No restart
0–∞ s Correct
behaviour at
power down
Restart time <180 s
Table 563: Frequency influence (reference standard: IEC 60255–1)

Dependence on Within nominal range Influence
Frequency dependence, fr ± 2.5 Hz for 50 Hz ± 1.0% / Hz
operate value fr ± 3.0 Hz for 60 Hz
Harmonic frequency 2nd, 3rd and 5th harmonic of fr ± 1.0%

dependence (20%
content)
Harmonic frequency 2nd, 3rd and 5th harmonic of fr ±5.0%
dependence for high
impedance differential
protection (10% content)
18.5.4 Type tests according to standard

Table 564: Electromagnetic compatibility
Test Type test values Reference standards
1 MHz burst disturbance 2.5 kV IEC 60255-22-1
100 kHz slow damped 2.5 kV IEC 61000-4-18, Class III
oscillatory wave immunity
test
Ring wave immunity test, 2-4 kV IEC 61000-4-12, Class IV
100 kHz
Surge withstand capability 2.5 kV, oscillatory IEEE/ANSI C37.90.1
test 4.0 kV, fast transient
Electrostatic discharge 15 kV air discharge IEC 60255-22-2, Class IV
Direct application 8 kV contact discharge
Indirect application 8 kV contact discharge IEC 61000-4-2, Class IV
Electrostatic discharge 15 kV air discharge IEEE/ANSI C37.90.1
Indirect application 8 kV contact discharge
Fast transient disturbance 4 kV IEC 60255-22-4, Class A
866
IED hardware

Surge immunity test 1-2 kV, 1.2/50 ms IEC 60255-22-5
high energy
Power frequency immunity 150-300 V, 50 Hz IEC 60255-22-7, Class A
test
Conducted common mode 15 Hz-150 kHz IEC 61000-4-16, Class IV
immunity test
Power frequency magnetic 1000 A/m, 3 s IEC 61000-4-8, Class V
field test 100 A/m, cont.
Damped oscillatory magnetic 100 A/m IEC 61000-4-10, Class V
field test
Radiated electromagnetic 20 V/m, 80-1000 MHz IEC 60255-22-3
field disturbance
1.4-2.7 GHz
Radiated electromagnetic 35 V/m IEEE/ANSI C37.90.2
field disturbance 26-1000 MHz
Conducted electromagnetic 10 V, 0.15-80 MHz IEC 60255-22-6
field disturbance
Radiated emission 30-1000 MHz IEC 60255-25
Conducted emission 0.15-30 MHz IEC 60255-25
Table 565: Insulation

Test Type test values Reference standard
Dielectric test 2.0 kV AC, 1 min. IEC 60255-5
Impulse voltage test 5 kV, 1.2/50 ms, 0.5 J
Insulation resistance >100 MW at 500 VDC
Table 566: Environmental tests

Test Type test value Reference standard
Cold test Test Ad for 16 h at -25°C IEC 60068-2-1
Storage test Test Ad for 16 h at -40°C IEC 60068-2-1
Dry heat test Test Bd for 16 h at +70°C IEC 60068-2-2
Damp heat test, steady state Test Ca for 4 days at +40 °C IEC 60068-2-78
and humidity 93%
Damp heat test, cyclic Test Db for 6 cycles at +25 IEC 60068-2-30
to +55 °C and humidity 93 to
95% (1 cycle = 24 hours)
Table 567: CE compliance

Test According to
Immunity EN 50263
Emissivity EN 50263
Low voltage directive EN 50178
867
IED hardware
Table 568: Mechanical tests

Vibration response test Class II IEC 60255-21-1
Vibration endurance test Class I IEC 60255-21-1
Shock response test Class II IEC 60255-21-2
Shock withstand test Class I IEC 60255-21-2
Bump test Class I IEC 60255-21-2
Seismic test Class II IEC 60255-21-3
868
Injection equipment hardware
Section 19 Injection equipment hardware
This chapter describes the hardware equipment used for sensitive rotor earth fault
protection and 100% stator earth fault protection by injection. The descriptions
includes diagrams from different elevations indicating the location of connection
terminals and modules as well as dimensions and drilling plan.
19.1 Overview
19.1.1 Front view of injection unit, coupling capacitor and shunt

resitor unit
19.1.1.1 REX060 Injection unit
The purpose of the injection unit REX060 is to protect the stator and the rotor of a
generator against an earth fault by injection of a voltage signal to the neutral point
of the generator or VT open delta secondary (100 % stator earth fault protection)
and to the exciter point of the field circuit (rotor earth fault protection).
For local operation, the REX060 unit is provided with a control panel on the front.
Local operation shall only be performed according to the operation

regulations set up by the relevant operation authority of the plant.
869
19.1.1.2 REX060 Front panel controls
IEC11000053 V1 EN
Figure 434: REX060 front panel
870
Table 569: HMI keys on the front of the injection unit REX060
Key Function
The Injection switch enables injection at rotor and stator 2
s after switching on. A LED indicates that the injection
switch is set to enable injection. The injection switch can
be padlocked in off position in order to cut-off both
injection signals.
The Key-lock button enables/disables the keypad.

Hold the Key-lock button for a period of 1.2 s to 4 s to lock
or unlock the keys. A key-lock LED indicates when the
keypad is unlocked.
• Moves the cursor in the direction of the arrows

• With the cursor is in value change state, pressing
the up button increases the value and pressing the
down button decreases the value.
Pressing the clear button cancels changes that have not

been stored.
Pressing the enter button stores the changed value. If the

value is outside range, the limit value is stored.
19.1.1.3 Coupling capacitor unit REX061
X1 X2
IEC11000019 V1 EN
Figure 435: Coupling capacitor unit REX061
871
IEC11000037 V1 EN
Figure 436: Measure and drilling plan
REX061 shall be mounted close to the generator in order to limit the exposure of
the field circuit. Alternatively it can be located in the excitation cubicle.
19.1.1.4 Shunt resistor unit REX062
X1
IEC11000038 V1 EN
Figure 437: Shunt resistor unit REX062
872
IEC11000039 V1 EN
Figure 438: REX062 measures and drilling plan
REX062 shall be mounted close to the IED. It is recommended that REX060 and
REX062 are mounted in the same cubicle as the IED.
19.1.2 Injection unit REX060 from rear side
19.1.2.1 Injection unit REX060
IED and
Injection Power
connectors Top view connector Back view Front view
X11 X61 X81

1 1 1
5
Stator Injection
Power Supply
Rotor Injection
18 18
X62 X82
1 1
5 5
Power
Stator
Rotor
BackPlane
Front-plate Injection switch

HMI and Logic
IEC11000018 V1 EN
Figure 439: Rear and top view of injection unit REX060
873
19.2 Injection unit REX060
19.2.1 Introduction
The injection unit REX060 is used to inject voltage and current signals to the
generator or motor stator and rotor circuits. REX060 generates two square wave
signals with different frequencies for injection into the stator and rotor circuits
respectively. The response from the injected voltage and currents are then
measured by the REX060 unit and amplified to a level suitable for the analog
voltage inputs of IED.
19.2.2 Design
REX060 consists of a standard enclosure (6U, 1/2 x 19"). In this enclosure, the
modules for stator (SIM) and/or rotor (RIM) earth fault protection are installed.
The stator injection transformer is also installed inside the enclosure.
On the front of the enclosure there is a backlit LCD, control buttons and a key switch.
In figure 440 below the content of display is shown for a REX060 with one SIM
and one RIM module. Row 1 contains mains frequency information. Row 2-3
contains stator information and row 4-5 rotor. Column 1 (empty) gives status,
column 2 and 3 are informative and column 4 contains variables, settable by the
keypad.
Column
Row 1 2 3 4
1 System f [Hz] : 50
2 STATOR f [Hz] : 087
3 UmaxEF [V] : 120
4 ROTOR f [Hz] : 113

5 Gain 4
IEC10000334 V1 EN
Figure 440: Normal display content
When the injection unit REX060 is energized, the ABB logotype is shown
followed by current REX060 revision status. When the start up sequence is
completed, the main menu (normal display content) is shown. The duration of the
start up sequence is a few seconds.
874
LCD backlight is active during a period of 30 seconds after pressing any button.
Backlight activation by pressing a button will not cause any normal button action.
Column 1 is a status column (empty in the above picture), where the following
symbols are displayed when applicable:
Table 570: Status symbols and their description

Status symbol Description of the status Priority
Over voltage occurred, injection is blocked. This can occur on
both X61/62 and X81/82 (Stator & Rotor) simultaneously or on
IEC10000329 V1 EN
either of them. The symbol is displayed in the status column 1
(column 1) in row 2 for X61/62 and in row 4 for X81/82. The
injection is blocked until a manual reset of the blocking occurs.
Injection blocked by the injection switch. The symbol is displayed 2
in the status column (column 1) and is always shown in both row Over voltage
IEC10000330 V1 EN
2 and 4. blocked status
overrides
displaying of
this status
Injection blocked by binary input. Blocked injection will be shown 3
in the status column (column 1) depending on binary in status. Injection
This can occur on both X61/62 then shown in row 2 and X81/82 switch and
then shown in row 4 (Stator & Rotor) simultaneously or on ether over voltage
Ø
of them. blocked
overrides
displaying of
this status
Analog output saturation. This status is set when the analog Not applicable
signal, current and or voltage, to REG670 IED is too high and
IEC10000332 V1 EN may thereby be incorrect due to saturation in amplifier stage.
Saturation status will be shown in the status column (column 1)
in row 3 or 5 depending on the saturation occurrence
Overvoltage reset
Stator module (SIM) and rotor module (RIM) injection outputs are protected
against voltages exceeding maximum operating range (10% of rated VT/DT for the
stator and 75 % of max voltage during gain dependent time for the rotor) by a relay
blocking the injection circuit. This blocking is controlled by measuring the sense
voltage, and remains blocked by stored status in non-volatile memory. Injection
block is released by performing the following sequence:
1. Power off the REX060
2. Simultaneous press the C and key buttons
3. Power on the REX060 and wait until status indication Over-voltage is
removed from display
Stator and rotor overvoltage protection of injection circuit
Both rotor and stator have two levels of protection, injection circuit interruption
controlled by the voltage sense input and a fuse for over-current protection. The
voltage controlled interruption, overvoltage, will normally occur prior to
interruption by fuse and the reset sequence is described above. A blown fuse
875
requires module disassembling to replace the fuse (F 4 A 250 V for stator and F
160 mA 250 V for rotor). However, if this occurs it is recommended to identify the
reason for the over-current and take necessary actions to reduce the current before
restarting the unit. The problem must be outside the injection unit since this unit
cannot provide enough energy to blow the fuse.
Saturation
When the voltage or current amplifiers in an injection module saturates due to high
voltage level, it is indicated with a warning symbol in the status column in the
REX060 display . Besides this a binary out for the specific module is set active to
indicate to the IED that the signal may not be reliable due to saturation and could
cause incorrect measurements.
Binary in
The injection can be blocked by application in the IED. For this purpose, two
binary inputs to the REX060 exist:
• BLOCK on X61 terminal 1, 2 or 3: Prohibits injection on the injection unit
inserted in X62
• BLOCK on X81 terminal 1, 2 or 3: Prohibits injection on the injection unit
inserted in X82
The used terminal is depending on actual binary voltage, pin 1 for 220 V, 2 for 110
V, 3 for 48 V and 4 for return (common).
Binary out
The following binary outputs exist on the REX060:

• INJ_BLOCKED_NC on X61 terminal 5:
Indicates to the IED that the injection on X62 is blocked. The reason for
blocking is indicated in the REX060 LCD.
• SAT_NO on X61 pin 6:
Indicates to the IED that there is a risk of saturated amplifier on voltage and/or
current output at X61, indication is also given in the REX060 LCD.
• COMMON on X61 terminal 7:
Common return for X61 terminal 5 and 6
• INJ_BLOCKED_NC on X81 pin 5:
Indicates to the IED that the injection on X82 is blocked. The reason for
blocking is indicated in the REX060 LCD.
• SAT_NO on X81 pin 6:
Indicates to the IED that there is a risk of saturated amplifier on voltage and/or
current output at X81, indication is also given in the REX060 LCD.
• COMMON on X81 terminal 7:
Common return for X81 terminal 5 and 6
Power status
• X11 terminal 3:
876
Fail, power off NC

• X11 terminal 1:
Ready, power off NO
• X11 terminal 2:
Common
19.3 Coupling capacitor unit REX061
19.3.1 Introduction
REX061 isolates the injection circuit from the rotor exciter voltage.
The REX061 coupling capacitor unit grounding point and grounding brush of the
rotor shaft should be properly interconnected.
19.3.2 Design
Measure points are added to the capacitor box that enables the measuring of rotor
voltages without any connection to a hazardous voltage, by the use of protective
impedance. This enables the usage of standard oscilloscope or handheld DVM.
The measure ports cause an additional rotor impedance of 20 MΩ

per terminal to ground. However, the rotor calibration procedure
extracts this impedance.
877
REX061
Coupling Capacitor unit
Measuring point +
Ground (measuring)
Rotor+
Injection
Ground (injection)
Rotor-
Measuring point-
PE
IEC11000040 V1 EN
Figure 441: REX062 principle design
19.4 Shunt resistor unit REX062
19.4.1 Introduction
REX062 is typically used when injection is done via a grounding transformer.
19.4.2 Design
REX062 for stator protection is used when either injection via a grounding
transformer (i.e. not via a VT) is used or when maximum voltage posed on
injection equipment by the generator is bigger than 120V.
878
REX062
Shunt Resistor unit
Injection A External A
Fuse
Injection B External B
I sense A
PE
I sense B
IEC11000041 V1 EN
Figure 442: REX062 Principal design
REX062 input protection
REX062 limits overvoltage by a varistor at the injection output to stator.

Normally , REX060 will interrupt the injection circuit in case of excessive over-
current in the injection chain. Fuse within REX062 is an additional protection in
case of failure within REX062 during over-voltage condition.
A blown REX062 fuse requires a module disassembling to replace the fuse (F 6.3
A 250 V). However, if this occurs it is recommended to identify the reason for the
over-current and do needed actions to reduce the current.
REX060 REG670
Injection unit X11:4 +
EL
Power Supply Module X11:5 -
Exciter REX061
Coupling Capacitor unit Ready; X11:1 BI
source
Common; X11:2 RL+
X1:1; Rotor + Fail; X11:3 (BI)
Rotor X82:1; InjA Rotor Module (RIM)
Injection; X1:9 X82:3; InjA Block 220V; X81:1
Block 110V; X81:2 BO
Ground; X1:10 X82:4; InjB
Block 48V; X81:3
X1:7; Rotor - X82:5; InjB Block Common; X81:4 RL-
X82:2; InjShB
PE
I Out; X81:10
X81:16; IA sense
A
X81:14; IA sense I Out; X81:11

B
X81:15; IB sense
U Out; X81:8
A
X81:12; UA sense
U Out; X81:9
B
X81:13; UB sense
Blocked; X81:5 BI
Saturation; X81:6 BI
REX062 Common; X81:7 RL+
Shunt Resistor unit Stator Module (SIM)
X62:1; InjExtA
X1:2; Injection A External A; X1:9 X62:3; InjA Block 220V; X61:1
Block 110V; X61:2 BO
R X1:4; Injection B External B; X1:10 X62:4; InjB
Stator Block 48V; X61:3
I sense A; X1:6 X62:5; InjB Block Common; X61:4 RL-
Distribution X62:2; InjExtB
Transformer I sense B; X1:8
PE X61:14; IA sense I Out; X61:10
A
AI (U), current measure

X61:15; IB sense I Out; X61:11
B
X61:12; UA sense U Out; X61:8

A
AI (U), voltage measure
X61:13; UB sense U Out; X61:9
B
Blocked; X61:5 BI
Saturation; X61:6 BI
PE Common; X61:7 RL+ PE
IEC11000017 V1 EN
Figure 443: Example installation when REX062 unit is required
879
19.5 Technical data
19.5.1 Hardware
Table 571: REX060 Technical data
Specifications Values
Case size 6U, 1/2 19”; 223.7 x 245 x 267 mm (W x D x H)
Weight 8.0 kg
Firmware 1p0r00, loaded in the HMI & Logic module

Function Range or values Accuracy
For machines with:
• rated field voltage up to 800 V DC -
• static exciter with rated 1600 V 50/60 Hz -

supply voltage up to
Case size 218 x 150 x 243 mm (W x D x H)
Weight 4.8 kg
Assembling 6 x 5 mm screws (3 at bottom and 3 at top)

Case size 218 x 150 x 243 mm (W x D x H)
Weight 4.5 kg
Assembling 6 x 5 mm screws (3 at bottom and 3 at top)
Table 574: Degree of protection

Description Values
REX060
Front side IP40
Panel mounted, front IP54
Rear side, connection terminals IP20
REX061 and REX062
Front and side IP41
Bottom side IP20
880
19.5.2 Type tests according to standards

Table 575: Electromagnetic compatibility tests
1 MHz burst disturbance 2.5 kV IEC 60255-22-1
100 kHz slow damped 2.5 kV IEC 61000-4-18, Class III
oscillatory wave immunity
test
Surge withstand capability 2.5 kV, oscillatory IEEE/ANSI C37.90.1
test 4.0 kV, fast transient
Electrostatic discharge 15 kV air discharge IEC 60255-22-2, Class IV
Indirect application 8 kV contact discharge IEC 61000-4-2, Class IV
Electrostatic discharge 15 kV air discharge IEEE/ANSI C37.90.3
Indirect application 8 kV contact discharge
Fast transient disturbance 4 kV IEC 60255-22-4, Class A
test
Surge immunity test 1-2 kV, and 2-4 kV, 1.2/50 µs IEC 60255-22-5
High energy
Power frequency immunity 150-300 V, 50 Hz IEC 60255-22-7, Class A
test
Power frequency magnetic 1000 A/m, 3 s IEC 61000-4-8, Class 5
field test 100 A/m, cont.
Radiated electromagnetic 20 V/m, 80-1000 MHz IEC 60255-22-3
field disturbance test 1.4-2.7 GHz
Radiated electromagnetic 20 V/m, 80-1000 MHz IEEE/ANSI C37.90.2
field disturbance test
Conducted electromagnetic 10 V, 0.15-80 MHz IEC 60255-22-6
field disturbance test
Voltage dips and short Dips: IEC 60255-11
interruptions 40% /200 ms
70% /500 ms
Interruptions:
0-50 ms: No restart
0… ∞ s: Correct behaviour at
power down
Radiated emission 30-1000 MHz IEC 60255-25
Conducted emission 0.15-30 MHz IEC 60255-25
Table 576: Insulation tests, REX060, REX062 and REG670

Dielectric test 2.0 kV AC, 1 min IEC 60255-5
Impulse voltage test 5.0 kV, 1.2/50 µs, 0.5 J IEC 60255-5
Insulation resistance >100 MΩ at 500V DC IEC 60255-5
881
Table 577: Insulation tests, REX061

Dielectric test 7.48 kV DC, 1min IEEE 421.3
(connections to rotor)
2.8 kV DC, 1 min IEC 60255-5

Impulse voltage test 12.0 kV, 1.2/50 µs, 0.5 J IEC 60664-1
(connections to rotor)
5.0 kV, 1.2/50 µs, 0.5 J

IEC 60255-5
Insulation resistance >100 MΩ at 500V DC IEC 60255-5
Table 578: Mechanical tests

Test Reference standards Requirements
Vibration response test IEC 60255-21-1 Class 2
Vibration endurance test IEC 60255-21-1
REG670 and REX060 Class 1
REX061 and REX062 Class 2
Shock response test IEC 60255-21-2 Class 2
Shock withstand test IEC 60255-21-2
Bump test IEC 60255-21-2
Seismic test IEC 60255-21-3
REX061 and REX062 Class 2 extended
Table 579: Environmental tests

Test Type test value Reference standard
Cold test IEC 60068-2-1
operation 16 h at -25°C
storage 16 h at -40°C
Dry heat test IEC 60068-2-2
operation 16 h at +70°C
storage 16 h at +85°C
Damp heat test IEC 60068-2-78
steady state 240 h at +40ºC IEC 60068-2-30
humidity 93%
cyclic 6 cycles at +25 to +55ºC
humidity 93-95%
882
19.5.3 Influencing factors

Table 580: Auxiliary DC supply voltage influence
Test Type test values Influence
Auxiliary voltage dependence, ±20% of EL 0.01% /°C
operate value
Ripple in DC auxiliary voltage, 15% of EL 0.01% /°C
operate value
Table 581: Temperature influence

Test Type test values Influence
Ambient temperature, operate -25° C to +55°C 0.01% /°C
value
Storage temperature -40° C to +85°C -
883
884
Labels
Section 20 Labels
About this chapter

This chapter includes descriptions of the different labels and where to find them.
20.1 Labels on IED
Front view of IED
2
3
6
6 5
7
xx06000574.ep
IEC06000574 V1 EN
885
Labels
1 Product type, description and serial number

2 Order number, dc supply voltage and rated
frequency
3 Optional, customer specific information
4 Manufacturer
5 Transformer input module, rated currents
and voltages
6 Transformer designations
IEC06000577-CUSTOMER-SPECIFIC V1 EN
7 Ordering and serial number
IEC06000576-POS-NO V1 EN
886
Labels
Rear view of IED
4
en06000573.ep
IEC06000573 V1 EN
1 Warning label
2 Caution label
3 Class 1 laser product label
IEC06000575 V1 EN
4 Warning label
887
Labels
20.2 Labels on injection equipment
Front view of injection unit REX060
IEC11000226 V1 EN
1a Product type, description and

1a serial number
1b 1b Order number and dc supply

voltage
1c Stator and rotor input module
designations
1c
1d Manufacturer
1d
IEC11000233 V1 EN
2 Ordering and serial number

2
IEC11000234 V1 EN
888
Labels
Rear view of injection unit REX060
IEC11000227 V1 EN
1 Warning label
2 Caution label
3 ESD label
4 Warning label
Front view of coupling capacitor unit REX061
IEC11000229 V1 EN
1 Warning label (hot surface)

2 Ordering number
889
Labels
Rear view of coupling capacitor unit REX061
IEC11000228 V1 EN
1 Warning label
2 Caution label
3 ESD label
4 Warning label
Front view of shunt resistor unit REX062
IEC11000231 V1 EN
1 Warning label (hot surface)

2 Ordering number
890
Labels
Rear view of shunt resistor unit REX062
IEC11000230 V1 EN
1 Warning label
2 Caution label
3 ESD label
4 Warning label
891
892
Connection diagrams
Section 21 Connection diagrams
This chapter includes diagrams of the IED with all slot, terminal block and optical
connector designations. It is a necessary guide when making electrical and optical
connections to the IED.
893
Connection diagrams
1MRK002801-AC 1 V1 EN
894
Connection diagrams
1MRK002801-AC 2 670 1.2 V1 EN
895
Connection diagrams
1MRK002801-AC 3 670 1.2 V1 EN
896
Connection diagrams
1MRK002801-AC 4 670 1.2 V1 EN
897
Connection diagrams
1MRK002801-AC 5 670 1.2 V1 EN
898
Connection diagrams
1MRK002801-AC 6 670 1.2 V1 EN
899
Connection diagrams
1MRK002801-AC 7 670 1.2 V1 EN
900
Connection diagrams
1MRK002801-AC 8 670 1.2 V1 EN
901
Connection diagrams
1MRK002801-AC 9 670 1.2 V1 EN
902
Connection diagrams
1MRK002801-AC 10 670 1.2 V1 EN
903
Connection diagrams
1MRK002801-AC 11 670 1.2 V1 EN
904
Connection diagrams
1MRK002801-AC 12 670 1.2 V1 EN
905
Connection diagrams
1MRK002801-AC 13 670 1.2 V1 EN
906
Connection diagrams
1MRK002801-AC 14 670 1.2 V1 EN
907
Connection diagrams
1MRK002801-AC 15 670 1.2 V1 EN
908
Connection diagrams
21.1 Injection equipment
Injection unit REX060
1MRK002501-BA 1 V1 EN
909
Connection diagrams
1MRK002501-BA 2 V1 EN
910
Connection diagrams
1MRK002501-BA 3 V1 EN
911
Connection diagrams
1MRK002501-BA 4 V1 EN
912
Connection diagrams
1MRK002501-BA 5 V1 EN
913
Connection diagrams
Coupling capacitor unit REX061
1MRK002551-BA 1 V1 EN
914
Connection diagrams
1MRK002551-BA 2 V1 EN
915
Connection diagrams
Shunt resistor unit REX062
1MRK002556-BA 1 V1 EN
916
Connection diagrams
1MRK002556-BA 2 V1 EN
917
Connection diagrams
Overview of connection diagram for Generator protection with

Injection unit
1MRK002504-AA V1 EN
918
Connection diagrams
Generator protection REG670 with Injection unit REX060
1MRK002504-BA 1 V1 EN
919
Connection diagrams
1MRK002504-BA 2 V1 EN
920
Connection diagrams
1MRK002504-BA 3 V1 EN
921
Connection diagrams
1MRK002504-BA 4 V1 EN
922
Connection diagrams
1MRK002504-BA 5 V1 EN
923
Connection diagrams
Injection unit REX060 with Coupling capacitor unit REX061
1MRK002504-CA 1 V1 EN
924
Connection diagrams
1MRK002504-CA 2 V1 EN
925
Connection diagrams
1MRK002504-CA 3 V1 EN
926
Connection diagrams
1MRK002504-CA 4 V1 EN
927
Connection diagrams
Injection unit REX060 and optional Shunt resistor unit REX062
1MRK002504-DA 1 V1 EN
928
Connection diagrams
1MRK002504-DA 2 V1 EN
929
Connection diagrams
1MRK002504-DA 3 V1 EN
930
Connection diagrams
1MRK002504-DA 4 V1 EN
931
Connection diagrams
1MRK002504-DA 5 V1 EN
932
Connection diagrams
1MRK002504-DA 6 V1 EN
933
Connection diagrams
1MRK002504-DA 7 V1 EN
934
Inverse time characteristics
Section 22 Inverse time characteristics
About this chapter

This chapter describes current and voltage dependant time functionality. Both
ANSI and IEC Inverse time curves and tables are included.
22.1 Application
In order to assure time selectivity between different overcurrent protections at

different points in the network different time delays for the different protections are
normally used. The simplest way to do this is to use definite time-lag. In more
sophisticated applications current dependent time characteristics are used. Both
alternatives are shown in a simple application with three overcurrent protections
operating in series.
I> I> I>

xx05000129.vsd
IEC05000129 V1 EN
Figure 444: Three overcurrent protections operating in series
Stage 3
Time
Stage 2 Stage 2
Stage 1 Stage 1 Stage 1
Fault point
position
en05000130.vsd
IEC05000130 V1 EN
Figure 445: Definite time overcurrent characteristics
935
Time
Fault point
position
en05000131.vsd
IEC05000131 V1 EN
Figure 446: Inverse time overcurrent characteristics with inst. function
The inverse time characteristic makes it possible to minimize the fault clearance
time and still assure the selectivity between protections.
To assure selectivity between protections there must be a time margin between the
operation time of the protections. This required time margin is dependent of
following factors, in a simple case with two protections in series:
• Difference between pickup time of the protections to be co-ordinated

• Opening time of the breaker closest to the studied fault
• Reset times of the protections
• Margin dependent of the time delay inaccuracy of the protections
Assume we have the following network case.
936
A1 B1
Feeder
I> I>
Time axis
t=0 t=t1 t=t2 t=t3
en05000132.vsd
IEC05000132 V1 EN
Figure 447: Selectivity steps for a fault on feeder B1
where:
t=0 is The fault occurs
t=t1 is Protection B1 trips
t=t2 is Breaker at B1 opens
t=t3 is Protection A1 resets
In the case protection B1 shall operate without any intentional delay

(instantaneous). When the fault occurs the protections start to detect the fault
current. After the time t1 the protection B1 send a trip signal to the circuit breaker.
The protection A1 starts its delay timer at the same time, with some deviation in
time due to differences between the two protections. There is a possibility that A1
will start before the trip is sent to the B1 circuit breaker. At the time t2 the circuit
breaker B1 has opened its primary contacts and thus the fault current is interrupted.
The breaker time (t2 - t1) can differ between different faults. The maximum
opening time can be given from manuals and test protocols. Still at t2 the timer of
protection A1 is active. At time t3 the protection A1 is reset, that is the timer is stopped.
In most applications it is required that the times shall reset as fast as possible when
the current fed to the protection drops below the set current level, the reset time
shall be minimized. In some applications it is however beneficial to have some type
of delayed reset time of the overcurrent function. This can be the case in the
following applications:
937
• If there is a risk of intermittent faults. If the current IED, close to the faults,
starts and resets there is a risk of unselective trip from other protections in the
system.
• Delayed resetting could give accelerated fault clearance in case of automatic
reclosing to a permanent fault.
• Overcurrent protection functions are sometimes used as release criterion for
other protection functions. It can often be valuable to have a reset delay to
assure the release function.
22.2 Principle of operation
22.2.1 Mode of operation

The function can operate in a definite time-lag mode or in a current definite inverse
time mode. For the inverse time characteristic both ANSI and IEC based standard
curves are available. Also programmable curve types are supported via the
component inputs: p, A, B, C pr, tr, and cr.
Different characteristics for reset delay can also be chosen.
If current in any phase exceeds the set start current value (here internal signal
startValue), a timer, according to the selected operating mode, is started. The
component always uses the maximum of the three phase current values as the
current level used in timing calculations.
In case of definite time-lag mode the timer will run constantly until the time is
reached or until the current drops below the reset value (start value minus the
hysteresis) and the reset time has elapsed.
For definite time delay curve ANSI/IEEE Definite time or IEC Definite time are
chosen.
The general expression for inverse time curves is according to equation 149.
æ ö
ç A
÷
t[ s ] = ç + B ÷×k
ç æ i öp ÷
çç ÷ -C ÷
è è in > ø ø
where:
p, A, B, C are constants defined for each curve type,
in> is the set start current for step n,
k is set time multiplier for step n and
i is the measured current.
938
For inverse time characteristics a time will be initiated when the current reaches the
set start level. From the general expression of the characteristic the following can
be seen:
ææ i öp ö
(top - B × k ) × ç ç ÷ - C ÷ = A×k
è è in > ø ø
where:
top is the operating time of the protection
The time elapsed to the moment of trip is reached when the integral fulfils
according to equation 151, in addition to the constant time delay:
t
ææ i öp ö
ò ç çè in > ÷ø - C ÷ × dt ³ A × k
0 è ø
For the numerical protection the sum below must fulfil the equation for trip.
n æ æ i( j ) ö p ö
Dt × å ç ç ÷ - C ÷ ³ A× k
j =1 è è in > ø ø
where:
j=1 is the first protection execution cycle when a fault has been
detected, that is, when
i
>1
in >
EQUATION1193 V1 EN
Dt is the time interval between two consecutive executions of the

protection algorithm,
n is the number of the execution of the algorithm when the trip
time equation is fulfilled, that is, when a trip is given and
i (j) is the fault current at time j
For inverse time operation, the inverse time characteristic is selectable. Both the
IEC and ANSI/IEEE standardized inverse time characteristics are supported.
For the IEC curves there is also a setting of the minimum time-lag of operation, see
figure 448.
939
Operate
time
tMin
Current
IMin
IEC05000133 V2 EN
Figure 448: Minimum time-lag operation for the IEC curves
In order to fully comply with IEC curves definition setting parameter tMin shall be
set to the value which is equal to the operating time of the selected IEC inverse
time curve for measured current of twenty times the set current start value. Note
that the operating time value is dependent on the selected setting value for time
multiplier k.
In addition to the ANSI and IEC standardized characteristics, there are also two
additional inverse curves available; the RI curve and the RD curve.
The RI inverse time curve emulates the characteristic of the electromechanical

ASEA relay RI. The curve is described by equation 154:
æ ö
ç k ÷
t[ s ] = ç
in > ÷
ç 0.339 - 0.235 × ÷
è i ø
where:
in> is the set start current for step n
k is set time multiplier for step n
i is the measured current
940
The RD inverse curve gives a logarithmic delay, as used in the Combiflex

protection RXIDG. The curve enables a high degree of selectivity required for
sensitive residual earth-fault current protection, with ability to detect high-resistive
earth faults. The curve is described by equation 155:
æ i ö
t[ s ] = 5.8 - 1.35 × ln ç ÷
è k × in > ø
where:
in> is the set start current for step n,
k is set time multiplier for step n and
i is the measured current
If the curve type programmable is chosen, the user can make a tailor made inverse
time curve according to the general equation 156.
æ ö
ç A
÷
t[ s ] = ç + B÷×k
ç æ i öp ÷
çç ÷ -C ÷
è è in > ø ø
Also the reset time of the delayed function can be controlled. There is the
possibility to choose between three different reset time-lags.
• Instantaneous Reset
• IEC Reset
• ANSI Reset.
If instantaneous reset is chosen the timer will be reset directly when the current
drops below the set start current level minus the hysteresis.
If IEC reset is chosen the timer will be reset after a set constant time when the
current drops below the set start current level minus the hysteresis.
If ANSI reset time is chosen the reset time will be dependent of the current after
fault clearance (when the current drops below the start current level minus the
hysteresis). The timer will reset according to equation 157.
941
æ ö
ç tr ÷
t [s] = ç ÷×k
çæ i ö ÷
2
çç ÷ -1 ÷
è è in > ø ø
where:
The set value tr is the reset time in case of zero current after fault clearance.
The possibility of choice of reset characteristics is to some extent dependent of the

choice of time delay characteristic.
For the definite time delay characteristics the possible reset time settings are
instantaneous and IEC constant time reset.
For ANSI inverse time delay characteristics all three types of reset time
characteristics are available; instantaneous, IEC constant time reset and ANSI
current dependent reset time.
For IEC inverse time delay characteristics the possible delay time settings are
instantaneous and IEC set constant time reset).
For the programmable inverse time delay characteristics all three types of reset
time characteristics are available; instantaneous, IEC constant time reset and ANSI
current dependent reset time. If the current dependent type is used settings pr, tr
and cr must be given, see equation 158:
æ ö
ç tr ÷
t [s] = ç ÷×k
çæ i ö ÷
pr
çç ÷ - cr ÷
è è in > ø ø
For RI and RD inverse time delay characteristics the possible delay time settings
are instantaneous and IEC constant time reset.
When inverse time overcurrent characteristic is selected, the

operate time of the stage will be the sum of the inverse time delay
and the set definite time delay. Thus, if only the inverse time delay
is required, it is of utmost importance to set the definite time delay
for that stage to zero.
942
22.3 Inverse characteristics
Table 582: ANSI Inverse time characteristics

Operating characteristic: k = (0.05-999) in steps of -
0.01 unless otherwise stated
æ A ö
t = ç P + B÷ × k
ç ( I - 1) ÷
è ø
EQUATION1249-SMALL V1 EN
Reset characteristic:
tr
t = ×k
(I 2
)
-1
I = Imeasured/Iset
ANSI Extremely Inverse A=28.2, B=0.1217, P=2.0 , ANSI/IEEE C37.112,

tr=29.1 class 5 + 40 ms
ANSI Very inverse A=19.61, B=0.491, P=2.0 ,
tr=21.6
ANSI Normal Inverse A=0.0086, B=0.0185,
P=0.02, tr=0.46
ANSI Moderately Inverse A=0.0515, B=0.1140,
P=0.02, tr=4.85
ANSI Long Time Extremely Inverse A=64.07, B=0.250, P=2.0,
tr=30
ANSI Long Time Very Inverse A=28.55, B=0.712, P=2.0,
tr=13.46
ANSI Long Time Inverse k=(0.05-999) in steps of 0.01
A=0.086, B=0.185, P=0.02,
tr=4.6
943
Table 583: IEC Inverse time characteristics

Operating characteristic: k = (0.05-999) in steps of 0.01 -
æ A ö
t = ç P ÷×k
ç ( I - 1) ÷
è ø
I = Imeasured/Iset
Time delay to reset, IEC inverse time (0.000-60.000) s ± 0.5% of set time ± 10
ms
IEC Normal Inverse A=0.14, P=0.02 IEC 60255-3, class 5 +
40 ms
IEC Very inverse A=13.5, P=1.0
IEC Inverse A=0.14, P=0.02
IEC Extremely inverse A=80.0, P=2.0
IEC Short time inverse A=0.05, P=0.04
IEC Long time inverse A=120, P=1.0
Programmable characteristic k = (0.05-999) in steps of 0.01 IEC 60255, class 5 + 40
Operate characteristic: A=(0.005-200.000) in steps ms
of 0.001
æ A ö B=(0.00-20.00) in steps of
t = ç P + B÷ × k 0.01
ç (I - C ) ÷ C=(0.1-10.0) in steps of 0.1
è ø
P=(0.005-3.000) in steps of
0.001
Reset characteristic: TR=(0.005-100.000) in steps
of 0.001
TR CR=(0.1-10.0) in steps of 0.1
t = ×k PR=(0.005-3.000) in steps of
(I PR
- CR ) 0.001
I = Imeasured/Iset
Table 584: RI and RD type inverse time characteristics

RI type inverse characteristic k = (0.05-999) in steps of 0.01 IEC 60255-3, class 5 +
40 ms
1
t = ×k
0.236
0.339 -
I
I = Imeasured/Iset
RD type logarithmic inverse characteristic k = (0.05-999) in steps of 0.01 IEC 60255-3, class 5 +
40 ms
æ I ö
t = 5.8 - ç 1.35 × In ÷
è k ø
I = Imeasured/Iset
944
Table 585: Inverse time characteristics for overvoltage protection

Type A curve: k = (0.05-1.10) in Class 5 +40 ms
steps of 0.01 unless
k otherwise stated
t =
æU -U >ö
ç ÷
è U> ø
U> = Uset
U = Umeasured
Type B curve: k = (0.05-1.10) in

k × 480 otherwise stated
t =
2.0
æ 32 × U - U > - 0.5 ö
ç ÷ - 0.035
è U > ø
Type C curve: k = (0.05-1.10) in

t =
3.0
æ 32 × U - U > - 0.5 ö
ç ÷ - 0.035
è U > ø
Programmable curve: k = (0.05-1.10) in

k×A otherwise stated
t = +D A = (0.005-200.000)
P
æB × U - U > ö in steps of 0.001
ç -C÷
B = (0.50-100.00) in
è U > ø
steps of 0.01
C = (0.0-1.0) in
steps of 0.1
D = (0.000-60.000)
in steps of 0.001
P = (0.000-3.000) in
steps of 0.001
945
Table 586: Inverse time characteristics for undervoltage protection

Type A curve: k = (0.05-1.10) in Class 5 +40 ms
k otherwise stated
t =
æ U < -U
ö
ç ÷
è U< ø
U< = Uset
U = UVmeasured
Type B curve: k = (0.05-1.10) in

t = + 0.055
2.0
æ 32 × U < -U - 0.5 ö
ç ÷
è U < ø
U< = Uset
U = Umeasured
Programmable curve: k = (0.05-1.10) in

é ù otherwise stated
ê ú A = (0.005-200.000)
k×A in steps of 0.001
t =ê ú+D
ê æ U < -U P
ú B = (0.50-100.00) in
ö
êçB × -C÷ ú steps of 0.01
ëè U < ø û C = (0.0-1.0) in
steps of 0.1
U< = Uset D = (0.000-60.000)
in steps of 0.001
U = Umeasured
P = (0.000-3.000) in
steps of 0.001
946
Table 587: Inverse time characteristics for residual overvoltage protection

Type A curve: k = (0.05-1.10) in steps of Class 5 +40 ms
0.01
k
t =
æU -U >ö
ç ÷
è U> ø
U> = Uset
U = Umeasured
Type B curve: k = (0.05-1.10) in steps of

0.01
k × 480
t =
2.0
æ 32 × U - U > - 0.5 ö
ç ÷ - 0.035
è U > ø
Type C curve: k = (0.05-1.10) in steps of

0.01
k × 480
t =
3.0
æ 32 × U - U > - 0.5 ö
ç ÷ - 0.035
è U > ø
Programmable curve: k = (0.05-1.10) in steps of

0.01
k×A A = (0.005-200.000) in
t = +D steps of 0.001
P
æB × U - U > ö B = (0.50-100.00) in
ç -C÷
steps of 0.01
è U > ø
C = (0.0-1.0) in steps of
0.1
D = (0.000-60.000) in
steps of 0.001
P = (0.000-3.000) in
steps of 0.001
947
A070750 V2 EN
Figure 449: ANSI Extremely inverse time characteristics
948
A070751 V2 EN
Figure 450: ANSI Very inverse time characteristics
949
A070752 V2 EN
Figure 451: ANSI Normal inverse time characteristics
950
A070753 V2 EN
Figure 452: ANSI Moderately inverse time characteristics
951
A070817 V2 EN
Figure 453: ANSI Long time extremely inverse time characteristics
952
A070818 V2 EN
Figure 454: ANSI Long time very inverse time characteristics
953
A070819 V2 EN
Figure 455: ANSI Long time inverse time characteristics
954
A070820 V2 EN
Figure 456: IEC Normal inverse time characteristics
955
A070821 V2 EN
Figure 457: IEC Very inverse time characteristics
956
A070822 V2 EN
Figure 458: IEC Inverse time characteristics
957
A070823 V2 EN
Figure 459: IEC Extremely inverse time characteristics
958
A070824 V2 EN
Figure 460: IEC Short time inverse time characteristics
959
A070825 V2 EN
Figure 461: IEC Long time inverse time characteristics
960
A070826 V2 EN
Figure 462: RI-type inverse time characteristics
961
A070827 V2 EN
Figure 463: RD-type inverse time characteristics
962
GUID-ACF4044C-052E-4CBD-8247-C6ABE3796FA6 V1 EN
Figure 464: Inverse curve A characteristic of overvoltage protection
963
GUID-F5E0E1C2-48C8-4DC7-A84B-174544C09142 V1 EN
Figure 465: Inverse curve B characteristic of overvoltage protection
964
GUID-A9898DB7-90A3-47F2-AEF9-45FF148CB679 V1 EN
Figure 466: Inverse curve C characteristic of overvoltage protection
965
GUID-35F40C3B-B483-40E6-9767-69C1536E3CBC V1 EN
Figure 467: Inverse curve A characteristic of undervoltage protection
966
GUID-B55D0F5F-9265-4D9A-A7C0-E274AA3A6BB1 V1 EN
Figure 468: Inverse curve B characteristic of undervoltage protection
967
968
Glossary
Section 23 Glossary
About this chapter

This chapter contains a glossary with terms, acronyms and abbreviations used in
ABB technical documentation.
AC Alternating current
ACT Application configuration tool within PCM600
A/D converter Analog-to-digital converter
ADBS Amplitude deadband supervision
ADM Analog digital conversion module, with time synchronization
AI Analog input
ANSI American National Standards Institute
AR Autoreclosing
ArgNegRes Setting parameter/ZD/
ArgDir Setting parameter/ZD/
ASCT Auxiliary summation current transformer
ASD Adaptive signal detection
AWG American Wire Gauge standard
BBP Busbar protection
BFP Breaker failure protection
BI Binary input
BIM Binary input module
BOM Binary output module
BOS Binary outputs status
BR External bistable relay
BS British Standards
BSR Binary signal transfer function, receiver blocks
BST Binary signal transfer function, transmit blocks
C37.94 IEEE/ANSI protocol used when sending binary signals
between IEDs
CAN Controller Area Network. ISO standard (ISO 11898) for
serial communication
CB Circuit breaker
969
Glossary
CBM Combined backplane module

CCITT Consultative Committee for International Telegraph and
Telephony. A United Nations-sponsored standards body
within the International Telecommunications Union.
CCM CAN carrier module
CCVT Capacitive Coupled Voltage Transformer
Class C Protection Current Transformer class as per IEEE/ ANSI
CMPPS Combined megapulses per second
CMT Communication Management tool in PCM600
CO cycle Close-open cycle
Codirectional Way of transmitting G.703 over a balanced line. Involves
two twisted pairs making it possible to transmit information
in both directions
COMTRADE Standard format according to IEC 60255-24
Contra-directional Way of transmitting G.703 over a balanced line. Involves
four twisted pairs, two of which are used for transmitting
data in both directions and two for transmitting clock signals
CPU Central processor unit
CR Carrier receive
CRC Cyclic redundancy check
CROB Control relay output block
CS Carrier send
CT Current transformer
CVT Capacitive voltage transformer
DAR Delayed autoreclosing
DARPA Defense Advanced Research Projects Agency (The US
developer of the TCP/IP protocol etc.)
DBDL Dead bus dead line
DBLL Dead bus live line
DC Direct current
DFC Data flow control
DFT Discrete Fourier transform
DHCP Dynamic Host Configuration Protocol
DIP-switch Small switch mounted on a printed circuit board
DI Digital input
DLLB Dead line live bus
970
Glossary
DNP Distributed Network Protocol as per IEEE/ANSI Std.

1379-2000
DR Disturbance recorder
DRAM Dynamic random access memory
DRH Disturbance report handler
DSP Digital signal processor
DTT Direct transfer trip scheme
EHV network Extra high voltage network
EIA Electronic Industries Association
EMC Electromagnetic compatibility
EMF (Electric Motive Force)
EMI Electromagnetic interference
EnFP End fault protection
EPA Enhanced performance architecture
ESD Electrostatic discharge
FCB Flow control bit; Frame count bit
FOX 20 Modular 20 channel telecommunication system for speech,
data and protection signals
FOX 512/515 Access multiplexer
FOX 6Plus Compact time-division multiplexer for the transmission of
up to seven duplex channels of digital data over optical fibers
G.703 Electrical and functional description for digital lines used by
local telephone companies. Can be transported over
balanced and unbalanced lines
GCM Communication interface module with carrier of GPS
receiver module
GDE Graphical display editor within PCM600
GI General interrogation command
GIS Gas-insulated switchgear
GOOSE Generic object-oriented substation event
GPS Global positioning system
GTM GPS Time Module
HDLC protocol High-level data link control, protocol based on the HDLC
standard
HFBR connector Plastic fiber connector
type
HMI Human-machine interface
971
Glossary
HSAR High speed autoreclosing

HV High-voltage
HVDC High-voltage direct current
ICT Installation and Commissioning Tool for injection based
protection in REG670
IDBS Integrating deadband supervision
IEC International Electrical Committee
IEC 60044-6 IEC Standard, Instrument transformers – Part 6:
Requirements for protective current transformers for
transient performance
IEC 60870-5-103 Communication standard for protective equipment. A serial
master/slave protocol for point-to-point communication
IEC 61850 Substation automation communication standard
IEEE Institute of Electrical and Electronics Engineers
IEEE 802.12 A network technology standard that provides 100 Mbits/s on
twisted-pair or optical fiber cable
IEEE P1386.1 PCI Mezzanine Card (PMC) standard for local bus modules.
References the CMC (IEEE P1386, also known as Common
Mezzanine Card) standard for the mechanics and the PCI
specifications from the PCI SIG (Special Interest Group) for
the electrical EMF (Electromotive force).
IED Intelligent electronic device
I-GIS Intelligent gas-insulated switchgear
IOM Binary input/output module
Instance When several occurrences of the same function are available
in the IED, they are referred to as instances of that function.
One instance of a function is identical to another of the same
kind but has a different number in the IED user interfaces.
The word "instance" is sometimes defined as an item of
information that is representative of a type. In the same way
an instance of a function in the IED is representative of a
type of function.
IP 1. Internet protocol. The network layer for the TCP/IP
protocol suite widely used on Ethernet networks. IP is a
connectionless, best-effort packet-switching protocol. It
provides packet routing, fragmentation and reassembly
through the data link layer.
2. Ingression protection, according to IEC standard
IP 20 Ingression protection, according to IEC standard, level 20
972
Glossary

IRF Internal failure signal
IRIG-B: InterRange Instrumentation Group Time code format B,
standard 200
ITU International Telecommunications Union
LAN Local area network
LIB 520 High-voltage software module
LCD Liquid crystal display
LDCM Line differential communication module
LDD Local detection device
LED Light-emitting diode
LNT LON network tool
LON Local operating network
MCB Miniature circuit breaker
MCM Mezzanine carrier module
MIM Milli-ampere module
MPM Main processing module
MVB Multifunction vehicle bus. Standardized serial bus originally
developed for use in trains.
NCC National Control Centre
NUM Numerical module
OCO cycle Open-close-open cycle
OCP Overcurrent protection
OEM Optical ethernet module
OLTC On-load tap changer
OV Over-voltage
Overreach A term used to describe how the relay behaves during a fault
condition. For example, a distance relay is overreaching
when the impedance presented to it is smaller than the
apparent impedance to the fault applied to the balance point,
that is, the set reach. The relay “sees” the fault but perhaps it
should not have seen it.
PCI Peripheral component interconnect, a local data bus
PCM Pulse code modulation
PCM600 Protection and control IED manager
PC-MIP Mezzanine card standard
973
Glossary
PISA Process interface for sensors & actuators

PMC PCI Mezzanine card
POR Permissive overreach
POTT Permissive overreach transfer trip
Process bus Bus or LAN used at the process level, that is, in near
proximity to the measured and/or controlled components
PSM Power supply module
PST Parameter setting tool within PCM600
PT ratio Potential transformer or voltage transformer ratio
PUTT Permissive underreach transfer trip
RASC Synchrocheck relay, COMBIFLEX
RCA Relay characteristic angle
RFPP Resistance for phase-to-phase faults
RFPE Resistance for phase-to-earth faults
RISC Reduced instruction set computer
RMS value Root mean square value
RS422 A balanced serial interface for the transmission of digital
data in point-to-point connections
RS485 Serial link according to EIA standard RS485
RTC Real-time clock
RTU Remote terminal unit
SA Substation Automation
SBO Select-before-operate
SC Switch or push button to close
SCS Station control system
SCADA Supervision, control and data acquisition
SCT System configuration tool according to standard IEC 61850
SDU Service data unit
SLM Serial communication module. Used for SPA/LON/IEC/
DNP3 communication.
SMA connector Subminiature version A, A threaded connector with constant
impedance.
SMT Signal matrix tool within PCM600
SMS Station monitoring system
SNTP Simple network time protocol – is used to synchronize
computer clocks on local area networks. This reduces the
974
Glossary
requirement to have accurate hardware clocks in every

embedded system in a network. Each embedded node can
instead synchronize with a remote clock, providing the
required accuracy.
SPA Strömberg protection acquisition, a serial master/slave
protocol for point-to-point communication
SRY Switch for CB ready condition
ST Switch or push button to trip
Starpoint Neutral point of transformer or generator
SVC Static VAr compensation
TC Trip coil
TCS Trip circuit supervision
TCP Transmission control protocol. The most common transport
layer protocol used on Ethernet and the Internet.
TCP/IP Transmission control protocol over Internet Protocol. The
de facto standard Ethernet protocols incorporated into
4.2BSD Unix. TCP/IP was developed by DARPA for
Internet working and encompasses both network layer and
transport layer protocols. While TCP and IP specify two
protocols at specific protocol layers, TCP/IP is often used to
refer to the entire US Department of Defense protocol suite
based upon these, including Telnet, FTP, UDP and RDP.
TEF Time delayed earth-fault protection function
TNC connector Threaded Neill-Concelman, a threaded constant impedance
version of a BNC connector
TPZ, TPY, TPX, Current transformer class according to IEC
TPS
UMT User management tool
Underreach A term used to describe how the relay behaves during a fault
condition. For example, a distance relay is underreaching
when the impedance presented to it is greater than the
apparent impedance to the fault applied to the balance point,
that is, the set reach. The relay does not “see” the fault but
perhaps it should have seen it. See also Overreach.
U/I-PISA Process interface components that deliver measured voltage
and current values
UTC Coordinated Universal Time. A coordinated time scale,
maintained by the Bureau International des Poids et
Mesures (BIPM), which forms the basis of a coordinated
dissemination of standard frequencies and time signals.
UTC is derived from International Atomic Time (TAI) by
the addition of a whole number of "leap seconds" to
975
Glossary
synchronize it with Universal Time 1 (UT1), thus allowing

for the eccentricity of the Earth's orbit, the rotational axis tilt
(23.5 degrees), but still showing the Earth's irregular
rotation, on which UT1 is based. The Coordinated Universal
Time is expressed using a 24-hour clock, and uses the
Gregorian calendar. It is used for aeroplane and ship
navigation, where it is also sometimes known by the
military name, "Zulu time." "Zulu" in the phonetic alphabet
stands for "Z", which stands for longitude zero.
UV Undervoltage
WEI Weak end infeed logic
VT Voltage transformer
X.21 A digital signalling interface primarily used for telecom
equipment
3IO Three times zero-sequence current. Often referred to as the
residual or the earth-fault current
3UO Three times the zero sequence voltage. Often referred to as
the residual voltage or the neutral point voltage
976
977
Contact us
1MRK 502 027-UEN A © Copyright 2011 ABB. All rights reserved.

ABB AB
Substation Automation Products
SE-721 59 Västerås, Sweden
Phone +46 (0) 21 32 50 00
Fax +46 (0) 21 14 69 18
www.abb.com/substationautomation

1MRK502027-UEN A en Technical Reference Manual REG670 1.2

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Relion® 670 series

Generator protection REG670

© Copyright 2011 ABB. All rights reserved

The software or hardware described in this document is furnished under a license

Section 2 Analog inputs..................................................................33

Section 3 Local HMI.......................................................................41

Input and output signals.........................................................50

Section 4 Basic IED functions........................................................61

Section 5 Differential protection...................................................103

Section 6 Impedance protection ..................................................175

Section 7 Current protection.........................................................255

Section 8 Voltage protection........................................................359

Section 9 Frequency protection....................................................419

Section 10 Multipurpose protection................................................433

General current and voltage protection CVGAPC..........................433

Section 11 Secondary system supervision.....................................467

Synchrocheck, energizing check, and synchronizing

Input and output signals.......................................................562

Controllable gate function block GATE......................................640

Voltage and current sequence measurements VMSQI,

Input and output signals............................................................732

Section 16 Station communication.................................................735

Input and output signals............................................................782

Section 17 Remote communication................................................799

Section 18 IED hardware...............................................................805

Line data communication module (LDCM)................................841

Type tests according to standard..............................................866

Section 19 Injection equipment hardware......................................869

Section 21 Connection diagrams...................................................893

Section 22 Inverse time characteristics..........................................935

About this chapter

1.1 Introduction to the technical reference manual

1.1.1 About the complete set of manuals for an IED

deinstalling & disposal

The Application Manual (AM) contains application descriptions, setting

The Technical Reference Manual (TRM) contains application and functionality

manual should be used as a technical reference during the engineering phase,

The Installation and Commissioning Manual (ICM) contains instructions on

The Operator’s Manual (OM) contains instructions on how to operate the

1.1.2 About the technical reference manual

• Hardware describes the IED and its components.

1.1.3 This manual

Outlines the implementation of a particular protection function.

1.1.3.2 Principle of operation

Describes how the function works, presents a general background to algorithms

Input and output signals

Figure 1: Logic diagram example with -int signals

Figure 2: Logic diagram example with an outgoing -cont signal

Figure 3: Logic diagram example with an incoming -cont signal

1.1.3.3 Input and output signals

1.1.3.4 Function block

Each function block is illustrated graphically.

Figure 4: Example of a function block

1.1.3.5 Setting parameters

1.1.3.6 Technical data

1.1.4 Intended audience

1.1.5 Related documents

Connection and Installation components 1MRK 513 003-BEN

More information can be found on www.abb.com/substationautomation.

1.1.6 Revision notes

Section 2 Analog inputs

A reference PhaseAngleRef can be defined to facilitate service values reading. This