Design and Control of Hybrid Multi-Stage Inverter For AC Drives

DESIGN AND CONTROL OF HYBRID MULTISTAGE
INVERTER FOR AC DRIVES

MOHAMAD N. ABDUL KADIR

THESIS SUBMITTED IN FULFILLMENT
OF THE REQUIREMENTS
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

FACULTY OF ENGINEERING
UNIVERSITY OF MALAYA
KUALA LUMPUR

OCTOBER 2010

ii
UNIVERSITI MALAYA

ORIGINAL LITERARY WORK DECLARATION

Name of Candidate: Mohamad N. Abdul Kadir (I.C./ Passport No.: G1857201)

Registration/ Matric No: KHA060024

Name of Degree: Doctor of Philosophy

Title of Thesis

DESIGN AND CONTROL OF HYBRID MULTISTAGE INVERTER
FOR AC DRIVES

Field of Study: Electrical Engineering

I do solemnly and sincerely declare that:

(1) I am the sole author/writer of this Work;
(2) This Work is original;
(3) Any use of any work in which copyright exists was done by way of fair dealing and for
permitted purposes and any excerpt or extract from, or reference to or reproduction of
any copyright work has been disclosed expressly and sufficiently and the title of the
Work and its authorship have been acknowledged in this Work;
(4) I do not have any actual knowledge nor do I ought reasonably to know that the making
of this work constitute an infringement of any copyright work;
(5) I hereby assign all and every right in the copyright of this Work to the University of
Malaya (UM), who henceforth shall be owner of the copyright in this Work and that
any reproduction or use in any form or by any means whatsoever is prohibited without
the written consent of UM having been first had and obtained;
(6) I am fully aware that if in the course of making this Work I have infringed any copyright
whether intentionally or otherwise, I may be subject to legal action or any other action
or any other action as may be determined by UM.

Candidates Signature Date

Subscribed and solemnly declared before,

Witnesss Signature Date

Name:
Designation:

iii
Abstract
Multilevel inverters are becoming increasingly popular for high and medium power
applications. In the course of improving features of multilevel inverters and enhancing
their competitiveness, hybrid multistage inverter has been introduced. Hybrid inverters
reduce the circuit size and cost for a given number of levels and improve devices
utilization. In this study a three-stage hybrid inverter has been designed. The inverter is
composed of high-voltage, medium-voltage and low-voltage stages. The high voltage
stage has been constructed using six-switch inverter while the other stages are three-
level stages built using cascaded H-bridge cells. The values of DC voltages of the three
stages have been selected to maximize the number of inverter levels by eliminating state
redundancy.
Two control modes have been proposed to operate the hybrid inverter: voltage vector
approximation mode and space vector modulation mode. In voltage vector
approximation mode, the proposed control algorithm produces the inverter voltage
vector which is nearest to the required output while the switching losses have been
minimized. A voltage space vector modulation control technique has been developed.
This method enables the multistage inverter designed with maximum number of levels
to be operated in pulse width modulation control mode without subjecting the high
voltage stage to high frequency switching. The voltage vector modulation algorithm
operates the high and medium voltage stages with low switching frequency regardless
of the output voltage amplitude. The low voltage stage is controlled using conventional
space vector modulation strategy.
Both control modes have been tested and the experimental results verify that the
proposed inverter system achieves its design goals in both voltage approximation and
space vector modulation modes.
iv
Acknowledgments
First of all, I would like to thank my supervisors: Dr. Saad Mekhilef and Dr. Hew Wooi
Ping for their support, help and understanding. I am very grateful to work with such
knowledgeable and cooperative advisors. Special thanks to Dr. Mekhilef for providing
research fellowship, without it, the study period would have been even tenser.
I would also like to thank many administrative staff in the Department of Electrical
Engineering, Faculty of Engineering and Institute of Graduate Studies for facilitating
several formalities.
Thanks are due to the Institute of Research Management and Consultancy (IPPP) at the
University of Malaya for providing some fund for this project.
I would like to extend my gratitude to my fellow colleagues in the postgraduate Electric
Machines Laboratory: Mr. Jefferi Jamaludin and Mr. Wijono for their kind willingness
to exchange knowledge and facilities.
Finally, I would like to thank Dr Jalel Abdul Salam Chebil from the International
Islamic University of Malaysia for proofreading the thesis manuscript.

v
Table of Contents
ABSTRACT .................................................................................................................. III
ACKNOWLEDGMENTS ........................................................................................... IV
TABLE OF CONTENTS ............................................................................................... V
LIST OF FIGURES .................................................................................................... XII
LIST OF TABLES ..................................................................................................... XVI
LIST OF SYMBOLS ............................................................................................... XVII
LIST OF ABBREVIATIONS ................................................................................... XXI
CHAPTER ONE ............................................................................................................. 1
INTRODUCTION ........................................................................................................... 1
1.1 Introduction ..................................................................................... 1
1.2 Motivation of the Study .................................................................. 1
1.3 Electric Drives ................................................................................. 2
1.4 Power Converters ........................................................................... 4
1.5 Desired Characteristics of AC Drives Inverter........................... 5
1.6 Problem Statement ......................................................................... 7
1.7 Project Objectives ........................................................................... 8
1.8 Thesis Outline .................................................................................. 9
1.9 Summary........................................................................................ 10
CHAPTER TWO .......................................................................................................... 11
REVIEW OF MULTILEVEL INVERTERS CIRCUITS AND CONTROL .......... 11
2.1 Introduction ................................................................................... 11
2.2 General Background..................................................................... 11
2.2.1 The concept of multilevel inverters ........................................... 11
2.2.2 Multilevel inverters advantages ................................................. 14
vi
2.2.3 Multilevel inverters drawbacks and limitations ........................ 15
2.2.4 Voltage equations of multilevel inverter ................................... 15
2.3 Basic multilevel inverter Circuits ................................................ 17
2.3.1 Neutral point clamped inverter .................................................. 17
2.3.2 Flying capacitor inverter ........................................................... 20
2.3.3 Cascaded H-bridges inverter ..................................................... 22
2.4 Innovative Multilevel Inverter Topologies ................................. 25
2.4.1 Asymmetrical CHB inverters ..................................................... 25
2.4.2 Mixed-level topologies ............................................................... 27
2.4.3 Hybrid inverter topologies ......................................................... 28
2.4.3.1 The use of singly-fed main stage ............................................. 29
2.4.3.2 Transformer-isolated multistage inverters ............................. 29
2.4.3.3 Inverters for open windings loads .......................................... 31
2.5 A View on Multilevel Inverter Control ....................................... 32
2.6 Full-Cycle Reference Voltage Control Methods ........................ 33
2.6.1 Low switching frequency control .............................................. 33
2.6.1.1 Harmonic distortion minimization .......................................... 34
2.6.1.2 Selected harmonics elimination .............................................. 34
2.6.2 High frequency carrier comparison PWM methods ................ 36
2.6.2.1 Amplitude-shifted carrier PWM ............................................. 36
2.6.2.2 Phase-shifted multicarrier ...................................................... 39
2.6.2.3 Other modified carrier signals ............................................... 40
2.7 Sampled Reference Control Methods ......................................... 41
2.7.1 Low frequency control methods ................................................ 41
2.7.1.1 Voltage vector approximation ................................................ 41
2.7.1.2 Voltage amplitude approximation .......................................... 42
2.7.2 High switching frequency methods ........................................... 43
2.7.2.1 Basic multilevel SVM .............................................................. 43
2.7.2.2 Three dimensional SVM .......................................................... 46
vii
2.7.2.3 Multiple-phase SVM ............................................................... 47
2.7.2.4 Carrier-based SVM ................................................................. 47
2.7.2.5 Uni-dimensional SVM ............................................................. 49
2.7.3 Flux modulation control ............................................................ 49
2.7.4 Hybrid control methods ............................................................. 50
2.8 Current Control of Multilevel Inverters ..................................... 52
2.9 The Selection of Multilevel Inverter Topology and Control
Strategy .......................................................................................... 53
2.9.1 Topology selection ...................................................................... 54
2.9.1.1 Desired voltage ....................................................................... 54
2.9.1.2 Desired frequency ................................................................... 55
2.9.1.3 Load current ........................................................................... 55
2.9.1.4 Power factor ........................................................................... 55
2.9.1.5 Distortion limits ...................................................................... 55
2.9.2 Control strategy selection .......................................................... 56
2.9.2.1 Multilevel inverter topology ................................................... 56
2.9.2.2 Quality needs .......................................................................... 56
2.9.2.3 Load type ................................................................................ 56
2.9.2.4 Supply limitations ................................................................... 57
2.10 Summary........................................................................................ 57
CHAPTER THREE ...................................................................................................... 59
DESIGN OF MULTILEVEL INVERTER ................................................................. 59
3.1 Introduction ................................................................................... 59
3.2 Load Considerations ..................................................................... 59
3.3 Inverter Topology Design ............................................................. 60
3.4 Inverters Switching States, Voltages and Voltage Vectors ...... 62
3.5 Voltage Vector Approximation Control ..................................... 64
3.5.1 The control concept ................................................................... 64
3.5.2 Control of high and medium voltage stages ............................. 69
viii
3.5.2.1 High and medium state domains ............................................. 70
3.5.2.2 The reference vector zone ....................................................... 73
3.5.3 Control of low voltage stage ...................................................... 77
3.5.3.1 Low stage state zones .............................................................. 78
3.5.3.2 Determination of the low reference vector zone ..................... 79
3.6 Voltage Vector Approximation by Axis Transformation ......... 84
3.6.1 The g-h axis system .................................................................... 85
3.6.2 Control of the high and medium voltage stages ....................... 88
3.6.3 Control of the low voltage stage ................................................ 90
3.7 Space Vector Modulation Control............................................... 91
3.7.1 The dilemma of high voltage stage switching ........................... 92
3.7.2 The voltage space vector control concept .................................. 94
3.7.3 Control of the three inverter stages ........................................... 95
3.7.3.1 Low voltage stage control: basic modulation ......................... 96
3.7.3.2 Low voltage stage: secondary modulation calculations ......... 98
3.7.4 Modified control algorithm ..................................................... 102
3.8 Summary...................................................................................... 107
CHAPTER FOUR ....................................................................................................... 108
IMPLEMENTATION OF MULTISTAGE INVERTER ........................................ 108
4.1 Introduction ................................................................................. 108
4.2 General Description of the Inverter Prototype ........................ 108
4.3 Power Circuit Description.......................................................... 109
4.3.1 Load specifications .................................................................. 109
4.3.2 DC link ..................................................................................... 110
4.3.3 Switching devices sizing........................................................... 111
4.3.4 Measuring equipment and testing load ................................... 113
4.4 The Controller ............................................................................. 113
4.4.1 General purpose input/output ................................................. 114
ix
4.4.2 General purpose timers ............................................................ 115
4.4.3 Event managers........................................................................ 115
4.4.4 Interrupt system ....................................................................... 116
4.4.5 The code composer studio ........................................................ 116
4.4.6 Header files and peripheral examples library ........................ 116
4.4.7 IQ-math library ........................................................................ 117
4.5 Auxiliary Circuits ....................................................................... 117
4.5.1 Reference input code ............................................................... 118
4.5.2 Switching signals decoding and Processing ........................... 119
4.6 Implementation of Vector Approximation Mode .................... 121
4.6.1 The main program ................................................................... 123
4.6.2 The interrupt service routine ................................................... 124
4.7 Implementation of Vector Approximation Mode Using g-h
Coordinates Transformation ..................................................... 125
4.8 Implementation of Vector Control Mode ................................. 127
4.9 Summary...................................................................................... 131
CHAPTER FIVE ......................................................................................................... 132
EXPERIMENTAL RESULTS ................................................................................... 132
5.1 Introduction ................................................................................. 132
5.2 Inverter Testing in Vector Approximation Mode .................... 132
5.2.1 Phase voltage measurements ................................................... 133
5.2.2 DC side current ........................................................................ 137
5.2.3 Inverter characteristics ............................................................ 138
5.2.3.1 Voltage waveform ................................................................. 138
5.2.3.2 The switching frequency ....................................................... 138
5.2.3.3 Current measurements .......................................................... 139
x
5.3 Inverter Testing Using g-h Axis Based Voltage Approximation
Method ......................................................................................... 139
5.3.1 Voltage waveforms ................................................................... 139
5.4 Inverter Testing in Space Vector Control Mode Using Basic
High State Domain ...................................................................... 143
5.4.1 Switching signals ..................................................................... 144
5.4.2 Voltage waveform .................................................................... 145
5.5 Inverter Testing in Space Vector Control Mode Using Modified
High State Domain ...................................................................... 152
5.6 Summary...................................................................................... 159
CHAPTER SIX ........................................................................................................... 160
ANALYSIS AND DISCUSSION ............................................................................... 160
6.1 Introduction ................................................................................. 160
6.2 Voltage Vector Approximation.................................................. 160
6.2.3 Currents waveforms ................................................................. 163
6.2.4 Basic d-q versus g-h axis calculations .................................... 163
6.2.5 Comparisons with previous studies ......................................... 164
6.3 Voltage Vector Control .............................................................. 166
6.3.2 Resultant voltage ...................................................................... 166
xi
6.3.3 The effect of high voltage domain adjustment ....................... 167
6.3.4 Comparison with previous studies ........................................... 168
6.4 The Achievement of the Study Objectives ................................ 170
6.4.1 Extended levels and optimized number of switching devices . 170
6.4.2 Applying hybrid topology ......................................................... 170
6.4.3 State redundancy elimination .................................................. 171
6.4.4 Switching losses minimization................................................. 171
6.4.5 Computationally efficient control ........................................... 171
6.4.6 High quality control ................................................................. 172
6.4.7 Simultaneous and high voltage stage high frequency
elimination. .............................................................................. 173
6.5 Summary...................................................................................... 174
CHAPTER SEVEN ..................................................................................................... 175
CONCLUSION ............................................................................................................ 175
7.1 Introduction ................................................................................. 175
7.2 Multistage Topology ................................................................... 175
7.3 Inverter Operation by Vector Approximation ......................... 176
7.4 Inverter Operation by Space Vector Modulation Control...... 177
7.5 Recommendations and Suggestions for Future Work............. 178
REFERENCES ............................................................................................................ 181
APPENDIX 1 ............................................................................................................... 195
APPENDIX 2 ............................................................................................................... 196

xii
List of Figures
Figure 1.1 Main components of electric drivers system. .................................................. 2
Figure 2.1 The three-phase six switch inverter. .............................................................. 12
Figure 2.2 Idealized model of the three-phase inverter................................................... 12
Figure 2.3 A hypothetical l-level MLI. ........................................................................... 13
Figure 2.4 Comparison between the conventional two-level inverter and a five-
level MLI operation to approximate a reference sine wave. ........................ 13
Figure 2.5 Five-level neutral point clamped inverter circuit........................................... 17
Figure 2.6 Output point voltage switching among the five voltage levels of NPC
inverter. ........................................................................................................ 18
Figure 2.7 Structure of pyramid voltage divider for five-level NPC inverter arm. ........ 19
Figure 2.8 One arm of a five-level flying capacitor MLI. .............................................. 20
Figure 2.9 Five-level cascaded H-bridge inverter. .......................................................... 22
Figure 2.10 Number of possible switching combinations to achieve various arm
voltages for various CHB levels................................................................... 23
Figure 2.11 Asymmetrical CHB inverter. ....................................................................... 26
Figure 2.12 Cascaded mixed topology H-bridges to construct a 9-level inverter. .......... 27
Figure 2.13 Hybrid inverter with a two-level 6-switch main stage................................. 28
Figure 2.14 A single-phase diagram of a singly-fed transformer-isolated
multistage inverter. ....................................................................................... 30
Figure 2.15 Two cascaded inverters to feed open windings motor................................. 31
Figure 2.16 Classification of the MLI voltage control strategies. .................................. 32
Figure 2.17 Multicarrier PWM with all carrier signals in phase..................................... 37
Figure 2.18 Two amplitude-shifted carrier signals proposed for multicarrier PWM
control........................................................................................................... 38
Figure 2.19 Phase shift carrier PWM for a CHB inverter with three cells. .................... 40
Figure 2.20 Voltage vector diagram of a five-level inverter and the corresponding
switching states. ........................................................................................... 44
Figure 2.21 Hybrid control algorithm structure. ............................................................. 51
Figure 2.22 Factors influencing the selection of the MLI topology and the control
strategy. ........................................................................................................ 54
Figure 3.1 Three-stage hybrid MLI topology. ................................................................ 61
xiii
Figure 3.2 Line A voltage levels of the three-stage inverter for all switching
combinations. ............................................................................................... 62
Figure 3.3 Eighteen-level inverter voltage vector diagram. ............................................ 63
Figure 3.4 The voltage vectors of the three inverter stages and the corresponding
stage states. ................................................................................................... 65
Figure 3.5 The three-stage inverter vector diagram as a result of the individual
stage vectors superposition........................................................................... 68
Figure 3.6 Flow diagram of the voltage vector approximation control algorithm. ......... 69
Figure 3.7 High voltage states domains. ......................................................................... 71
Figure 3.8 Examination of a reference vector with respect to high state domain. .......... 72
Figure 3.9 Zones partitioning of general high voltage stage sector. ............................... 74
Figure 3.10 Zones partitioning of general medium voltage stage sector. ....................... 76
Figure 3.11 Flow chart of nearest medium state selection if-then tree. .......................... 78
Figure 3.12 Low state vectors and their corresponding zones. ....................................... 79
Figure 3.13 The v-w coordinate axis with respect to the d-q axis. ................................. 80
Figure 3.14 v-w-d coordinates of low voltage stage zones. ............................................ 81
Figure 3.15 The g-h axis system. .................................................................................... 85
Figure 3.16 The g-h coordinates of the two-level high voltage stage inverter. .............. 85
Figure 3.17 The g-h coordinates of a three-level inverter. .............................................. 86
Figure 3.18 Voltage approximation control algorithm using g-h coordinate system
calculations. .................................................................................................. 87
Figure 3.19 Voltage levels of the three-stage topology. ................................................. 93
Figure 3.20 Switching variables variation with the time for the 18-level inverter
with a phase reference voltage peak equivalent to 5Vs and multiple
carrier PWM control..................................................................................... 93
Figure 3.21 Flow diagram of the voltage vector control algorithm designed for
MLI............................................................................................................... 96
Figure 3.22 Raw modulation using the g-h axis and normalized reference vector. ........ 98
Figure 3.23 The three triangles types around the reference vector defined to
determine the switching states sequence. ..................................................... 99
Figure 3.24 State sequence assignments according to the reference vector
triangular type. ........................................................................................... 101
Figure 3.25 High voltage stage domains, the areas outside the PWM control
region are marked by dark shade................................................................ 103
xiv
Figure 3.26 The two ranges of reference vector amplitude during which the
inverter is subjected to distortion. .............................................................. 103
Figure 3.27 The proposed modified high voltage stage domains in the inverter
vector space. ............................................................................................... 104
Figure 3.28 Inverter operation with the modified high stage domain. .......................... 105
Figure 3.29 Flow diagram of the SVM control algorithm, the high stage domains
adjusted according to the reference amplitude. .......................................... 106
Figure 4.1 Main units of the MLI system. .................................................................... 109
Figure 4.2 The experimental setup. ............................................................................... 118
Figure 4.3 The reference angle coding used to implicate the sector as the three
MSBs of the angle representation. ............................................................. 119
Figure 4.4 The bit allocation of the GPIOB. ................................................................. 121
Figure 4.5 The switching signal decoder function. ....................................................... 121
Figure 4.6 Flow chart of the voltage vector approximation program. .......................... 122
Figure 4.7 Flow chart of the voltage approximation using g-h transformation. ........... 126
Figure 4.8 The SVM control program flow chart. ........................................................ 128
Figure 4.9 The high state domain condition represented in g-h coordinates. ............... 129
Figure 4.10 Coding used for low voltage stage states to imply the reference type....... 130
Figure 5.1 Load phase voltage of the inverter operating in the voltage
approximation mode with 50Hz frequency and various values of
reference amplitude. ................................................................................... 134
Figure 5.2 Number of levels and harmonic distortion against the reference
amplitude. ................................................................................................... 136
Figure 5.3 The load phase voltage with 80% reference amplitude and the
corresponding voltages due to high-, medium-, and (low+ medium)-
voltage stages. ............................................................................................ 136
Figure 5.4 The load and sources currents of the 18-level inverter with reference
amplitude= 80%. ........................................................................................ 137
Figure 5.5 Phase voltage waveforms of the inverter operating with g-h
approximation mode with 50Hz frequency and various values of
reference amplitude. ................................................................................... 140
Figure 5.6: The fundamental voltage amplitude and the harmonic distortion
against the reference amplitude for inverter operating in g-h
approximation mode. .................................................................................. 142
xv
Figure 5.7 Switching signals at the DSP card port for voltage vector control mode
with 80% amplitude, 50Hz reference signal. ............................................. 145
Figure 5.8 Phase voltage measurements with various values of reference
amplitude. ................................................................................................... 146
Figure 5.9 The inverter phase voltage wave and frequency spectrum, with
reference amplitude of 10%. ...................................................................... 148
Figure 5.10 Spectrum of the output voltage waveform with 80% reference
amplitude. ................................................................................................... 149
Figure 5.11 Build up of the inverter voltage by the three inverter stages from the
top high voltage stage, high and medium voltage stages, and the three
inverter stages. (5msec/div, 50V/div.) ....................................................... 149
Figure 5.12 The phase voltage distortion every 30 with the basic high voltage
domain and 45% reference amplitude. ....................................................... 150
Figure 5.13 Measured THD versus the reference amplitude with the basic high
state domain................................................................................................ 151
Figure 5.14: Measured phase voltage waveforms for various values of reference
amplitude with modified high stage domain. ............................................. 154
Figure 5.15 The phase voltage with 45% reference amplitude and modified high
stage domain. .............................................................................................. 156
Figure 5.16 Phase voltage measurements with M=45% showing the individual
stage voltages with modified high stage domain. ...................................... 157
Figure 5.17 Measured THD versus the reference amplitude for SVM controlled
inverter with modified high stage domain.................................................. 158
Figure 5.18 Optimum harmonic distortion results from switching the domain
between the basic and modified. ................................................................ 158

xvi
List of Tables
Table 2.1 Possible switching combination to achieve various output levels of a 5-
level FC inverter. .......................................................................................... 21
Table 2. 2 Possible switching combination for various output levels of a 5-level
CHB inverter. ............................................................................................... 24
Table 3.1 Next feasible high voltage stage states for the general sector......................... 75
Table 3.2 Next feasible medium voltage stage states for the general sector................... 76
Table 3.3 The integer identifiers of the 19 low state zones. ........................................... 83
Table 4.1 Motor parameters considered in inverters components sizing. ................... 110
Table 6.1 Comparison between the suggested inverter system topology and three
other systems. ............................................................................................. 165
Table 6.2 Comparison of the proposed algorithm with the HPWM and 1-DM
algorithms. .................................................................................................. 169

xvii
List of Symbols
( )
2
Indicates a number represented in binary system.
( )
3
Indicates a number represented in triary system.
( )
A
Refers to a value corresponding to phase A.
( )
h
Indicates a number in represented hexadecimal system.
( )
H
Corresponding to high voltage stage.
( )
i, ii, iii
Refer to the first, second and third specific solutions of a
linear equations.
( )
ini
Initial value.
( )
L
Corresponding to low voltage stage.
( )
M
Corresponding to medium voltage stage.
( )
n
Normalized value.
( )
X
Refers to a value corresponding to the general phase, X.
a A vector constant =1Z120.
c Number of cascaded cells of cascaded H-bridges inverter.
d Duty ratio (p.u.).
f
C
Carrier frequency.
g
ref

The reference vector g-components.
h
ref
The reference vector h-components.
j Number of subintervals within the switching interval.
k Number of equivalent states sharing the same voltage
vector.
l Number of multilevel inverter levels.
M Magnitude control ratio, %.
xviii
n An arbitrary integer
P
i
The polynomial corresponding to the ith low voltage stage
zone.
2 , 2 , 2 w v d
r

Nearest integer rounding of the [(d- , v- and w-
dimensions)+0.5] of the reference vector.
w v d
r
, ,

Nearest integer rounding of the d- , v- and w- dimensions
of the reference vector.
s
ABC
=[s
A
s
B
s
C
]

The general switching state vector.
state
j
j-element switching states vector for one switching period,
T
S.

T
C
Switching sub-interval period / carrier signal period.
t
db
Dead-band time
T
S
Sampling interval.
U
M
Medium voltage stage state the corresponding to a general
sector center vector.
v
AB
, v
BC
, v
CA
instantaneous line-to-line voltages, V.
v
ABC,0
=[v
A,0
v
B,0
v
C,0
] The instantaneous output voltages vector with respect the
reference point denoted by 0, V.
v
An
, v
Bn
, v
Cn
instantaneous line-to-neutral voltages, V.
V
C
DC-side capacitor voltage equivalent to V
DC
/(l-1).
v
d,ref
, v
q,ref
Instantaneous reference voltage vector d-q components.
V
dc
A stages DC voltage.
V
DC
Inverters total DC side voltage or the value of the longest
voltage vector.
v
g,ref
, v
h,ref
Instantaneous reference voltage vector g-h components.
V
H
High voltage stage state the corresponding to a general
xix
sector start vector.
V
H,d
(x) The d-components of the high voltage stage vector
corresponding to state x.
V
H,q
(x) The q-components of the high voltage stage vector
corresponding to state x.
V
ll
Line-to-Line voltage (rms).
V
ll,peak
The peak value of the line-to-line-voltage, V.
V
m
Main stage DC voltage.
V
M
Medium voltage stage state the corresponding to a general
sector start 2V
dc
vector.
v
M
, v
M
Medium voltage stage equivalent states the corresponding
to a general sector start V
dc
vector.
V
M,d
(y) The d-components of the medium voltage stage vector
corresponding to state y.
V
M,q
(y) The q-components of the medium voltage stage vector
corresponding to state y.
V
ph,peak
The peak value of the phase-to-neutral voltage, V.
v
ref
, w
ref
The reference vector v-w components
V
S
Multilevel inverter voltage step.
V
v
Voltage vector
V
v,max
The maximum voltage vector located in the voltage vector
space.
W
H
High voltage stage state corresponding to a general sector
end vector.
W
M
Medium voltage stage state corresponding to a general
sector end 2V
dc
vector.
xx
w
M
, w
M
Medium voltage stage equivalent states corresponding to a
general sector end 2
dc
vector.
x
ABC
=[x
A
x
B
x
C
] High voltage stage switching state vector, binary.
y
ABC
=[y
A
y
B
y
C
]

Medium voltage stage switching state vector, trinary.
z
ABC
=[z
A
z
B
z
C
]

Low voltage stage witching state vector, trinary.
z
H
, z
H
High voltage stage zero states.
ZHi The ith high voltage stage sector zone
ZLi The ith low voltage stage zone
z
M
, z
M
, z
M
Medium voltage stage zero states.
ZMi The ith medium voltage stage sector zone
o
Switching angle.
u
A stage switching variable, (x, y or z).
u
X1,
u
X0
Two-bit to represent the trinary digit u
X
.

Refer to a state of outer vector of the 3-level inverter.
u
ref
Reference vector angle.
o
A three level inverter non-zero state corresponding to an
inner vector of a three level inverter.
o
1
,o
1
Two equivalent os with (one 1
3
and two 0
3
) and ( one 2
3

and two 1
3
)
o
2
o
2
Two equivalent os with (two 1
3
and one 0
3
) and ( two 2
3

and one 1
3
)
,,,,,
The three equivalent zero states of a three-level inverter.

xxi
List of Abbreviations
1-DM Unidimensional modulation.
A Ampere.
AC Alternating current.
ADC Analogue-to-digital converter.
ALU Arithmetic and logic unit.
APO Alternatively opposite amplitude shifted carrier signals.
CHB Cascaded H-bridge.
CCS Code composer studio.
CPU Central processing unit.
DC Direct current.
DSP Digital signal processing.
d-q Direct- quadrature, the orthogonal coordinates axis system.
DTC Direct torque control.
EV Event manager.
FC Flying capacitor.
FOC Field-oriented control.
g-h A 60-displaced two axis system with g along the d-axis.
GPIO General purpose input output.
HPWM Hybrid pulse width modulation.
IER Interrupt enable register.
ISR Interrupt service routine.
I/O Input/ Output.
LSB Least significant bit.
MIPS Mega instructions per second.
xxii
MLI Multilevel inverter.
MSB Most significant bit.
NPC Neutral point clamped.
NZ Nearest zero.
PD Phase disposition amplitude shifted carrier signals.
PIE Peripheral interrupt expansion.
PLL Phase-locked loop
PO Phase-opposite related amplitude shifted carrier signals.
PWM Pulse width modulation.
RMS Root mean square.
SV Space vector.
SVM Space vector modulation.
T0, T1, T2 Timer 0, Timer 1 , Timer 2.
THD Total harmonic distortion.
v-w A 60-displaced two axis system with v axis lags the d-axis by 30.

1
Chapter One
Introduction
1.1 Introduction
This chapter presents the motivations and field of the study and its significance. The
problem statement has been defined and objectives of the study have been listed
followed by the thesis outline.
1.2 Motivation of the Study
Energy, its consumption, reserves and future technologies draw major concern from the
politicians and economists as well as the engineers and scientists. There is a global
concern regarding the fossil fuel, which forms more than 80% of the present world
energy consumption; its unsustainability and harmful environmental consequences are
among the most critical world issues.
The most realistic short- and medium- term solution for the energy reserves and
environment problem is to focus of enhancing the energy efficiency. Energy efficiency
is the practice of reducing the amount of energy used without reducing the end use
benefits enabled by that energy. Energy efficiency includes end-use efficiency and end-
to-end efficiency (EPRI, 2009).
2
Most of the electrical energy generated worldwide is consumed in electrical motors
(Agency, 2009). In many cases, a great increase in motor efficiency can be achieved by
replacing the uncontrolled motors by adjustable speed drives.
This project focuses on one of the major variable speed drives components: the inverter,
and aims to present solution for some critical problems associated with the use of
conventional inverters.
1.3 Electric Drives
The term drive in general refers to motion control system and the electric drive is the
drive that applies the electric motor to produce mechanical power (Dubey, 2001). The
main components of an electric drive system are shown in Figure 1.1. It consists of the
interconnected motor, power converter and controller besides some other supporting
sub-systems or elements such as sensors and protecting elements (Vukosavi, 2007).
The motion control in electric drive is done at its most basic level by the motor torque
M
Power
Converter
Mech.
Load
Power
Supply
Controller
Sensors
signals Command
Signals
Switching
pulses

Figure 1.1 Main components of electric drivers system.

3
control. The speed control and the position control when needed are usually added as an
outer control loops to the inner torque control loop (Bose, 2002).
The electric drive has wide industrial applications. High performance speed and position
controlled drives play vital role in industrial automation. In addition, electric drives
have a very important role in energy saving (Mohan., 2003, Trzynadlowski, 2001),
where most of the energy consumed in industry can be traced back to large electric
motors which are not so demanding in terms of performance, such as pumps,
compressors, blowers etc. By introducing variable speed drives for such applications,
considerable energy saving can be achieved. It has been estimated that the use of
variable speed drives leads to 20-40% of energy saving in several applications.
Currently small portion of the motors used in such applications operate within energy
saving adjustable speed drives systems, while this type of control makes sense for more
than 35% of such industrial drives (Stadler, 2002). Introducing adjustable speed drives
to such application provides ten or more digits number of US dollars worth in energy
saving annually in some large industrial nations (Krishnan, 2001; Stadler, 2002).
Applying the variable speed drives has been extended from the industrial sector to other
applications for the sake of improving performance and efficiency. The energy saving
home appliances, hybrid vehicles, electric wheel chairs, variable speed tools are a few
examples (Wilson, 2010).
The merits of electrical drive system depend on the quality and performance of the drive
components as shown in Figure 1.1. Major enhancement in drives systems has been
achieved by introducing the AC motors to replace the traditional easily controllable DC
motors. AC motors are more reliable, less expensive, with higher power-to-weight ratio
(Chapman, 2005). AC motors, on the other side, are more difficult to control than DC
motors (Boldea and Nasar, 2006). The introduction of AC motors for high performance
drives was only possible with the vector control dynamic model based methods, such as
4
field oriented control, sensorless control and direct torque control (Krause et al., 2002).
These control methods require high speed real time digital controllers.
During the past decades, there has been no remarkable evolution in machines theory,
but the technology development improved the motors characteristics and contributed in
recent important developments such as cost reduction of permanent magnet motors
(Gieras, 2008; Vas, 1998) and enhancing the efficiency of induction motors (Chuvashev
et al., 2009).
Drive controllers achieved considerable boost in the past few decades due to the
advancement in microelectronics and digital systems design fields. Several options are
available for implementing high performance real time strategies (Ice and Akin, 2009,
Kowalski et al., 2007, Shen and Ji, 2007). The developments in control theory and their
application in drives systems contributed also in enhancing the controller performance
(Espinosa et al., 1999).
This research focuses on the third main part of the drive system, the power converter,
which is discussed in the next section.
1.4 Power Converters
Power converter is a semiconductor switches based circuit that is designed to process
the power by adjusting its level and frequency according to the load needs. The most
common adjustable voltage and frequency AC producing converter is the six switch
voltage source inverter (Trzynadlowski, 1998).
Despite its wide spread, conventional inverter causes many problems to the drive
system. Mainly, the current distortion results from the nonsinusoidal voltage waveforms
reduces the motor efficiency and introduces undesirable vibrating torque. Also, as the
inverter output lines switches between zero and full voltage, high and frequent fast
5
voltage rise (represented by high dv/dt) stresses subject the motor isolation to
breakdown (DeWinter and Bin, 1996).
In the course of improving the inverter characteristics, multilevel inverter (MLI) has
been proposed by several researchers. MLI have more than two output voltage levels
and therefore multiple steps of voltage changing rather than one step to full voltage
(Khomfoi and Tolbert, 2006). MLIs have been initially proposed for high voltage and
power applications (Marchesoni, 1992), but due to their ability to produce less distortion
and save switching losses, its application has been extended to other voltage levels
(Chaturvedi et al., 2008).
AC drive inverters are required to produce little distorted current over a wide range of
voltage and frequency variation (Slemon, 1992). In drives, for the speed range below
rated speed, the voltage/frequency relationship is linear with small voltage offset
(Mohan et al., 2003). Unfortunately, this implies that the highest level of harmonic
distortion associated with the lowest voltage amplitude occurs at the lowest frequency.
At this point the motor is least immune to harmonic distortions as the harmonics
filtering inductive reactance is proportional to the frequency (Murphy and Turnbull,
1988). It is common to design the drives to operate the inverter in square wave mode
with the highest voltage demand associated with the high speed region. At lower speed
range the inverter is operated in linear pulse width modulation (PWM) mode where the
dominant harmonics frequency can be controlled by setting the carrier frequency
(Trzynadlowski, 2001).
1.5 Desired Characteristics of AC Drives Inverter
Variable speed AC drives have different levels of performance according to the control
concept. This variety reflects on the specifications of the drives inverter. In this section
6
the demands of the high performance vector controlled drives as well as the basic scalar
drives are highlighted.

a. Wide amplitude and frequency control range
While some applications, such as grid connection applications operate the inverter at
basically constant amplitude and frequency, AC motors require the voltage and the
frequency to be controlled from almost zero to maximum values. The basic method to
change the AC motor speed is by changing the supply frequency. The frequency change
must be accompanied by voltage amplitude change as the motor flux, which is close to
the voltage-to-frequency ratio, is usually maintained around its rated value up to the
rated speed. Accordingly, the inverter control method should be capable to provide the
full voltage and frequency control range.
b. Effective method for harmonics distortion reduction at low voltage range
Harmonics have undesirable effects such as increasing the motor losses and producing
negative mechanical torque and vibration torque. Limiting the harmonics negative
effects is usually done through the inverter control. Appropriate control strategies can
adjust the dominant harmonics frequency to a level that makes the motors inductive
reactance act as a filter that maintain the distortion level within the permissible limit.
To take the added losses due to harmonics into account, motors derating, i.e. oversizing
to account for the additional losses, is common in the drives application besides the use
of AC filters.
c. Sampled reference input for vector controlled drives
The current or voltage vector control methods based on the AC machines dynamic
models, rather than the steady state models, always produces reference voltage values
that are in the sampled, or instantaneous, form. Therefore, the inverter control strategies
7
which are based on full cycle reference, such as switching angles adjustment, are not
suitable for this type of drives.
d. Other generally desired features
Advantageous features are generally required for all kinds of application including
variable speed drives. The most important ones are:
1 Reduced dv/dt stress: It is desirable to avoid the abrupt large voltage changes as it
may lead to partial discharge in the motor insulation that lead to isolation breakdown.
The output LC filter is usually applied for this purpose (Rashid, 2004).
2 Low switching losses: switching losses reduction is desirable for all kinds of
applications. For motor drives there is a special importance for reducing the
switching losses as it directly affect the drives efficiency, reliability and size.
3 Fault tolerance: fault tolerance is the character of being able to continue operating
with some faulty components. This option is usually considered for critical
applications. There will be added cost for this feature as it incurs additional
components and control functions (Xiaomin et al., 2004).
1.6 Problem Statement
There are several crucial characteristics for AC drives inverter, such as wide voltage
and frequency control range, reduced dv/dt and low switching losses. The deficiency or
lacking of the conventional inverter in some of these features led to costly measures
such as motors derating and addition of filters. In some cases it leads to operational
problems such as torque ripple, extra losses or motor breakdown.
The design of MLI for the AC drive application with particular emphasis on using the
MLI features to avoid the conventional inverters drawbacks is the topic of this
8
research. The design includes the inverter topology identification and the inverters
control strategy development.
1.7 Project Objectives
The general aims of this thesis are to design an MLI and develop its control strategy to
meet the AC drives needs. In the inverter design the project focuses on increasing the
number of levels while maintain the inverter circuit size manageable. The control
strategy development is directed to a balanced tradeoff between the switching losses and
harmonics contents. The specific and assessable project objectives are listed as follows:
1- To design and construct a multistage MLI with extended number of levels and
optimized number of switching devices.
2- To reduce inverters cost and improve the devices utilization by considering the
hybrid topologies for the inverter design.
3- To maximize the number of steps of the designed inverter for its topology by
eliminating state redundancy.
4- To develop a voltage approximation technique for hybrid multistage MLI that
ensures switching losses minimization.
5- To form a computationally efficient control algorithm that allows the use of low
cost processors for inverter control.
6- To develop a high quality voltage vector control strategy to operate the inverter
to produce the reference voltage vector with harmonics frequency that can be
adjusted to suit the ripple minimization requirement.
7- To avoid any problematic high switching frequency including simultaneous
stages switching of the multistage inverter.
9
1.8 Thesis Outline
In Chapter 2 a comprehensive introduction about the MLI is presented. The existing
MLI basic topologies are presented with discussion about the features and weak aspects
of these topologies. Chapter 2 also surveys the innovative MLI topologies that do not
belong exactly to any of the basic topologies with emphasis on the multistage
topologies. Control methods have been classified and investigated. The innovative
control techniques and concepts for multistage inverters have been surveyed. Chapter 2
is concluded by relating the control strategies to the inverter topology and the
application, or load type to, the topology and control strategy options.
Chapter 3 presents the inverter design and control strategies. The topology has been
selected. A set of switching variables definition has been presented to simplify the
description of the inverter switching state. Then the inverter voltages as a function of
the switching variables have been derived.
Two novel control strategies have been developed. The first is the voltage vector
approximation strategy which is intended for high to medium voltage and frequency
range. And the second is the voltage vector modulation strategy intended for medium-
to-low voltage and frequency operation. The development of the two control strategies
has been included in Chapter 3.
Chapter 4 presents the practical implementation of the designed inverter and the
developed control strategies. The inverter design includes the switching device
selection, the auxiliary circuits design and the controller selection. The strategies
implementation includes a description of the developed control programs.
The experimental test results are presented in Chapter 5. The two control strategies have
been tested. Switching pulses, voltage and currents measurements have been presented
to demonstrate the inverter performance with the proposed control strategies.
10
In Chapter 6 the results have been discussed. Some figures of merits of the proposed
inverter system have been shown. Comparisons with relevant work have been
conducted. Then achievements of the project objectives have been evaluated.
Chapter 7 presents the study conclusions and provides some suggestion for future
studies as continuation or extension for this study.
All chapters, except the last, started with a short paragraph to describe the chapter
contents and ended with a summary section.
1.9 Summary
The application of adjustable speed AC drives provides considerable saving in energy
besides its importance for industrial applications. The power semiconductor-based
inverter is one of the main drive parts.
Motivated by the conventional voltage source inverter drawbacks, this project aims to
develop an MLI for AC drives system with optimized circuit design and improved
control strategies.
The project objectives have been listed and the thesis outline has been highlighted.

11
Chapter Two
Review of Multilevel Inverters Circuits and Control
2.1 Introduction
Over the past two decades, MLI has been developed and its applications have been
expanded. Literature survey is presented in this chapter to demonstrate the various
approaches and trends that led to the present standing of MLI technology. First the basic
approach and characteristics of MLI are presented. The practical MLI topologies are
classified to basic and innovative topologies. The MLI control methods proposed in the
literature are classified according to the reference input type and switching frequency.
Finally the interrelationship linking the load demands, MLI circuit and control method
has been outlined and indented to provide rational guidelines for topology and control
algorithms design.
2.2 General Background
2.2.1 The concept of multilevel inverters
The most common power electronic circuit to supply adjustable amplitude and
frequency AC voltage is the six-switch inverter shown in Figure 2.1 (Trzynadlowski,
1998). An idealized model of this circuit is shown in Figure 2.2, on which the three
half-bridge branches have been replaced by the ideal two-position switches. Figure 2.2
shows that any inverter output point can be set to have one of two voltage levels,
12
denoted by (p) and (n), therefore the inverter of Figure 2.1 is described as a two-level
inverter.
The two levels output voltage limits the line-to-line voltages possible values to V
DC
, 0
and V
DC
and hence the shape of the output voltage waveforms will be quasi-square and
far from the desired ideal sinusoidal.
The common solution for the output voltage distortion in inverters is the high frequency
PWM switching. This option, despite its effectiveness in current distortion reduction,
has some drawbacks such as higher switching losses, frequent high dv/dt stress,
common mode voltage at the load side, the need for high speed switching devices and
the resultant electromagnetic noise.

V
DC
A
B
C
p
n

Figure 2.1 The three-phase six switch inverter.
V
DC
A
B
C
p
p
p
p
n
n
n
n

Figure 2.2 Idealized model of the three-phase inverter.
13
Consider the hypothetical inverter of Figure 2.3 with l-input multiport switches
connecting the output points to the DC supply with capacitive voltage divider (Bhagwat
and Stefanovic, 1983). In Figure 2.3, the connections are shown between only one
output point (A) and the DC supply for simplicity. Each output point can be connected
to any of the l-input points and hence has l possible voltage levels. The output line-to-
line voltage has (2l1) possible values, this gives the inverter the capacity to produce a
C
l-1
C
1
C
2
C
3
C
l-2
.
.
.
0
DC
V
V
C
V
C
V
C
V
C
V
C
C
V
C
V 2
C
V 3
C
V l ) 2 (
Z
B
Z
A
Z
C
A
B
C
V
AB
V
BC
V
CA
V
DC S
A
S
B
S
C

Figure 2.3 A hypothetical l-level MLI.
V
ll
*
V
ll, 2-level
0
V
DC
V
ll
*
V
ll, l-level
0
(l-1)Vc=V
DC
V
C
V
DC

Figure 2.4 Comparison between the conventional two-level inverter and a five-level
MLI operation to approximate a reference sine wave.
14
stepped waveform which is more close to the ideal sine wave compared that of the two-
level inverter as shown in Figure 2.4.
2.2.2 Multilevel inverters advantages
By comparing the line voltage waveforms of Figure 2.4, we can notice that the
hypothetical MLI outperforms the two-level inverter because of the following:
1- The waveform profile is more close to the pure sine wave which implies reduced
harmonic distortion.
2- The smaller voltage step implies reducing the dv/dt stress on the load and
therefore smaller chance for isolation failure.
3- The availability of higher number of steps eases the need for the high switching
frequency PWM and provides the potential to reduce switching losses.
These features, however, do not represent the only advantages of the MLI; instead the
capability to have a voltage levels beyond the switching device voltage limit is
considered the most important MLI benefit (Jih-Sheng and Fang Zheng, 1995, Tolbert
and Habetler, 1999). MLI practical circuits given in the Section 2.3 explains the total
voltage sharing by switching devices which leads to the inverter higher voltage
capability.
The elimination or the reduction of the common mode voltage represents one of the
MLI advantages. The common mode voltage is the instantaneous analogous of the zero
sequence voltage and it has a harmful effects on the machines loads such as eddy
currents in the motor bearings which leads to overheating and premature breakdown. In
addition to the common mode ground current causes electromagnetic interference
emission and possible trip of protection devices (Hyeoun-Dong and Seung-Ki, 1999).
The common mode voltage equals to the summation of the three output voltages divided
by 3. Therefore the conventional inverter of Figure 2.1 has a common mode voltage of
15
V
DC
/6 or V
DC
/2 when operates to produce nonzero and zero voltages respectively.
Thus, as the voltage wave converges to pure sinusoidal, the common mode voltage
approaches zero. MLI can also eliminate common mode voltage with very limited
number of levels when controlled to operate in the states that produce zero common
mode voltages (Haoran et al., 2000).
The voltage dividing capacitors present at the DC side act as a low pass filter for the DC
current and therefore the current drawn from the DC supply will be of reduced ripple
compared to the basic inverter. The less rippled DC current can be considered as
another advantage of multilevel inverter.
2.2.3 Multilevel inverters drawbacks and limitations
The realization of MLI requires the implementation of multiport switch function using
semiconductor power devices. This can be only done by a complicated network of
switches compared to the conventional inverter. Therefore, MLI applies more devices,
more expensive to implement and more prone to malfunction (Babaei and Hosseini,
2009).
The capacitive voltage divider at the DC side of the inverter shown in Figure 2.3 implies
the need for some means to divide the total DC input voltage. This increases the DC
supply cost and complexity. If this voltage division is done using capacitors it is
required to maintain the capacitors voltage balance (Veenstra, 2003).
The high number of switches combinations implies added control complexity compared
to the basic inverters (Corzine, 2002).
2.2.4 Voltage equations of multilevel inverter
The derivation of the line voltages equation for l-level inverter is given in this section.
Referring to Figure 2.3 and considering the voltage of the output point A with respect to
16
the negative side of the of the DC source denoted by (0). This voltage (v
A,0
) depends on
the position of the switch S
A
and can be represented as:
A
DC
A
s
l
V
v
1
0 ,
= (2.1)
where, s
A
is an l- based digit that represents the position of the ideal multiport switch
(S
A
), where:
| | ) 1 ( , 0 e l s
A
(2.2)
s
A
=n means that S
A
is connected to the upper side of the DC side capacitor C
n
or the
lower side of the capacitor C
n+1
in Figure 2.3. Equations (2.1) and (2.2) can be applied
to the output points B and C. The line-to-line output voltages are given by the following
equations:
(
(
(
(
(
(
=
(
(
(
=
(
(
(
C
B
A
DC
A C
C B
B A
CA
BC
AB
s
s
s
l
V
v v
v v
v v
v
v
v
1 0 1
1 1 0
0 1 1
1
0 , 0 ,
0 , 0 ,
0 , 0 ,
(2.3)
The line-to-line voltages have a maximum of V
DC
and a minimum of V
DC
and uniform
step of V
S
, which is given by:
1
=
l
V
V
DC
S
(2.4)
In Equation (2.4) V
S
is equivalent to the capacitor voltage, V
C
, in Figure 2.3.
Equation (2.3) implies what has been shown in Figure 2.4 that the line-to-line voltage
has 2l1 voltage steps of V
C
each.
17
V
DC
V1
V1 V1
V2 V2 V2
V3
V3
V3
C
C
C
C
A
B C
0
V
DC
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D
C
1
D
C
2
D
C
3
D
C
4
D
C
5
D
C
6
D
C
1
D
C
2
D
C
3
D
C
4
D
C
5
D
C
6
D
C
1
D
C
2
D
C
3
D
C
4
D
C
5
D
C
6

Figure 2.5 Five-level neutral point clamped inverter circuit.
2.3 Basic multilevel inverter Circuits
Various multilevel circuits can be viewed as attempts to implement the hypothetical
inverter of Figure 2.3 using practical semiconductor switching devices. A review of
what has been known as the basic MLI circuits is given in this section. Throughout this
section, the implementation of five-level inverter circuit is shown using the three basic
topologies for explanation and comparison. The three topologies presented are the
neutral point clamped (NPC), the flying capacitor (FC) and the cascaded H-bridge
(CHB) topologies.
2.3.1 Neutral point clamped inverter
Figure 2.5 shows a five-level NPC inverter (Jih-Sheng and Fang Zheng, 1996). From
the DC supply side, we can notice that there are four, i.e. (l-1), capacitors that divide the
18
DC supply voltage (V
DC
) to four equal voltages. The DC source is connected to each
arm of the inverter circuit by five links at points (0, V1,V2, V3, and V
DC
). At any time
each AC lines (A, B, and C) will be connected to one of the five DC supply lines.
As shown in Figure 2.6, to connect an output point to V
DC
, transistors (Q1-Q4) must be
turned ON while transistors (Q5-Q8) are turned OFF. The connection will be
established through the four series connected transistors, or their anti-parallel diodes.
Other levels of output voltage are achieved by switching ON four successive switches
as shown in Figure 2.6. The connection will be continued through one of the six
clamping diodes when the output voltage is at one of the three middle levels (V1, V2 or
V3). For example, to connect an output point to V2, switches (Q3-Q6) will be turned
ON. In this case if the load current is positive this current will be flow through D
C
2 to
Q3 and Q4, while the negative load current will be conducted though Q5-Q6 and to
D
C
5.
V1
V1 V1
V2 V2 V2
V3
V3
V3
C
C
C
C
V1
V2
V3
V1
V2
V3
o/p
o/p o/p o/p
o/p
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D
C
1
D
C
4
D
C
2
D
C
5
D
C
3
D
C
6

(a)V
o/p
=V
DC
(b) V
o/p
=V
3
(c) V
o/p
=V
2
(d) V
o/p
=V
1
(e) V
o/p
=0
Figure 2.6 Output point voltage switching among the five voltage levels of NPC
inverter.
19
As shown in Figure 2.6, the current passes through a number of switching devices
ranges between (l1) to 2. And each switching device is subjected to an OFF-state
voltage of V
DC
/(l1). The clamping diodes, however, are subjected to various voltage
levels depend on their position, but the maximum voltage to be blocked by clamping
diode is equivalent to V
DC
(l2 )/(l1) and this value converges to V
DC
as l increases.
In high voltage inverters it is highly desirable to have all devices subjected to equal
voltages of (V
DC
/(l1)) to enable the construction of inverters with high voltage ratings.
This has been achieved for the NPC inverters controlled switching devices (Q1-Q8).
But the clamping diodes need to block different voltages of maximum voltage that
would be close to the total DC input voltage as l increases. To overcome this problem
and bring the clamping diodes voltage ratings to V
DC
/(l1), the pyramid arrangement
shown in Figure 2.7 has been suggested (Xiaoming and Barbi, 2000). One inverter leg is
shown for simplicity. With this arrangement, the numbers of component required to
V
DC
V1
V2
V3
C
C
C
C
A 0
V
DC
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8

Figure 2.7 Structure of pyramid voltage divider for five-level NPC inverter arm.
20
construct l-level NPC inverter are:
- (l1) voltage divider capacitors.
- 6(l1) switching devices.
- 3(l1)(l2) clamping diodes
The quadric relationship makes the number of diodes escalates fast as the number of
level increases.
Capacitors voltage balancing is the main challenge in the control of NPC inverter which
needs to be carefully handled by the controller (du Toit Mouton, 2002; Chen and
Xiangning, 2006).
2.3.2 Flying capacitor inverter
A five-level FC inverter is shown in Figure 2.8, only one inverter leg is shown for
simplicity. The voltage across each of the 10 capacitors (Vc) is maintained to the level
V
DC
C
C
C
C
A
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
C1
C2
C2
C3
C3
C3
V1
V2
V3
V
c
V
c
V
c
V
c
V
c
V
c
V
c
V
c
V
c
V
c

Figure 2.8 One arm of a five-level flying capacitor MLI.
21
of V
DC
/4. The series connected capacitors C2 and C3 are drawn to indicate the voltage
levels and to have all the capacitors of the same voltage rating for cost comparison.
The FC inverter provides more flexibility in the switching compared to the NPC
inverter. To obtain the five voltage levels at the output points, the possible switching
combinations are shown in Table 2.1. The last three columns indicate the change of the
flying capacitors charge under the corresponding switching status assuming positive
load current. This flexibility is used to maintain capacitors voltage balance (Corzine and
Kou, 2003).
It can be noticed from Figure 2.8, that the l-level FC inverter requires:
- 6(l1) switching devices,
- (l-1) voltage divider capacitors, and
- 3[(l-1)(l-2)/2] flying capacitors.
Table 2.1 Possible switching combination to achieve various output levels of a 5-level
FC inverter.
Sw.
V
A

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Capacitor
charge
(,, -)*
C1 C2 C3
V
DC
1 ON ON ON ON OFF OFF OFF OFF - - -
V3
1 ON ON ON OFF ON OFF OFF OFF - -
2 OFF ON ON ON OFF OFF OFF ON - -
3 ON OFF ON ON OFF OFF ON OFF -
V2
1 ON ON OFF OFF ON ON OFF OFF - -
2 OFF OFF ON ON OFF OFF ON ON - -
3 ON OFF ON OFF ON OFF ON OFF
4 ON OFF OFF ON OFF ON ON OFF -
5 OFF ON OFF ON OFF ON OFF ON
6 OFF ON ON OFF ON OFF OFF ON -
V1
1 ON OFF OFF OFF ON ON ON OFF - -
2 OFF OFF OFF ON OFF ON ON ON - -
3 OFF OFF ON OFF ON OFF ON ON -
0 1 OFF OFF OFF OFF ON ON ON ON - - -
* : charging, : discharging : - steady

22
As for the number of diodes in the NPC inverter, in FC inverter the number of flying
capacitors has a quadric relationship to the number of levels.
2.3.3 Cascaded H-bridges inverter
A five level cascaded H-bridge inverter is shown in Figure 2.9 (Tolbert and Habetler,
1998). Each inverter arm is composed of a number of full-bridge units and their outputs
are connected in series. Each unit is supplied by a DC voltage denoted by V
S
and its
output voltage will be:
- (+V
S
) when (Q1 and Q4) are ON
- 0 when (Q1 and Q3) or (Q2 and Q4) are ON
- (V
S
) when (Q2 and Q3) are ON
Therefore, the full bridge unit can be viewed as an arm of a three-level inverter. Two
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
A
B C
Vs
Vs
Vs
Vs
Vs
Vs
C1 C1
C1
C2 C2 C2

Figure 2.9 Five-level cascaded H-bridge inverter.
23
series connected units, as shown in Figure 2.9, provide arm voltage that ranges from
+2V
S
to 2V
S
with a step of V
S
or 5-level voltage. In general the c -cells per arm
inverter has (l= 2c+1) levels.
The number of switching combinations to achieve certain output voltage level in a CHB
inverter depends on c and the required voltage level. In any case, the CHB topology
provides maximum flexibility compared to the previous two topologies. The number of
switching combinations to achieve various arm voltages for 3, 5, 7, and 9 -level
inverters are shown in Figure 2.10. For 5-level inverter, for example, it is shown that the
voltage levels of 0, V
S
and 2V
S
can be achieved with 6, 4 and 1 switching
combinations as listed in Table 2.2. This flexibility can be used to minimize the
switching actions, balance devices current or other purposes decided by the designer.
1
2
1
1
1
1
1
1
1
8
28
28
8
52
52
72
4
6
6
15
20
4
6
15
C1
C2
C3 C4
0
Vs
2Vs
3Vs
4Vs
Vs
2Vs
4Vs
3Vs
3
-
l
e
v
e
l

5
-
l
e
v
e
l

7
-
l
e
v
e
l

9
-
l
e
v
e
l

Figure 2.10 Number of possible switching combinations to achieve various arm
voltages for various CHB levels.
24
The three-phase, l-level CHB inverter applies 6(l1) switching devices. Other than the
switchs anti-parallel diode, no additional diodes are required. The voltage and current
ratings of the switching devices in this case is similar to those of the two previous
circuits, where each switch carries the load current and operates with 50% duty ratio.
The turned off device is subjected to a voltage of V
S
which is equivalent to V
DC
/(l1).
There is no essential need for capacitors. The number of components of the CHB
inverter is linearly proportional to the number of levels, while in NPC and FC inverters
the number of some devices is proportional to the square of inverter levels. Other
advantages for this topology are its modular structure; where the inverter is composed
of identical cells, besides the flexibility provided by the large number of switching
Table 2. 2 Possible switching combination for various output levels of a 5-level CHB
inverter.
Cell
V
A
\
C1 C2
C1 C2
V
o,C1
V
o,C2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
2V
S

V
S
V
S

ON OFF OFF ON ON OFF OFF ON
V
S

V
S
0
ON OFF OFF ON ON OFF ON OFF
V
S
0
ON OFF OFF ON OFF ON OFF ON
0 V
S

ON OFF ON OFF ON OFF OFF ON
0 V
S

OFF ON OFF ON ON OFF OFF ON
0
V
S
V
S

ON OFF OFF ON OFF ON ON OFF
0 0
ON OFF ON OFF ON OFF ON OFF
0 0
ON OFF ON OFF OFF ON OFF ON
0 0
OFF ON OFF ON ON OFF ON OFF
0 0
OFF ON OFF ON OFF ON OFF ON
V
S
V
S

OFF ON ON OFF ON OFF OFF ON
V
S

0 V
S

ON OFF ON OFF OFF ON ON OFF
0 V
S

OFF ON OFF ON OFF ON ON OFF
V
S
0
OFF ON ON OFF ON OFF ON OFF
V
S
0
OFF ON ON OFF OFF ON OFF ON
2V
S

V
S
V
S

OFF ON ON OFF OFF ON ON OFF

25
combinations at the middle voltage levels. The main drawback, however, is the need for
large number of isolated DC supplies where the l-level inverter requires (1.5(l1))
isolated DC supplies.
2.4 Innovative Multilevel Inverter Topologies
It has been found that more effective designs in terms of overall cost, number of levels,
losses and device utilization can be achieved by modified or hybrid designs which are
derived from the basic topologies with some modifications. Many researchers have
introduced designs that belong to this category (Rodriguez et al., 2009). In this section,
description for the three most common categories of these designs is presented.
2.4.1 Asymmetrical CHB inverters
The large number of switching combinations available for the middle voltage levels of
the CHB topology has been described by some researches to be redundant (Rotella et
al., 2009). It has been shown that a CHB inverter of a given number of cells per arm can
produce more levels if the cascaded cells are fed by unequal voltages (Mariethoz and
Rufer, 2004a). Altering the design of the CHB inverter by simply supplying the arm
cells by unequal voltages results in an asymmetrical CHB inverter.
To show the effect of unsymmetrical DC sourcing, consider Figure 2.11 which shows
an inverter similar to the five-level inverter shown in Figure 2.9 except that the cells C2
are fed by a voltage equals to 2V
S
while C1 cells are still supplied with V
S
. The inverter
output voltage v
A,0
now can take the values range between +3V
S
to 3V
S
with steps of
V
S
, which leads to seven levels output voltage.
Studies considered the various voltage levels have concluded that the maximum number
of uniform voltage steps for asymmetrical CHB inverter are achieved when the DC
26
voltages of the cascaded cells are related by the ratio of three, i.e V
S
, 3V
S
, 9V
S
, etc.
With this voltage selection the c-cells per arm inverter will have 3
c
levels (Kadir and
Hussien, 2005). Therefore the number of levels is exponentially, rather than linearly,
proportional to the number of components applied. This ratio has some limitation which
is discussed in detail in the next chapter.
While the conventional MLI design aims to divide the input voltage equally between the
switching devices, asymmetrical MLI design depends on the feature of semiconductor
switching devices technology which implies a tradeoff in device selection in terms of
switching frequency and voltage sustaining capability (Rodriguez et al., 2002a;
Mariethoz and Rufer, 2004b; Lai and Shyu, 2002). The main or higher voltage inverter
stage handles the highest voltage is justified when this stage operates at lowest
frequency compared to other stages where slow high rating switching devices such as
GTO or IGCT can be employed if the inverter is to be constructed with high voltage
ratings.
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
A
B C
2Vs
Vs
2Vs
Vs
Vs
2Vs
C1 C1
C1
C2 C2 C2
0

Figure 2.11 Asymmetrical CHB inverter.
27
0
2Vs
C
C
Q1
Q2
Q3
Q4
Vs
Vs
5
-
l
e
v
e
l

H
-
B
r
i
d
g
e

u
n
i
t
Q1'
Q2'
Q3'
Q4'
2Vs
C
C
Q1
Q2
Q3
Q4
Vs
Vs
5
-
l
e
v
e
l

H
-
B
r
i
d
g
e

u
n
i
t
Q1'
Q2'
Q3'
Q4'
9
-
l
e
v
e
l

I
n
v
e
r
t
e
r

A
r
m

Figure 2.12 Cascaded mixed topology H-bridges to construct a 9-level inverter.
Despite the obvious advantages of asymmetrical multilevel inverter in its capability to
increase the number of levels for the same circuit topology, the large number of isolated
DC sources required is still considered as a major limitation. Several alternatives
discussed in the following subsections deal with this drawback.
2.4.2 Mixed-level topologies
The mixed topology cell has a cell composed of a multilevel NPC or FC arm rather than
the simple half bridge arm. Figure 2.12 shows a cascaded MLI arm composed of a five-
level rather than three-level cells. The cell voltage ranges from +2V
S
to 2V
S
with a
step of V
S
, therefore it forms a 5-level inverter. The c-cells branch forms a (4c+1) level
arm. The arrangement provides saving in isolated DC supplies compared to the CHB
28
inverter and saving in diodes and circuit complexity compared to NPC and FC
topologies (Gupta and Khambadkone, 2007; Leon et al., 2008; Zhou and Li, 2008).
2.4.3 Hybrid inverter topologies
The term hybrid cascaded, or multistage inverter, or in short hybrid inverter used by
many authors to refer to any inverter constructed by smaller dissimilar stages.
Accordingly, the asymmetrical CHB inverter has been described using the term
hybrid by some authors (Manjrekar and Lipo, 1998; Manjrekar et al., 2000; Zhong et
al., 2009). In this thesis we will refer to an inverter as hybrid if at least one of the
cascaded stages is of different topology from other stages, or if the stages outputs are
not directly connected in series.
The main aim of the hybridization is to reduce the DC supply cost by reducing the
number of desired DC supplies as this number is still considered the major drawback of
the asymmetrical MLI.
Hybrid MLIs have been constructed in several topologies in the following subsections.
We are going to present three groups of the suggested topologies found in the literature.
V
S
V
m
C B
A
Main inverter
Harmonics reduction subinverter
V
S
V
S

Figure 2.13 Hybrid inverter with a two-level 6-switch main stage.
29
2.4.3.1 The use of singly-fed main stage
Hybrid multilevel inverters have been constructed by replacing the highest voltage stage
of the asymmetrical MLI by singly-fed stage. Mariethoz and Rufer (2004a, 2006)
proposed the configuration of a main two-level conventional inverter connected to
harmonics reduction CHB stage to reduce the DC source cost. The voltage ratio of the
main to harmonics reduction stages, (V
m
/V
S
) according to Figure 2.13, has been studied.
It has been shown that the harmonics reduction stage needs DC supplies with
bidirectional current capability (Mariethoz and Rufer, 2006). Further improvement has
been achieved by replacing the harmonic reduction stage DC supply by capacitors
(Haiwen et al., 2008).
Veenstra and Rufer (2003) used a three level NPC stage as a main inverter supplied by a
unidirectional DC source. The harmonic reduction cells DC sides have been connected
to capacitors that are charged to the desired voltage during initialization stage. The
inverter is controlled to assure that the harmonic reduction stage supplies zero average
power. Supplying the harmonics reduction stage by capacitors saves the cost of the DC
supply considerably but the inverter is difficult to control, highly nonlinear, time-
varying and operation point dependent. Similar topology is used by Jianye and
Yongdong (2007) and the ultra capacitors at the DC side of the harmonic reduction H-
bridge cells used when the load motor in braking mode to save the braking energy and
reuse it in the motoring mode.
Yun et al. (2007) connected a five-level NPC main stage to one CHB stage, both
supplied with equal voltages to construct a 9-level inverter.
2.4.3.2 Transformer-isolated multistage inverters
The number of required DC supplies of the multistage MLI can be reduced to one by
isolating the cascaded stages outputs using isolating transformer that has multiple
primary windings as shown in Figure 2.14. The n inverters could be of similar or they
30
could be of different topologies (Ortuzar et al., 2003; Kang, 2009; Fukuda et al., 2009).
The selection of the turns ratio of the cascaded stages (N1, Nn) has the effect of
varying the stage voltage step and used to increase the number of levels. Further, the
transformers wye-to-delta windings connections provide a 30-phase shift that has been
used to extend voltage amplitude limit (Fukuda et al., 2009).
Ortuzar et al. (2003) modified the four-stage, 81-level CHB asymmetrical inverter by
using a transformer of multiple primary windings with turns ratio of 3 (i.e. N2=3N1,
N3=3N2 etc.). The DC side has been connected to ultra capacitor where the inverter
is used as a shunt active filter supplying reactive power.
The use of multiple-primary transformer reduces the DC-source cost, this design,
however, is suitable only for inverters with fixed output frequency (line frequency).
When the desired frequency has a wide range with very small minimum frequency
values the transformer size to operate in such low frequencies becomes impractical.
Inverter 1
Inverter n
Multiple -
primary
transformer
V
DC
N1
N
n
vo

Figure 2.14 A single-phase diagram of a singly-fed transformer-isolated multistage
inverter.
31
2.4.3.3 Inverters for open windings loads
This arrangement is applicable only for loads with open windings as for some models of
AC machines. Figure 2.15 describes the open winding inverter configuration. In this
configuration the two inverters connected to the two load sides could be of two or more
levels with identical or different topologies (Gopinath et al., 2009; Keivani et al., 2006).
The number of DC supplies can be reduced to one if inverter 2 is controlled to stabilize
its DC side capacitor (Keivani et al., 2006). When the two subinverters are similar in the
number of levels (l) and DC voltage, the resultant inverter will be a (2l1) level
inverter.
Shuai et al. (2007) used two three-level NPC inverters at the two sides of the machine.
The DC side of the second inverters is connected to ultracapacitors. The controller
maintains the capacitors voltage to one third of that of the first, or main, inverters DC
supply. The resultant 9-level singly fed inverter is proposed for vehicle propulsion
drive.
Rotella et al. (2009) used open winding machine to eliminate two of the three DC
supplies of three-stage asymmetrical-CHB MLI, and hence to considerably reduce the
DC supplies cost.

Open-windings motor load
Inverter 1 Inverter 2
Main dc
supply
VS

Figure 2.15 Two cascaded inverters to feed open windings motor.
32
2.5 A View on Multilevel Inverter Control
Concurrent to the development of MLI topologies, the need for suitable control methods
emerged. Compared to the two-level traditional inverter control, MLI control is more
complex. This complexity, however, implies a positive side; it provides more freedom
by having several solutions for a given desired control performance. The multiple
solution options could be utilized by the designers to achieve some additional targets
(Leon et al., 2009a).
MLI control algorithms are classified according to Figure 2.16. This figure reveals that
there are many control methods proposed for MLIs. Many of these methods are simply
an extension from their two-level ancestors. In Figure 2.16 the first level of
classification divides the control methods according to the reference voltage type:
MLI
control
Sampled
reference
Full-cycle
reference
Low
frequency
High
frequency
Hybrid
methods
Low
frequency
High
frequency
Angle
adust.
Selected
Harmonic
elimination
Carrier
comparison
Amplitude-
shifted
carriers
Phase-
shifted
carrier
Modified
carrier
SV
modulation
Carrier
based SV
Vector
Approx.
Amplitude
Approx.
Vector-
based SV
1-dimens.
modulation

Figure 2.16 Classification of the MLI voltage control strategies.
33
sampled or full-cycle reference. For the sampled reference only the instantaneous
amplitudes of the next desired voltages are given to the controllers, while the full cycle
reference assumes a sinusoidal output voltage and the controller is provided with the
desired sine wave amplitude, frequency and, in some cases, the phase angle. Note that
the sampled reference based methods can be operated with a full-cycle reference while
the opposite is not true.
The reference type classes have been subdivided according to the switching frequency.
The low frequency here indicates up to few multiples of the fundamental frequency,
while the high switching frequency range starts at 1 kHz.
The detailed explanation of the full cycle reference methods is presented in Section 2.6,
while the sampled reference methods are discussed in Section 2.7.
2.6 Full-Cycle Reference Voltage Control Methods
When the inverter switching signals are defined as a function of the reference voltage
amplitude, frequency or phase angle, the full cycle of the reference voltage must be
known to implement this control strategy. The reference amplitude is commonly defined
through the amplitude modulation index, M. In this case the reference voltage is usually
considered to be sinusoidal and represented by two or three parameters of the general
sine wave: amplitude, frequency and, sometimes, phase angle.
2.6.1 Low switching frequency control
As mentioned in Section 2.1, MLI is capable of producing multiple voltage levels, and
therefore can produce stepped wave that is a close approximate of the desired pure sine
wave. Low frequency control methods count on the multiple steps feature to save the
34
switching losses. This method is suitable and sufficient when the number of levels is
sufficiently high (Yu and Fang Lin, 2008).
The low frequency methods differ in the objectives that determine the switching angles.
The most common two objectives which are discussed in the following subsections are
to minimize the total harmonic distortion (THD) and to eliminate the lowest order
harmonics.
2.6.1.1 Harmonic distortion minimization
Early suggestion of the multilevel inverter presented the analysis of a three-level
inverter operating with two switching angles per quarter cycle, i.e. the full amplitude is
reached by two voltage steps. The control method is extended from the conventional
inverters quasi square wave switching. The switching angles to obtain minimum THD
have been derived and these found to provide about 50% reduction in THD compared to
the conventional inverter (Bhagwat and Stefanovic, 1983).
One development has been presented by Yu et al. (2009), where a real-time switching
angles calculation has been proposed in order to minimize the THD for varying
reference voltage amplitude.
2.6.1.2 Selected harmonics elimination
The l-level inverter has up to (l1) steps per quarter cycle. Assuming one switching
action for each step, there are (l1) independent switching angles. Fourier series
expression of the voltage waveform is a function of (l1) switching angles. The concept
of the optimum control or selected harmonics elimination is to set the switching angles
to satisfy (l1) conditions as follows:
- one condition to produce the desired fundamental component amplitude, and
- (l2) conditions to eliminate the lowest (l2) harmonics.
35
Wanki et al. (1999) constructed seven-level inverter using three-stage CHB. This
inverter is controlled by individual quasi square wave control of each stage, i.e. each
stage is treated as a single phase full bridge unit that produces quasi square wave
voltage. The three switching angles for the three stages provide three degrees of
freedom that have been used to eliminate the three lowest order harmonics. No clear
explanation has been given on how the fundamental has been controlled and obviously
this method does not fully utilize the inverter capability.
Dahidah and Agelidis (2005) used Gauss-Newtons method based nonlinear equation
solver to determine the switching angles of a five-level inverter. It has been shown that
the three lowest order harmonics have been eliminated.
Due to the nonlinearity of the equations, the solution is not easy and it is usually done
offline to generate a switching angles lookup table for various fundamental amplitudes.
Jingang and Tianhao (2007) used genetic algorithm for providing the solution for the
equations. The switching angles of 11-level inverter have been determined to reduce the
amplitude of the four lowest order harmonic to less than 1%.
Agelidis et al. (2008) proposed the multiple selected harmonics elimination PWM for a
five-level inverter. With 17 switching angles per quarter cycle, the fifteen lowest order
harmonics has been eliminated. The minimization technique has been used to solve the
large number of the nonlinear transcendental equations and generate solution tables.
Dahidah and Agelidis (2008) used the genetic algorithm cost function to simplify the
solution of the selected harmonic elimination equations of five and seven level
inverters. For the asymmetrical CHB inverter, fundamental frequency operation of the
higher voltage stage has been imposed.
Zhong et al. (2009) combined the selected harmonics elimination with voltage balancing
control, where a seven level unsymmetrical CHB inverter has been considered with the
lower DC voltage cells connected to capacitors. The control is designed to maintain the
36
balance of the capacitors voltages by selecting the appropriate one of the two equivalent
states to charge or discharge the capacitor. The switching angles to eliminate the 5
th
and
7
th
harmonics have been calculated for various values of the modulation depth to form
the controller look-up table.
Chung-Ming et al. (2009) studied the elimination of the 11st, 13th, 23rd and 25th
harmonics of a transformer isolated two-stage inverter. The zigzag isolation
multiwinding system cancels all the harmonics except those of order 12n1. Therefore
the offline calculations have been used to generate a lookup table of the angles that
eliminate the above mentioned harmonics. The proposed real time implementation uses
approximation polynomials derived from the obtained curves to determine the switching
angles as quadric functions of the modulation index.
2.6.2 High frequency carrier comparison PWM methods
Due to the limited number of voltage levels that can be achieved with the basic
topologies, the low frequency methods suffer from the presence of low order voltage
harmonics. Therefore high frequency switching has been introduced. The high
frequency methods are mainly modified from the basic two-level PWM with several
modifications in the carrier signals as shown in the following subsections.
2.6.2.1 Amplitude-shifted carrier PWM
The first common multilevel PWM is the multicarrier PWM proposed by Carrara et al.
(1992) by extending the PWM concept as fast switching between the inverter voltage
levels that are higher than and lower than the desired voltage. The technique implies
that to control an l-level inverter, l1 carrier signals are generated. The carrier signals
are triangular waveforms and shifted by a DC offset level equivalent to the peak-to-peak
amplitude of the carrier signals as shown in Figure 2.17. In that study, three types of
37
carrier signals have been considered, which are besides the all carrier signals in phase
(PD) shown in Figure 2.17, the all carriers are alternatively opposite (APO) and the
carriers above zero are in phase and opposite to the carriers below zero (PO) as shown
in Figure 2.18.
Carrara et al. (1990) presented mathematical analyses for the three carrier types
assuming a 3- and 5-level single-phase inverter and harmonics spectra has been shown.
It has been found that for PD strategy, the dominant harmonics are the carrier frequency
component. For APO and PO carriers, the dominant harmonics are at the side bands of
the carrier frequency. The results also demonstrated the quality superiority of the five-
level inverter over the three-level inverter.
0
V
DC
/4
V
DC
/4
V
DC
/2
Carrier signals
1/fc
Reference signal
Five-level inverter voltage
V
DC
/2

Figure 2.17 Multicarrier PWM with all carrier signals in phase.
38
Sinha and Lipo (1997, 2000) used the PD carrier comparison technique to control a
four-level NPC inverter. Del'Aquilla et al. (1997) implemented a digital algorithm that
emulates the carrier comparison process for five-level inverter using a microprocessor.
Concurrent to the method suggested by Carrara et al. (1990) and Steinke (1988)
suggested the switching frequency optimal PWM (SFO-PWM) for three-phase three-
level inverter. This method has the same concept except that a common mode triple
harmonics has been added to the reference voltage to increase the maximum output
voltage.
Another study by Menzies and Yiping (1995) considered the effect of shifting angle
between the modulating reference and the carrier waveforms. The shifting angle has
been changed incrementally and the resultant switching losses and THD have been
1/fc
V
D
C
/
(
l
-
1
)
All Carriers Alternatively in Opposition (APO)
V
D
C
/
(
l
-
1
)
1/fc
Opposite Polarity Phase Opposition (PO)

Figure 2.18 Two amplitude-shifted carrier signals proposed for multicarrier PWM
control.
39
compared, it is concluded that this method can be used to reduce the switching losses.
Tolbert and Habetler (1998; 1999) combined the carrier angle phase shifting with
reduced carrier frequency of the top and bottom carrier signals to balance the switching
rate of all the switches of 6-level NPC inverter.
Haoran et al. (1998, 2000) modified the carrier comparison technique to eliminate the
common mode voltage. For three-level inverter, one carrier signal has been used instead
of two. And the phase switching signal has been calculated as a difference of two
comparisons; one the carrier with the corresponding phase reference and the other with
the lagging phase reference.
McGrath and Holmes (2002a) performed mathematical analysis to show why particular
fundamental and carrier phase relationships have distinct harmonic advantages when
used in multilevel cascaded inverter topologies. The analysis led to explanation to the
resultant voltage spectrum that helps to select the optimum phase relation between the
modulation and carrier signals. These analyses have been extended to over modulation
region (McGrath and Holmes, 2002b).
2.6.2.2 Phase-shifted multicarrier
The phase-shifted carrier PWM (PSCPWM) is proposed for CHB inverter (Yiqiao and
Nwankpa, 1999). Using this approach, the sinusoidal reference waveforms for the two
switch branch of each inverter are phase shifted by 180 , while each inverters carrier is
phase shifted by T
C
/c, where T
C
is the carrier period and c is the number of H-bridge
cells per inverter arm. With this strategy the harmonics appear as a side band around the
frequency (2c/T
C
) and its multiples (Holmes and McGrath, 2001). Figure 2.19
illustrates the carrier and reference waveforms for a single phase arm of seven levels,
i.e. three cascaded cells inverter. This method, besides its higher order harmonics
advantage balances the loading and the switching frequency of the CHB cells.
40
Ts
Ts/3
Vref
Vref
Vcar1 Vcar2 Vcar3
Varm
Vs
2Vs
3Vs

Figure 2.19 Phase shift carrier PWM for a CHB inverter with three cells.
2.6.2.3 Other modified carrier signals
Kouro et al. (2008) considered the capacitors voltage unbalance and developed adaptive
carrier based PWM for both amplitude-shifted and phase-shifted multicarriers. The
adaptive modulator measures the DC link voltage and feed-forward it to modify the
carrier signals to compensate for voltage fluctuations. Zaragoza et al. (2009a, 2009b)
presented hybrid modulation strategy based on combining low and high frequency
control methods by developing a special discontinuous modulating signals. The most
important feature of this discontinuous reference is the control of the capacitors voltage
ripple of the NPC converter.
Rotella et al. (2009) considered an asymmetrical CHB inverter and aimed to eliminate
the lower voltage stage DC sources and replace it by capacitors. The PWM control has
been introduced to the level-approximation controlled inverter. The suggested control
41
method avoids certain voltage level and replaces them by a combination charging and
discharging adjacent levels with PWM-adjusted duty ratio to maintain the capacitor
voltage.
2.7 Sampled Reference Control Methods
When the reference desired voltage is given in the sampled form there is no direct
information about the desired output voltage amplitude, frequency and phase angle and
therefore the switching functions cannot be defined in terms of these parameters. This
section presents control methods designed to generate the switching signals using
sampled reference.
2.7.1 Low frequency control methods
The low frequency control methods are usually approximation methods that provide one
fixed output voltage over the sampling interval. The priority in these methods is given
to efficiency rather than high accuracy.
2.7.1.1 Voltage vector approximation
The voltage vector approximation method suits the inverters with a large number of
levels. The l-level inverter has (3l(l1)+1) equally-spaced voltage vectors in its
voltage space diagram. This number is proportional to the square of the number of
levels. When there is sufficient high number of levels, any reference voltage vector in
the vector space can be approximated to the nearest inverter vector with the desired
accuracy.
This concept was first suggested by Rodriguez et al. (2001, 2002b) and applied to 11-
level inverter constructed using 5-cell per arm CHB inverter. Normalization is applied
to make the normalized inverter vectors coordinates integers. The nearest inverter vector
42
is determined by comparing the higher and lower nearest integers of the reference
vector coordinates to a pre-generated table of the corresponding values of the inverter
vectors and selects the inverter vector accordingly.
The same method is applied to a four-cell per phase asymmetrical CHB with the
maximized 81-levels by Yu and Fang Lin (2008). This inverter has been constructed
with DC sources with bidirectional current capability to ensure that the DC voltages of
all the cells are at the desired levels.
The low switching frequency and control simplicity are the basic advantages of this
method. As for the control complexity, however, it has to be indicated that the
determination of the target inverter vector is only the first controllers task. This vector
is associated with k-equivalent states where k is the depth of the target inverter vector
hexagon as shown in Figure 2.20. So as the reference vector amplitude reduces, the
inverter target vector will be located further form the outer layer and the number of the
states associated with this vector will be increased. The selection of a particular
switching state among the equivalent states will add more computational time and need
to be optimized according to certain target or targets.
2.7.1.2 Voltage amplitude approximation
Jih-Sheng and Fang Zheng (1996) proposed a control method for a five- and six-levels
inverters by selecting the switching state that produces the output voltage which is
nearest to the reference output voltage. The same approach has been used to control the
11-level CHB inverter (Peng et al., 1997; Fang Zheng et al., 1998; Tolbert and Peng,
2000).
This method is the simplest control method and even with low number of switching
angles it has been considered for low power high frequency applications such as
electrostatic induction micromotors (Neugebauer et al., 2002).
43
With limited number of levels the stepped voltage has considerable distortion that
would not be permissible for many applications.
Asymmetrical CHB inverters designed with maximized levels produce nearly sinusoidal
waveforms and, therefore, this method can be effective due to its simplicity (Abdul
Kadir and Hussien, 2004).
2.7.2 High switching frequency methods
2.7.2.1 Basic multilevel SVM
The representation of the three-phase set of voltages as a voltage vector is drawn from
Park transformation
Cn Bn An
av av v v + = , (2.5)
where a is the 120 rotation operator, a=1Z120, v
An
, v
Bn
and v
Cn
are the load phase
voltages. This transformation provides a representation of the three-phase voltage as a
voltage vector in the two-dimensional plane known as the vector space. There are some
references that multiply right side of Equation (2.5) by (2/3), to result in a vector length
equivalent to the peak of the phase voltage (Bose, 2002) or ) 3 / 2 ( (Shoulaie et al.,
1997). In this thesis the voltage vectors are determined according to equation (2.5) and
therefore the voltage vector amplitude is equivalent to 1.5 times the phase voltage peak.
The inverter vector diagram is obtained by plotting the vectors corresponding to all the
inverter states, resulted by applying Park transformation on the resultant phase voltages.
The number of inverter vectors is less than the inverter states as there are always
equivalent states that produce the same voltage vectors. The l-level inverter has l
3

switching states and (1+3l(l1)) voltage vectors. The vector diagram of a five-level
inverter vectors is shown on Figure 2.20. The inverters vector diagram is a hexagonal
44
area with side length equivalent to the maximum voltage between two inverter output
lines.
Any reference voltage vector within the hexagonal vector diagram can be represented as
sum of different portions of the three nearest vectors using the basic geometrical
equations (van der Broeck et al., 1988). The concept of the space vector modulation is
based on constructing the reference voltage vector from components of the three nearest
inverter vectors. During the sampling period the inverter operates to produce these
adjacent vectors in duty ratios proportional to each vector component.
Prior to its application to MLI, the SVM has been developed and well-established for

Figure 2.20 Voltage vector diagram of a five-level inverter and the corresponding
switching states.
45
the two-level inverter. In conventional inverters, there is some flexibility available due
to the freedom in the state sequence selection, this has been utilized for either efficiency
or quality optimization (Rashid, 2004). MLI provides much higher degrees of freedom
as each inverter in the k
th
inner layer of the inverter vector diagram is corresponding to k
equivalent states, so as the number of levels increase, more parameters are involved in
specifying the switching state among the equivalent states. This complicates the control
process, but at the same time provides higher degree of freedom that can be used to
further optimize the inverter operation. Besides the use of these options for quality and
efficiency optimization, it has been exploited for other purposes such as inverters
capacitors voltage balancing, producing fault handing capability, common mode voltage
elimination, etc. (Franquelo et al., 2008, da Silva et al., 2006). In short the space vector
control complexity problem can be turned to advantage for multilevel inverters with
higher number of levels if properly handled. The following paragraphs discuss the
development and application of SVM for MLI.
Celanovic and Boroyevich (2001) introduced a general method applicable to any
number of levels for determining the nearest vectors to be used to form the reference
vectors and their corresponding duty ratios. The normalization and transformation to 60
displaced axes system provide considerably simplified computations. However in that
work there is no indication regarding the state sequencing or the selection of the
operating state among the equivalent states sharing the same vector.
McGrath et al. (2001, 2003) applied the flux trajectory concept to specify the state
sequence as starting and ending the switching interval with equivalent states. The other
two states are centered in the middle of the switching interval.
The alternative method proposed by Gupta and Khambadkone (2007) and Gupta et al.
(2004) avoids vector transformation and used equations similar to those of two-level
SVM to determine the duty ratios of the nearest three states. The vector space is divided
46
into (l-1)
2
triangles per sector and by comparing the reference vector triangle to the two
levels 60 sector, one of the nearest vectors is treated as a virtual zero state while the
other two as the adjacent states. The method is claimed to be applicable to any number
of levels, however increasing the number of levels increases the calculations
dramatically.
In SVM control, the selection from the equivalent states has been used for capacitors
voltage balancing in the NPC and FC. For example (Bhalodi and Agrawal, 2006)
studied the capacitor voltage unbalance in a three-level NPC inverter. It has been found
that the two equivalent states sharing the same voltage vector change the capacitors
voltage in opposite fashion. Open-loop and closed-loop voltage balancing schemes have
been developed based on alternating the equivalent states.
The method presented by Massoud et al. (2008) suggested the control of CHB inverter
by dividing the inverter to three level inverters (stages) and applying the SVM for
individual stages and therefore limiting the complexity associated with the MLI-SVM
control. All the cascaded stages operated with the same magnitude control ratio and the
switching periods of the cascaded stages have been shifted symmetrically over the
switching period. The computation time has been reduced considerably but the method
implies higher switching losses and harmonic distortion.
2.7.2.2 Three dimensional SVM
The three-dimensional space vector is presented by Leon et al. (2009c), where three
perpendicular axis forming the three-dimensional space vector are selected to be the
inverters A, B and C lines. To realize any reference vector, the sub-cube in which the
reference vector located is identified. In the next step, this sub-cube is divided into six
tetrahedrons, and the reference vector tetrahedron is calculated. From the above
calculations the four states in which the inverter will be operated to produce the
reference and their duty ratios are determined. This method has the advantage of its
47
capability to handle 3-phase, 4-wire systems, unbalanced system, unequal DC sources
and other irregular cases.
2.7.2.3 Multiple-phase SVM
Lopez et al. (2009) presented a general multilevel multiphase SVM algorithm for
multiphase inverters with state redundancy, the algorithm aims to mitigate the switching
states sequence selection among the set of redundant switching states. The proposed
algorithm is designed to accommodate many goals such as switching reduction,
capacitors voltage balancing, DC-source current control and fault tolerance. The method
applies p-dimensional space analysis for the p-phase inverter and makes use of the
given hypothesis that the p-phase inverter switching redundancy analysis can be carried
out by means of two-level (p-1)-phase SVM algorithm without redundancy.
2.7.2.4 Carrier-based SVM
In SVM control there is a difficulty in the controller implementation, where the process
has two stages. The first stage is to determine the nearest vectors and the desired duty
ratios. The difficulty of this stage is due to vector transformation and sector
determination. The second stage aims to optimize the state sequencing and specify the
optimum among equivalent states having the same voltage vector. With higher number
of levels, the task of the second stage becomes more complicated and time consuming.
The carrier-based PWM techniques, on the other hand, are preferred for their simplicity.
The carrier comparison mechanism usually produces the switching signals and does not
require secondary processing following the modulation stage. Also, the implementation
process which is based on counters, comparators, etc. is strongly linked to the common
digital controller hardware and does not involve complicated mathematical and logical
operations and therefore can be implemented very fast. In terms of performance the
48
SVM provides higher DC voltage utilization and lower switching losses compared to
the carrier comparison PWM (Kim and Sul 1995).
The carrier based SVM is based on the hypothesis that; if a specific zero sequence
voltage, i.e. common mode voltage, is added to the basic reference voltages, the carrier
comparison PWM performance can approach the performance of some SVM
algorithms. This concept is originally developed for the two level inverter (Kim and Sul,
1995) to centre the two active states in the middle of the switching interval. The
common mode voltage can be calculated from the reference voltages and the DC
voltage.
Fei (2002) demonstrated that a common mode voltage needed to centre the middle
inverter vectors for three level inverters is a function of the modulation index, M. This
finding shifts this method out of the sampled reference class.
Kanchan et al. (2005) presented a technique to determine the common mode modulating
signal, based only on the sampled amplitudes of the reference phase voltages. The
scheme is extended from the 2-level max/min offset voltage equation developed by Kim
and Sul (1995) to suit the level-shifted multicarrier PD scheme. The proposed method
can be applied to inverters with higher number of levels.
One of the advantages of the basic SVM over the carrier based strategies including
carrier-based SVM is that as the reference voltage amplitude decreases, the number of
level available to construct the reference voltage reduces in steps of one. This number in
the carrier-based control strategies reduces in steps of two as the reference is centered in
the middle of the carrier signals. Therefore, the seven level carrier comparison
controlled MLI, for instance, will produce 7, 5, or 3 -level voltage depends on the
reference amplitude. The same inverter goes down by one step down to two levels when
controlled using the basic SVM method. A modification for the carrier-based SVM is
presented by McGrath et al. (2006) who suggested a solution to overcome this drawback
49
by adding a DC level to the reference signal equivalent to half of the carrier amplitude
for certain values of the reference amplitude.
2.7.2.5 Uni-dimensional SVM
A method based on unidimensional geometric representation of one phase of MLI (1-
DM) has been proposed in a recent study (Leon et al., 2009b). This method defines the
two nearest inverter voltage levels to the reference voltage and determines the duty
ratios corresponding to the two levels by simplified calculations. This concept has been
applied to the symmetrical and asymmetrical CHB and with various voltage ratios. In a
follow up publication, the authors have shown that 1-DM, when applied to three phase
inverter, is equivalent to the conventional SVM control method with simplified
switching signals calculation (Leon et al., 2009a).
2.7.3 Flux modulation control
The flux modulation is a voltage control method that is based on using hysteresis
controllers to generate the switching signals and controls the voltage indirectly by its
integral, where the term flux here stands for the voltage time integral. The concept is to
compare the reference flux to the actual flux on the two dimensional synchronously-
rotating space vector diagram, and determine the desired change. Based on the sextant
on which the present flux vector exist, one of two adjacent active states or zero state
will be selected to make the actual vector moves toward the reference vector. The flux
vector moves in the direction of the selected vector and the inverter holds its switching
state as long as the flux vector is within some tolerance band that has a rectangular
shape and perpendicular to the flux vector. Otherwise, the switching state changes
according to four rules for the four tolerance band sides (Poh Chiang and Holmes,
2002b).
50
The flux modulation method has been extended for MLI by Poh Chiang and Holmes
(2002a), the state selection rules have been modified based on the three nearest
multilevel inverter vectors. The performance has been shown to be similar to that of
basic SVM method in terms of switching losses and harmonics. However it has been
claimed that the use of the hysteresis controllers results in less complicated and more
robust controller structure.
2.7.4 Hybrid control methods
Hybrid control methods are implemented by operating the inverter using combined
control methods, i.e. the inverter total control signals is produced by more than one part
operating according to different control strategies. Hybrid control suits asymmetrical
CHB and hybrid inverters as it is desirable to operate the higher voltage cells at lower
switching frequency. Normally the higher voltage stages are controlled to operate in
square wave mode while the low voltage stage is operated using PWM control to
generate a total voltage of sinusoidal profile and carrier frequency ripple.
This type of control is strongly related to the method developed in this work and
therefore the previous suggestions are demonstrate in more details and their basic
features are stated.
Manjrekar and Lipo (1998) and Manjrekar et al. (1999, 2000) considered asymmetrical
multilevel inverter composed of two cascaded cells fed by DC voltages of 2V
S
and V
S
.
A three-level comparator is used to determine the state of the high voltage stage
according to the reference amplitude. Where the high voltage H-bridge cell will produce
+2V
S
, zero or 2V
S
when the corresponding phase reference voltage is greater than V
S
,
within (+V
S
,V
S
) and less than Vs respectively. The low voltage cell is PWM
controlled to complement the desired output. The results verified that the high voltage
51
cell operates in quasi square wave mode with switching cycle equals to the reference
voltage frequency.
The hybrid control structure described above has been applied to a three-stage inverter
composed of a five-level mixed topology bridge cell of voltage step equivalent to 2V
S
.
The mixed topology cell is cascaded with two three-level H-bridge cells of voltage step
equivalent to V
S
. The nine-level arm controller has a 5-level comparator part that
control the mixed topology H-bridge cell while the two three levels cells are treated as
one symmetrical 5-level inverter and controlled using carrier comparison PWM (Yun et
al., 2007).
The inverter systems presented by Rech et al. (2002), Rodriguez et al. (2007) and
Vazquez et al. (2009) have a three-stage and 19-level asymmetrical CHB inverter that
has been controlled by modifying the two-stage inverter proposed by Manjrekar et al.
(1999, 2000). The three cascaded cells DC voltages are related by the ratio 1:2:6, and
the controller structure shown in Figure 2.21 is composed of two three-level
comparators to produce the switching signals of the high and medium voltage stages.
The lower voltage stage is controlled using carrier comparison PWM. In this design, the
voltage ratios have been selected to achieve the maximum number of levels that can be
reached by this topology and controller structure.
V
h
-V
h
h
h
h
h
V
m
-V
m
h
m
h
m
+
PWM
v
ph
* v
h
v
2
* v
m
v
1
*
v
l
+
+
+
v
ph

Figure 2.21 Hybrid control algorithm structure.
52
The inverter presented by Fukuda et al. (2009) is composed of three cascaded stages
with transformer-isolated outputs. The three stages are two high voltage two-level
stages and one low voltage three-level stage. The two high voltage stages of equal DC
voltages have been controlled in square wave mode and the output is controlled by
opposite shifting of the two stages switching angles. The shifting angle determines the
resultant voltage waveform of the high voltage stages and determines its fundamental
output. The low voltage stage is controlled by a carrier comparison PWM after adding a
third harmonic component to the reference signal to allow higher reference amplitude.
The third harmonic signal and the high voltage stages shift angle are calculated based on
the modulation depth.
2.8 Current Control of Multilevel Inverters
The current control of a voltage source inverter is a closed loop control system that
compares the actual inverter current to the reference current and generates the switching
signals to minimize the error. The current controllers have been built for two level
inverters according to a few concepts some of these have been extended to the
multilevel inverters. In this section an overview of MLI current control is given to
complete the presentation of the MLI control.
In the early research by Marchesoni (1989), the design that uses multiple two-level
hysteresis controllers to control the current of single-phase three-level NPC and five-
level CHB has been described. The current error signal has been used to generate the
switching signals.
Manguelle et al. (2001) proposed hysteresis current controller that uses the time
derivative of the current error to determine whether a switched level transition is
sufficient to return the current error to a level within the tolerance band. If not, it keeps
switching through more inverter levels.
53
Loh et al. (2005) proposed a modular hysteresis current control technique for
controlling hybrid inverters. Different three-level hysteresis controllers have been
integrated with H-bridge inverter to form a standalone power bridge, and the hysteresis
controllers of multiple power bridges have been coordinated to implement a modular
hysteresis-controlled hybrid MLI.
In the study of Busquets-Monge et al. (2006), the current control of a three-level NPC
inverter has been presented. The reference currents have been transferred to reference d-
q currents and the current error is supplied to PI controller that generates a reference
voltage vector which is realized by SVM control. The d-q current control approach is
also applied by Maharjan et al. (2008) to achieve a decoupled control of the active and
reactive power of an energy storage system build using CHB inverter with capacitors at
the DC side.
2.9 The Selection of Multilevel Inverter Topology and Control Strategy
From the previous sections we have seen that there are many options for the designers
in terms of MLI topologies and control strategies. Different topologies are needed for
their various features depending on the load demands and limitations. Also various
control strategies offer different features that suits certain topologies, load demands and
implementation medium. Figure 2.22 shows the parameters that determine the MLI
topology and control strategy. It can be seen that the load type influences the MLI
topology and control strategy directly and indirectly. This section attempts to identify
the main factors that influence the topology and control strategy selection.
54
C
a
p
a
c
i
t
o
r
s

b
a
l
a
n
c
i
n
g

Load Type
& demands
Quality
needs
MLI
Topology
MLI
control
strategy
L
o
a
d

c
o
n
s
t
r
a
i
n
t
s

H
i
g
h
/
L
o
w

f
r
e
q
u
e
n
c
y

s
t
r
a
t
e
g
y
H
a
r
m
o
n
i
c

d
i
s
t
o
r
t
i
o
n

l
i
m
i
t
s

R
e
f
e
r
e
n
c
e

t
y
p
e
/
P
o
s
t

p
r
o
c
e
s
s
i
n
g

p
r
i
o
r
i
t
i
e
s

T
H
D

l
i
m
i
t
Supply
limitations
Supply current ripple and polarity
C
a
p
a
c
i
t
o
r
s

b
a
l
a
n
c
i
n
g

d
e
m
a
n
d

Figure 2.22 Factors influencing the selection of the MLI topology and the control strategy.

2.9.1 Topology selection
The main factors influencing the inverter topology selection are indicated in Figure 2.22
and described briefly in the following section. This section discusses the load
constrains: voltage, frequency, current, power factor and THD limit individually.
2.9.1.1 Desired voltage
The load required voltage determines the topology in a few ways. For high voltage
levels, the basic topologies should be considered to divide the total voltage equally
between the switching devices, so the device voltage rating problem could be overcome.
55
For medium voltage ranges, the availability of switching devices that can handle all or
most of the inverter voltage enables the designer to consider the hybrid topologies
option.
The range of the desired voltage must also be considered where the minimum number of
voltage steps is associated with the lowest load voltage amplitude.
2.9.1.2 Desired frequency
When the load operates at fixed frequency, it is reasonable to consider the option of
isolating the multistage inverter from the output side using one transformer with
multiple primary windings rather than using isolated supplies. This option is invalid if
the load frequency lower level is close to DC.
2.9.1.3 Load current
Increased load current implies a higher current ratings of the switching devices, and
hence lower switching frequency. Increasing the number of levels can improve the
voltage quality of low frequency control methods.
2.9.1.4 Power factor
The load power factor determines if the DC supply need to be of unidirectional or
bidirectional current capability. In some power conditioning applications when the
inverter power factor is close to zero, the option of replacing the DC supplies by
capacitors is appropriate (Corzine and Kou, 2003).
2.9.1.5 Distortion limits
As indicated in Figure 2.22, the harmonic distortion limit is the main quality parameter.
Satisfying this demand is realized by a combination of control method and the number
of levels. The maximum voltage distortion occurs at minimum M.
56
2.9.2 Control strategy selection
The four factors to determine the control strategy options indicated in Figure 2.22 are
discussed in this section.
2.9.2.1 Multilevel inverter topology
As a rule of thumb, we can say that a high frequency algorithm should be considered to
control the inverter with a small number of levels. The low frequency algorithm would
likely satisfy the quality needs with large number of steps.
As we have indicated earlier that certain algorithms suits specific topologies, for
instance the phase-shift carrier described in Figure 2.19 is suitable for CHB topology.
More obviously, the hybrid control algorithms are exclusively suitable for hybrid
topologies.
Additionally some topologies require support by the control algorithm, for instance for
hybrid inverters with low voltage stage DC side fed by capacitors, the control algorithm
should ensure zero average power of the capacitors.
2.9.2.2 Quality needs
The minimum tolerable current distortion is achieved by controlling the voltage
harmonic distortion and the order of the dominant harmonics. Therefore the
performance needs determine the algorithm type, e.g. low or high frequency, and the
parameters of the selected algorithm, e.g. the carrier frequency, PWM type, etc.
2.9.2.3 Load type
Depending on the load, there are two reference signal types; the sampled and the full
cycle references. The full cycle allows more control options than the sampled reference
while the sampled reference type restricts the control algorithms options.
57
Some application required special features and some designs use the flexibility in state
selection for certain goals. Some common examples are the common mode voltage
elimination and fault handling capability.
2.9.2.4 Supply limitations
For NPC and FC topologies it is important to maintain the capacitors voltages at the
intended levels. This is done by including a capacitor balancing mechanism in the
control algorithm. The flexibility provided by multiple switching combinations for a
given voltage level in FC type described in Table 2.1 facilitates this task. As for the
NPC, there is exactly one switching state for each arm voltage level, and the capacitor
balancing is maintained by other methods such as voltage vector control.
2.10 Summary
In this chapter, the MLI has been defined. The basic MLI features are the ability to have
an output voltage higher than the switching devices rating and the reduced distortion by
generating stepped voltage waveform. On the other hand MLI circuits are more
complicated than the basic inverter circuits.
The basic MLI topologies have been used to build MLI with limited number of levels as
the circuit complexity increases dramatically with the number of levels. These
topologies are the NPC, FC and CHB. CHB topology is distinguished by its modular
structure, where the inverter can be extended simply by adding more cells. This
topology suffers from the drawback of the large number of isolated DC supplies.
Some innovative topologies have been introduced to improve MLI characteristics,
devices utilization and enable practical implementation of inverter with large number of
levels. These innovative topologies can be classified into asymmetrical-CHB, mixed-
58
level and hybrid topologies. There are many designs suggested under the hybrid class
mainly to reduce the number of the desired DC sources.
MLIs can be controlled using high frequency and low frequency switching strategies.
These two classes are mainly developed from their two-level analogies. Many studies
have been conducted to upgrade the various two level strategies for multilevel inverters,
facilitate practical implementation or adjust the optional parameters to improve the
switching strategies characteristics. Other control algorithms are specially developed for
the multilevel structure such as vector approximation and the hybrid algorithms.
The selection of a specific inverter topology is mainly determined by the load
requirements. The load voltage, power and frequency are the main factors. Other factors
include the distortion limits, regenerative capability etc. The control algorithm selection
depends mainly on inverter type and load requirements.

59
Chapter Three
Design of Multilevel Inverter
3.1 Introduction
The inverter design according to the project objectives is presented in this chapter. The
requirements of the intended AC drives application were taken into consideration and
the design begins by selecting the inverter topology and followed by control algorithms
development.
Two control algorithms have been proposed. In the first algorithm, the inverter is
controlled to approximate the reference vector to the nearest inverter vector. The second
algorithm aims to produce the reference vector by SVM control.
3.2 Load Considerations
The objectives of this research as indicated in Chapter 1 include the design of multistage
MLI with extended number of levels, inverter cost reduction and maximized number of
levels for the selected topology. In general the reported studies that consider the
mutilstage MLI for drive applications show that inverters of more than 9 levels and
more than two stages enable effective switching angles adjustment control, or voltage
vector approximation control (Rodriguez et al., 2004); (Ruderman and Schlosberg,
2008, Abdul Kadir et al., 2007). Also with this number of levels the control strategy can
be extended to higher number of stages in a straightforward manner.
60
In AC drives as the motor speed reduces, the inverters reference voltage and frequency
reduces simultaneously. Note that in vector controlled drives, the frequency is changed
indirectly through the reference voltage vector angle. At low voltage and low frequency
region, the reference vector amplitude or M decreases. This leads to a decline in the
number of inverter steps available to construct the desired voltage which increases the
voltage distortion. As the voltage and frequency decreases simultaneously, the motor
inductive reactance reduction will further worsen the current distortion. So, the designed
inverter must be operated in SVM mode besides the voltage approximation mode. This
requirement needs to be considered in the control algorithm development stage.
The considerations that need to be fulfilled by the inverter topology and control
algorithm may be summarized by:
1- The inverter should be designed with three stages and should have more than nine
levels.
2- The DC supplies should be set to maximize the number of inverter levels.
3- Hybrid topology approach needs to be applied to reduce the DC supply cost.
4- The inverter must be operated in both voltage approximation and SVM control
methods.
5- The control algorithm receives sampled voltage vector reference rather than the full
cycle reference amplitude and frequency.
3.3 Inverter Topology Design
The inverter has been designed according to the considerations indicated in the previous
section. The topology selection is concerned with points 1 to 3.
In order to reduce the DC supply cost, the hybrid topology with singly fed main stage is
selected. The inverter has been designed with two-level six-switch three-phase main or
61
high voltage stage as shown in Figure 3.1. The medium and low voltage stages are
three-level CHB cells stages.
In order to maximize the number of inverter levels with equal voltage steps, the DC
supply voltages of the low, medium and high voltage stages are selected to be V
S
, 3V
S

and 9V
S
respectively. The resultant inverter has 18 voltage levels as shown in Figure
3.2. In Figure 3.2 all the possible voltage levels of the output point A have been
identified with respect to arbitrary reference point which is the common emitter side of
the main stage as indicated in Figure 3.1. The three stages voltages corresponding to
phase A have been denoted by V
A,H,
, V
A,M
and V
A,L
as indicated in Figures 3.1 and 3.2.
The resultant number of levels meets the requirements indicated in Section 3.2
concerning the number of levels.
Vs
Full-
Bridge
3Vs
Full-
Bridge
Vs
Full-
Bridge
3Vs
Full-
Bridge
Vs
Full-
Bridge
3Vs
Full-
Bridge
A B C
3-level
Low-voltage
stage
3-level
Medium-voltage
stage
2-level
High-voltage
(main) stage
9Vs
0V
V
A,H
V
A,M
V
A,L

Figure 3.1 Three-stage hybrid MLI topology.
62
3.4 Inverters Switching States, Voltages and Voltage Vectors
According to Equation (2.1) of the general MLI, each arm can be controlled by a based-
18 switching variable. Referring to Figure 3.2, with respect to the reference point
indicated in Figure 3.1, the three output voltages are given by:
S X X
V s V ) 4 (
0 ,
= (3.1)
where X could be substituted by phase A, B or C and s is a base-18 digit that represents
the arm switching state i.e.
1, 2, 2
1, 2, 1
1, 2, 0
1, 1, 2
1, 1, 1
1, 1, 0
1, 0, 2
1, 0, 1
1, 0, 0
0, 2, 2
0, 2, 1
0, 2, 0
0, 1, 2
0, 1, 1
0, 1, 0
0, 0, 2
0, 0, 1
0, 0, 0
x
A
, y
A
, z
A
0
V
A,H
V
A,0
9
V
s
3
V
s
V
A,M
V
A,L
V
s
x
A
=0
x
A
=
1
y
A
=
0
y
A
=
0
y
A
=1
y
A
=1
y
A
=
2
y
A
=
2
zA
=
2
z
A=
0
z
A
=1
v
A,0
/V
S
s
A
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Figure 3.2 Line A voltage levels of the three-stage inverter for all switching
combinations.
63
| | 17 , 0 e s (3.2)
As shown in Figure 3.2, these voltages have a minimum value of 4V
S
when s
X
is 0 and
a maximum of 13V
S
when s
X
is at its maximum.
From Equation (2.3) the three line to line voltages can be defined as:
(
(
(
(
(
(
=
(
(
(
C
B
A
S
CA
BC
AB
s
s
s
V
v
v
v
1 0 1
1 1 0
0 1 1
(3.3)
The balanced Y connected load phase voltages are given by:
(
(
(
(
(
(

=
(
(
(
(
(
(
=
(
(
(
C
B
A
S
BC
AB
CA
CA
BC
AB
Cn
Bn
An
s
s
s
V
v
v
v
v
v
v
v
v
v
2 1 1
1 2 1
1 1 2
3 3
1
3
1
(3.4)
Equations (3.3) and (3.4) imply that the line-to-line voltages have 35, or (2l1), steps of

17Vs
s
A
=17
s
B
=0
s
C
=0
s
A
=17
s
B
=17
s
C
=0
s
A
=0
s
B
=17
s
C
=0
s
A
=0
s
B
=17
s
C
=17
s
A
=0
s
B
=0
s
C
=17
s
A
=17
s
B
=0
s
C
=17
Vs

Figure 3.3 Eighteen-level inverter voltage vector diagram.
64
V
S
and the load phase voltages have 69, or (4l3), steps of V
S
/3. The inverter voltage
vector diagram shown in Figure 3.3 has been determined by applying Park
transformation given in Equation (2.5) to convert the phase voltages, obtained from
Equation (3.4), to voltage vectors and plotting these vectors in the d-q plan for all the
18
3
possible switching combinations.
3.5 Voltage Vector Approximation Control
In voltage approximation control, the target is to operate the inverter to approximate the
reference vector to the nearest inverters vector with minimum switching losses. The
switching reduction priority is for the higher voltage stage. This section presents the
method developed for voltage approximation. First the control concept with its
associated definitions is presented. Then the control technique is described in details.
3.5.1 The control concept
In order to handle the control of inverter with large number of levels, there are two
approaches: inverter-based approach and stage-by-stage based-approach.
The first approach is to divide the control process into two stages. The first stage
determines the desired inverter vector and the second stage specifies the inverter state
among the equivalent states sharing that vector in a way that meets the design
requirements (Rodriguez et al., 2004). The first stage of calculations can be conducted
using simplified techniques regardless of the number of inverter levels. On the other
hand, the second stages calculations become more complicated as the number of
equivalent states increases as indicated in Section 2.7.1. The second approach is to
adopt the stage-by-stage controller structure similar to that of the hybrid controllers
discussed in section 2.7.4. In this study the stage-by-stage control has been selected as it
65
is more suitable for the inverter structure and the number of levels (Vazquez et al.,
2009).
To explain the controller concept, the three stages will be considered as individual two
and three-level inverters. The high voltage stage is a two level inverter which has the
vector diagram shown in Figure 3.4(a). The medium and low voltage stages are three-
level stages and their vector diagrams are composed of 19 vectors as shown in Figures
3.4(b) and 3.4(c) respectively.

9Vs
x
ABC
=100
x
ABC
=110 x
ABC
=010
x
ABC
=011
x
ABC
=001
x
ABC
=101
x
ABC
=
000,111
(0,0)
(9,0)V
S
(-9,0)V
S
(4.5,43)V
S
(-4.5,43)V
S
(-4.5,-43)V
S
(4.5,-43)V
S

(a) High voltage stage vector diagram.
Figure 3.4 The voltage vectors of the three inverter stages and the corresponding stage
states.
66
6Vs
y
ABC
=100,211 y
ABC
=200
y
ABC
=220
y
ABC
=210
y
ABC
=110,221
y
ABC
=020 y
ABC
=120
y
ABC
=022
y
ABC
=021
y
ABC
=010,
121
y
ABC
=011,122
y
ABC
=002
y
ABC
=012
y
ABC
=001,112
y
ABC
=102
y
ABC
=202
y
ABC
=101,212
y
ABC
=201
000,
111,
222
(3Vs,0) (6Vs,0)
(3Vs,0) (6Vs,0)
(0, 33Vs)
(0, 33Vs)
(3Vs, 33Vs)
(3Vs, 33Vs)
(4.5Vs, 1.53Vs)
(1.5Vs, 1.53Vs)
(1.5Vs, 1.53Vs)
(4.5Vs, 1.53Vs)
(4.5Vs, 1.53Vs) (4.5Vs, 1.53Vs)
(1.5Vs, 1.53Vs)
(1.5Vs, 1.53Vs)
(3Vs, 33Vs) (3Vs, 33Vs)

(b) Medium voltage stage vector diagram.
2Vs
z
ABC
=100,211 z
ABC
=200
z
ABC
=220
z
ABC
=210
z
ABC
=110,221
z
ABC
=020
z
ABC
=120
z
ABC
=022
z
ABC
=021
y
ABC
=010,121
z
ABC
=011,122
z
ABC
=002
z
ABC
=012
y
ABC
=001,112
z
ABC
=102
z
ABC
=202
z
ABC
=101,212
z
ABC
=201
000,
111,
222

(c) Low voltage stage vector diagram.
Figure 3.4, continued The voltage vectors of the three inverter stages and the
corresponding stage states.
67
The switching variable, s
X
, can be viewed as a weighted sum of the three stages
inverters switching variables denoted in Figures 3.2 and 3.4 by x, y and z as follows:
X X X X
z y x s + + = 3 9
(3.5)
where x
X
is a binary digit representing the control variable of arm X for the high voltage
two level inverter, y
X
and z
X
are trinity digits: the control variables of cell X of the
medium and low voltage stages three-level inverters respectively.
We can view the inverters vector diagram as a resultant of two superposition steps.
First the medium voltage stage vector diagram is superimposed at the tips of each of the
seven high voltage stage vectors. In the second step the low voltage stage vector
diagram is placed at the ends of each vector of the medium stage vector diagrams as
shown in Figure 3.5. The resultant three-stage inverter vector diagram is similar to that
shown in Figure 3.3, but the vectors are drawn using lines with different thickness and
color rather than points to mitigate the relationship between a given inverter vector and
the switching states of the three stages.
Despite the elimination of the state redundancy by having each inverters branch voltage
realized by exactly one combination of stage states (x, y, z) as shown in Figure 3.2,
Figure 3.5 shows that there is a flexibility in the realization of the reference vector.
Consider for example vector, V1, in Figure 3.5. This vector has been once resulted from
the three high, medium and low vectors (V1
H
, V1
M
and V1
L
) and next from other stages
vectors (V1
H
, V1
M
and V1
L
). Our aim is to use this kind of flexibility to minimize the
switching losses by holding the higher voltage stage as long as it can be used to
approximate the reference vector.
68

Figure 3.5 The three-stage inverter vector diagram as a result of the individual stage
vectors superposition.

The proposed voltage vector approximation algorithm flow diagram is shown in Figure
3.6. This figure reveals that the stage-by-stage control approach is adopted. Where the
calculation starts by the determination of the high voltage stage switching state,
followed by the medium stage, and ends by the low voltage stage. After determining the
next high voltage stage state, the voltage vector corresponding to the next high voltage
state is subtracted from the reference vector. Then, the result which represents the
balance that need to be supplemented by the medium and low voltage stages and
denoted by middle reference is provided as reference vector to the medium voltage
stage. Similarly, the medium vector corresponding to the new medium state is
subtracted from the middle reference and the balance represents the low voltage stage
reference. The following two subsections describe the control of the three stages.
69
3.5.2 Control of high and medium voltage stages
The high and medium voltage stages are controlled using the same concept and
therefore they are presented together. The high voltage stage is first described. Then the
medium voltage stage is presented by highlighting the differences compared to the high
voltage stage.
The high voltage stage controller, reads the sampled reference voltage vector, and
determines the next state according to the following rules:
Reference voltage
vector (Vref)
Comparing
reference vector &
high state domain
Nearest
high state
table
Middle reference
Low reference
1
2
1
2
Z
-1
_
+
c
u
r
r
e
n
t

h
i
g
h

v
o
l
t
a
g
e

v
e
c
t
o
r
_
+
new high
voltage
vector
Comparing
reference vector &
med state domain
Nearest
med state
function
1
2
Z
-1
_
+
_
+
new med
voltage
vector
c
u
r
r
e
n
t

m
e
d

v
o
l
t
a
g
e

v
e
c
t
o
r
Low Zone
Determine
Low State
Z
-1
new low
state
current low
state
X Y Z
next switching signals vector
8Vs
2Vs
2
1
sector
& zone
sector
& zone
High voltage stage
calculations
Medium voltage stage
calculations
Low voltage stage
calculations

Figure 3.6 Flow diagram of the voltage vector approximation control algorithm.

70
1- If the reference voltage can be realized by adding medium and low stage vectors to
the present high voltage stage state vector, the next high voltage stage state remains
as in the present state.
2- Otherwise, the inverter determines the high voltage states that can be used to realize
the reference vector. If there is more than one possible high voltage state, the next
state is the one reachable with minimum switching actions from the present high
voltage stage state.
The application of these two rules is explained in the following.
3.5.2.1 High and medium state domains
In order to determine whether the reference vector is reachable by a given high voltage
state, the region formed by the medium and low voltage vector diagrams superimposed
on a given high voltage state vector is defined as the high voltage domain of that state.
A given reference vector can be realized by certain high state if and only if this vector is
located on its domain. The domains of the seven high voltage stage vectors are shown in
Figure 3.7.
The high state domain is a hexagonal area that is centered on the corresponding inverter
vector end and has a side length equivalent to 8V
S
as shown in Figure 3.7. By
introducing the domain definition the problem of determining whether a given reference
vector can be reached by a certain high state is modified to the question if that reference
vector is located within that state domain.
To determine if the reference vector is located within the current state domain, the high
state vector is subtracted from the reference vector and it has been checked if the result
is located within the 8V
S
hexagon using the following two conditions which are
explained in Figure 3.8:
71

Figure 3.7 High voltage states domains.
S ini ABC q H ref q
V x V v 3 4 ) (
. , ,
< (3.6)
and
S ini ABC q H ref q ini ABC d H ref d
V x V v x V v 8 ) ( ( ) ( (
, , , , , ,
< + (3.7)
where v
d,ref
and v
q,ref
are the reference vector d-q coordinates, V
H,d
(x
ABC,ini
) and
V
H,q
(x
ABC,ini
) are the d-q coordinates of the high voltage vectors indicated in Figure
3.4(a) in parentheses at each high state vector. If the reference vector is located within
the current high voltage stage domain, then the high voltage stage inverter state will be
72
preserved during the next switching inverter. Otherwise the high voltage stage state
need to be changed. It can be seen from Figure 3.7 that the seven high state domains
overlap in some regions, for example the region denoted by R2 is the overlap of the
domains of states x
ABC
=010
2
and x
ABC
=011
2
. If the reference vector is located in
overlap region, there will be more than one high voltage state that can realize the
reference vector. This gives flexibility in the states selection that has been used to
minimize the switching actions. The determination of the domain overlap for any
reference vector is explained in the next subsection.
After determining the next high state, the difference between the reference voltage
vector and the next high voltage stage vector is required to be approximated by the
medium and low stages. This difference is taken as the reference vector by the medium
stage controller.
Similar to the high voltage stage, the medium state domain is defined as the region
covered by the low voltage stage vector diagram centered on the vector corresponding
to that state. For illustration, the medium state domain corresponding to state [x
ABC
,
8V
S
43V
S
q=43V
S
d
+
q
=
8
V
S
S
S
V q d
V d
8
3 4
< +
<
d-axis
q
-
a
x
i
s
(V
H,d
,V
H,q
)

Figure 3.8 Examination of a reference vector with respect to high state domain.
73
y
ABC
] = [100,200], is shown in Figure 3.7. Note that besides the medium state, providing
the high state is required for specifying the medium state domain within the multistage
inverter vector space. The medium state domain is a hexagon of a side length equivalent
to 2V
S
and the reference location conditions given in Equations (3.6) and (3.7) become:
S ini ABC q M M ref q
V y V v 3 ) (
, , , ,
< (3.8)
and
S ini ABC q M M ref q ini ABC d M M ref d
V y V v y V v 2 ) ( ( ) ( (
, , , , , , , ,
< + (3.9)
where v
d,ref,M
and v
q,re,f,M
are the medium reference vector d-q coordinates, V
M,d,
(y
ABC,ini
)
and V
M,q
(y
ABC,ini
) are the d-q coordinates of the medium voltage vectors shown in Figure
3.4(b) in parentheses at each high state vector.
As for high state domains, adjacent medium state domains overlap as shown in Figure
3.7 for the medium domains based on the high state x
ABC
=101. The domains overlap
provides flexibility in state selection that has been used to minimized switching losses
as shown in the next subsection.
3.5.2.2 The reference vector zone
If any of the conditions described in (3.6) and (3.7) is not satisfied, the next high state is
determined to assure that the reference vector is located in the new high state domain. If
the reference vector is located in domains overlap, there is more than one option for the
next high state, the selected one is the state that minimizes the switching losses.
In order to establish a routine for the process of determining the next high state, the high
states sector zones have been defined as shown in Figure 3.9. Dividing the inverter
vector space into six sectors between the high stage vectors, in each sector, there are
seven zones which are described according to the adjacent domains overlap. Table 3.1
74
presents the next feasible states for the seven zones based on the general sector shown
in Figure 3.9. Note that V
H
and W
H
denote the adjacent states corresponding to the
general sector, with W
H
is the state of leading vector and (z
H
, z
H
) represent the zeros
states x
ABC
=(000, 111).
Calculation of the next voltage stage state is done in the following steps:
1- The reference state sector is determined as follows:
|
.
|
\
|
=
t
u
ref
3
floor sector (3.10)
where 0< u
ref
<2t is the reference vector angle and (floor) stands for rounding to
the lower nearest integer.
2 The reference zone (ZH1-ZH7) is determined using an if-then tree.
3 The reference sector, zone and the initial high stage state are used to determine the
next high state using a lookup table that has been extended from Table 3.1 by
considering all initial states to specify the nearest feasible state as the next high
voltage state.

Figure 3.9 Zones partitioning of general high voltage stage sector.
75
As stated earlier, medium stage calculations follow a similar concept to the high voltage
stage. The medium voltage stage is a 3-level inverter and the sector is formed by six
vectors, including the zero vector, as shown in Figure 3.10. In this figure, the zero states
are denoted by z
M
, z
M
and z
M
corresponding to states y
ABC
= 000, 111 and 222
respectively. The equivalent states corresponding to the leading vector of 3V
S
amplitude
are denoted by w
M
and w
M
. Those corresponding to the lagging states are denoted by
v
M
and v
M
. The states corresponding to the leading and lagging 6Vs amplitude vectors
are denoted by W
M
and V
M
respectively. While state U
M
is corresponding to the 3\3V
S

vector at the middle of the sector. The feasible medium states for the zones of the
general sectors shown in Figure 3.10 are stated in Table 3.2.
Table 3.1 Next feasible high voltage stage states for the general sector.
Reference vector zone Next feasible states
ZH1 z
H
, z
H

ZH2 z
H
, z
H
, v
H

ZH3 z
H
, z
H
, w
H

ZH4 z
H
, z
H
, v
H
, w
H

ZH5 v
H

ZH6 v
H
, w
H

ZH7 w
H

76

Figure 3.10 Zones partitioning of general medium voltage stage sector.
Table 3.2 Next feasible medium voltage stage states for the general sector.
Reference vector zone Feasible next medium states
ZM1 z
M
,z
M
,z
M

ZM2 z
M
,z
M
,z
M
,v
M
,v
M

ZM3 z
M
,z
M
,z
M
, w
M
,w
M

ZM4 v
M
,v
M

ZM5 v
M
,v
M
, w
M
, w
M

ZM6 w
M
, w
M

ZM7 v
M
, v
M
, V
M

ZM8 v
M
,v
M
,U
M

ZM9 w
M
,w
M
,U
M

ZM10 w
M
,w
M
, W
M

ZM11 V
M

ZM12/ZM12 V
M
, U
M

ZM13 U
M

ZM14/ZM14 U
M
, W
M

ZM15 W
M

77
The calculation of the next state of the medium stage starts with the determination if the
medium reference is located within the present medium state domain. The checking is
done with the two conditions stated in Equations (3.8) and (3.9). If so, the medium state
will be maintained for the next sampling interval. Otherwise, the medium reference
sector and zone will be determined using if-then comparison tree as for the high voltage
stage.
To determine the next medium stage state, we have avoided to extend Table 3.2 as the
resultant lookup table size will be of (6 sectors 15 zones 27 initial states) which
implies large memory requirement. Instead the if-then tree shown in Figure 3.11 has
been designed to determine the next state. This tree specifies one element of the two
dimensional matrix denoted by vect as the next state. The constant matrix vect has
6 columns for each inverter sector and five rows. The column elements are (in order)
v
M
, w
M
, V
M
, U
M
and W
M
states of the corresponding sector (column) according to the
general sector vector notation shown in Figure 3.10. The vectors of two equivalent
states (v
M
and w
M
) are shown in the diagram underlined to denote that the state is one of
two equivalent states which is the nearer to the initial state. A function has been
constructed to compare various states to the initial state is denoted by in Figure 3.11 by
Nearest. Similar function has been used to compare the reference vector to the zero
states: z
M
, z
M
and z
M
and the nearest zero state is denoted in Figure 3.11 by (NZ) for
nearest zero.
3.5.3 Control of low voltage stage
The low voltage stage controller produces the switching state that generates the low
state inverter vector which is nearest to the low reference vector. As shown in Figure
3.6, the low reference vector results by subtracting the vector corresponding to the next
78
medium state from the medium reference. In this section the concept of determining the
nearest inverter vector to the reference vector and the calculation steps are presented.
3.5.3.1 Low stage state zones
Within the low voltage stage state space, the area which in nearest to each low voltage
stage vector has been identified as the vector zone. The low state vector zones division
is shown in Figure 3.12. The low voltage stage control is performed by first identifying
the low reference zone. Once the zone is indentified the state that produces the
corresponding reference vector should be selected. The inner nonzero vectors are
mutual between two equivalent switching states and there are three zero states. If the
Initial med state
Zone (ZM1-ZM15)
Zonee
[ZM1,ZM6]
Zonee
[ZM1,ZM3]
Zone=ZM1 Zone=ZM5
Zonee
[ZM11,ZM15]
Zone=
ZM12 or
ZM14
Zone=
ZM7 or
ZM10
state=Nearest{NZ,
vect[zone-2]}
state=NZ
state=Nearest{vect[0],
vect[1]}
state=vect[(zone-4)/2]
state=vect[(zone-7)/2]
state=Nearest{vect[3],
vect[zone-10]}
state=Nearest{vect[(zone-7)/3],
vect[(zone-5)+(zone-7)/3]}
state=Nearest{vect[3], vect[zone-8]}
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Determine nearest zero
(NZ)
N

Figure 3.11 Flow chart of nearest medium state selection if-then tree.
79
reference vector belongs to the zones of such vectors, i.e. zones ZL1to ZL7 in Figure
3.12, the initial state will be considered to select the nearest next state.
3.5.3.2 Determination of the low reference vector zone
To determine the zone of a given low stage reference vector, a special axis system is
introduced. In this system the equations of the boundary lines between the zones defined
in Figure 3.12 have the form (axis=constant). This system uses three axes: the standard
d-axis, besides the v- and w- axes defined in Figure 3.13. In the two dimensional space
the two-axis system is sufficient to specify any point, and the third coordinate is
dependent. However, the use of three-axis system in this case is required as the zones
have the following boundary lines:
- vertical lines of equations (d=constant),
- positive slop lines of equations (v=constant), and
- negative slop lines of equations (w=constant).
Vs
2Vs
ZL1
ZL2
ZL8
ZL3 ZL4
ZL5
ZL6 ZL7
ZL9
ZL10
ZL11 ZL12
ZL13
ZL14
ZL15
ZL16 ZL17 ZL18
ZL19

Figure 3.12 Low state vectors and their corresponding zones.
80
The determination of the low voltage zone has been carried out in three steps; (a) axis
transformation, (b) coordinates rounding and (c) polynomial interpolation.
a. Axis transformation
To transfer the reference vector axes (d
ref
, q
ref
) to the v-w coordinate system (v
ref
, w
ref
)
defined in Figure 3.13, the following transformation has been applied:
(
(
(
(
(
=
(
ref
ref
ref
ref
q
d
.
.
w
v
2
3
5 0
2
3
5 0
(3.11)
b. Coordinates rounding
To determine the low state zone of a given low stage reference vector, the coordinates
v
ref,L
and w
red,L
besides d
ref,L
have been used. The coordinates rounding is performed to
d
=
0
w
=
0
v
=
0
d-axis
q
-
a
x
i
s
w
-
a
x
i
s
v
-
a
x
i
s
t
/
6
v
ref
d
ref
q
r
e
f
v
r
e
f
w
r
e
f
+
+
d
=
c
o
n
s
t
a
n
t
w
=
c
o
n
s
t
a
n
t
v
=
c
o
n
s
t
a
n
t

Figure 3.13 The v-w coordinate axis with respect to the d-q axis.
81
define the six nearest integer parameters:

) , , (
, , , , , , , , n L ref n L ref n L ref w v d
w v d round r
(3.12)
) 5 . 0 , 5 . 0 , 5 . 0 (
, , , , , , 2 , 2 , 2
+ + +
n L ref n L ref n L ref w v d
w v d round r
(3.13)
where the subscripts (L and n) stand for values corresponding to low voltage stage and
normalized on the basis of V
S
respectively. With the reference vector dimensions

Figure 3.14 v-w-d coordinates of low voltage stage zones.
82
normalized on the base of V
S
, each of the 19 zones has a unique combination of three
out of the six integer parameters as shown in Figure 3.14. These identification
parameters are listed Table 3.3. Figure 3.14 shows that the equations of the three
diagonals of any zone is in one of the two forms: (axis=integer) or (axis=integer+0.5).
To explain the concept of identification parameters consider, the zone ZL16 in Figure
3.14. The reference vector is located within ZL16 if and only if it has (1.5<
d
ref,L,n
.<0.5), (+0.5< v
ref,L,n
.<+1.5) and (2.5< w
ref,L,n
.<1.5) and hence the integer
rounding of d
ref,L,n
, v
ref,L,n
. and w
ref,L,n
. are 1, +1 and 2 respectively as shown in Figure
3.14. These three integers have been used as identification parameters of ZL16.
When any of the zone diagonals is in the form (axis=integer+0.5), then not all
coordinates of all points in that zone will be rounded to the same integer. In this case,
axis shifting by 0.5 is performed to have the coordinates of the shifted axis round to the
same integer. This can be seen, for example, in ZL17 in Figure 3.14, which has (0.5<
d
ref,L,n
.<+0.5), (+1.0< v
ref,L,n
.<+2.0) and (2.0< w
ref,L,n
.<1.0). In this zone, the d-
component of any vector located within has an integer rounding of 0. But the v-
component is rounded to 1 or 2 when v
ref
is less than or greater than 1.5 respectively. In
this case we are going to define the unique zone parameters using the shifted v-axis and
instead of considering (+1.0< v
ref,L,n
.<+2.0), we will consider (+1.5<( v
ref,L,n
.+0.5)<+2.5)
its rounding to be r
v2
=2. Similarly, r
w2
=1. The unique combinations of the
identification parameters of the 19 zones are given in Table 3.3.
For example if the low reference vector d-q coordinates are 1.3V
S
and 0.9V
S
, then
using Equation (3.11) its corresponding v
ref,
and w
ref
will be v
ref,L,n
1.43 and w
ref,L,n

0.129. The six rounded parameters for this reference are: r
d
=1, r
v
=1, r
w
=0, r
d2
=2,
r
v2
=2 and r
w2
=0. When these six numbers compared to Table 3.3, we can see that the
reference vector parameters conflict with the identification parameters of ZL1-ZL18 and
match only the identification parameters of ZL19 r
d2
, r
v2
and r
w
without conflict.
83
c. Zone determination by polynomial interpolation
After determining the six integer parameters corresponding to the reference vector an
interpolating polynomial is used to determine which zone these parameters are matched
to. The polynomial has the following form
=
=
19
1
2 2 2
) , , , , , ( * ZL
I
w v d w v d i
r r r r r r P i i

(3.14)
Table 3.3 The integer identifiers of the 19 low state zones.
Zone r
d
r
d2
r
v
r
v2
r
w
r
w2

ZL1 0 - 0 - 0 -
ZL2 1 - - 1 - 1
ZL3 - 1 - 0 1 -
ZL4 - 0 1 - - 1
ZL5 1 - - 0 - 0
ZL6 - 0 - 1 1 -
ZL7 - 1 1 - - 0
ZL8 2 - 1 - 1 -
ZL9 - 2 0 - - 2
ZL10 1 - 1 - 2 -
ZL11 0 - - 1 - 2
ZL12 1 - 2 - 1 -
ZL13 - 1 - 1 0 -
ZL14 2 - 1 - 1 -
ZL15 - 1 0 - - 1
ZL16 1 - 1 - 2 -
ZL17 0 - - 2 - 1
ZL18 1 - 2 - 1 -
ZL19 - 2 - 2 0 -

84
where P
i
is a product term that produces 1 when reference vector rounded coordinates
d
,
w,v
and
d2
,
w2
,
v2
matches the values of the ZLi, otherwise P
i
produces zero. P
i
has the
following form:
( ) ( ) ( )
( ) ( ) ( )
[ [ [
[ [ [
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

=
3
2
3
2
3
2
) 2 ( ) 2 ( ) 2 (
3
2
3
2
3
2
) 2 ( ) 2 ( ) 2 (
j
r j
j
j
r j
j
j
r j
j
i w i v i d
j
r j
j
j
r j
j
j
r j
j
w v d
i
di vi wi
di vi wi
j r j r j r
j r j r j r
P

(3.15)
In (3.15), at least one of the product terms at the numerator will be zero if the reference
vector rounded coordinates do not match all the three parameters of ZLi. If the three
parameters matched, the denominator will be equal to the numerator to bring the value
of P
i
to one.
Following the zone determination, z
ABC
will be the identified. This state is unique for
ZL8 to ZL19. For zones ZL1 to ZL7, equivalent states associated with the zone are
compared to the initial z
ABC
and the state that can be reached with minimum switching
actions is selected.
3.6 Voltage Vector Approximation by Axis Transformation
The approximation method presented in Section 3.5 has some difficulties in
implementation and some calculations bottlenecks. The most time consuming steps are
the zone identification functions of high and medium stages which are based on
comparisons. Also the calculations involve floating point numbers which will be time
consuming if low cost fixed point controller is used. In this section, the procedure has
been modified to perform the calculations in a 60 displaced axes-coordinate system.
The axis transformation is aimed to achieve the same switching action minimization
using simpler calculations.
85
3.6.1 The g-h axis system
The g-h axis shown in Figure 3.15 will be used to represent the voltage vector in the
proposed control algorithm. This system allows simpler and faster calculations as it is
tightly related to the inverter states voltage vectors. Figure 3.16 shows that the voltage
vectors of the high voltage stage inverter have a g-h coordinates of +1, 0 or 1 multiples
of the high voltage stage DC source. For the three-level medium and low voltage stage
inverters as shown in Figure 3.17, the inverter vectors coordinates are also integers
g
h
Vref
uref
gref
href
t/3

Figure 3.15 The g-h axis system.

100,
(Vdc,0)
110,
(0,Vdc)
010,
(Vdc,Vdc)
011,
(Vdc,0)
001,
(0,Vdc)
101,
(Vdc,Vdc)
g
h

Figure 3.16 The g-h coordinates of the two-level high voltage stage inverter.

86
range between +2 and 2 multiplied by the stage DC voltage which is denoted by V
dc
.
The integer coordinates of the inverter vectors allow the inverter control to be
completed with simple fixed point calculations. The g-h coordinates of any sub-inverter
voltage vector as a function of the switching variable are given by:
(
(
(
=
(
C
B
A
dc
h
g
V
V
V
u
u
u
1 1 0
0 1 1
(3.16)
where can be substituted by x, y or z according to the stage, so Equation (3.16) is
applicable for all the three inverter stages after substituting the corresponding DC
voltage and switching variables.
100/211,
(Vdc, 0)
200,
(2Vdc,0)
210,
(Vdc, Vdc)
110/221,
(0, Vdc)
220,
(0, 2Vdc)
120,
(Vdc, 2Vdc)
020,
(2Vdc, 2Vdc)
021,
(2Vdc, Vdc)
022,
(2Vdc, 0)
011/122,
(Vdc, 0)
010/121,
(Vdc, Vdc)
012,
(Vdc, Vdc)
002,
(0, 2Vdc)
001/112,
(0, Vdc)
102,
(Vdc, 2Vdc)
101/212,
(Vdc,Vdc)
202,
(2Vdc, 2Vdc)
201,
(2Vdc, Vdc)

Figure 3.17 The g-h coordinates of a three-level inverter.
87
As explained in Section 3.5, the reference voltage vector input is required to be
approximated during the following sampling interval. The controller operates the
inverter in the state that produces the vector nearest to the reference vector and holds
this state during the entire sampling interval.
In voltage approximation using g-h transformation, the next switching state is
determined as illustrated in the flow diagram shown in Figure 3.18. This process is
carried out in three consecutive stages: the high, medium and low stages. Each stage
considers its previous output in the calculation of its new state. The previous output is
provided by the memory blocks (Z
1
). The process starts with the d-q to g-h reference
coordinate transformation according to the following equations:

Figure 3.18 Voltage approximation control algorithm using g-h coordinate system
calculations.

88
|
|
.
|
\
|
=
3
sin
cos
ref
ref ref ref
V g
u
u (3.17)
|
|
.
|
\
|
=
3
sin 2 u
ref ref
V h (3.18)
The remaining calculations are carried out in the g-h coordinate system as explained in
the following subsections.
3.6.2 Control of the high and medium voltage stages
As in the method presented in Section 3.5, there is a close similarity between the high
and medium stages calculations. The calculation of x
ABC
begins by the determination if
the reference vector is located in the domain of the present high voltage state. If so, x
ABC

holds its value during the next switching interval. The examination conditions are as
follows:
S S ini C ini B ref h
V V x x v 8 9 ) (
, , ,
< (3.19)
and
S
S ini C ini B ref h
S ini B ini A ref g
V
V x x v
V x x v
8
) 9 ) ( (
) 9 ) ( (
, , ,
, , ,
<

+

(3.20)
Comparing to Equations (3.6) and (3.7), the conditions stated in equations (3.19) and
(3.20) are simpler as the switching variables are multiplied only by integers and no
additional constants are required to define the inverter vectors coordinates.
If the conditions given in equations (3.19) and (3.20) are not satisfied, the reference
vector is located outside the present high voltage state domain. Hence, a new high
voltage state is determined in two steps. The first step is to generate the feasible next
89
x
ABC
vector which is formed by the states that have the reference vector located in their
domains or valid candidates as next states. The feasible states vector is basically
generated by applying conditions similar to equations (3.19) and (3.20) for all the eight
possible x
ABC
combinations. The number of iterations can be reduced by excluding one
of the zero states, and the present state from the comparison. Also the iteration can be
stopped if the number of feasible vectors reached three, which is the maximum number
of overlapping high stage domains as shown in Figure 3.7. The second step is to
compare the feasible next states vector to the current x
ABC ,ini
and choose the nearest
element as the next high voltage stage state.
The above procedure does not involve any sector and zone determination and far more
computationally efficient than the methods presented in Section 3.5.
As in the q-d based algorithm, the medium reference is determined by subtracting the
vector corresponding to the selected high state from the reference vector, as follows:
( )
S B A ref g M ref g
V x x v v = 9
, , ,
(3.21)
( )
S C B ref h M ref h
V x x v v = 9
, , ,
(3.22)
Determining the next values of y
ABC
is similar to that of the high voltage stage, with
similar conditions to those given in Equations (3.19) and (3.20) except the size of the
domains is changed to 2V
S
rather than 8V
S
. Also the feasible states vector is generated
if the medium reference vector is not within the present medium state domain. This list
represents one or two vectors, as there is no more than two medium domains overlap as
shown in Figure 3.10. The feasible states list, however, may have up to five states when
the reference vector is located in the overlap regions represented in Figure 3.10 by
zones ZM2 and ZM3, in this case the five feasible states will be (z
M
, z
M
, z
M
, v
M
, v
M
)
and (z
M
, z
M
, z
M
, u
M
, u
M
) respectively as indicated in Table 3.2.
90
3.6.3 Control of the low voltage stage
The reference voltage for the low voltage stage is determined by subtracting the vector
corresponding to the calculated y
ABC
from the medium stage reference vector as shown
in Figure 3.18. This can be done using the switching variables in the way followed in
Equations (3.21) and (3.22).
By substituting the DC voltage and the switching variables for the low voltage stage
into equation (3.16):
(
(
(
=
(
C
B
A
S
L h
L g
z
z
z
V
V
V
1 1 0
0 1 1
,
,
(3.23)
Inverting equation (3.23) and substituting the low voltage vector by the low reference
vector gives,
(
(
(
(

=
(
(
(
L ref
L ref
C
B
A
vh
vg
Vs
z
z
z
,
,
2 1
1 1
1 2
3
1
'
'
'
(3.24)
where z
ABC
represent the general solution of z
ABC
. Equation (3.23) represents the matrix
form of two linear equations for three unknowns, which gives a linear solution space for
z
ABC
, and in order to obtain a specific solution for z
ABC
, we will use the third equation:
0 ' ' ' = + +
C B A
z z z (3.25)
Considering Equation (3.25), the resultant specific solution will represent the desired
values of z
ABC
.shifted by a constant. Taking into account that the switching variables are
trinary digits with minimum value of 0 and maximum value of 2, the switching
variables are determined as follows:
91
) ' , ' , ' min(
'
'
'
,
C B A
C
B
A
i
C
B
A
z z z
z
z
z
z
z
z
(
(
(
=
(
(
(
(3.26)
| | ) ' , ' , ' max( 2
, ,
C B A
i
C
B
A
ii
C
B
A
z z z
z
z
z
z
z
z
+
(
(
(
=
(
(
(
(3.27)
Equation (3.26) sets the minimum z to zero and Equation (3.27) sets the maximum z to
2. When Equations (3.26) and (3.27) have two distinct solutions, the one nearer to the
initial state is selected. If the two solutions are identical this implies that the voltage
vector is corresponding to one inverter state and this state must be selected. For the zero
vector that is represented by three equivalent switching states, the following condition
has been used to detect this case and define the third solution:
then , if
, , , i C i B i A
z z z = =
(
(
(
=
(
(
(
1
1
1
,iii
C
B
A
z
z
z
(3.28)
3.7 Space Vector Modulation Control
The voltage vector approximation method presented in Sections 3.4 and 3.5 is suitable
for large number of inverter vectors which are available to approximate the reference
vector. But as the reference vector amplitude decreases, its corresponding voltage vector
amplitude reduces and the number of voltage steps forming the reference voltage
approximation reduces. The inverter voltage vectors are equally displaced by V
S
as
shown in Figure 3.3. When a given reference vector is approximated to the nearest
inverter vector, the maximum amplitude error is V
S
/2. As the reference amplitude
reduces the error ratio increases with inverse relationship. Similar character can be
noted with regarding the phase error. In order to limit the current distortion at low
92
reference voltage amplitude, fast switching PWM control need to be applied as
discussed in Chapter 2.
This section presents the proposed SVM control. The unfitness of the designed inverter
for conventional fast switching control techniques is explained first to draw the attention
to the advantage of the proposed control method. Then the control technique is
described in detail.
3.7.1 The dilemma of high voltage stage switching
The ratio of the cascaded stages DC voltages in the designed inverter led to eighteen
voltage levels and this is the maximum number of levels that can be achieved by this
circuit. This design is advantageous in voltage approximation control, however the
design involves a serious problem when controlled by high switching frequency
strategies.
The modulation condition defined by Mariethoz and Rufer (2004) identifies the
cascaded MLI suitable for high frequency control as the one designed to achieve
switching between any two adjacent voltage levels by changing the states of the low
voltage stage while holding the switching state of other stages. The perception behind
this definition is that the high frequency control normally involves repetitive fast carrier
frequency switching between adjacent voltage levels. The hybrid inverters operating in
high switching frequency should be designed to avoid involving higher voltage stages
and prevent simultaneous switching at the carrier frequency.
The cascaded inverters designed with maximum number of levels do not meet the
modulation condition. This 18-level inverter is no exception. Figure 3.19(a) shows the
transitions between adjacent states that cannot be achieved by switching the low state
voltage stage only. Figure 3.19(b) shows the voltage ratios and voltage levels that the
inverter should have at most if the modulation condition is being satisfied. It can be seen
93
1,2,2
1,2,1
1,2,0
1,1,2
1,1,1
1,1,0
1,0,2
1,0,1
1,0,0
0,2,2
0,2,1
0,2,0
0,1,2
0,1,1
0,1,1
0,0,2
0,0,1
0,0,0
x,y,z
0
v
AH v
AM
v
AL
v
A,0
9Vs
3Vs
Vs
switching involves
medium& low stage
switching involves all three stages

1,2,2
1,2,1
1,2,0/1,1,2
1,1,1
1,1,0/ 1,0,2
1,0,1
1,0,0/ 0,2,2
0,2,1
0,2,0/0,1,2
0,1,1
0,1,0/0,0,2
0,0,1
0,0,0
x,y,z
0
v
AH v
AM
v
AL
VA0
6Vs
2Vs
Vs

(a) Voltage ratio 1:3:9 eliminating state
redundancy.
(b) Voltage ratio 1:2:6 satisfying the
modulation condition.

Figure 3.19 Voltage levels of the three-stage topology.
High frequency
switching of high
voltage stage
Simultaneous high
frequency
switching

Figure 3.20 Switching variables variation with the time for the 18-level inverter with
a phase reference voltage peak equivalent to 5Vs and multiple carrier PWM control.
94
that satisfying the modulation condition reduces the number of inverter levels from 18
to 13 levels.
Figure 3.20 shows a simulated inverter three stages switching variables when the 18-
level inverter is controlled using the level shifted multiple-carrier PWM strategy. Figure
3.20 verifies that the inverter is subjected to the undesirable high voltage and
simultaneous switching.
It is important to mention here that the hybrid control strategies presented in Section
2.7.3 are also not suitable for this design. If these comparator-based controllers were
applied, it will lead to a low voltage state reference amplitude which is higher than V
S

and hence beyond the inverter voltage limit. For example, if we consider the reference
voltage with respect to the negative side of the 9V
S
source is 4.5V
S
. The high voltage
stage comparator is operated to set the high stage output voltage to 9V
S
, then the three-
level medium stage will produce 3V
S
and the low voltage stage reference voltage will
be 1.5V
S
which is out of the reach of the low voltage stage. On the other hand if the
high voltage stage comparator is operated to set the high stage output voltage to 0, then
the three-level medium stage will produce 3V
S
and the low voltage stage reference
voltage will be 1.5V
S
which is also out of the reach of the low voltage stage.
In the next section, a fast switching voltage vector control algorithm is developed for
the 18-level inverter and this algorithm is unique in permitting the inverter which is
designed with maximum number of levels to be controlled by high switching strategy
effectively without any undesirable high frequency switching.
3.7.2 The voltage space vector control concept
The control concept suggests that a reference voltage vector of circular trajectory due to
a systematic 3-phase voltage cause the voltage approximation methods presented in
Sections 3.5 and 3.6 to operate the high voltage stage in the square wave mode. Further
95
with this reference the medium voltage stage will operate at low frequency which is
about three-to-five times the fundamental frequency. The resultant low stage reference
voltage vector will be within the SVM controlled area of the low voltage stage.
Therefore, instead of approximating the low voltage stage reference to the nearest
vector, we can realize this reference using the SVM control.
3.7.3 Control of the three inverter stages
The SVM control flow diagram show in Figure 3.21 indicates that the high and medium
stages controls are identical to those presented in Section 3.6. The low voltage stage
reference results from subtracting the vectors corresponding to the high and medium
next states from the reference voltage vector is suppose to be located within the low
voltage stage hexagonal vector space. The low voltage stage is a three-level inverter and
its SVM control can be handled effectively with any three-level SVM control strategy.
As indicated in Figure 3.21, the outputs of the high and medium stages routines are the
values of x
ABC
and y
ABC
to be applied during the following sampling period. The low
voltage stage routine determines the three vectors nearest to the low stage reference and
their corresponding duty ratios during the following switching period. The output of the
low voltage routine is a j-element states vector [z
ABC
], rather than one state z
ABC
. During
the following sampling period, the vector elements will be assigned for z
ABC

consecutively for sub-periods of T
C
=T
S
/j.
The high and medium stages control will not be explained further. As for the low
voltage stage, it has been chosen to apply the control algorithm presented by Celanovic
and Boroyevich, (2001) to determine the nearest three inverter voltage vectors and their
duty ratios. This algorithm is based on the 60 displaced g-h axis, and since the low
stage reference is represented in this system, there is no need for further vector
96
transformation. The control of the low voltage stage is divided to two steps and
described in the following subsections.
3.7.3.1 Low voltage stage control: basic modulation
Basic modulation refers to specifying the low voltage stage vectors which are nearest to
the low reference and will be generated during the next sampling period and their duty
ratios.
The low reference voltage vector represented by its g-h components will be normalized
with a base voltage of V
S
. The reference coordinates are denoted by (g
ref,n,L
, h
ref,n,L
)
where the subscript (n) indicates the normalization. The g-h coordinates of the nearest
Reference voltage
vector (Vref)
Nearest
state
Middle reference
Low reference
1
2
Z
-1
_
+
c
u
r
r
e
n
t

h
i
g
h

v
o
l
t
a
g
e

v
e
c
t
o
r
_
+
new high
voltage
vector
Z
-1
_
+
_
+
new med
voltage
vector
c
u
r
r
e
n
t

m
e
d

v
o
l
t
a
g
e

v
e
c
t
o
r
nearest states and
duty ratios
Z
-1
new low
state
last low
state
X Y Z
2Vs
2
1
feasible
next states
S/H
sampling
rate=fs
feasible
next states
Nearest
state
state sequence
Ref.
type
switching vector
formation
j
dq
gh
Comparing ref.
vector & hi domain
1
2
8Vs
Comparing ref. vector
& med domain
1
2

Figure 3.21 Flow diagram of the voltage vector control algorithm designed for MLI.

97
four vectors around the reference vector are:
v
1
=(ceil(g
ref,n,L
), floor(h
ref,n,L
)) (3.29)
v
2
=(floor(g
ref,n,L
), ceil(h
ref,n,L
)) (3.30)
v
3
=(floor(g
ref,n,L
), floor(h
ref,n,L
)) (3.31)
v
4
=(ceil(g
ref,n,L
), ceil(h
ref,n,L
)) (3.32)
where ceil (g
ref,n,L
) is the next integer higher than the real g
ref,n,L
and floor (g
ref,n,L
) is the
next integer lower than the real g
ref,n,L
.
As shown in Figure 3.22, the three inverter states around the reference vector are vector
v
1
and v
2
of Equations (3.29) and (3.30) besides one of the vectors v
3
or v
4
given in
Equations (3.31) and (3.32). The third nearest vector is determined according to the
following condition in which the third vector is denoted by v
x
:
( )

= >
= <
= +
+
4
3
, , , ,
, , , ,
then 0
then 0
) ( floor ) ( ceil
) (
v v
v v
h g
h g
x
x
L n ref L n ref
L n ref L n ref
(3.33)
After determining the three nearest vectors, their corresponding duty ratios are
determined as follows:
If v
x
= v
3
d
v1
= g
ref,n,L
floor(h
ref,n,L
)

(3.34)
d
v2
= h
ref,n,L
floor(h
ref,n,L
) (3.35)
d
v3
=1d
v1
d
v2
(3.36)
Otherwise, if v
x
= v
4

d
v1
= ceil(h
ref,n,L
) h
ref,n,L
(3.37)
d
v2
= ceil(g
ref,n,L
) h
ref,n,L
(3.38)
98
V
ref
g-axis g
ref
h
ref
f
l
o
o
r
(
g
r
e
f

)
c
e
i
l
(
g
r
e
f

)
floor(h
ref
)
ceil(h
ref
)
v
1
v
2
v
3
v
4
g
+
h
=
c
e
i
l
(
g
r
e
f
)
+
f
l
o
o
r
(
g
r
e
f
)
d
v
1
d
v2
h
-
a
x
i
s

Figure 3.22 Raw modulation using the g-h axis and normalized reference vector.
d
v4
=1d
v1
d
v2
(3.39)
Figure 3.22 explains the calculations for an example reference vector denoted by V
ref
,
the corresponding nearest vectors v
1
-v
4
are indicated. The diagonal of the parallelogram
connecting v
1
and v
2
is used in the testing condition given in Equation (3.33) to
determine the third nearest vector which is v
4
for V
ref
. The duty ratios are also indicated.
3.7.3.2 Low voltage stage: secondary modulation calculations
In the secondary modulation calculations, the switching signals are extracted from the
basic modulation stage. In this stage the flexibility provided by the optional selection of
equivalent states sharing the same vector and the sorting of the states sequence should
be utilized for performance enhancement.
99
type 1
type 2
type 3
2
o
1,
o
1
o
2,
o
2
o
,
o
,,,,,
o
1,
o
1
o
2,
o
2

Figure 3.23 The three triangles types around the reference vector defined to determine
the switching states sequence.
It has been indicated in Chapter 2 that the harmonic distortion is minimized when the
two active states are centered in the switching period for the two-level inverter. The
extension of this concept to three-level has been made by selecting one vector which
must be mutual between more than one switching state as a reference to start and end
the period with. While the other two vectors as treated as active states to be centered in
the switching period (McGrath et al., 2006).
The inverter is operated in four switching states within each sampling interval, T
S
, to
realize the reference vector. The first and the last switching states are equivalent. The
states sequence has been determined first by identifying the type of the triangle in which
the reference vector is located according to Figure 3.23. The three types of the triangles
are defined as follows:
i. Type 1: the triangle is formed by two outer vectors and one inner vector.
ii. Type 2: the triangle is formed by one outer vector and two inner vectors.
iii. Type 3: the triangle is formed by zero vector and two inner vectors.
100
The outer vectors are associated with unique switching states and each of the inner six
vectors is associated with two equivalent switching states, while the center zero vector
is associated with three zero states. In Figure 3.23, the outer vector states are denoted by
. The inner vectors states are denoted by
1
,
1
,
2
and
2
where the three trinary
digits (z
ABC
) of
1
state are composed of one (1)
3
and two (0)
3
digits. State
1
is
equivalent to
1
but with one (2)
3
and two (1)
3
digits. On the other hand
2
has in its
trinary expression (z
ABC
) one (0)
3
and two (1)
3
digits while
2
is its equivalent of one
(1)
3
and two (2)
3
digits.
The states sequence has been assigned according to Figure 3.24. For any branched next
state in Figure 3.24, the controller selects the path with minimum switching transitions
and when there is a unique next state, the switching involves exactly one digit switching
to adjacent position, i.e. 0
3
1
3
or 1
3
2
3
.
The state sequence and duty ratio information are extended to form the j-element
switching states vector with the four switching states repeated according to their duty
ratios. Consider for example type 1 triangle and assuming the sequence (,
1
,
2
, ) is
to be followed according to the nearest state criteria. Denoting the duty ratios of states
,
1
, and
2
by d

, d
1
and d
2
respectively, the low voltage stage states vector will be
of the following form:
) (
) 1 (
) (
) 1 (
) (
) 1 (
) (
) 1 (
'
'
) : 1 (

A
2 1
2 1
1
1
2
2
1
1
j z
n n n z
n n n z
n n z
n n z
n z
n z
z
j z
BC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
abc
+ + +
+ +
+ +
+
+
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
(
o
o
o
o
o
o
o
o
o
o
(3.40)
101

where;
n
= round (j*d
/2) (3.41)
n
1
= round (j*d
1
) (3.42)
o
o
2
initial
state
2
o
1

2
2

1
o

(a) State sequence of type 1

o
1
o
1
o
1
o
2
o
2
Initial
state
o
2

o
2
o
1
o
1
o
1
o
2
o
2

(b) State sequence of type 2

Initial
state
, o
1
o
2
,
, o
2
o
1
,
, o
2
o
1
,

(c) State sequence of type 3
Figure 3.24 State sequence assignments according to the reference vector triangular
type.
102
n
2
= round (j*d
2
) (3.43)
In equations (3.41)-(3.43) round stands for rounding to the nearest integer.
The vector [z
ABC
] given in equation (3.40) is produced as the output of the low voltage
stage calculations.
3.7.4 Modified control algorithm
The dual SVM control algorithm presented in Section 3.7.2 inherits from the vector
approximation methods presented in Sections 3.5 and 3.6 their high and medium state
domains. If we refer to Figure 3.10, we can notice two triangular areas denoted by
ZM12 and ZM14. These areas have been appended to zones ZM12 and ZM14
respectively and not actually belonging to the corresponding vectors domains, instead
they are equally distant from both domains which are the nearest areas to these
triangles. However, the triangles genuinely do not belong to any domain. This
assumption may lead to some distortion, where the worst case occurs if the reference
vector is just less than V
S
away from the selected medium state domain and
consequently it will be at the same distance from the low voltage stage PWM control
region. Figure 3.25 shows these triangles for the entire high voltage stage domains
corresponding to states x
ABC
=100, 010 and 001, in the inverter vector space. These areas
are shown in Figure 3.25 for only three secluded domains for clarity. Figure 3.26
identifies two ranges of the reference amplitude within which, the output voltage may
experience distortion. Note that the 100% amplitude reference belongs to the maximum
radius that fits in the space vector hexagon 8.5\3V
S
. In this section, the control
algorithm is modified to avoid the selection of high and medium states that lead to a low
stage reference vector beyond the low voltage stage vector space.
103

Figure 3.26 The two ranges of reference vector amplitude during which the inverter is
subjected to distortion.

Figure 3.25 High voltage stage domains, the areas outside the PWM control region are
marked by dark shade.
104
x=100
y
=
2
2
0
Basic
Domain
Modified
Domain
8Vs
7Vs
Vs 3 7
V
s
3
5 .
8

Figure 3.27 The proposed modified high voltage stage domains in the inverter vector
space.
Figure 3.25 shows the actual high state domain as the previously defined domain
minus the triangles out of the PWM control reach, marked in red color for the domain of
state x
ABC
=100. Obviously we can redefine the shape of the high voltage states domains
and exclude the areas out of PWM controlled region to avoid the consequences of the
imprecise assumption. This process, however, involve a computation complications due
to the details that need to be described. To avoid this complexity, it has been decided to
consider the largest hexagonal area which is fully covered by PWM controlled region
and define this area as the modified high state domain as shown in Figure 3.27.
To examine the characteristics of the inverter using the modified high state domains,
consider Figure 3.28 which shows the voltage vector space with high states domains of
7Vs. It can be noticed that the ranges outside the PWM area have disappeared so the
7Vs domain solves the PWM control problem at the two ranges of reference amplitude
indicated in Figure 3.26. Figure 3.28 also shows that the proper SVM operation will be
105
lost as the reference amplitude exceeds 82%. If the reference vector amplitude is higher
than 82% there will be a distortion in the output voltages which occurs every 60 and
expected to increase dramatically as the reference amplitude increases.
To solve the distortion problem that occurs with the modified high state domains at
large reference amplitude, the basic amplitude domains that have no distortion problem
if the reference amplitude is higher than 71% are reapplied. As the control algorithms of
the basic and modified domains are similar except for the domain size, it will not be
difficult to choose the basic domain for reference amplitude larger than 71% and the
modified domain for amplitudes less than 82%. The optional selection of the domain for
reference more than 71% and less the 82% can be used to provide hysteresis
characteristics for the domain determination block as shown in Figure 3.29, to avoid any
undesirable domain bouncing when the reference amplitude is on the border line.

Figure 3.28 Inverter operation with the modified high stage domain.
106
Figure 3.29 which shows the flow diagram of the proposed SVM control algorithm
reflects that the high and medium stage controllers are similar to those presented in
Section 3.6 for the vector approximation control except for the high state domain
adjustment. Three level SVM strategy is applied to control the low voltage stage as
explained.
Reference voltage
vector (Vref)
Nearest
state
Middle reference
Low reference
1
2
Z
-1
_
+
c
u
r
r
e
n
t

h
i
g
h

v
o
l
t
a
g
e

v
e
c
t
o
r
_
+
new high
voltage
vector
Z
-1
_
+
_
+
new med
voltage
vector
c
u
r
r
e
n
t

m
e
d

v
o
l
t
a
g
e

v
e
c
t
o
r
nearest states and
duty ratios
Z
-1
new low
state
last low
state
X Y Z
2Vs
2
1
feasible
next states
S/H
sampling
rate=fs
feasible
next states
Nearest
state
state sequence
Ref.
type
switching vector
formation
j
amplitude
Domain type
7/8Vs
dq
gh
Comparing ref.
vector & hi domain
1
2
8Vs
7Vs
Comparing ref. vector
& med domain
1
2

Figure 3.29 Flow diagram of the SVM control algorithm, the high stage domains
adjusted according to the reference amplitude.
107
3.8 Summary
In this chapter, multiple-stage hybrid topology has been selected to achieve the desired
number of levels and the DC source cost reduction. The ratio of the DC supplies of the
three inverter stages has been selected to maximize the number of levels.
Two control algorithms have been developed: the voltage vector approximation control
for high speed operation and the voltage vector control for the low speed region.
In the voltage approximation mode the concept of separated control for the cascaded
stages has been employed. Two voltage approximation algorithms have been developed,
the first handles the calculation in d-q axis system and applies special polynomial-
interpolation based control concept for the low voltage stage. The second voltage
approximation strategy handles the control in the 60-displaced g-h axis system. The
axis transformation provides shorter control procedure to enable faster processing.
The developed voltage vector control algorithm is a dual algorithm that operates the
inverter higher voltage stages in low frequency modes while the SVM is applied only to
the low voltage stage. While the hybrid control concept has been applied previously, the
developed SVM control strategy is unique in using the two-dimensional vector space to
determine the switching instants for the three phase stage. Thus it provides extended
allowance in terms of the maximum number of levels. The PWM control area in the
high state domain has been discussed. It has been found that certain ranges of reference
amplitude can cause voltage distortion. The adjustment of high voltage domain
definition has been proposed to resolve this problem.

108

Chapter Four
Implementation of Multistage Inverter
4.1 Introduction
This chapter presents the implementation of the designed inverter and the control
algorithms developed in Chapter 3. The implementation description represents a part of
the system design besides its importance to comprehend the experimental results.
Firstly the inverter construction is described in terms of the devices ratings
determination. Then a brief description of the digital signal processor (DSP), controller
is given to verify its suitability for this application. The supporting circuits, equipment
and software used for the experimental system have been highlighted.
Finally, the control programs flowcharts for the control strategies developed in Chapter
3 is given with general explanation to clarify its operation.
4.2 General Description of the Inverter Prototype
At the present implementation stage, we need to develop a workable system in order to
test the designed topology and algorithms. The inverter system that can be used to
supply a practical load is shown in Figure 4.1. It consists of the power circuit, the
controller and the auxiliary circuits that process the control signal before applying it to
the power components. Each of these three units will be described in the next three
sections.
109
Power
Converter
Load DC link
Switching
signals
conditioning
Controller

Figure 4.1 Main units of the MLI system.
4.3 Power Circuit Description
In this section, the intended load parameters are considered for the devices sizing. The
DC link prototype is described, and the measurement devices used in testing are
presented.
4.3.1 Load specifications
The 18-level inverter has been build based on a permanent magnet synchronous motor
(PMSM) load requirements. The PMSM model is BSH 1002 P and its data sheet is
given in the Appendix 1. For easier referencing, the basic parameters considered in the
inverter design are given in Table 4.1 considering the target speed range of 1000 rpm.
These parameters will be considered in the following two subsections for the DC link
and the switching devices sizing.

110
Table 4.1 Motor parameters considered in inverters components sizing.
Parameter Unit Rated values
Voltage (line-to-line) Volt 115
Rated current A 3.8
Stand still current A 4.8
Maximum Current A 17.1

4.3.2 DC link
The term DC link refers to the DC supplies of various inverter stages, and the DC link
design includes specifying the value of the basic voltage V
S
and identifying the DC
supply of the three stages. Recall that the high voltage stage sub-inverter is designed to
operate in square wave mode, and the bidirectional current capability is not required as
the regenerative mode is not considered. This stage supplies most of the load real
power. The medium and low voltage stages on the other hand have multiple switching
cycles within each high voltage stage cycle and therefore the bidirectional current
capability is essential for these stages.
Considering the motor desired voltage shown in Table 4.1, the amplitude of the voltage
vector corresponding to a line-to-line voltage of 115V is:
3
2 115 5 . 1
=
v
V (4.1)
Consider the 18-level inverter voltage vector diagram, the maximum amplitude of the
voltage vector that has its circular trajectory located within the vector space is
\3*17V
S
/2. Assuming that the amplitude of the maximum voltage vector trajectory that
can be drawn within the inverter vector space is given in by Equation (4.1), the
corresponding value of V
S
is:
S v
V V 17
2
3
3
2 115 5 . 1
max ,
=
= (4.2)
111
gives
V V
S
57 . 9
17
2 * 115
~ = (4.3)
It has been chosen to set V
S
to 12V. This selection is safe in terms of the voltage
withstand level as the motor is designed to operate at much higher voltage levels for
higher speed range as indicated in the Appendix 1. Furthermore, this selection allows
the use of standard batteries to supply the low and medium stages sub-inverters.
The high voltage stage has been supplied with 108V using the laboratory DC supply
model (TDK-Lambda Gen 600A-5.5A). The medium and low voltage stages have been
supplied using 12V, 5.5Ah lead acid batteries model YB5L-B and YBx7A-Bs for
medium and low stages respectively. Three units connected in series are used for the
medium stage cells and one unit for each low voltage stage cells. These batteries besides
their bidirectional current capability found to have good voltage stability due to the low
internal resistance; and for short term use, they are capable to supply several amperes
besides the low cost due to their popularity for small motorbikes.
4.3.3 Switching devices sizing
In this section the selection of the switching devices is given. The desired frequency,
current and voltage are considered for this purpose.
With reference to the control algorithms developed in Chapter 3, the high voltage stage
will operate at the fundamental frequency and the medium voltage stage will also
operate at low frequency. Therefore, the switching speed parameter is not critical in the
selection of these stages devices.
As for low voltage stage, the switching time limit needs to be estimated from the
voltage SVM control mode presented in Section 3.7. Assuming a maximum sampling
112
frequency (f
S
=1/T
S
) of 10 kHz. With j of 200 subintervals per sampling time, the
minimum switching time will be:
sec 1 2
2
= =
C
S
T
j
T
(4.4)
where the multiplication by 2 is due to the state sequence assignment that leads to one
switching pulse per switching variable digit per two switching intervals. The devices
turn ON plus turn OFF times must be much lower than 1sec. So the low voltage stage
devices are selected to have a maximum turn ON plus turn OFF time which is not more
that 100nsec, or 10% of the minimum switching pulse or notch width.
The voltage rating is not a critical factor due to the small voltage levels stated as DC
supply voltages, but it is important to select devices with low on-state voltage drop.
The current ratings are selected based on the maximum current given in Table 4.1. This
current is much higher than the rated operating current therefore a safety margin of 20%
should be sufficient. The devices current rating lower limits are given by
Rated peak current; A 29 2 1 . 17 2 . 1 ~ (4.5)
Average current rating: A 2 . 9
2 1 . 17
2 . 1 ~
t
(4.6)
RMS current rating: A 5 . 14
2
1 . 17
2 . 1 ~ (4.7)
In equations (4.5)-(4.7), the switch current is assumed to be the positive half of the sine
wave. The multiplication by 1.2 is to account for the safety margin. In Equations (4.5)
and (4.6) the \2 multiplicand is to obtain the peak of the sine wave from its RMS. The
peak to average ratio of the positive half of the sine wave is (t) as shown in Equation
(4.6). The full-wave to half-wave RMS ratio is \2 as in Equation (4.7).
113
IGBTs have been used for the high voltage and medium voltage stages and MOSFETs
are used for the low voltage stage due to their lower switching losses. The devices
models are:
High voltage stage: IRGB4056DPBF (International Rectifier, 2008)
Medium voltage stage: IRG4BC20FDPBF (International Rectifier, 2003)
Low voltage stage: SPP11N80C3 (Infineon Technologies AG, 2005)
A parallel RC snubber has been added to prevent voltage surges during turning off and
reduce the electromagnetic interference.
4.3.4 Measuring equipment and testing load
A 0.9 kW asynchronous motor has been used as a testing load. This motor is coupled to
a self-excited DC generator with adjustable load resistor to adjust the load torque.
The waveform measurements have been conducted by the oscilloscope model LeCroy-
44Xi (LeCroy, 2008a). The voltage measurements have been done through a 1400V
differential probe. The current measurements are captured by LeCory CP030 current
probe (LeCroy, 2008b).
4.4 The Controller
For control algorithm implementation, the controller card eZdsp F2818 based on the
TMS320F2812 DSP has been selected. The TMS320F2812 is 32-bit 150 MIPS
processor with on chip flash memory and on chip high-precision analog peripherals.
The device architecture is specially optimized for C/C++ programming. Additionally
the IQ math formatting capability enables the user to use the floating point features on
this low-cost fixed-point processor without tedious scaling process or delay resulting
from the direct use of the floating point arithmetic (Spectrum Digital, 2003).
114
This DSP is very common in drives and power converters applications as it is equipped
with many peripherals specialized for this kind of application. In this section, the main
DSP peripherals that have been used in the inverter control are reviewed.
The eZdsp F2812 is a stand-alone card to develop and run software on the
TMS320F2812 processor. The card includes the processor, standard 30 MHz clock, and
64k SRAM besides many other parts.
To facilitate the code development and debugging process, the code composer studio
(CCS), a software package, is provided with the card. Also Texas Instruments
developed and provided other supporting libraries such as the Header Files and
Peripheral Examples library and the IQmath Library that have been used in this project.
A brief description of the peripherals and software tools used in our implementation has
been presented in the following subsections.
4.4.1 General purpose input/output
There are two 16-bit general purpose input/output (GPIO) ports, denoted by GPIOA and
GPIOB besides other smaller digital I/O ports. All the I/O interface lines of the DSP are
multiplexed with the peripheral signals to save the number of pins. Special registers
need to be programmed to determine the access of the line and the signal direction.
The program has been designed to use one of these 16-bit ports as input for the
reference signal and the other 16-bit port as output for the switching signals. This
selection is done for two reasons. First, the DSP peripherals connected to these ports
have not been used by the control algorithm. Second this method is simple and fast (TI,
2004a).
115
4.4.2 General purpose timers
The DSP has three general purpose timers (T0, T1 and T2). One timer, T0, is available
for users applications while the other two timers are specially allocated for the system
use. The general purpose timer (T0) can be used as an internal source of timed interrupt
signal and has been used for timing the sampling process or the output update process.
The general purpose timers are 32-bit counters with presettable periods and 16-bit clock
prescaling. The timers generate the interrupt signal when the counters reach zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting.
After reaching zero the timers reloaded by the present value.
4.4.3 Event managers
The SVM control program needs two timers, one to control the reference sampling
process and the second to update the switching signals at the frequency equivalent to j
multiplied by the input sampling frequency. Only one general purpose timer is available
for user applications. Therefore the event manager (EV) timer has been used.
The DSP is equipped with two identical EV units. The EV is a group of hardware that is
designed for broad range of applications particularly useful for drives control
applications. The EV unit contains counters, comparators, timers besides other
peripherals.
Each EV has two timers. The EV timer can be programmed to control one of the DSP
peripherals or can be used as a general purpose timer. The EV timers are four 16-bit
timers.
The EV timer needs to be programmed so it can be used to initiate its interrupt service
routine (ISR). The programming includes, besides specifying the preset and the clock
116
signal prescale, specifying the function of the timer and programming the peripheral
interrupt enable (PIE) assignment table registers (TI, 2004b).
4.4.4 Interrupt system
The core interrupt system of the F2812 DSP is consists of 16 interrupts lines: two non-
maskable interrupts (reset and NMI) and 14 maskable interrupt lines (INT1-to-INT14).
All 16 lines are connected to a table of interrupt vectors that contains the start address of
the ISR. The DSP has a number of interrupt sources much higher than the number of
interrupt lines. This shortage in interrupt lines has been handled by multiplexing which
is done through the peripheral interrupt extension (PIE) table. PIE is a group of registers
used to multiplex 96 interrupt sources to 12 interrupt lines. The interrupt programming
includes setting of the interrupt flag register (IFR) and the interrupt enable register
(IER) and enable the particular interrupt by programming some other registers (TI,
2002a).
4.4.5 The code composer studio
The eZdsp F2812 is accompanied with the software package known as the code
composer studio (CCS) that forms the essential means to access the controller. CCS is
an integrated development environment for Texas Instruments DSPs. CCS provides
tools for developing and debugging applications including: source code editor,
compilers, debugger and other tools. (TI, 2005).
4.4.6 Header files and peripheral examples library
This library provides a package of files that can be incorporated into a project to provide
a platform for accessing the DSP peripherals using C code. The library is presented in
117
the form of examples that have been developed to control various peripherals by
initializing and setting the necessary hardware through programming the corresponding
registers. By understanding the bit-filed structure approach for mapping and accessing
peripheral register, the user can edit the corresponding file accordingly to set the desired
options for various peripherals (TI, 2007).
4.4.7 IQ-math library
The IQ-format is a special format to represent the floating point numbers designed for
processor with fixed point arithmetic and logic unit (ALU) architecture. In IQ format
the binary number is divided into integer and fraction parts separated by a virtual binary
point. In order to extend the range of representation and maximize the resolution, the
IQ- format allows the manual or automatic adjustment of the binary point location so
the user can make optimum use of the processor word size (TI, 2002b).
The IQmath library is a set of C mathematical functions that is designed to handle the
floating point arithmetic operations. The use of IQmath library speeds up the calculation
process and maintains its precision.
4.5 Auxiliary Circuits
A diagram of the experimental setup of the inverter system is shown in Figure 4.2. In
this figure the right side represents the power circuit described in Section 4.3. The
controller function is done by the F2812 eZdsp card described in Section 4.4 , the three
blocks between the DSP card and the power circuit represent the auxiliary circuit which
is described in this section. The codes representing the reference input and controller
output are also given here.
118
4.5.1 Reference input code
The DSPs parallel port GPIOA is used to read the reference voltage signal. The eight
MSB are used to represent the reference amplitude and the voltage scale is defined by:
h S ref v
V V 10
,
= = (4.8)
The subscript (h) indicates the hexadecimal base. The maximum voltage vector
amplitude reference for linear control region is given by:
h S ref v
EC V V ~ = = 56 . 235 17
2
3
max , ,
(4.9)
This value has been taken as 100% normalized amplitude.
The reference vector angle is represented by the eight LSB of port GPIOA. Two coding
systems for reference angle representation have been used according to the control
mode: the direct scaling and the sector implication codes.
Interface
Computer
Decoder
Blanking
time
Gate
drive
i
l
o
a
d
v
load
H-
Bridge
H-
Bridge
H-
Bridge
H-
Bridge
H-
Bridge
H-
Bridge
Three phase inverter
A B C
12V
36V
Adjustable
torque load
Reference
angle counter
Reference
amplitude
8-bit 8-bit
15-
bit
IM
108V
Controller
Power circuit
Auxiliary circuits

Figure 4.2 The experimental setup.
119
The direct scaling angle code is simply a linear scale with 00
h
represents zero reference
angle and FF
h
represents 358.59375 or with (360/256)/bit, this coding is used in the
SVM mode and in the g-h axis transformation approximation mode.
In sector implication angle coding, the three MSBs of the angles byte (GPIOA
7
-
GPIOA
5
) range from 001
2
to 110
2
according to Figure 4.3. The five LSBs range in the
normal sequence and take 32 values within each sector. The purpose of this
representation is to simplify the determination of the reference vector sector where it
can be taken as the three MSBs of the reference angle byte. There is a loss in resolution
in this representation, as only 192 combinations out of the 256 8-bit combinations were
used. This loss of resolution has no effect on the voltage selection as the smallest angle
between any two adjacent inverter voltage vectors is about 2.83 while the resolution of
this coding is 1.875/bit.
4.5.2 Switching signals decoding and Processing
Among the auxiliary circuits shown in Figure 4.2 is the switching signals decoding and
dead-time insertion linking the DSP to the gate drives circuit. Due to the limited number
001 0 0000 =0x20
Sector
sector angle
0
0
1

1

1
1
1
1

=
0
x
3
F
0
1
0

0

0
0
0
0

=
0
x
4
0
0
x
5
F
0
x
6
0
0x7F
0x80
0
x
9
F
0
x
A
0
0
x
B
F
0
x
C
0

Figure 4.3 The reference angle coding used to implicate the sector as the three MSBs
of the angle representation.
120
of GPIO bits available in the DSP board and the large number of switching signals used,
it has been decided to drive each sub-inverter arm, rather than each switch, with one
DSP output bit. As shown in Figure 4.4, three of the 16 GPIO port bits have been
assigned to represent (x
ABC
). Each of the trinary digits of the medium and low voltage
stages switching signals (y and z) is represented by two bits. So, 6 out of the 16 GPIOB
port bits have been allocated to each of (y
ABC
) and (z
ABC
).
To complete the description, it should be indicated here that the code used of the trinary
digits is as follows:
y
X
=0, or v
X
= V
dc
is presented by (y
X1
, y
X0
) =(0, 1).
y
X
=1, or v
X
= 0 is presented by (y
X1
, y
X0
) =(0, 0) or (1,1).
y
X
=2, or v
X
= +V
dc
is presented by (y
X1
, y
X0
) =(1, 0).
The same code has been used for the low stage switching variable, z. This code is
selected so that each bit represents switching signal for one inverter arm as in the high
voltage stage case. For the second value of the trinity switching signal (when v
o
=0), the
DSP determines whether this state is represented by (0,0) or (1,1) using a zero balancing
routine.
The decoder used is a digital circuit based on monostable timers to provide the
complemented switching bits with inserted dead band time (t
db
). Figure 4.5 shows the
function of the switching signals decoder where the rising edge of the DSP generated
switching bit and its complement is delayed by t
db
to produce the upper and lower
switches gates signals of the corresponding inverter branch respectively.
Following the decoding stage the switching signals are applied to the switching devices
through isolation and amplification gate drive circuits as indicated in Figure 4.2. The
gate drive is based on a standard IGBT/MOSFET optocoupler integrated circuit. The
isolated DC voltages of the optocouplers are obtained by rectifying the isolated voltage
generated by digital oscillator.
121
x
A
x
B
x
C
nu y
A1
y
A0
y
B1
y
B0
y
C1
z
A1
z
A0
z
B1
z
B0
z
C1
z
C0
B
15
B
14
B
13
B
12
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
y
C0
B
2
B
1
B
0
GPIOB

Figure 4.4 The bit allocation of the GPIOB.
t
db
t
db
Arm switching
signal from DSP
Upper switch
switching signal
from decoder
Lower switch
switching signal
from decoder

Figure 4.5 The switching signal decoder function.
4.6 Implementation of Vector Approximation Mode
This section describes the implementation of the voltage approximation algorithm
which is presented in Section 3.5.
The flow chart of the voltage control by voltage vector approximation program is given
in Figure 4.6. It can be seen that the program has two major parts: the main program and
the ISR. The main program contains the initial part, configuration and peripherals
enabling part and infinite loop. While the ISR reads the reference input vector and
calculates the switching signals to be applied during the next sampling interval.
The program initial part has the memory management section besides the usual
include, functions prototypes and variable declaration sections. The IQmath library
and some other header files from the Header Files and Peripheral Examples Library
must be included in the program.
122

Start
Initialize system
control
Configure timer
Enable inturrupts
Infinite loop
ISR
ISR
Update state
output
Read new
voltage
vector
Determine next
high state
Determine medium
reference
Determine next
med. state
Determine low
stage reference
Determine next
Low state
Zero state balance
and the new
switching state
return
Acknowledge
interrupt
Main Program ISR
Memory Map
Include IQmath &
libraries, declear
and prototypes
Initializing and
setting GPIO
Initializing PIE
control
I
n
i
t
i
a
l

p
a
r
t
C
o
n
f
i
g
u
r
a
t
i
o
n

a
n
d

p
e
r
i
p
h
e
r
a
l

e
n
a
b
l
i
n
g

p
a
r
t
I
n
f
i
n
i
t
e

L
o
o
p

Figure 4.6 Flow chart of the voltage vector approximation program.
123
In the memory management section, external memory zones have been defined and
some of the program functions have been allocated in external memory, i.e. on board,
rather than on-chip memory. This has not been avoidable as the program requires a
space beyond the 18k word on chip memory capacity. The start address and the length
of these zones, i.e. the memory map, are specified in the (.cmd) file.
4.6.1 The main program
The main program contains the setting and initializations of the peripherals used as
indicated below:
1- The system control initialization which is responsible of initializing system clock,
PLL, watchdog timer and peripherals clock. This initialization is required the
peripherals to be used.
2- The general purpose input/output initializing and setting. In this step the
corresponding registers have been set to define the ports as general I/O ports. The
direction registers set port A as an input port and port B as an output port.
3- PIE Vector initialization to allocate the interrupt source TINT0 controlled by timer
T0 by remapping it in the PIE vector table.
4- Timers initializations and setting is performed to define the timer initial setting and
prescaling parameters to match the desired sampling time.
5- Enabling interrupt by the defining the corresponding interrupt enable IER register
bit.
After the above steps the DSP became ready to execute the control algorithm so the
main program reaches the infinite loop which is solely a waiting function for the
interrupt timer to produce the interrupt command every T
S
.
124
4.6.2 The interrupt service routine
The flow chart of the ISR is shown in Figure 4.6. Within each sampling intervals the
ISR executes the actual control algorithm described in Section 3.5. The ISR starts by
sending the last calculated value of the switching state [XYZ] to the output port GPIOB.
Next, the new reference voltage is received from GPIOA port and the control algorithm
is used to determine switching state.
Based on the amplitude coding and the sector implication angle coding indicated in
Section 4.5.1 and the switching signals coding in Section 4.5.2, the program determines
the next switching state by the following steps:
1- Determining the next high stage state using the reference voltage vector and the
initial high voltage stage state.
2- Calculating the medium reference vector using the next high voltage state and the
reference voltage vector.
3- Determining the next medium stage state using the medium reference vector and the
initial medium voltage state.
4- Calculating the low reference vector using the next medium voltage state and the
medium reference voltage vector.
5- Calculating the low reference zone and determine the next low state.
6- Zero states balancing for the medium and low voltage stages
7- Acknowledging the interrupt to return the execution to the main program infinite
loop.
125
4.7 Implementation of Vector Approximation Mode Using g-h Coordinates
Transformation
The flow chart of the voltage approximation program using g-h transformation is
described in Figure 4.7. Several similarities can be noticed between the initialization
part and the main function of this program and the sector-zone based program
introduced in Section 4.6. This program, however, uses fewer functions and global
variables and therefore does not allocate external memory zones and uses only the DSP
on chip memory. This is one indication that the g-h transformation achieves the
intended implementation simplicity.
The program uses the two 16-bit GPIO ports in a similar way to the previous program
except that the direct scaling code is used to represent the reference vector angle as
indicated in section 4.5.1 where the sector determination is not required.
The ISR approximates the reference g-h voltages to the nearest integers and performs
the high and medium voltage stages control using pure integer arithmetic. The deducted
fraction is re-added to the low voltage stage reference that results from subtracting the
next medium stage vector from the medium stage vector. So the resultant low voltage
stage actual reference represents the exact difference between the sampled reference and
the next high and medium stages voltage vectors. This procedure made the control of
the high and medium voltage stages pure integer and therefore saves the execution time.
The real numbers in the low voltage stage calculations are handled using IQ math.
126

ISR
Update output
Read new
voltage
vector
Determine next
high state
Determine medium
reference
Determine next
med. state
Determine low
stage reference
Determine next
Low state
Zero state balance
and the new
switching state
return
Acknowledge
interrupt
dq-gh
transformation
Approximate to
nearest integer
Start
Initialize system
control
Configure timer
Enable inturrupts
Infinite loop
ISR
Include IQmath &
libraries, declear
and prototypes
Initializing and
setting GPIO
Initializing PIE
control
I
n
i
t
i
a
l

p
a
r
t
C
o
n
f
i
g
u
r
a
t
i
o
n

a
n
d

p
e
r
i
p
h
e
r
a
l

e
n
a
b
l
i
n
g

p
a
r
t
I
n
f
i
n
i
t
e

L
o
o
p

Figure 4.7 Flow chart of the voltage approximation using g-h transformation.
127
4.8 Implementation of Vector Control Mode
The SVM control program flow chart is shown in Figure 4.8, this program has a main
program and two ISRs. The program receives the reference input at a constant sampling
rate which is the outer loop interval. During T
S
, the program determines the j-element
next output switching signals vector denoted by State
j
. The process of sampling the
reference voltage and determining the next State
j
is carried out in the ISR which is
controlled by the lower priority EV timer T1. The higher priority ISR, TINT0 controlled
by timer T0, is used to update to the output port at constant interval T
C
=T
S
/j.
The main program has initialization part similar to that described in Section 4.6. The
external memory has been used to store State
j
. The actual calculation process is carried
out by the lower priority interrupt service routine (ISR_EVTimer1). In this routine the
calculations of the high and medium stages switching signals are very similar to those of
the voltage approximation mode except for the adjustment of the high state domain
definition according to Figure 4.9. In this program, it has been chosen to use the g-h
coordinates based calculations. Using the g-h representation of the inverters vector
simplifies the process of modifying the high state domain to solely changing the number
equivalent to the domain size from 8Vs to 7Vs in the high state domain comparison
step.
The low voltage stage calculations start with a systematic procedure to determine the
three nearest vectors and their duty ratios. The state sequence, as indicated in Chapter 3,
depending on the reference vector location which has been described by the triangle
formed by the three nearest vectors. In order to determine the reference vector triangle
and hence the state sequence, a special coding for the low voltage states has been used
and defined in a constant matrix denoted by lowstates. The elements of this matrix are
shown in Figure 4.10 with respect to the low voltage stage vectors. The element of the
128
Start
Initialize system control,
GPIO, PIE control, Timer0,
EVTimer 1
Configure timers
& Enable
interrupts
Infinite loop
ISR_Timer0(Ts/j)
ISR_EVTimer1(Ts)
ISR
EVTimer1
Read new
voltage
vector
Determine next
high state
Determine medium
reference
Determine next
med. state
Determine low
stage reference
Determine nearest
three vectors and
duty ratios
Zero state balance
and the new
switching state
return
Acknowledge
interrupt
dq-gh
transformation
Approximate to
nearest integer
Determine
reference triangle
type
Extract the State(j)
Vector
ISR_timer0(Ts/j)
Update O/P =
State(counter)
Counter 1:j
Counter =j?
yes
Counter =0
Update State(j)
No
Counter ++
return
Memory Map
Include IQmath &
libraries, declear
and prototypes

Figure 4.8 The SVM control program flow chart.
i
th
row and j
th
column represents the (g, h) normalized vector dimensions equal to (i-3,
j3). The 8-bit code is described as follows:
129
h
-
a
x
i
s
g-axis
h=0x80
h=0x80
g
=
0
x
8
0
g
=
0
x
8
0
g
+
h
=
0
x
8
0
g
+
h
=
0
x
8
0
(0x80,0)
(0,0x80)
(0x80,0x80)
(0x80,0)
(0x80,0x80) (0x80,0x80)
g
+
h
=
0
x
7
0
h=0x70
h=-0x70
g
+
h
=
-
0
x
7
0
g
=
0
x
7
0
g
=
0
x
7
0
High state domain for
ref. Amplitude <0XAA
High state domain for
ref. Amplitude >0XBE
Hysteresis band

Figure 4.9 The high state domain condition represented in g-h coordinates.

Lowstate (i, j)=(L
1
L
0
z
A1
z
A0
z
B1
z
B0
z
C1
z
C0
)
2
(4.10)
The six least significant bits represent the switching state as indicated in the code
described in Section 4.5.2. The two most significant bits are used to indicate the vector
layer as follows:
(L
1
,L
0
)=(0,0) for outer vectors
(L
1
,L
0
)=(0,1) for inner nonzero vectors
(L
1
,L
0
)=(1,1) for zero vector
The invalid low state vectors are denoted by (0xFF) as shown in Figure 4.10.
The reference vector triangle type is determined by a variable denoted by Type that has
been found by adding the two most significant bits of the three nearest vectors and it is
found as follows:

130
Type =1: reference triangle formed by two outer vectors and one inner vector.
Type =2: reference triangle formed by one outer vector and two inner vectors.
Type >2: reference triangle formed by two inner vectors and zero.
This coding leads to a definition of the variable Type which is compatible with the
reference triangle type described in Figure 3.23.
The sampling time T
S
is divided into j subintervals each of a length equivalent to
T
C
=T
S
/j. During the subinterval, one element of the recent State
j
vector is transferred to
the output port. So the output port is updated every T
S
/j. This process is handled by the
higher priority ISR (ISR_Timer0). Figure 4.8 indicates that when the index pointer
reaches the end of the vector, this occurs at the last (j
th
) subinterval within the switching
intervals, the State
j
vector is updated with the newly determined vector.
For proper operation it must be assured that ISR_EVTimer1 has finished determining
the new State
j
within T
S
. By testing the program speed, we have found that with T
S
=
g
=
2
g
=
1
g
=
0
g
=
1
g
=
2
h=2
h=1
h=0
h=1
h=2
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x1A
0x18
0x19
0x12
0x50
0x51
0x09 0x29
0x41
0xC0
0x54
0x16 0x06 0x26
0x24
0x44
0x45 0x25
0x21

Figure 4.10 Coding used for low voltage stage states to imply the reference type.
131
100 sec and j = 100, the DSP can run the program properly. This sampling time
represents 200 samples over the 50Hz reference and therefore sufficient for many
applications recalling that the voltage vector control mode is intended for low voltage
and then low frequency operation.
4.9 Summary
This chapter describes the experimental setup of the 18-level inverter and the control
algorithms implementation. The intended load motor data has been considered for the
current and voltage levels identification and hence the switching devices and the DC
link selection. The switching frequency is estimated based on the control algorithm
described in Chapter 3. The DSP card eZdspF2812 has been found suitable for its low
cost, optimization with C-code, and the availability of appropriate peripherals such as
the interrupt system, input/output unit, and the supplement of the supporting libraries.
The switching signal decoding has been done in external auxiliary circuit that has been
described. The control programs have been discussed, the flow charts are given and the
control programs have been described.
132
Chapter Five
Experimental Results
5.1 Introduction
The inverter is designed and the control algorithm is developed in Chapter 3. During the
design stage many claims made concerning the proposed control concept and
calculations need to be verified. This chapter presents the measurements necessary to
prove the achievement of the desired features of the inverter and control strategies by
measuring voltages, switching signals and currents in various conditions. The inverter
performance mainly in terms of harmonics contents and switching losses has been
examined. The two voltage approximation algorithms and the SVM algorithm in basic
and modified high state domains have been tested. The testing results are presented to
verify that the performance targeted at the design stage has been achieved.
5.2 Inverter Testing in Vector Approximation Mode
The testing results of the MLI when controlled by the voltage approximation algorithm
presented in Section 3.5 and with the control algorithm implementation described in
Section 4.6 is presented. The voltage approximation control has been designed to
produce low distorted voltage exploiting the large number of inverter levels. This mode
also designed to operate the high voltage stage at the fundamental frequency and the
lower voltage stages controlled to operate at low switching frequency. The DC current
133
is supposed to be unidirectional for the high voltage stage. To verify these features,
measurements of voltages, currents and switching signals are presented in this section.
5.2.1 Phase voltage measurements
The load phase voltages are shown in Figure 5.1 for various values of reference voltage
amplitudes and reference frequency of 50Hz. It can be seen that the number of voltage
steps goes up when the reference amplitude increases. The smaller number of steps
resulting higher harmonic distortion at the lower range of output voltage. The variation
of the number of levels and the load phase voltage harmonic distortion as a function of
the reference amplitude is given in Figure 5.2. In this figure the number of levels is
taken as the number of inverter arm voltage steps or the number of steps of the voltage
measured between the output point and common emitter point of the main stage.
The harmonic distortion is considerably higher for reference amplitude below 40% and
with very small reference amplitude the harmonic distortion converges to that of basic
two-level inverter in six-step mode. Furthermore the stepped voltage waveform implies
that the dominant harmonics will be of low order and therefore can cause considerable
current distortion.
With 80% reference amplitude, the load phase voltage corresponding to individual
inverter stages and the total voltage are shown in Figure 5.3. This figure shows that the
phase voltage corresponding to the high voltage two-level stage denoted by v
an_High
has
a six-step waveform which verifies that this stage operates in the square wave mode,
and subsequently at fundamental frequency. The medium stage voltage denoted by
v
an_Med
switching frequency which is 5 multiples of the fundamental frequency. The load
voltage corresponding to the low voltage stage is denoted by v
an_Low
is shown added to
that of the medium voltage stage as it will not be clear on the same voltage scale. This
voltage brings the inverter voltage to the nearest level of the reference voltage.
134

(a) Reference voltage amplitude=20%

(b) Reference voltage amplitude=30%

(c) Reference voltage amplitude=60%
Figure 5.1 Load phase voltage of the inverter operating in the voltage approximation
mode with 50Hz frequency and various values of reference amplitude.

135

(d) Reference voltage amplitude=70%

(e) Reference voltage amplitude=80%

(f) Reference voltage amplitude100%

Figure 5.1 ,continued Load phase voltage of the inverter operating in the voltage
approximation mode with 50Hz frequency and various values of reference amplitude.

136

Figure 5.2 Number of levels and harmonic distortion against the reference amplitude.
v
an
v
an_High
v
an_Med
v
an_Med+Low

Figure 5.3 The load phase voltage with 80% reference amplitude and the corresponding
voltages due to high-, medium-, and (low+ medium)-voltage stages.
137
5.2.2 DC side current
With a reference voltage of 80%, and load power factor of 0.8, the load current
measurements and the DC supply currents are shown in Figure 5.4 together with the
load voltage. This figure shows that the load current waveform shown in Figure 5.4(a) is
very close to the pure sinusoidal. The high voltage stage inverter DC current is shown in
Figure 5.4(b) confirms that the high voltage stage is operating in square wave mode and

(a) The load voltage and current. (b) The load voltage and main stage
DC current.

(c) The load voltage and medium
voltage stage DC current.
(d)The load voltage and low voltage stage
DC current.
Figure 5.4 The load and sources currents of the 18-level inverter with reference
amplitude= 80%.
138
also this current is unidirectional for non-regenerative loads. Figure 5.4(b) verifies the
feature of reduced DC supply cost and losses of this hybrid design by having
unidirectional low ripple current. The medium and low voltage stage DC currents are
shown in Figure 5.4(c) and 5.4(d) respectively. These stages currents are highly reactive
and these stages need bidirectional current sources. The medium stage current shows
that this stage is operating at 3 times the fundamental frequency while Figure 5.4(d)
shows that the low voltage stage is operating at 12 times the fundamental frequency.
5.2.3 Inverter characteristics
The voltage vector approximation control has been implemented using the domain-zone
based calculations to control the high and medium voltage stages employing the
flexibility available with optional state selection to minimize the switching losses.
Interpolating polynomial is implemented to select the low voltage stage sub-inverter
producing the voltage vector which is nearest to the reference vector. The main findings
can be listed as follows.
5.2.3.1 Voltage waveform
With M>40% there is little distortion due to the large number of steps available to
construct the reference voltage. As M goes down the distortion level increases inversely,
the stepped voltage waveform implies that there will be low order harmonics distortion
for small values of M.
5.2.3.2 The switching frequency
The high voltage stage operates in square wave mode, i.e. at the output frequency.
Medium voltage stage operates at few multiples of this frequency, while the low voltage
stage operates at frequency few multiples of that of the medium stage. The number of
multiples depends on M. The total number of switching actions is minimized.
139
5.2.3.3 Current measurements
With M=80% and without any external filter the load current is close to pure sine wave.
The DC side currents verify that the high voltage stage current is unidirectional while
the medium and low voltage stages have bidirectional current. The medium voltage
stage DC side current average depends on the reference amplitude. As anticipated in
Chapter 3, the low voltage stage average current is close to zero.
5.3 Inverter Testing Using g-h Axis Based Voltage Approximation Method
The inverter has been operated to approximate the reference vector using the control
algorithm proposed in Section 3.6 and the implementation described in Section 4.7. This
mode is designed to operate the inverter is a way similar to the method presented in the
previous section using faster calculations. The voltage measurements are conducted to
verify that the two methods lead to equivalent characteristics and the processing speed
is compared.
5.3.1 Voltage waveforms
With various values of the reference voltage amplitude and reference frequency of
50Hz, the load phase voltages are shown in Figure 5.5. The corresponding fundamental
peak values and harmonic distortion as a function of the reference voltage vector
amplitude are shown in Figure 5.6. These two figures when compared to Figures 5.1
and 5.2 verify that the g-h approximation mode is essentially equivalent to the basic
domain-zone calculations based approximation. Some waveforms in Figure 5.5 have
been shown for different values of reference amplitude compared to Figure 5.1 to show
more details at the lower range of M.

140

(a) Reference voltage amplitude10%

(b) Reference voltage amplitude40%

(c) Reference voltage amplitude 50%
Figure 5.5 Phase voltage waveforms of the inverter operating with g-h approximation
mode with 50Hz frequency and various values of reference amplitude.
141

(d) Reference voltage amplitude70%

(e) Reference voltage amplitude 80%

(f) Reference voltage amplitude 100%
Figure 5.5 continued, Phase voltage waveforms of the inverter operating with g-h
approximation mode with 50Hz frequency and various values of reference amplitude.

142

Figure 5.6: The fundamental voltage amplitude and the harmonic distortion against
the reference amplitude for inverter operating in g-h approximation mode.
0
2
4
6
8
10
12
14
16
0
20
40
60
80
100
120
140
10 20 30 40 50 60 70 80 90 100
F
u
n
d
a
m
e
n
t
a
l

o
u
t
p
u
t

V
o
l
t
a
g
e

(
V
)
Reference Amplitude %
T
H
D

Reference Amplitude %
T
H
D

(
%
)

As indicated in Chapter 4, the g-h approximation program has been executed using the
DSP memory only and without the need for the external memory. This save in memory
space is explained by comparing the basic d-q calculations and the g-h based
calculations as follows:
1- The lookup table used in controlling the high voltage stage in the basic
approximation program is not used.
2- The number and size of variables needed is smaller.
3- The functions are easier and shorter; pure integer functions used for high and medium
stages calculations.
Besides the reduction in the memory space, the g-h based approximation program works
faster than the basic program used in Section 5.2. In order to test the execution speed,
143
the programs have been slightly modified by making the reference angle internally
generated by a counter rather than received externally from the GPIO port, so the
program will not skip any reference values when busy with calculations. The ISR timer
decreases the sampling time gradually to find the shortest time that the ISR routine can
keep up with. It has been found that the g-h based approximation algorithm can be
executed within 48sec while the basic approximation algorithm needs about twice this
time.
The measured voltage waveforms are very close to those obtained in the basic control
mode. And the THD variation with the reference amplitude is very similar to that
presented in Section 5.3.
The fundamental voltage peak as a function of the reference amplitude is also shown in
Figure 5.6. When compared to the ideal case (117.8*M Volts), we can notice that the
resultant voltage, for any value of M, is (2.0 to 3.5 Volts) less than the ideal value. This
reduction is mainly due to the switching devices voltage drop that is partially
compensated by the battery voltage being slightly higher than the nominal 12 Volts.
5.4 Inverter Testing in Space Vector Control Mode Using Basic High State
Domain
The vector control mode based on the SVM concept presented in Section 3.7 with the
implementation described in Section 4.8 has been tested. In this section, the basic
domain of 8Vs is considered as the only high state domain, where the hysteresis domain
adjustment part described in Section 3.7 has been disabled. The voltage waveforms and
switching signals measurements have been conducted in order to examine the dominant
harmonics order and verify that the high and medium voltage stages operate at low
switching frequency as that of voltage approximation methods. Additionally, the testing
is conducted to examine the switching frequency of the low voltage stage and its
144
relationship with the sampling frequency. The output voltage and the harmonics
distortion when the reference vector passes the regions beyond PWM control reach
indicated in Section 3.7 are also tested.
5.4.1 Switching signals
With 50Hz frequency and 80% amplitude reference voltage, and with T
S
of 111sec and
j of 100, the resultant switching signals are shown in Figure 5.7. The four displayed
signals are, from the top; the high voltage stage switching signal x
A
, the MSB of the
medium stage switching signal y
A1
and the MSB of z
A1
, and the fourth signal is a 50
time zoom in the third signal.
The high voltage stage switching signal confirms that this stage operates in square wave
mode and hence at fundamental frequency. The medium voltage stage switching signal
shows what has been anticipated earlier that the medium voltage stage switching
frequency is a few times that of the fundamental frequency, in this case it is four times
the fundamental frequency. This ratio, as indicated earlier, depends on M. The low
voltage switching frequency is considerably higher than the high and medium stage
frequencies and not comprehensible on the same time scale. Over 1 msec the low
voltage stage switching signal has 4.5 pulses as seen in the fourth waveform of Figure
5.7, this interval represents 9 switching intervals (9msec/111sec), so as expected
according to the switching sequence proposed in Section 3.7, the switching variable
changes its value once every T
S
which results one switching pulse every 2T
S
. This
confirms that the suggested states sequencing order achieved its target of having one
switching pulse every 2T
S
for each switching variable.

145
Figure 5.7 Switching signals at the DSP card port for voltage vector control mode with
80% amplitude, 50Hz reference signal.
5.4.2 Voltage waveform
With reference frequency of 50Hz, T
S
of 111sec, j of 100 and with various values of
the reference voltage magnitude, the resultant phase voltage waveforms are shown in
Figure 5.8. To study the characteristics of the waveforms of Figure 5.8, the frequency
spectrum of two waveforms when the reference amplitude is 10% and 80% are shown in
Figures 5.9 and 5.10. For 10% reference amplitude, Figure 5.9 shows that the harmonic
distortion has increased to 17.5%. This increase is due to the limited number of voltage
steps in the small M range. The distortion effect of the harmonics is mainly determined
by the harmonics order or frequency. Figure 5.9 shows that the dominant harmonics
order is around 180. Recall that this figure represents the number of samples in each
voltage cycle (20msec/ 111sec). From another side, the dominant harmonics frequency

146
is around 9kHz and this represents double the average switching frequency of the low
voltage stage, i.e 4.5 cycles/1 msec as shown in Figure 5.7.

(a) The amplitude of Vref=10%

(b) The amplitude of Vref=20%

(c) The amplitude of Vref=30%
Figure 5.8 Phase voltage measurements with various values of reference
amplitude.
147

(d) The amplitude of Vref=40%

(e) The amplitude of Vref=70%

(f) The amplitude of Vref=95%

Figure 5.8 Continued. Phase voltage measurements with various values of reference
amplitude.
148

Figure 5.9 The inverter phase voltage wave and frequency spectrum, with reference
amplitude of 10%.
Figure 5.10 shows the spectrum of the voltage waveform with reference amplitude of
80%. With this value of M, the THD is very small and despite the visible concentration
of the harmonics around the order 180, comparable level of harmonics, which is due to
various sources, can be seen at lower frequency levels, these harmonics are due to
several imperfections and visible only because the overall harmonic contents is very
small. Figure 5.11 shows the total voltage build up by the three inverter stages for a
reference voltage of 90% amplitude. The upper waveform shows the phase voltage due
to the high voltage stage only. As in the voltage approximation mode, this voltage is has
a six step waveform. The middle figure shows phase voltage due to the high and
medium voltage stages, again this voltage verify the low frequency operation of the
medium voltage stage. The bottom waveform shows the total voltage due to the three
inverter stages.
149

Figure 5.10 Spectrum of the output voltage waveform with 80% reference amplitude.

Figure 5.11 Build up of the inverter voltage by the three inverter stages from the top
high voltage stage, high and medium voltage stages, and the three inverter stages.
(5msec/div, 50V/div.)
Harmonics Order

150

Figure 5.12 The phase voltage distortion every 30 with the basic high voltage domain
and 45% reference amplitude.
The other feature that can be observed from the waveforms shown in Figure 5.8, is
some distortion in the waveform with the reference amplitude of 70% and 95%. This
type of distortion is highlighted in Figure 5.12 for M= 45%. Figure 5.12 shows that the
distortion is occurring every 30 and this can be related to Figure 3.26 in Section 3.7. As
indicated in Chapter 3, the basic definition of the high state domain as a hexagon of 8Vs
side length leads with certain ranges of M a low voltage stage reference which is beyond
the SVM control region.
The variation of the THD as a function of the reference voltage amplitude is shown in
Figure 5.13. This figure confirms that the inverter operated in SVM control mode has a
wide range of low harmonic distortion. Recalling that the increase in the harmonic
distortion at low reference amplitude is occurring with dominant harmonics order which
is around (T/

T
S
) provides the option to control the harmonics order, therefore the
voltage quality is not as affected as it looks in Figure 5.13, as the switching frequency
can be adjusted to make the inductive reactance large enough at the dominant harmonics
frequency. Figure 5.13 also reflects the effect of intersecting the areas indicated in
151
Figure 3.26 outside the SVM control region as local peaks in the harmonic distortion
characteristics.

Figure 5.13 Measured THD versus the reference amplitude with the basic high state
domain.

The results shown in this section confirm that the proposed control method ensures that
the high voltage stage operates at the fundamental frequency and the medium voltage
stage operates at a few multiples of the fundamental frequency and there is no
simultaneous and high voltage stage high switching frequency.
It has been also shown that the low voltage stage has an average switching frequency
that is equivalent to half of the sampling frequency and this agrees with the state
sequence proposed in Section 3.7.
The dominant harmonic frequency is around the sampling frequency and this is a
general feature for SVM controlled inverters. In the tested inverter, however, the
advantage is that the overall output voltage has this character despite that only the low
152
voltage stage is SVM controlled while the high and medium stages are operated at low
frequency which implies considerable reduction in switching losses.
For certain range of frequency amplitude some additional distortion is experienced. This
has been anticipated at the design stage in Chapter 3 and the proposed solution for this
distortion is tested in the following section.
5.5 Inverter Testing in Space Vector Control Mode Using Modified High State
Domain
With the domain adjustment comparator disabled and the high state domain fixed to the
modified domain of (7V
S
), the inverter has been tested to examine the inverter
characteristics. The effect of domain modification on the distortion during the
intermitted ranges indicated earlier is examined and the behavior of the inverter at large
values of M is also tested.
With 111sec sampling interval and j= 100 subintervals per sampling period, 50Hz
reference frequency and various values of the reference amplitude, the resultant phase
voltage waveforms are shown in Figure 5.14. It can be noticed that the distortion
occurred with the basic high stage domain for certain reference amplitude is avoided in
this mode. On the other hand for M of 95%, an obvious distortion appears in the output
voltage every 60.
To examine the elimination of the modified domain on the distortion appeared in
intermitted regions, consider Figure 5.15 which shows the load voltage when the
reference voltage is 45%. Distortion which has been observed every 30 in Figure 5.12
for the basic domain has vanished. To further examine the difference in operation
153
between this mode and the basic domain mode, consider Figure 5.16. The switching
signals corresponding to the high voltage stage is shown in Figure 5.16(a) and the phase
voltage corresponding to the high voltage stage only is shown in Figure 5.16(b). Figure
5.16(c) shows the phase voltage corresponding to the medium and high voltage stages.
Figure 5.16 (a) shows that the high voltage stage switching state takes the sequence
(x
ABC
= 000, 100, 000, 010, 000, 001). This implies that this stage in this case goes
through zero state between the nonzero states. With the basic (8V
S
) domain, the
reference vector will always be in the high state domain of the zero state, and the
inverter always produces zero high voltage state. This will lead to a low stage reference
which in beyond the SVM control region of the low voltage stage. Figure 5.16(b) shows
that the high voltage waveform resultant from this mode is consistent to the switching
signals, where a phase voltage will be 2V
dc
/3 when the corresponding switching
variable is 1 and the other two variables are zeros, in this case the other two phase
voltages will be V
dc
/3. The low and medium stage voltage waveforms shown in Figure
5.16 (c) confirm that the low stage reference is always within the low voltage SVM
control region. It has to be mentioned here that the high voltage stage is still operating at
the fundamental frequency without any unwanted high frequency switching.

154

(a) The amplitude of Vref=10%

(b) The amplitude of Vref=20%

(c) The amplitude of Vref=40%
Figure 5.14: Measured phase voltage waveforms for various values of reference
amplitude with modified high stage domain.
155

(d) The amplitude of Vref=50%

(e) The amplitude of Vref=70%

(f) The amplitude of Vref=95%

Figure 5.14, continued Measured phase voltage waveforms for various values of
reference amplitude with modified high stage domain.

156

Figure 5.15 The phase voltage with 45% reference amplitude and modified high stage
domain.
The phase voltage THD is shown in Figure 5.17, we can notice from this figure that up
to 80% reference amplitude, the characteristics are similar to those corresponding to the
basic high state domain shown in Figure 5.13 except for the two intermitted rise in the
harmonics distortion around M=45% and M=65% has been eliminated in the modified
domain method. For the values of M higher than 80% we have measured a fast rise in
the harmonic distortion for the modified method. In this region the basic domain
provides better performance.
The application of the control strategy that switches between the two domains, as
suggested in Figure 3.28 will not imply any added complexity. By switching between
the basic and modified domains in the way shown in Figure 5.18 optimized
characteristics can be achieved. Figure 5.18 indicated that the suggested switching to the
basic domain when the reference amplitude exceeds 82% and to the modified domain
when the reference amplitude is below 71%, is consistent with the measured THD for
the two domains.
157

(a) high voltage stage switching signals

(b) phase voltage due to high voltage stage only

(c ) phase voltage due to medium and low stages only
Figure 5.16 Phase voltage measurements with M=45% showing the individual stage
voltages with modified high stage domain.
158

Figure 5.17 Measured THD versus the reference amplitude for SVM controlled inverter
with modified high stage domain.

It has been verified by measurements that with the basic domain, the distortion due to
crossing the zones (ZM12) and (ZM14) results low state reference that cannot be
realized by the basic SVM control of the low voltage stage. This distortion can be
eliminated using the modified domain concept for the ranges of M which are around
45% and 65 %.
proposed domain switching
7Vs
8Vs
switching
region

Figure 5.18 Optimum harmonic distortion results from switching the domain between
the basic and modified.
159
5.6 Summary
The experimental testing results of the 18-level inverter for various modes of operation
have been presented. The basic voltage approximation method based on direct
calculations in the d-q axis system has been implemented. The voltage approximation
method reduces the switching losses considerably and the THD is less than 5% as long
as the reference amplitude is higher than 40%. With lower values of reference
amplitude, the number of steps available to construct the reference voltage is reduced
and the harmonic distortion increases considerably.
It has been shown that the proposed voltage approximation method can be also applied
using the 60 displaced g-h axis system. The testing results show that the two methods
are basically equivalent in terms of the resultant switching signals and hence the output
voltage and DC currents characteristics. The g-h approximation method however
provides considerable saving in the processing time and program memory.
In SVM mode it has been verified that the high frequency switching of the high voltage
stage and the high frequency simultaneous switching have been eliminated. It has been
also shown the dominant harmonic frequency is around twice the average switching
frequency of the low voltage stage.
The control algorithm based on the basic domain of 8Vs is tested and it has been shown
to cause additional distortion within two intermitted ranges of the reference voltage
amplitude. The proposed high state domain adjustment has been shown to prevent this
distortion effectively.

160

Chapter Six
Analysis and Discussion
6.1 Introduction
This chapter analyzes and discusses the experimental results which have been presented
in Chapter 5. The inverter characteristics have been furnished from the obtained results.
The performance of voltage approximation algorithm is compared to previous studies
that applied standard control methods. While the inverters features when operating in
SVM control mode is compared to other studies that used innovative control
approaches.
The last part of this chapter discusses the study outcomes against to the objectives of
this thesis and highlights the study achievements.
6.2 Voltage Vector Approximation
The measured results show that the two voltage approximation algorithms, the d-q and
the g-h based algorithms, lead to the same output voltages. Accordingly, the discussion
presented in this section covers the two algorithms.
As for the voltage harmonic distortion, It has been noted that with reference amplitude
higher than 40%, the harmonic distortion is less than 5%, this figure is usually
161
comparable or better than what has been obtained by other studies that use fewer
number of levels and apply high switching frequency, (McGrith et.al., 2003; Jingang
and Tianhao, 2007). Therefore, we can suggest that this mode is suitable to control the
drives in medium and high speed range where the voltage is not very far from the rated
value and the frequency is not much lower than the rated frequency.
There is an inverse relationship between the harmonic distortion and the reference
amplitude. This is due to the reduction in the number of steps as the reference amplitude
decreases. It can be noted from the measured waveforms, such as the waveforms shown
in Figure 5.5(a), that the load phase voltage step is equivalent to one third of the low
voltage stage supply (V
S
). Consequently, the lower reference amplitude is approximated
by fewer steps and therefore has more distortion.
The voltage fundamental peak as a function of the reference amplitude has been
measured and it has been found that this value is always about 2.0-3.5Volts below its
ideal value. The reason is mainly due to the switching devices voltage drop as there are
six series switching devices in the current loop. The actual voltage drop is higher than
this value but it has been partially counterbalanced by the battery voltages which are
higher than the nominal 12 Volts. This drop can be always compensated by various
ways that lead to higher reference amplitude to account for this voltage drop. Being
almost independent from the supply voltage, this drop should be less effective if the
inverter is designed with higher voltage rating.
As for the switching frequency it has been shown that the high voltage stage operates at
the fundamental frequency while the medium voltage stage at a few multiples of the
fundamental frequency. In addition the low voltage stage frequency is a few multiples
of the medium stage frequency.
162
To compare the switching losses, we consider the total number of switching actions for
the 30 inverter switches. Assuming the medium voltage stage frequency is five times the
high voltage stage frequency since this frequency has been found by measurements to
be three to five times the high voltage stage frequency. The low voltage stage frequency
will be taken as five times the medium voltage stage frequency based on Figures 5.3 and
5.4. Both ratios agree with the theory presented and the performance anticipated in
Chapter 3. According to the above assumptions, the total inverter switching actions per
output voltage cycle will be:
For high voltage stage: 6 switches 2 switching actions
For medium voltage stage: 12 switches 25 switching actions
For low voltage stage: 12 switches 255 switching actions
Results n
cycle
=732 total switching actions per output voltage cycle.
Compare this number with that of a conventional 6 switching inverter operating to
generate 50 Hz with carrier frequency f
C
.
The number of switching action = 6 switches 2 switching actions f
C
/50.
By comparing the two numbers we can notice that the number of switching pulses is
equal to n
cycle
when the conventional inverters carrier frequency is 3.05kHz. If we take
into account that the medium and low voltage stages are expected to have much lower
switching losses compared to the high voltage stage, where the switching losses are
proportional to the off state voltage level (Erikson and Maksimovic, 2001), then the
switching losses of the MLI will be only a fraction of the PWM controlled conventional
inverters losses. On the other hand, it has to be taken into account that the current of
the MLI always passes through six switching devices, and this leads to higher
conduction loss, which is about triple that of the conventional inverter. But the
conduction loss can be reduced by selecting switching devices of low ON-state voltage
163
drop for the high and medium stages making use of the tolerance provided by the low
switching frequency.
6.2.3 Currents waveforms
With respect to the current waveforms, we have seen that the AC current is very close to
the ideal sinusoidal current. The DC sources current are largely different between the
three stages sources. The high voltage stage DC source current is basically
unidirectional and similar to that of a conventional square wave inverter which implies a
considerable reduction in the source cost compared to the CHB topology. The medium
and low voltage stages currents are bidirectional. Due to the relatively low operation
frequency of the medium voltage stage and the current average variation with the
reference amplitude, it is difficult to prevent the use of bidirectional supply for this
stage. The average of the low voltage stage current, however, is close to zero and with
proper modification of the control algorithm the supply of this stage could be changed
by capacitors if the control algorithm is developed to assure zero average current for this
stage. This option, however, is not among the objectives of this study and has not been
attempted.
6.2.4 Basic d-q versus g-h axis calculations
The voltage vector approximation control has been implemented using the domain-zone
based calculations in the d-q plane to control the high and medium voltage stages. The
flexibility available with optional state selection is solely used to minimize the
switching losses. Interpolating polynomial is implemented to select the low voltage
stage sub-inverter producing the voltage vector which is nearest to the reference vector.
The g-h approximation algorithm has been found to provide the same performance as
the primitive calculations algorithm in terms of voltage and current waveform and
164
harmonics distortion. The g-h based algorithm, however, provides considerable
reduction in memory and processing time. This similarity in performance is expected
since both algorithms depend on the same theory.
With the selected DSP, the g-h transformation technique is more computationally
efficient as many calculation steps become pure integer. The polynomial interpolation
used to control the voltage stage in basic d-q calculations, however, could be more
efficient with other processors. It is anticipated that this technique will be suitable for
ALUs with zero-look-ahead multiplication units (Ackland et al., 2000), where the
polynomial interpolation technique to determine the reference location could be
extended to the medium and high voltage stages calculations.
6.2.5 Comparisons with previous studies
Table 6.1 compares the 18-level inverter system operating in voltage approximation
mode to other multistage and MLIs operating with standard high and low frequency
strategies. The topologies selected for comparison use comparable number of switching
devices and DC supply sources. These designs, however, did not aim to provide the
maximum number of levels allowed by the inverter topology. Therefore the proposed
MLI has higher level-to-devices ratio and the lowest THD for M between 0.8 and 0.9
due to the highest number of levels.
The inverters considered for comparison in Table 6.1 apply harmonic distortion
reduction techniques based on high frequency PWM control (Yun et al., 2007 and Mc
Grath et al., 2003), and the low frequency selected harmonics elimination techniques
(Jingang and Tianhao, 2007). Table 6.1 shows that the proposed approach of
maximizing the number of levels provides reduced harmonics distortion and switching
losses. It has to be mentioned at this point that the harmonics order has not been taken
into account in this comparison. It is expected however that this parameter is not so
165
effective at the high range of M. As M decreases, the low order harmonics of the voltage
approximation method is expected to degrade its quality compared to the high frequency
methods.

Table 6.1 Comparison between the suggested inverter system topology and three other
systems.
Topology
description

Property
.
Hybrid
cascaded
3-stages

(Proposed
Inverter)

Cascaded 5-
level and
two three-
level stages

(Yun et al.,
2007)
Cascaded H-bridge
symmetrical

(Mc Grath et al., 2003)

Hybrid 3-level
NPC arm plus
half bridge DC
shifter.

(Jingang and
Tianhao, 2007)
2-stage 3-stage
Control
Method
Vector
Approximatio
n
Modified
SPWM
Optimized SVPWM
Selective
harmonic
elimination
No. of
switching
devices (3-
phase)
30 48 24 36 18
DC Supply
Main
unidirectional
and 6
auxiliary
bidirectional
Main
unidirectional
and 6
auxiliary
bidirectional
6 bi-
directional
9 bi-
directional
Main and 2
auxiliary
No. of levels 18 13 5 7 6
(level/switch)
ratio
0.60 0.27 0.21 0.19 0.33
Main stage
switching
frequency/ f
o

1 1 21 21 1
THD%
(M=0.8-0.9)
2.4-2.9 7.6 12.85 10.5 16.5

166
6.3 Voltage Vector Control
The proposed SVM controlled inverter's features, which were verified by the
measurements presented in section 5.4,and 5.5, are discussed in this section.
The testing results confirm that the proposed control method ensures that the high
voltage stage operates at the fundamental frequency and the medium voltage stage
operates at few multiples of the fundamental frequency and there is no simultaneous or
high voltage stage high switching frequency. This confirms the realization of the project
objective related to this point.
It has been also shown that the low voltage stage has an average switching frequency
that is equivalent to half of the sampling frequency which verifies the success of the
state sequence proposed in Section 3.7 to realize this feature.
6.3.2 Resultant voltage
The dominant harmonics frequency is around the sampling frequency and this is a
general feature for SVM controlled inverters. In the examined inverter however, the
advantage is that the overall output voltage waveform has the dominant harmonic
frequency around (1/T
S
) with only the low voltage stage is controlled using SVM at
switching frequency of (1/2T
S
), while the high and medium stages are operated at low
frequency, this implies considerable saving in switching losses.
The THD increases at the low range of M. But this should not affect the load current
quality as the dominant harmonics are of high frequency which can be adjusted by the
setting the sampling time.
167
6.3.3 The effect of high voltage domain adjustment
For two ranges of reference amplitude, around 45% and 65% some additional distortion
is experienced when the high state basic domain of 8V
S
is exclusively used. This has
been anticipated during the design stage in Chapter 3 and the cure for this distortion has
been proposed in Section 3.7. This distortion is due to the fact that around these two
values of M, a low reference voltage beyond the low voltage stage vector space may be
produced. High voltage stage domain modification has been proposed to prevent this
case.
The test of the inverter with modified high voltage stage domain show that the
additional distortion in the two indicated amplitude ranges has been eliminated.
Furthermore, the individual stage voltage measurements show that this modification
does not imply any effect on the high voltage stage switching frequency. Controlling the
inverter based on the modified high voltage stage domain, however, causes sixth
harmonic distortion in the output voltage at the high reference amplitude range,
therefore switching between the two domains according to the reference amplitude is
necessary
It has been shown that the modification of the program from the basic to the modified
domain can be done with minimal change when the control is performed using the g-h
axis based calculations.
For M close to 100%, the same kind of distortion experienced with basic domain but the
distortion cannot be canceled at this range. However, with large values of M, it is
expected from the nature of the AC drives voltage demand that the inverter will be
operated with the voltage approximation or with high reference frequency mode and this
distortion will not be effective.
168
6.3.4 Comparison with previous studies
A comparison between the proposed algorithm and two other recently reported
algorithms is shown in Table 6.2. The algorithms described in Chapter 2 are the HPWM
algorithm suggested by Rech and Pinheiro (2007) and the 1-DM method reported by
Leon et al. (2009b, 2009a) as both methods are proposed as alternatives for the basic
PWM and SVM techniques for multilevel inverters. Also both methods are suitable for
multistage inverters. Indeed the HPWM is exclusively applicable for multistage
inverters.
It can be seen from the comparison that the control method suggested in this project is
unique is combining the inverter design with maximized number of levels with the
effective high switching frequency capability. Although the high frequency switching
has been applied to an inverter with maximized number of levels by Leon et al, (2009a)
results presented by that study confirmed there is high voltage stage and simultaneous
high switching frequency. Thus this feature represents one of the most important
advantages of the proposed algorithm.
By comparing the dominant harmonics frequency to the switching frequency, it can be
noted that the proposed SVM strategy provides improvement compared to the two other
methods. Where the HPWM dominant harmonics frequency is around the switching
frequency of the PWM controlled lowest voltage stage. While the presented SVM
provides dominant harmonics around twice the average switching frequency of the
lowest voltage stage. When compared to the 1-DM, the suggested strategy surpasses by
the low switching frequency of the high and medium voltage stages.
As for the calculations complexity, the proposed method requires more computational
effort than the other two methods. The added computational burden is not a problem as
the strategy can be implemented using a fixed-point low cost DSP processor as shown.
169
Table 6.2 Comparison of the proposed algorithm with the HPWM and 1-DM
algorithms.
Algorithm

Compared
Character
Proposed Voltage
Vector Control
Method
HPWM
(Rech and Pinheiro,
2007)
(1-DM)
(Leon, et.al, 2009a)
Applicable inverter
topology
Multistage Multistage
Topology independent
method
Main advantage over
conventional control
methods
Preventing high
switching frequency of
higher voltage stages
with the maximum
number of levels of the
topology
Simple comparator-
based low-frequency
for the higher voltage
stages
Simpler modulation
method with
performance similar to
the common SVM
technique applicable to
various
topologies/levels
Maximum number of
levels by eliminating
state redundancy
design
Applicable, without
any undesirable
effects, particularly
high voltage stage high
frequency.
Not applicable
Applicable but causes
high voltage stage (and
simultaneous) high
switching frequency
High Voltage stage
frequency
Fundamental
(for any M)
Fundamental
(for any M)
Depends on M
Dominant harmonics
frequency
Around f
C
2 Around f
C
Around 1/T
S

Algorithm complexity
The difficulty is in the
initial vector
transformation, which
involve trigonometric
functions.
Simplest, the controller
is composed of a three
level comparators and
one three-level PWM
modulator.
The modulator is
simplified but a detailed
post processing is
needed to choose one
state among a number of
equivalent states
depends of the number
of levels
Post processing: after
initial modulation
Need to be considered
for the three-level low
voltage stage only.
Not required
Need to be considered
for all inverter
equivalent states
170
6.4 The Achievement of the Study Objectives
This project has seven objectives which have been listed in Section 1.7. This section
shows the fulfillment of these objectives as confirmed by the results.
6.4.1 Extended levels and optimized number of switching devices
An 18-level inverter has been designed and implemented. This number of levels
provides sufficient number of steps to develop the desired output voltage with THD less
than 5% and for wide range of M. Therefore, the voltage approximation control without
involving any high frequency PWM can be applied for 40%<M<100% to produce low
distorted output voltage.
The inverter is designed with a ratio of 18 levels-to-30 switches. This ratio is higher
than all of the reviewed three stages topologies except the asymmetrical CHB with
ratio-3 sourcing which has 27 levels-to-36 switches. The latter, however, requires three
isolated main stage sources with high reactive power. So it can be said that this
objective has been satisfied.
6.4.2 Applying hybrid topology
The hybridization has been applied to optimize the design in two aspects. First
designing the high voltage stage is constructed using two-level six-switch inverter while
the other stages have been built using CHB stages. This choice reduces the DC source
cost considerably, where the three high voltage sources have been replaced by one
source which is operating with less current ripple and therefore reduced losses.
The second aspect is applying different switching devices for different stages, as
indicated in Chapter 4, the low voltage stage has been built with the higher speed
MOSFETs while other stages used the lower ON state losses IGBTs.
171
6.4.3 State redundancy elimination
The state redundancy has been eliminated and the maximum number of symmetrical
levels for inverter topology has been obtained. As indicated in Chapter 3, this has been
made possible by the voltage ratio of the cascaded stages.
6.4.4 Switching losses minimization
In the switching state selection of the three stages, any flexibility in the state selection
has been exploited to minimize the switching losses. In addition, the cascaded controller
structure starts with high voltage stage calculations and ends with low voltage, which
implies giving the priority for the higher voltage stage in holding the switching state for
the subsequent sampling period. This prioritization reduces the switching losses in two
ways. First, due to the voltage level and the switching time of the high voltage stage
devices, the per-pulse switching energy of this stage is higher than the other two stages.
Second, due to the rotation of the reference voltage vector it is almost certain that any
high voltage stage switching should be accompanied by simultaneous switching of other
stages therefore reducing the switching actions of this stage implies total switching
reduction.
6.4.5 Computationally efficient control
By the staged structure of the controller, a great deal of computational effort has been
saved.
In the voltage approximation using basic d-q axis calculations, many options have been
applied to reduce the computational effort, for example, implying the sector of the
reference angle in the angle coding system and determining the low state zone using
single sum of integer product step. Additionally the polynomial-based calculations of
172
the low voltage stage gives the reference zone in one fixed-point sum-of-products term
with all product terms except one are zeros.
The computational efficiency of the voltage approximation control has been greatly
improved by applying the g-h based calculation concept and the required memory has
been considerably reduced. The high and medium stages calculations have been made
pure integer calculations, and the developed low voltage stage calculations is avoids the
axis transformation step that would be required if the polynomial low state zone
identification is used.
In the SVM control method, the high and medium stages control is done using the g-h
axis based calculations. This method provided simple integer calculations that made the
high voltage domain modification as simple as it could be. For the low voltage stage the
calculations have been greatly simplified by choosing and space vector modulation
calculation which besides being simple and fast, uses the same axes system used in high
and medium stages calculations. Additionally, the stage-by-stage structure of the control
algorithm implies an appropriate tradeoff between the modulation and the post
modulation calculations. Since the post modulation calculations involve only a three-
level stage, the application of optimized equivalent states and state sequencing
calculations as an easy task.
6.4.6 High quality control
The SVM control which provides dominant harmonics around twice the switching
frequency has been successfully implemented. To assure the high quality of the voltage
spectrum, the implemented state sequence centers two switching states in the middle of
the switching interval that has been started and ended with equivalent states. This
reduces the harmonics distortion according to the flux trajectory concept. Adjustment of
the high voltage stage domain has been implemented to assure minimum harmonic
173
distortion over the entire range of the reference amplitude variation. The increased
harmonic distortion with low reference amplitude is unavoidable due to the reduced
number of steps available to construct the output voltage. However, the effect of these
harmonics can be controlled by setting the sampling frequency.
6.4.7 Simultaneous and high voltage stage high frequency elimination.
The proposed inverter does not meet the modulation condition, and accordingly
subjected to high switching frequency of the high voltage stage and simultaneous
switching. Nevertheless, the proposed control method satisfies the objective of avoiding
high switching frequency of the high voltage stage or cascaded stages simultaneously as
shown by measurements. This became possible mainly by using the inverters two-
dimensional vector space rather than the individual phase reference voltage in the
switching signals calculations of the high and medium voltage stages. In comparison
with the studies reported in the literature, it has been noted that the previous studies
have either avoided the design with maximum number of voltage levels when the high
frequency control is needed. Few studies have attempted to apply high frequency
control of multistage inverters designed with maximum number of levels. It has been
shown that this controlled to high voltage stage high switching frequency (Leon et al.,
2009b). Therefore, up to the candidates knowledge to date, this study is unique in
permitting the inverter designed with maximum number of levels to be controlled in
high frequency strategy without subjecting the high voltage stage to high switching
frequency.
174
6.5 Summary
The experimental results demonstrated in Chapter 5 have been discussed. For the
voltage approximation control it has been shown that the voltage waveforms, switching
signals and the current waveforms meet the main design objectives and in line with the
anticipated performance. Applying g-h axis transformation considerably simplifies the
calculation of the controller without affecting the performance.
By comparing the voltage approximation with other studies that use the standard control
methods, it has been shown that the inverter in this mode provides low harmonic
distortion with reduced switching losses thanks to the extended number of levels.
With SVM control strategy, the various waveforms measurements show that the various
design objectives have been achieved, mainly the switching frequency of the various
stages and the order of the dominant harmonics.
In SVM control, the adjustment of the high voltage stage domain is important to
maintain the minimum harmonics distortion.
An assessment of the achieved results compared to the study objectives shows that these
objectives have been achieved to a large extent.
175

Chapter Seven
Conclusion
7.1 Introduction
Hybrid multistage MLI provides significant improvements for electric-drives
applications, and its added cost can be justified by the improved performance. Different
voltage steps of cascaded stages can produce a larger number of output voltage levels
with less number of components.
This study presented improved MLI design and control algorithms. The features of the
developed inverter system and the achievements of this project are presented in this
conclusion chapter.
7.2 Multistage Topology
In this project a multistage inverter has been designed and constructed. The main
characteristics of the inverter are:
1- Three-stage inverter to provide the sufficient number of levels.
2- The high voltage stage is constructed using a six-switch, two-level sub-inverter, in
order to reduce the DC supply cost, where the number of the high voltage stage
supplies, compared to the asymmetrical CHB topology, is reduced from three to
one, furthermore the high voltage stage supply operates at lower current ripple and
176
therefore unidirectional current capability is sufficient over a wider range of the load
power factor.
3- The DC supply of the three inverter stages have been selected to eliminate the state
redundancy and provide the maximum number of levels with uniform voltage steps.
The resultant three-stage inverter has 18 levels.
4- The medium and low voltage stages need six isolated bidirectional supplies with
highly reactive power demand, but with voltage ratio that forms only one third and
one ninth of the main stage supply voltage. The lower voltage levels have enabled
the implementation of these stages by using battery units.
In this thesis, two voltage control methods for controlling the multistage inverter have
been developed; the voltage approximation control and the voltage SVM control. Both
methods assume a sampled reference input and determine the switching signal for the
next sampling interval.
7.3 Inverter Operation by Vector Approximation
As for the voltage vector approximation control, the inverter is controlled in order to
produce the nearest inverter vector to the reference vector during the next sampling
intervals. It has been shown that there is a number of switching combinations that leads
to any inverter vector. The proposed voltage approximation control achieved the
objective of using the optional states selection to minimize the switching losses giving
the priority to the high voltage stage. This was possible by introducing the definitions of
the high and medium stages state domain and developing the controller based on
comparing the reference vector to the present state domain.
The vector approximation control has been implemented, the coding of the reference
values and the states have been carefully chosen to enable the implementation using a
177
low-cost fixed point processor. Furthermore a special polynomial-based technique has
been applied to control the low voltage stage using single sum of products term.
The developed voltage approximation control concept has been applied using a 60-
displaced axis system denoted by the g-h axis as alternative implementation method.
The calculation time and the program memory space have been considerably saved
using this transformation. This simplification is due to the simple and integer
relationship between the inverter vectors g-h coordinates and switching variables. This
relationship enables pure integer calculations for the high and medium stages.
When the inverter is used to supply variable speed AC motor, this mode is suitable for
high and medium speed operation. In low speed range the AC motors operate with low
voltage and frequency, and voltage approximation mode could cause a high distortion in
the current waveform due to the simultaneous reduction in the number of voltage steps
and load inductive reactance.
7.4 Inverter Operation by Space Vector Modulation Control
A voltage vector control has been developed. The control algorithm is designed to
maintain the low voltage stage reference voltage vector within the low voltage stage
vector space.
The low voltage stage voltage vector is realized using a typical space vector modulation
control for a three-level inverter. The resultant total voltage has the characteristics of the
space vector modulation controlled voltage when the dominant harmonics frequency is
around the sampling frequency which is twice the average switching frequency of the
low voltage stage.
The high voltage domain definition has been adjusted according to the reference vector
amplitude to ensure that the resultant low voltage stage reference is always within its
178
vector space. The measured waveforms have shown the role of this measure in voltage
distortion reduction.
The effective high frequency control of the inverter designed with state redundancy
elimination has been successfully achieved with reasonable level of calculations that has
been effectively implemented using a fixed point low cost processor.
When the inverter is used to supply variable speed AC motor, this mode is suitable for
low range of speed where the dominant harmonics frequency can be easily adjusted.
7.5 Recommendations and Suggestions for Future Work
Although the developed inverter and control methods meet the study objectives, several
issues require further investigation.
One is the possibility of eliminating the low voltage stage DC supplies and replacing
these supplies by capacitors. This is to be done by developing a control method that
ensures a zero average power of this stage over the entire range of reference amplitude.
As shown, the optional switching state selection flexibility has been entirely used to
minimize the switching actions, using this flexibility for low or low and medium
voltage stages to stabilize the DC side voltage provides important improvement by
further reducing the DC supply cost.
The fluctuations of the individual stages DC supplies lead to the disturbance of the
assumed voltage ratio. Adjusting the DC supply to maintain the ratio-3 relationship of
the three stages DC voltages may be considered as a future work.
Another suggestion is related to the implementation technique, where the zone
identification by single polynomial term has been abandoned after considering the g-h
transformation control. This method has the potential to be very computationally
efficient if a processor with zero-look-ahead multiplier is used. Further, the concept can
179
be extended to the high and medium stages control. It is believed that this technique is
worth further investigation.
As an alternative way to speed up the calculations in vector approximation control, the
use of artificial neural network could be considered, the entire control process could by
simplified to three consecutive sum of product term calculations if the network is
successfully trained to generate the switching signals from the present state and the
reference voltage inputs for the three individual stages.
Basically the voltage approximation method is based on what can be viewed as two-
dimensional hysteresis control. Implementing the proposed concept using a group of
hysteresis controllers is suggested as future study.
Regarding the implementation technique, the inverter has been implemented using
individual switching devices. Using smart modules to implement the inverter could
improve the inverter reliability, simplify the implementation, and reduce noise.
A simplified analysis has been presented in Section 6.2 for comparing the inverter
switching losses with those of the conventional six switch inverter. A future study may
consider more accurate determination of the inverter efficiency and compare it to other
available options, including other MLI.
The application of the proposed inverter as a part of a vector control AC drive is
recommended for future studies. The exploitation of the low distorted wave in
improving the drive characteristics is one study. The development of a DTC control
strategy that is directly linked to the MLI switching state is another possibility, as the
DTC concept provides a reference voltage vector, rather than current reference. Other
studies may consider furnishing data about of the overall drive performance and
characteristics and compare it to those of a drive supplied with a conventional inverter.
The proposed voltage approximation and SVM control methods could be extended to
inverters used in other applications such as the power system related applications, where
180
the use of transformer isolation for the cascaded stages eases eliminates the multiple DC
supplies requirement and encourages the application of the cascaded topology.
181
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Appendix 1

196
Appendix 2
List of publications from this wok
Journals and Transactions
1- Dual Vector Control Strategy for a Three-Stage Hybrid Cascaded Multilevel
Inverter
Journal of Power Electronics, vol. 10, no. 2, pp.155-164, 2010
2- Voltage vector control of a hybrid three-stage 18-level inverter by vector
decomposition
IET Power Electronics, vol.3, no.4, pp.601-611, July 2010
3- Voltage Control of Three-Stage Hybrid Multilevel Inverter Using Vector
Transformation
IEEE Transactions on Power Electronics, vol.25, no.10, pp.2599-2606, Oct. 2010
4- Novel Vector Control Method for Three-Stage Hybrid Cascaded Multilevel Inverter.
IEEE Transactions on Industrial Electronics, (in press), 2010, available online at
(http://ieeexplore.ieee.org)
Proceedings:
1- Direct Torque Control Permanent Magnet Synchronous Motor drive with
asymmetrical multilevel inverter supply,
7th Internatonal Conference on Power Electronics, 2007. ICPE '07. , vol., no., pp.1196-
1201, 22-26 Oct. 2007
2- Comparison of Basic Direct Torque Control Designs for Permanent Magnet
Synchronous Motor
7th International Conference on Power Electronics and Drive Systems, 2007. PEDS
'07., vol., no., pp.1344-1349, 27-30 Nov. 2007
3-Novel control strategy for three-stage 18-level hybrid multilevel inverter.
6th International Multi-Conference on , Systems, Signals and Devices, 2009. SSD '09.
vol., no., pp.1-6, 23-26 March 2009
4- Eighteen-level inverter control with minimum switching losses
13th European Conference on Power Electronics and Applications, 2009. EPE '09. pp.1-
10, 8-10 Sept. 2009
197
5- Voltage control of three-stage hybrid multilevel inverter using vector transformation,
5th IET International Conference on Power Electronics, Machines and Drives (PEMD
2010), , vol., no., pp.1-6, 19-21 April 2010.

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