HIGH SPEED LASER ABLATION OF MICROVIA HOLES IN NONWOVEN ARAMID REINFORCED PRINTED WIRING BOARDS TO REDUCE COST

David J. Powell, Senior Development Engineer DuPont Advanced Fiber Systems, Wilmington, DE Michael Weinhold Product Applications Manager DuPont Advanced Fiber Systems, Geneva, Switzerland
ABSTRACT Emerging chip-size IC packages, and bare flip-chips, require new substrate properties if high lead count chips are to be reliably interconnected on printed wiring boards and multichip modules at low cost. Blind via holes have been shown to significantly increase interconnect density without adding layers which contribute to high cost. Until recently, the use of blind vias has been limited to high-end applications since standard fabrication methods, either sequential lamination or controlled depth drilling, are too slow and expensive for most high volume commercial applications. To maintain a low layer count while inter-connecting higher I/O packages, commercial and consumer electronics requires a substrate technology which supports high speed, micro-via hole formation. This paper describes a process for fabricating high speed micro-vias in dimensionally stable non-woven aramid reinforced laminates using laser ablation technology. Laser equipment capable of producing over 100 blind micro-via holes per second will be discussed. The process steps of hole cleaning and plating will be reviewed, showing how existing PWB manufacturing technologies can be used. This process will be compared with other methods of generating small holes and blind vias in printed wiring boards. In addition, requirements for flip-chip and chip-size packages, including a coefficient of thermal expansion of <10 ppm/_C and thin laminate dimensional stability of <0.03%, will be explained.

INTRODUCTION To interconnect chips with finer pitch sizes and higher I/O counts, designers of printed wiring boards have gradually selected finer lines, smaller holes and pads, and additional layers to wire the required number of components into a given wiring area. Improving line resolution and reducing drilled hole size has yielded the best economy towards achieving higher interconnect density without escalating costs. The PWB fabrication industry has developed equipment and processes which produce 0.005 (125 m) lines/spaces with 0.012 (300 m) drilled holes in 4-10 layer PWBs at yields in excess of 90 per cent. Adding wiring layers contributes significantly to multilayer printed wiring board cost and is chosen as a last resort. LOWERING COSTS AND INCREASING WIRING DENSITY There is a continuing drive to lower PWB costs, while interconnecting chips with even higher I/Os (>400 leads), by both reducing layer count and the size of the interconnect holes. The latest ASICs, packaged in ceramic and plastic BGAs, require additional PWB layers to wire area array pad configurations using conventional S18-3-1

plated-through-hole technology1. Furthermore, Chip size packaging driven by small size, lower profile and weight, and higher speed2 has placed even greater demand on PWB routing density.

Figure 1. Comparison of blind micro-via hole interconnect scheme vs. through-via hole.

The most efficient method of reducing the volume of space consumed by the layer-to-layer interconnects is a blind via hole (Figure 1). Blind via holes, if small enough, can be placed in the component pad, saving considerable routing area around the component for high density wiring. To date, blind vias have been manufactured using techniques which produce either large holes or with fabrication techniques, such as

sequential lamination and controlled depth drilling, which are too costly for most commercial applications. SMALL HOLE GENERATION Several technologies are under development to meet the electronic industrys need for small blind via interconnects. Three techniques offer the greatest opportunity to deliver small holes at a low cost in large scale production. These are laser ablation, plasma etching, and photo-defined vias3. These technologies can also be combined with conventional drilling and traditional substrates to yield the most cost-effective solution, as demonstrated in PWBs manufactured by Schoeller Elektronik (Figure 2) and Mommers Print Service (Figure 3).

equipment is now commercially available in the price range of 250-375 thousand dollars, producing 10-150 holes per second. When, in the PWB fabrication process, this equipment is positioned after the conventional mechanical drilling operation for tooling holes and large connector holes, ultra small micro-vias can be produced at low cost without disrupting the process flow. Standard hole cleaning, metalization and finishing processes follow laser ablation, yielding a high density PWB with fewer interconnect layers. On the other hand, the photo-imageable dielectric materials require major investment in coating lines, Class 1000 clean rooms and changes in plating processes. The thin, non-reinforced dielectric between layers forces the fabricator to produce ultra fine lines (0.003 (75 m)) for matched impedance which impacts on product yields. Sequential build-up of layers using photo-imageable resists magnifies the yield loss on subsequent operations. This technology has also been found to introduce planarity problems for surface mount components. Plasma etching of micro-vias offers many of the advantages of laser ablation. However, since plasma has an isotropic etch behaviour, it is more difficult to form blind micro-vias without introducing undercut and potential plating problems. These issues have been overcome by specialty fabricators like Diconex, of Zurich, Switzerland. To adopt this process, PWB fabricators need to make major investments, notably in the plasma ablation equipment, but also in the handling and processing of flexible materials. Special plasma etch chambers have been developed to maximize plasma etch uniformity, but the cost exceeds half a million dollars for units which produce approximately six 18x24 inch (457 mm x 610 mm) panels every 30 minutes. The advantage of plasma etching is that millions of holes are potentially formed simultaneously when the process is properly controlled. The process is also compatible with high performance organic substrates like polyimide and LCP films, and non-woven aramids. THE ADVANTAGE OF LASERS Using etched copper foil as a mask for accurate laser hole formation, the large installed base of PWB fabricators is capable of offering significantly higher wiring density to PWB designers. The depth of the laser ablated hole is controlled by a copper stop-pad of 0.010"-0.018" (250450 m) diameter, opening up wiring lanes on other layers and around the miniature pads. Laser formed micro-via holes can be placed directly in BGA, area array, or FP-SMT pads, eliminating the wasted space consumed by through-hole vias and their associated fanout lines4. By decreasing the size of the via pads on layers 2 and 3 of the PWB, additional room becomes available for routing circuitry without adding expensive layers to the PWB (Figure 4). Studies have shown that, with blind

Figure 2. Laser ablated blind via holes and plasma ablated buried via holes in non-woven aramid. (Courtesy of Schoeller Elektronik)

Figure 3. Laser ablated blind via holes and mechanically drilled holes in non-woven aramid with a FR-4 core. (Courtesy of Mommers Print Service, Echt, Holland) While each small hole formation technology is promising, laser ablation is the easiest process to implement in conventional PWB fabrication processes while minimizing investment. Since lasers produce a collimated etch source, hole geometry can be controlled and the resulting hole quality is excellent. Laser drilling S18-3-2

micro-vias, 12-layer PWBs can be redesigned to have 8 layers, lowering the total cost of PWB manufacture.

Figure 4. FP-SMT and BGA area array with microvias in the pads. MATERIALS FOR LASER ABLATION FR-4 (epoxy resin with woven E-glass reinforcement) is the most widely used substrate material in multilayer PWBs. E-glass, however, is not the preferred reinforcement for laser ablation since it cannot be ablated as cleanly as organic materials5. Woven E-glass also lacks the dimensional stability required in the most costeffective thin dielectric constructions manufactured on large format panels. In order to connect multiple layers, for example layers 1-2 and layers 1-3, using blind vias and small capture pads, 0.002 - 0.004 (50-100 m) dielectric is required between layers. Non-woven aramid reinforcement materials with epoxy or polyimide resins offer the optimum combination of excellent dimensional stability and uniform laser ablation in single-ply thin core laminates, while being available in a wide range of prepreg and laminate thicknesses for multilayer printed wiring boards6.

Figure 6. DK vs. epoxy resin content for E-glass and non-woven aramid reinforcement. THE ADVANTAGES OF NONWOVEN ARAMID REINFORCEMENT In addition to uniform laser ablation and consistent dimensional stability, nonwoven aramid reinforcement offers other benefits which are demanded when high performance chips are used. With a dielectric constant of 4.0 (Figure 5), compared to 6.2 for E-glass, aramid reinforcement lowers the laminate Dk to 3.9 for epoxy 7 resin and 3.7 for polyimide resin. With aramid, the dielectric constant is also more consistent (Figure 6) across a wide range of resin contents, since the Dk of the resin and of the reinforcement are closely matched. Uniform Dk values between the prepreg and laminate dielectric openings make this combination attractive for controlled impedance applications. Aramid reinforcements have another unique property which makes them exceptionally well suited for high performance chip packages, such as TSOP, LCCC, SCA, BGA and direct chip attach. With a negative coefficient of thermal expansion (CTE), non-woven aramid reinforcement is capable of restraining epoxy and polyimide thermoset resins during thermal cycling8. The resulting combination is a low in-plane CTE of 7-9 ppm/_C at a 47-53 per cent resin content by weight, as shown in Table1 .

Figure 5. DK vs. frequency for the E-glass and non-woven aramid/epoxy.

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COMPARISON OF LAMINATE PROPERTIES

Material Property Non-woven Aramid/ Epoxy 45 -4.5 7-9 0.02% 2200 3.9 1.3 Uniform, consistent Woven E-glass/ Epoxy 45 3 16-18 0.05% 4200 4.6 1.7 Molten glass residue

Epoxy Resin CTE (ppm/ C) Reinforcement CTE (ppm/ C) Laminate CTE (ppm/ C) Dimensional Stability (%) Laminate Smoothness () Dielectric Constant (@ 1Mhz) Density (g/cc) Laser Ablation

Non-woven aramid reinforcement is available in several thicknesses to meet the impedance requirements for various applications. The thickness of each ply will depend on the resin content and on the amount of copper circuitry which needs to be filled with resin. The nonwoven 100 per cent aramid product discussed in this article is called Thermount, which is a DuPont registered trademark. The thicknesses of the aramid reinforcement, the prepreg and the laminate are shown in Table 2. Comparison of Material Thickness

Table 1. CTE comparison and laminate properties Since silicon and ceramic materials used in high performance IC packaging have a CTE of, respectively, ~3 ppm/_C and ~8 ppm/_C, non-woven aramid substrates have been shown to increase solder joint reliability and to extend service life in commercial and military electronics. Strain on solder joints, the principal cause of fatigue cracks after thermal cycling, is directly proportional to the CTE mismatch between the component and the PWB. For direct chip attach components, and other chip-scale IC packages, nonwoven aramid reinforced PWBs are being considered in order to eliminate the need for costly, unreworkable, underfill materials (Figure 7).

Table 2. Thickness of Thermount reinforcement, prepreg and laminate LASERS FOR PWB MANUFACTURE Four types of laser are widely used to ablate organic materials. CO2 lasers, offering high productivity and low cost over a large format area (18" x 24" [457 mm x 610 mm] or larger) have been mostly widely used in microvia applications to date. Recent developments have minimized the resin charring previously associated with CO2 lasers in small hole formation. Use of a conformal copper foil mask, with etched clearances which define the hole locations, has further reduced thermal damage to the organic resin by acting as a heat sink. Nd:YAG lasers have attracted attention recently due to their capability to cut copper. Various laser options for printed wiring board fabrication are described below. TEA-CO2 9000-11000 nanometer IR laser which is noted for its exceptional hole quality since it generates very little heat in the hole wall. These atmospheric lasers, such as Lumonics Impact laser, require multiple pulses to ablate non-woven aramid reinforced laminates. However, the ablated hole wall is typically very uniform and holes are consistent across the panel. CO2 1060 nanometer IR laser which is noted for its high ablation rates in organic materials. The latest equipment (e.g. Convergent Energy Gemini, and Diamond laser) uses sealed, solid state lasers with long life times and minimal resin charring. These lasers have sufficient power to drill 0.008 deep holes in non-woven aramid reinforced laminates using a single pulse. EXCIMER

DCL

Strain = DCL

( CTEpackage/board * T) 2H

Figure 7. Solder joint strain is proportional to CTE mismatch between the chip package and the printed wiring board. Furthermore, new technologies have been developed which utilize non-woven aramid-reinforced thin laminate as a flexible connector between rigid multilayer PWBs. By eliminating large connectors and cables, this technique, developed by Dynaco (Tempe, AZ), enables even higher density packaging in tight spaces, as found, for example, in portable computers, hard disks, and military electronics.

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Figure 8. Nd:YAG laser-ablated hole. (Photo courtesy of ESI) Figure 9. Nd:YAG laser ablated hole. (Photo courtesy of ESI) METHODS FOR DEFINING SMALL HOLES WITH LASERS10 POINT-TO-POINT. When a laser tool is operated in a point-to-point mode, it functions like a NC drill. The panel is moved according to specific X,Y axes, the laser fires one or more pulses and a hole of specific diameter is formed without the use of a mask. Unlike an NC drill, where drill bits must be changed to drill different hole diameters, the laser system uses different apertures that can be switched in fractions of a second to drill different hole diameters. The limitations of this technology include low productivity, due to the fact that the NC table must stop for each hole location; poor hole resolution, since the edge of the laser beam is not uniform; the possibility of residues from the laser process, which are difficult to clean without disturbing the dielectric surface; and the need for fully additive plating after hole formation. CONFORMAL MASK SCANNING. A conformal mask is a metal layer, attached to the dielectric, which is patterned using conventional lithographic techniques and wet etching. Once the metal layer has been patterned with openings, the dielectric film with its integral copper foil mask is scanned under the beam. Any residue from the laser processing step can be readily removed in an in-line cleaner. The advantages of using this technique are that the definition of smaller features can be obtained due to the intimate contact of the mask with the dielectric; it is an almost 100 per cent diffraction limited system; the edge quality of the features is better than with non-conformal mask methods; and there is no need for a highly accurate alignment system on the NC table. This approach is most appropriate when the hole density per unit area is very high. POINT-TO-POINT WITH A CONFORMAL MASK. Frequently, the most productive process for manufacturing blind micro-vias in PWBs combines both point-to-point and conformal mask techniques. After forming the conformal mask in copper foil, holes are ablated by moving the NC table at a constant rate and firing the laser when the beam position is aligned with the openings in the copper foil. The laser beam diameter is 0.008-0.016 (200-400 m) larger than the clearance in the copper foil to ensure complete ablation of the hole. By maintaining a constant velocity, laser ablation rates can exceed 20 holes per second with standard hole arrays and up to 300 holes per second in closely spaced hole arrays. The processing speed is a function of the hole S18-3-5

Available in 193, 248, and 308 nanometer versions, these UV lasers ablate very uniform holes in very thick laminates reinforced with non-woven aramid. The slow etch rate associated with excimer lasers make them impractical for cost-effective printed wiring board hole formation at this time. NdYAG This is a near-IR laser with an output centered at approximately 1064 nanometers. The fourth harmonic, or

Quad YAG, is the UV output for this laser at 266 nanometers and is capable of ablating uniform holes in organic and inorganic materials, including copper. Nd:YAG lasers, such as ESI Quad YAG, use a 0.001-0.002 (25-50 m) beam, so larger holes must be excised by trepanning around the perimeter of the desired feature9. Because YAG lasers will ablate copper, it is more difficult to control the formation of blind vias using a copper stop-pad, but it can be done. YAG lasers are compatible with non-woven aramid reinforced laminates and offer ultra small hole capability (0.002 (50 m) diameter) as well as multilayer throughhole drilling capability, since they are capable of cutting copper. The third harmonic of Nd:YAG lasers at 355 nanometers is also being evaluated for increased ablation speed (Figures 8 and 9).

pitch, the thickness of the substrate and the laser power. Some manufacturers are also developing galvanometerdirected lasers, where small X and Y axis motors direct the beam to the desired locations without indexing the table. Galvanometers and multiple head lasers offer productivity which dramatically exceeds the capability of the fastest mechanical drilling machines. DESIGN RULES FOR MICRO-VIA HOLES Via hole diameter, via hole depth, and stop-pad size are dependent on the manufacturing tolerances of the fabrication process, the panel size, and the number of layers which need to be interconnected. The following guidelines are effective for 16"x18" (406 mm x 457 mm) panels. For larger panels, slightly larger stop-pads may be required, depending on the tooling system (Table 3).

OPTIMISING REGISTRATION AND STOP-PAD GEOMETRY To minimize stop-pad size and optimize layer-to-layer registration, a layer n/layer n-1 innerlayer lay-up is recommended (i.e. layer 1/2, layer 3/4, layer 5/6 for a 6layer printed wiring board). Registration between the clearance hole in layer 1 and the stop-pad on layer 2 is typically accurate to within +/- 0.0015 (+/- 38 m) over an 18x24 (457 mm x 610 mm) area when laser plotted first generation silver halide phototools are used. The stop-pad diameter can be reduced to only 0.006-0.008" (150-200 m) over the via diameter using this method while maintaining sufficient annular ring for high reliability interconnects. The conformal copper foil mask is formed at essentially no additional cost, since layer 1 and the corresponding last layer (i.e. layer 6) of a multilayer are typically covered with photoresist and processed with a blank image during innerlayer fabrication. This technique also enables automatic optical inspection (AOI) of clearances in innerlayers, rather than the more expensive laminated multilayer panels. FABRICATION TECHNIQUES FOR LASER MICRO-VIA HOLES A. INNERLAYER IMAGE PROCESSING Clearance holes are imaged in layer 1 copper foil at the same time as the image is patterned on layer 2, providing optimum front-to-back registration. Developing 0.004" (100 m) clearances in 0.0013" (33 m) photoresist may require two passes through a developer, depending on the spray pressure. If two passes are required to resolve small clearances, the Mylar should be left on layer 2 during the first pass and removed just prior to the second pass. Flipping the inner layer upside down between the first and second passes will improve developing uniformity. B. LAMINATION OF MULTILAYERS Innerlayers and prepreg reinforced with non-woven aramid must be thoroughly dried prior to lamination. Vacuum lamination under 300-400 psi will provide complete encapsulation and removal of volatiles.12 After lamination, the oxide treatment should be chemically removed with sodium persulfate or an equivalent microetch prior to further processing. The oxide treatment, if not completely removed, will absorb, rather than reflect, light during laser ablation, potentially resulting in copper foil damage. C. LASER PROCESSING Laser power should be optimized to produce a hole which is slightly tapered from top to bottom, with no undercut of the clearance copper pad. A perfectly straight hole wall or negative hole wall should be avoided, since it will S18-3-6

Table 3. Design rules for non-woven aramid printed wiring boards Conventional copper electroplating limits the aspect ratio of blind vias to 1:1, since it is more difficult to throw copper into a cavity than into a through-hole, which permits solution to pass through. Even with the 1:1 aspect ratio limitation of conventional electroplating solutions, up to 4-layers can be interconnected using laser drilled blind vias. Since blind vias are positioned on both sides of the PWB, an extremely high wiring density can be achieved in 4-8 layer boards. Mechanically-drilled holes can be combined with laser vias to make connections to power and ground planes. Connections can also be made between internal layers in a multilayer stack11. For example, layer 2 and layer 3 can be connected by placing a 0.010 (250 m) clearance on layer 1, an 0.008 (200 m) opening in the layer 2 pad, forming a doughnut shape, and a stop-pad on layer 3. This option gives the designer the ability to connect multiple layers, while the fabricator can form these interconnects in a single laser ablation operation without multiple drilling and without costly sequential lamination operations (Figure 10).

Figure 10. Multiple layer interconnection scheme with doughnut pads.

be difficult to electroplate copper uniformly into the holes without forming plating folds. The connection area on the stop-pad should be at least 50 per cent of the diameter of the surface hole, and should have a minimum diameter of 0.003 (75 m) (Figure 11).

Vapor honing has also been used successfully to clean holes after laser ablation. This one step mechanical process removes surface residues and smoothes the laser

Figure 11. Preferred taper for a micro-via hole Mechanical drilling of larger holes may follow laser drilling using the same panel tooling slots or holes. Offsets should not be added to mechanically drilled holes, otherwise the outerlayer registration will be compromised. D. HOLE AND SURFACE CLEANING CO2 laser ablation leaves a fine residue of re-deposited resin on the copper stop-pad and the surface copper foil surrounding the clearance hole. This residue must be removed, along with any resin smear generated in the mechanical drilling operation, to ensure good electroless copper adhesion and reliable interconnects. Plasma is most effective in the removal of this redeposited residue. A plasma cycle which removes approximately 0.0001-0.0003 (3-8 m) of hole wall resin is recommended. This should be followed by a high

ablated hole wall. Deburring is not recommended for these small diameter vias. Hole Formation using Laser Technology Figure 12. SEM of laser-ablated hole after laser process. (Lumonics IMPACT) If a connection is being made to a oxide treated layer, the exposed stop-pads should to be stripped of oxide after hole cleaning. The oxide layer can be stripped using sodium persulfate or equivalent chemistry, depending on the type of oxide treatment. The oxide treatment on the stop-pad may be cleaned sufficiently in the pre-clean portion of the electroless line, so no additional cleaning steps may be required. E. ELECTROLESS COPPER PLATING Standard electroless copper with a minimum thickness of 80 micro-inches (20 m) should be plated in the blind micro-vias. Vibration systems which increase panel agitation assist in removing air bubbles in micro-vias which can prevent full coverage of the holes. To prevent etch-out of vias in subsequent plating processes, 0.0003 -0.0006 (8-15 m) of electrolytic copper strike will improve the reliability and plating distribution in 0.004 (100 m) blind via holes. Tooling holes should be covered prior to electrolytic plating to maintain the proper hole size for artwork tooling. Direct plate systems may offer advantages over traditional electroless copper in catalyzing micro-via holes prior to electroplating .

pressure spray water rinse to remove any ash remaining in the hole (Table 4). Table 4. Recommended plasma hole cleaning cycle (APS 4800) Permanganate desmear chemistry has also been demonstrated to be an effective method for residue removal after laser processing. Standard process chemistry used for conventional drilled hole cleaning, including a solvent swelling solution and potassium permanganate, will remove laser residues. DMF and NMP solvents are not recommended for solvent swelling solutions since they may attack the aramid reinforcement binder. Glass etch chemistry is not required after permanganate hole cleaning, but is not detrimental to the non-woven aramid reinforced hole wall. S18-3-7

electrolytic Cu and SnPb plating and reflow. (Lumonics IMPACT) F. OUTERLAYER IMAGING During panel scrubbing prior to photoresist lamination, top-side vias may fill up with pumice, aluminum oxide, or copper particulates, depending on the panel cleaning method. Flipping the panel over after the final rinse and passing it through the final rinse a second time will remove any residue. Standard photo-imaging and developing techniques should be utilized to prepare a pattern plate resist image. Full-build panel plate, followed by print-and-etch processes, may also be used. G. ELECTROLYTIC PLATING A minimum of 0.0007" (18 m) of copper plating should be deposited in the blind via holes using standard copper electroplating technology. Rack vibration systems and turbulent solution agitation will assist in removing air bubbles from blind micro-via holes which could prevent uniform plating. To improve the throwing power of the copper electroplating process, lower current density may be required for small micro-via holes. Either tin/lead, tin, or nickel/gold may be plated as an etch resist after copper plating. H. FINISHING Standard photoresist stripping and copper foil etching processes complete outerlayer image formation. If solder is reflowed after etching, the reflowed solder will typically fill the blind micro-via, depending on hole diameter and depth. SUMMARY OF MICRO-VIA HOLE FABRICATION PROCESS 1. Hole Formation using Laser Technology after Flash Electro Plating Figure 14. SEM of laser-ablated hole after electrolytic copper plating. (Lumonics IMPACT) Clean, photo-image, etch, strip resist, and oxide innerlayers with clearances in layer 2. Laminate multilayer after drying innerlayers and prepreg as recommended 3. Remove oxide from outerlayer copper surfaces 4. Laser ablate blind vias by scanning or point-to-point ablation through copper mask 5. Mechanically drill through-holes and tooling holes as required 6. Clean holes using plasma, permanganate, or vapor hole processes 7. Remove oxide treatment from stop-pads if present on layers 2 or 3, and inspect 8. Electroless copper plate 9. Cover tooling holes and flash copper electroplate (0.0003-0.0006 [8-15 m] recommended) 10. Clean, photo-image, copper and solder electroplate, strip resist, and etch copper S18-3-8

Hole Formation using Laser Technology after Plasma Cleaning Figure 13. SEM of laser-ablated hole after plasma hole cleaning. (Lumonics IMPACT)

Hole Formation Using Laser Technology After Permanaganat Desmear and Plating Figure 15. Cross-section of laser ablated holes after

11. Bake, reflow (or solder strip for HASL) soldermask, legend, rout, and test. THE RELIABILITY OF BLIND MICRO-VIA HOLES Blind micro-via holes of 0.003-0.008 (75-200 m) diameter and a depth of 0.003 (75 m), formed in nonwoven aramid reinforcement with epoxy resin, have been shown to survive over 2,000 thermal cycles from -55 _C <> +125_C. Further testing by an independent laboratory has shown that microvias 0.006 (150 m) wide and 0.006 (150 m) deep, and micro-vias 0.004 (100 m) wide and 0.002 (50 m) deep, pass MIL-P55110 thermal shock requirements of 100 cycles from 65 _C <> +125 _C. They also pass the M&IR requirements of this specification. A test report documenting thermal shock test results is available from DuPont Advanced Fiber Systems. Highly Accelerated Stress Testing HAST Hast Test Conditions - 50 volt DC bias applied to both sides of dielectric - 1M resistor in each circuit to limit amperage - 120 C 85%RH - 2 atmospheres pressure (10.8 psig) - 96 hours - Equivalent to 1000 hours @ 85C/85%RH HAST Results for 0.002 (50 m) lines/spaces - Line-to-line: > 1010 insulation resistance 10 - Layer-to-layer: >10 insulation resistance Table 5. Highly Accelerated Stress Testing (HAST) HAST testing has also demonstrated the reliability of a 0.002 (50 m) 1-ply Thermount E210 dielectric between layers after the equivalent of 1,000 hours at 85% RH and 85 _C with an applied bias of 50 volts DC. The laminate and prepreg used in these reliability studies passed the requirements of MIL-S-13949 /23B. The reliability of non-woven aramid reinforcement is further demonstrated by its use in demanding avionics and military applications and its qualification to MIL-P55110 by numerous printed wiring board fabricators. THE COST AND IMPACT ON MINIATURIZATION New technologies are often regarded as factors which increase the cost of electronic equipment. However, new technologies and materials always need to pay for themselves and should not drive up the cost of electronics. This part of the paper will show the cost impact of new Thermount reinforced laminate constructions used in multilayer manufacturing processes S18-3-9

as well as the value-in-use of these new types of PWB in different applications. The driving forces for the use of aramid reinforced laminates in advanced electronics are: improved Coefficient of Thermal Expansion (CTE) of <10 ppm/C improved dimensional stability reduced weight laser hole formation for cost-effective micro-via holes a smooth surface for easy photo-imaging of fine lines and spaces. These features have a different impact on cost, depending on the electronic application in which the material is used. In the following section, various applications are reviewed to determine the potential cost reductions available through the use of aramid-reinforced PWBs. AVIONIC AND AEROSPACE APPLICATIONS In a study made by BPA13, it is shown that weight has a major impact on the cost of launching a commercial satellite. In it, is stated that: One gram will cost approximately US$ 10,000 extra on fuel during the launch. Based on this information and the knowledge that Thermount aramid-reinforced laminate constructions are 25 per cent lighter than the same constructions in FR4, it is easy to calculate the cost savings that can be achieved when glass is replaced with aramid as a reinforcement material for PWBs used in avionics equipment. In addition, the improved coefficient of thermal expansion of aramid-reinforced PWBs often makes it possible to eliminate Copper Invar Copper. This leads to a substantial saving in the weight of the PWB, thus leading to lower overall satellite launch costs (Figure 16).

Cost Reduction in Avionic Application Figure 16. Fuel saving by weight reduction is directly

proportional Based on this example, such a substantial reduction in costs can be re-stated in terms of value-in use. If the actual cost reduction for a commercial airline application was 1 per cent of the calculated values, it would be worth considering the use of aramid-reinforced PWBs in avionic equipment due both to the initial savings and the savings obtainable during the operational life of the avionics equipment. MOBILE, COMMERCIAL AND CONSUMER APPLICATIONS It is relatively easy to calculate the potential cost reductions for the aramid-reinforced multilayer constructions in high end applications such as avionics and aerospace, since the in service cost savings are known and may have a greater impact on costs than the initial cost of making the printed wiring boards. However, in mobile, commercial and consumer applications, the cost of each individual component is critical to the purchase and use of these products. In this type of industry, any cost increase on the component side is more difficult to justify. This is because the consumer and end-user has come to expect that he will be able to obtain a higher performance mobile telephone or mobile computer at lower cost. Nevertheless, in this section we are going to show how costs can be reduced by using the

structure and because of component land pattern requirements. This means that the only possible solution for reducing costs is to reduce the number of layers. As described earlier in this paper, routing space can be drastically increased by using small holes formed by using laser ablation technology. This can be used to create small holes in surface mount land patterns used for BGA, fine pitch SMD or flip-chip applications. In addition, the improved dimensional stability of the aramid multilayer construction makes it possible to reduce the keep out area which designers have to respect to provide tolerance for conductor routing. Based on this experience, an 8 layer multilayer can be redesigned as a 6-layer construction or even as a 4-layer multilayer (see Figure 17). Indeed, a study made by BNR14 in Nov. 1995 indicated that present-day technologies will allow the re-design of multilayer circuits with a reduced number of layers. The BNR study indicated that US$ 19.08 can be saved if a 6-layer multilayer is manufactured instead of an 8-layer multilayer. If an 8-layer multilayer can be re-designed to have four layers, this would yield a cost reduction of US$ 31.08 for the 8 by 10 inch multilayer (Figure 18).

Figure 18. Total cost reduction by designing Multilayer with lower numbers of layers.

miniaturization potential of multilayer circuits based on aramid-reinforced laminates.

14 Figure 17. Cost reduction potentialindicated (BNR in Nov. 1995) by designing Multilayer with less layers

The basic cost of PWBs is impacted by the surface area, the layer count, the density of lines and spaces, and by the hole diameter and the number of holes. Some cost items are related to whether the surface is nickel/gold or and/or whether it has been Hot Air Solder Leveled. To achieve the largest cost reduction, it is necessary to reduce the surface area and/or the layer count. In many applications, the surface area cannot be altered, since the PWB is an integral part of the mechanical

Further examples can be worked out. However, this needs to be done with an actual case and depends on the manufacturing capabilities of the PWB manufacturer to work with the new materials and processes. If cost reduction is required, the use of laser technology to form small holes, combined with the improved dimensional stability of aramid-reinforced laminates, offers considerable potential for helping to achieving this. SUMMARY Laser ablated micro-vias in non-woven aramid reinforced substrates provide an efficient method of interconnecting high density chips with ultra small <0.010 (250 m) holes and <0.020 (500 m) stop-pads. This technology can be produced using standard fabrication processes with minimal equipment investment. By reducing layers in multilayer PWBs, lowering drilling costs, and

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increasing real estate for routing lines, laser ablated micro-vias offer significant cost savings. To fully extract the performance advantages of nonwoven aramid PWBs and obtain lower cost, new product designs will need to be developed. Cooperation between materials suppliers, advanced fabricators, and designers will lead to the most effective use of these new technologies in a broad number of applications.

3.

Blind Vias: Demands, Challenges and Solutions, Paul Waldner, Multiline Europa, D, IEC Conference, May 1995 Vias in Pads, Curtis Hart, Circuits Assembly Magazine, February 1995, p. 42 CO2 Lasers Take the Low-Power Route, Peter Gwynne, Photonics Spectra Magazine, December 1994, p.104 Laminate Technology Update for Multichip Modules, Jim Trent, Motorola SPS, Electronic Packaging and Production, July 1995, p. 39 Fabricating PWBs and MCM-Ls with a New Nonwoven Aramid Reinforcement, D.J. Powell, DuPont Fibers, Surface Mount International Technical Conference, September 1993 Non-woven Aramid - A Cost-effective Surface Mount Laminate Reinforcement, M.P. Zussman and D.J. Powell, DuPont Fibers, Journal of Surface Mount Technology, October 1992. High Density Packaging: Micro-vias with the UV Laser, Alan Cable and Mark Owen, SMT Magazine, July 1995, p. 30 Small Via Generation, J.M. Morrison, T.G. Tessier, B. Gu, Advanced Packaging Magazine, November/ December 1994, p.26 Laser Via Technologies for High Density MCM-L Fabrication, Joan Tourne, Mommers Print Service B.V., ISHM Conference, April 1995 Preliminary Process Guide for DuPont Thermount Non-woven Aramid Reinforcement, DuPont Advanced Fibre Systems, H-46299, December 1993. EIPC Marketing Meeting in Zrich, Switzerland,1992. Trends and Developments in the Electronic Industry presented by Roger L. Tyler, Senior Consultant, BPA The Cost Impact on PWB Design using Aramid Technology Options, by M. Cotton, presented during the First European Aramid Forum, at BNR Europe Limited, London Road, Harlow, Essex CM17 9NA, England, on November 2nd and 3rd, 1995.

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6. BIOGRAPHIES David J. Powell is a Senior Development Engineer with the DuPont Company, Wilmington, DE. Since obtaining a B.S. degree in Chemistry from Bates College, he has accumulated fifteen years of manufacturing, engineering, and development experience in the printed wiring board industry. He is presently working on the development of new non-woven aramid reinforcements for laminates and prepregs. Mr. Powell is a member of the North East Circuits Association, ISHM, and the IPC. Michael Weinhold was born in the Federal Republic of Germany, where he obtained qualifications in Business Economics and Engineering. Mr. Weinhold has worked in the printed circuit industry since 1964. He is a member of the Board of Directors of the European Institute of Printed Circuits (EIPC). He represents Switzerland at the IEC TC 52 and TC 91 committees, writing standards for the PCB fabrication and assembly industry. He is a founder of the ICDA (the International Circuit Designers Association). Since joining DuPont in 1970, Mr. Weinhold has held various technical and product marketing assignments with the RISTON Products Division. He is currently Product Application Manager, where his work relates to the latest developments in new Aramid laminate reinforcements, PWB image transfer technologies, as well as in SMD fine pitch, BGA and Flip Chip component soldering technologies. BIBLIOGRAPHY 1. 2. C4 Packaging for CMOS ASICs, Matt Nowak and John Nelson, Assembly Magazine, August 1995, p. 9 Chip-Scale Packaging and Assembly, J. S. Hwang, SMT Magazine, July 1995, p. 17 7.

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