Instructor-in-Charge (Section -1)

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Outline
Handout Introduction to Microelectronics M Moore`s Law ` L Power dissipation issues

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Handout

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Scope and Objective of the Course The objective of this course is to provide to Theobjectiveofthiscourseistoprovideto thestudentanintroduction tothe fundamentals and practical considerations andpracticalconsiderations pertainingtothedesignofintegratedcircuits. The scope encompasses both analog and Thescopeencompassesbothanalog and digitalintegratedcircuits.Theimportanceof CADtoolsinICsystemdesignprocessisalso CAD tools in IC system design process is also acknowledgedandstressedupon.
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BOOKS
PrimereferenceBooks
(R1))Kang.S.MandLeblebiciY.,CMOSDigitalIntegrated Circuits:AnalysisandDesign,McGrawHillInternational Editions3rd Edition2003.

TextBook :
(T1)JanM.Rabaey;AnanthaChandrakasan;BorivojeNikolic,
DigitalIntegratedCircuits ADesignPerspective,(Second Edition)PrenticeHallElectronicsandVLSISeries.(2003) Edition) Prentice Hall Electronics and VLSI Series (2003) (T2)BehzadRazavi,DesignofAnalogCMOSintegrated circuits,McGrawHillInternationalEdition.2001.
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BOOKS
Other Reference Books : OtherReferenceBooks:
NeilH.E.Weste,KamranEshraghian,"PrinciplesofCMOSVLSI Design,AddisonWesleyPublishingCompany. PucknellD.A.,EshraghianK.,"BasicVLSIdesign,systemsand circuits",Thirdedition,PrenticeHallofIndiaPvt.Ltd. F b i i E D "I FabriciusE.D.,"IntroductiontoVLSIdesign",McGrawHill d i VLSI d i " M G Hill internationaleditions. Gregorian R., Temes G.C.,"Analog Mos integrated circuits for GregorianR.,TemesG.C., AnalogMosintegratedcircuitsfor signalprocessing",Wileyintersciencepublication.

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BOOKS
Other Reference Books : OtherReferenceBooks:
SzeS.M.,"VLSITechnology",Secondedition,McGrawHillInternationalEdition. RandallAGeiger,PhillipsE.allen,NoelRStrader,"VLSIDesigntechniquesfor analoganddigitalcircuits, McGraw Hill International Edition' 1990 analog and digital circuits "McGrawHillInternationalEdition 1990. BhaskharJayram,"AVHDLPRIMER",PrenticeHall. IEEEJournalsofsolidstatecircuits,VLSIsystem. Martin.Ken, DigitalIntegratedCircuitDesign Oxford University Press Inc Martin Ken Digital Integrated Circuit Design,OxfordUniversityPress,Inc. Johns.DavidA.andMartinK,AnalogIntegratedCircuitDesign,JohnWily&Sons. Inc.2002. LabManuals Lab Manuals Referencesfordesignassignments Michael.L.Bushnell,andVishwani.D.Agrawal,EssentialsOfElectronicTesting ForDigital,MemoryAndMixedSignalVLSICircuits.KluwerAcademicPublishers, g , y g , ThirdEdition,2004
7

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Scope and Objective of the Course Forpracticalexposure,PSPICEandMAGIC For practical exposure PSPICE and MAGIC layouttool basedlaboratoryisincluded.

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Prerequisites
Thestudentsarerequiredtoreviewthe The students are required to review the followingtopics Basiccircuittheoryanddesign, BJTandMOStheoryandfundamentalsoflogic d OS h df d l fl i design.

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Text Book
Eshraghian Kamran & Others Essentials of Eshraghian,Kamran&Others,Essentialsof VLSICircuitsandSystems,PHI2005.

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Reference books
R: Jan M. RabaeyDigitalIntegratedCircuits R:JanM.Rabaey Digital Integrated Circuits PrenticeHallIndia,2000

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Course Plan
No of Lec. Topic To be Covered Learning Objectives Ref. to Text Book

2 2 3

Common Topics 1. 1 Introduction to VLSI Design Methodogies 2. Scaling 3. CMOS Technology, Design Rules, MOS Capacitances

Introduction to the semiconductor industry Technology Generation transition and its effects on performance Introduction to layouts and industry design flow for analog and digital integrated circuits

Chapter I ((T1), Chapter-I ((T1) R1) Chapter-3,3, (T1), R1), (RJ) Chapter 2,1 (T1),RJ)

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Course Plan
No of Lec. 5 5 4 5 Topic To be Covered Learning Objectives Ref. to Text Book

Digital Design 1. 1 MOS i inverter- St ti and switching t Static d it hi characteristics, Combinational MOS logic circuits static logic 2. Synchronous system and Sequential circuits design 3. Memory Circuits Design 4. Design verification & test g

Basic building block for most digital sub-systems and Speed of digital s stems systems Study and design of various CMOS logic gate families Synchronous design, timing metrics, Design of flipflops Design of SRAM, DRAM, decoders, sense amplifiers p Verification of functionality, manufacturing defects

Chapter 5 ,6 (R1) , (T1) Chapter7, (R1),(T1) Chapter 8,9 (R1) ,(T1) Chapter 10 (R1) ,(T1) Reference bookRm & internet resources

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Course Plan
No of Lec. Topic To be Covered Learning Objectives Ref. to Text Book

6 8 4

Analog Design 1. Advanced Current Sources & sinks; Current Reference circuit, C tR f i it Operational amplifiers Architectures, feed back 2. Noise

Building temperature independent voltage and current references, Basic building block for most t f B i b ildi bl k f t analog subsystems Quantification of various types of noise in analog circuits

Chapter 6, (RJ), (T2) Chapter (RJ), Ch t 6 (RJ) (T2) Chapter 7 (RJ), (T2) Chapter 7 (T2)

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Course Plan
No of Lec. 2 2 3 Topic To be Covered Common Topics 1. Introduction to VLSI Design Methodogies 2. Scaling 3. CMOS Technology, Design Rules, MOS Capacitances Analog Design 1. Advanced Current Sources & sinks; Current Reference circuit, Operational amplifiers Architectures, feed back 2. Noise Digital Design 1. MOS inverter- Static and switching characteristics, Combinational MOS logic circuits static logic 2. Synchronous system and Sequential circuits design 3. Memory Circuits Design 4. Design verification & test Learning Objectives Ref. to Text Book Introduction to the semiconductor industry Technology Generation transition and its effects on performance Introduction to layouts and industry design flow for analog and digital integrated circuits i it Building temperature independent voltage and current references, Basic building block for most analog subsystems Quantification of various types of noise in analog circuits Basic building block for most digital subsystems and Speed of digital systems Study and design of various CMOS logic gate families Synchronous design, timing metrics, Design of flip-flops Design of SRAM, DRAM, decoders, sense amplifiers Verification of functionality, manufacturing defects Chapter-I ((T1), R1) Chapter-3,3, (T1), R1), (RJ) Chapter 2,1 (T1),RJ) (T1) RJ) Chapter 6, (RJ), (T2) Chapter 6 (RJ), (T2) Chapter 7 (RJ), (T2) Chapter 7 (T2) Chapter 5 ,6 (R1) , (T1) Chapter7, (R1),(T1) Chapter 8,9 (R1) ,(T1) Chapter 10 (R1) ,(T1) Reference bookRm & internet resources

6 8 4 5 5 4 5

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Evaluation Scheme
Component Test I Test II Surprise Test/ Assignments Comp. Exam 3 Hours Duration 60 Mts. 60 Mts Marks 50 50 20 Date & Time 25/9 & 8.00 -- 9.00 AM
6/11 & 8.00 -- 9.00 AM

Venue

Remarks

Spread across semester

80

14/12 AN

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Makeup policy
Makeup for any component will be given only Make upforanycomponentwillbegivenonly ingenuine cases.Inallcasespriorintimation mustbegiventoIC must be given to IC

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Notices
All notices related to the course will be put on Allnoticesrelatedtothecoursewillbeputon theEEE/ECE NoticeboardandEDUCAN only

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Chamber Consultation Hour

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Digital Integrated Circuits

Introduction:Issuesindigitaldesign g g TheCMOSinverter Layout Combinationallogicstructures Sequentiallogicgates Designmethodologies Design methodologies Interconnect:R,LandC Timing g Arithmeticbuildingblocks Memoriesandarraystructures

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Introduction
Wh i d i i di it l Whyisdesigningdigital ICsdifferenttodaythan itwasbefore? it b f ? Willitchangeinfuture?

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The First Computer p

The Babbage Difference Engine (1832) 25,000 parts cost: 17,470

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ENIAC - The first electronic computer (1946)

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The Transistor Revolution

PNP BIPOLAR TRANSISTOR

First transistor Bell Labs, 1948

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The First Integrated Circuits g

Bipolar logic 1960s

ECL 3-input Gate Motorola 1966

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Intel 4004 Micro-Processor

1971 1000 transistors 1 MHz operation

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Intel Pentium (IV) microprocessor

Intel 2005 125,000,000 transistors 3.8Ghz operation 90nm Technology

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Intel Core 2 Microprocessor

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IC Classification
Circuitsize(transistorcount) Circuittechnology(BJT,BiCMOS,NMOS,CMOS) Designstyle standardcell t d d ll gatearray custom

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IC Classification Sizeclassification(historical)
<100 1003000 300030,000 3000 30 000 30,000500,000 >500,000 SSI MSI LSI VLSI ULSI 1963 1970 1975 1980 1990

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Transistor Counts
K 1,000,000 100,000 10,000 , 1,000 100 10
8086
Source: Intel

1 Billion Transistors

i486 i386 80286

Pentium III Pentium II Pentium Pro Pentium

1 1975 1980 1985 1990 1995 2000 2005 2010

Projected
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Courtesy, Intel

Moore s Moores Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubles p every 18 to 24 months. He made a prediction that gy semiconductor technology will double its effectiveness every 18 months

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F R LOG2 OF THE NUMBER OF CO OMPONENTS PER INTEGRATE FUNCTION ED

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975

Electronics, April 19, 1965.

Moore s Moores Law

Moores law in Microprocessors

1000 Tra ansistors (MT) 100 10 1 0.1 01 0.01 8080 8008 4004 386 286 486

2X growth in 1.96 years!

P6 Pentium proc

8086 8085 Transistors on Lead Microprocessors double every 2 years 0.001 1970

1980

1990 Year

2000

2010

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Courtesy, Intel

Moores Law, Intel Processors

Source: Intel web page (www.intel.com)

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Frequency q y
10000 Frequenc (Mhz) cy 1000 100 486 10 1 0.1 1970 8085 8086 286 386 Doubles every 2 years P6 Pentium proc

8080 8008 4004 1980 1990 Year 2000 2010

Lead Microprocessors frequency doubles every 2 years

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Courtesy, Intel

Power Dissipation p
100 P6 Pentium proc 10 8086 286 1 8085 8080 486 386 Power (Watts)

8008 4004

0.1 1971 1974 1978 Year 1985 1992 2000

Lead Microprocessors power continues to increase

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Courtesy, Intel

Power will be a major problem

100000 10000 Power (Watts) r 1000 100 18KW 5KW 1.5KW 1 5KW 500W Pentium proc

286 486 8086 386 10 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year

Power delivery and dissipation will be prohibitive

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Courtesy, Intel

PowerDensity
10000 Pow Densi (W/cm2) wer ity 1000

Rocket Nozzle Nuclear Reactor

100

8086 Hot Plate 10 4004 P6 8008 8085 Pentium proc 386 286 486 8080 1 1970 1980 1990 Year 2000 2010

Courtesy, Intel

State-of-the Art: Lead Microprocessors

EE 534 Summer 2004 University of South Alabama

EE 534 Summer 2004 University of South Alabama

EE 534 Summer 2004 University of South Alabama

EE 534 Summer 2004 University of South Alabama

EE 534 Summer 2004 University of South Alabama

EE 534 Summer 2004 University of South Alabama

EE 534 Summer 2004 University of South Alabama

EE 534 Summer 2004 University of South Alabama

Why Scaling?
Technology shrinks by ~0.7 per generation With every generation can i t ti integrate 2 more f t 2x functions on ti a chip; chip cost does not increase significantly Cost of a function decreases by 2x But
How to design chips with more and more functions? Design engineering population does not double every two years

Hence, Hence a need for more efficient design methods

Exploit different levels of abstraction

EE 534 Summer 2004 University of South Alabama

Design Abstraction Levels

Behavior description (Verilog, HDL, etc.) Silicon compilation

+

SYSTEM

Physical description (layout, circuit, etc.)

MODULE

Simulation for system specification

GATE

CIRCUIT

DEVICE G S n+ D n+

EE 534 Summer 2004 University of South Alabama

Challenges in Digital Design g g g

Microscopic Problems Microscopic Problems

Ultra-high speed design Interconnect Noise, Crosstalk R li bilit Manufacturability Reliability, M f t bilit Power Dissipation Clock distribution. Everything Looks a Little Different

Macroscopic Issues p
Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc.

?
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and Theres a Lot of Them!

Design Abstraction Levels

SYSTEM

MODULE + GATE

CIRCUIT

DEVICE G S n+ D n+

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Designflow

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VLSIDesignStages
LogicDesign/Simulation
Partitionarchitectureintocycles/latches / Verifyagainstarchitecturespecification

CircuitDesign/Simulation
Transistorsizing i ii Performanceverification

StaticTimingAnalysis
V if Verifymarginrequirements i i

PhysicalDesign
Drawmasksforlayout,followingdesignrules Pl Placementandrouting t d ti Parasiticextraction

VLSICADTools VLSI CAD Tools

Synthesis
Architectural,Logic,Physical

StaticAnalysis
Designrulechecking(DRC) g g( ) Circuitextraction Designverification Testgeneration g

DynamicAnalysis
Logicsimulation Switchlevel simulation Switch levelsimulation Circuitsimulation(SPICE)

LogicDesign/Simulation

VLSIDesignStages

Partitionarchitectureintocycles/latches Verifyagainstarchitecturespecification

CircuitDesign/Simulation
Transistorsizing Performanceverification

StaticTimingAnalysis
Verifymarginrequirements

PhysicalDesign
Drawmasksforlayout,followingdesignrules Placementandrouting Parasiticextraction

WhatisVerification(Simulation)? What is Verification(Simulation)?

Impl

Yes! Verifier V rifi r

Here is a counterexample

Spec
Anytime, brake implies slowdown

No!

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Whyverification? Why verification?

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VerificationProblems Verification Problems

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Verification(Simulation)inVerilog Verification(Simulation) in Verilog

Everyoneknowsdebuggingistwice

ashardaswritingaprograminthefirst p place
BrianKernigham Brian Kernigham

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VerificationEnvironment Verification Environment

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VerificationinVerilog

DUT

DUT: Design Under Test g

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Verificationof1BitFullAdder

DUT: Design Under Test or DUV: Design Under Verification

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Synthesis
Logic Synthesis is the automated process of converting a functional model of a system into a gate level circuit. gate-level circuit

Constraints

Technology Library

DESIGN(RTL code)

Synthesis Engine

Synthesis Report
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Technology Net list

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WHYSYNTHESISISREQUIRED
Benefits of synthesis :

Highleveldesignentry Increaseddesignerproductivity Reductionoflayoutdesignexpertise y g p requirement

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WHYSYNTHESISISREQUIRED
Benefits of synthesis :

Improvedquality I d lit Technologyindependence Facilitatesdesignreuseandsharing

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WHYSYNTHESISISREQUIRED
Benefits of synthesis :

Improvedquality I d lit Technologyindependence Facilitatesdesignreuseandsharing

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ModernDesignMethodology g gy

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VLSI Fact of Life

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Reference
CMOS Digital Integrated Circuits CMOSDigitalIntegratedCircuits AnalysisandDesignbyKangandLeblebici

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