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Three Phase Three-Level PWM Switched Voltage Source Inverter With Zero Neutral Point Potential
Won-Sik Oh, Student Member, IEEE, Sang-Kyoo Han, Seong-Wook Choi, Student Member, IEEE, and Gun-Woo Moon, Member, IEEE

AbstractA new three phase three-level pulsewidth modulation (PWM) switched voltage source inverter with zero neutral point potential is proposed. It consists of three single-phase inverter modules and each module is composed of a switched voltage source and inverter switches. The major advantage is that the peak value of the phase output voltage is twice as high as that of the conventional neutral-point-clamped PWM inverter. Thus, the proposed inverter is suitable for applications with low voltage sources such as batteries, fuel cells, or solar cells. Furthermore, three-level waveforms of the proposed inverter can be achieved without the switch voltage unbalance problem. Since the average neutral point potential of the proposed inverter is zero, a common ground between the input stage and the output stage is possible. Therefore, it can be applied to a transformerless power conditioning system. The proposed inverter is veried by a PSpice simulation and experimental results based on a laboratory prototype. Index TermsNeutral-point-clamped (NPC), power conditioning system (PCS), pulsewidth modulation (PWM), switched voltage source (SVS).

I. INTRODUCTION

N RECENT years, industry has begun to demand higher power equipment. Multilevel inverters have been attracting increasing attention for power conversion in high-power applications due to their lower harmonics, higher efciency, and lower voltage stress compared to two-level inverters. Numerous topologies for multilevel inverters have been introduced and widely studied [1][5]. The most important topologies of these topologies, as shown in Fig. 1, are the diode-clamped [neutral-point-clamped (NPC)] inverter [6], the capacitor-clamped (ying capacitor) inverter [7], and the cascaded H-bridge inverter with separated dc sources. In the diode-clamped inverter [6] as shown in Fig. 1(a), the dc-bus voltage is split into three levels by two series-connected bulk capacitors, and two diodes clamp the switch voltage to half of the level of the dc-bus has three states: 2, 0, and voltage. The output voltage 2. It is noted that although the output voltage is alhas a direct current (dc) component. ternating current (ac), and is the voltage Therefore, the difference between
Manuscript received March 9, 2005; revised September 9, 2005. This paper was presented at PESC04, Aachen, Germany, June 2025, 2004. This work was supported by the University IT Research Center Project. Recommended by Associate Editor J. H. R. Enslin. W.-S. Oh, S.-W. Choi, and G.-W. Moon are with the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Korea (e-mail: owons77@angel. kaist.ac.kr; elecdol@angel.kaist.ac.kr; gwmoon@ee.kaist.ac.kr). S.-K. Han is with the School of Electrical Engineering, Kookmin University, Seoul 136-702, Korea (e-mail: djhan@kookmin.ac.kr). Digital Object Identier 10.1109/TPEL.2006.880300

, which is 2. Two series-connected switches of across the diode-clamped inverter can achieve the multilevel output waveforms and reduce the voltage stress to half of the input voltage. However, the diode-clamped inverter has the unbalance of the blocking voltage between the inner and the outer devices due to the difference of the switching characteristics. This problem results in the larger voltage stress in the inner devices [7], [8] Furthermore, the diode-clamped inverter has undesirable features such as a ripple in the neutral-point voltage due to the current owing out of or into the neutral point of the dc link and steady-state unbalance in the neutral-point voltage due to a variety of factors including component imperfections, transients and other non-idealities [9][11]. Meynard et al. proposed a multilevel structure where the device off state voltage clamping was achieved by using clamping capacitors rather than clamping diodes as shown Fig. 1(b) [7]. Although this topology solves the problem of static and dynamic sharing of the voltage across the switches, it still has the voltage unbalance problem in the neutral-point voltage and dc offset voltage of the output. To solve neutral-point balancing problem, various strategies have been presented [12][14]. Although balancing techniques can be used to reduce the voltage unbalance in the neutral-point there are still limitations on the maximum amount of reduction [11]. In case of the dc offset voltage of the output, can be split into a positive 2 if the input voltage and a negative 2 part with the midpoint connected to the neutral, the dc offset problem of the output disappears. These problems appear to be inherent to the topology. The cascaded H-bridge inverter shown in Fig. 1(c) is an alternative approach to achieve multilevel waveforms based on the series connection of full-bridge inverters with a multiple isolated dc bus [15]. Although the modular structure solves the voltage unbalance problem, this approach requires many isolated dc sources and a link voltage controller. To solve all these drawbacks of conventional multilevel inverters, a new three-level pulsewidth modulation (PWM) switched voltage source (SVS) inverter is proposed. Fig. 2 shows the circuit conguration of the proposed three-level PWM SVS inverter. It consists of three single-phase inverter modules. Each module is composed of a main inverter stage and a switched voltage source stage which includes two switches, one ying capacitor, one diode and a small snubber inductor as shown in Fig. 3. It provides a three-level output across and , i.e., , 0, or . Therefore, the peak value of , and the peak value of the line to line the phase voltage is voltage is 2 . Since the phase voltage of the SVS inverter is twice as high as that of the conventional NPC inverter, it is

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Fig. 1. Major topologies of multilevel inverter: (a) diode-clamped inverter, (b) capacitor-clamped inverter, and (c) cascaded H-bridge inverter.

Fig. 2. Circuit diagram of the proposed SVS inverter.

well suited for inverters with a low input voltage such as a fuel cell, battery, and solar cell. In addition, the SVS inverter does not have the voltage unbalance problem which is often the case with the conventional three-level inverters with a divided input source. Furthermore, since the dc offset of the output phase voltage is zero, the neutral point of the output load stage can be connected to the ground, and the SVS inverter is safe without

Fig. 3. Operational principles of switched voltage source: (a) Node A: V (b) node A: 0 V.

and

an electrical isolation. Therefore, it can easily be applied to a transformerless power conditioning system.

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Fig. 4. Operational modes of three-level inverter: (a) v 0 V, (c) v V , and (d) v 0 V.

=0

=V

, (b) v

=
Fig. 5. Gate signals of one of three modules.

II. OPERATIONAL PRINCIPLES A. Circuit Operation The circuit conguration of the three-level PWM SVS inverter consists of three single-phase inverter modules as shown in Fig. 2. Each module can be independently operated with a single input source. The basic operational modes of the SVS inverter are shown in Figs. 3 and 4. Since the ying capacitor is charged to input voltage when the switch turns can be assumed to be a constant voltage on, voltage across , and snubber inductor can be ignored. As can be source seen in Fig. 3, the voltage of node can be changed to input and 0 V by switch and , respectively. The voltage by switch difference between node and is 0 and and , respectively, as shown in Fig. 4. Therefore, the SVS inverter has four different cases and three states of the output , 0, and which are twice those terminal voltage does not of the conventional NPC inverter. Furthermore, have a dc component. is and is Case 1) [Fig. 4(a)]: The output voltage , when switches and turn on. charged to The snubber inductor limits the inrush current of when the voltage of is different from . is 0 V when Case 2) [Fig. 4(b)]: The output voltage and turn on. switches and turn on, the Case 3) [Fig. 4(c)]: When switches turns off. In addition, the output voltage diode is clamped to and the ying capacitor is discharged. is 0 and diode Case 4) [Fig. 4(d)]: The output voltage is off, when switches and turn on. The same analysis can also be applied to the other modules. B. PWM Signal Generation To generate the three-level PWM waveform, the sine-triangular PWM method [16], [17] is used. The sine-carrier PWM is generated by comparing the three reference control signals with two triangular carrier waves. Three reference sinusoids are 120 apart to produce a balanced three-phase output, and the corresponding output signals for a three-level PWM can be expressed as for for for

(1)

. where For the rst module, the reference signal, two triangular carrier waves, and corresponding switch gate signals are shown in turns Fig. 5. When the reference signal is positive, switch turns off as shown in Fig. 4(a) and (b). In this on and switch turns on when the instantaneous value of the mode, switch , and reference signal is larger than the triangular carrier turns on when the instantaneous value of the referswitch . When the reference ence signal is less than the carrier turns on and switch turns off signal is negative, switch turns on as shown in Fig. 4(c) and (d). In this mode, switch when the instantaneous value of the reference signal is less than , and switch turns on when the instantaneous carrier . value of the reference signal is larger than carrier

III. ANALYSIS OF THE PROPOSED INVERTER In the preceding section, the voltage across capacitor of the switched voltage source (SVS) stage shown in Fig. 2 was as. However, the voltage sumed to be a constant voltage source is slightly different from the input across the capacitor , . The difference between the voltage across voltage source and the input voltage source may cause an the capacitor and diode when the switch inrush current on the switch turns on. To solve this problem, a small snubber inductor is inserted between the diode and capacitor . However, this small snubber inductor does not affect the operation of the proposed SVS inverter. The effect of the small snubber inductor is considered in this section.

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Fig. 6. Operation of the SVS inverter: (a) powering mode and (b) freewheeling mode. Fig. 7. Buck converter: (a) powering mode and (b) freewheeling mode.

Fig. 6 shows the circuit operation when , and Fig. 7 shows the buck circuit. The SVS stage shown in Fig. 2 is operated as a buck converter as seen in Figs. 6 and 7. Therefore, to analyze the operation of the SVS stage according to the value of the inductor, the simple buck converter can be considered. is small, the buck converter operIf the snubber inductor ates in discontinuous conduction mode (DCM). When the buck converter is operated in DCM, its voltage conversion ratio is expressed as (2)

where ; switching period; duty ratio; lter inductance; load resistance. can Based on this equation, the voltage conversion ratio be plotted as shown in Fig. 8. This gure shows that the less inclose to the ductance can make the voltage conversion ratio unity for a wide range of the duty ratio. In the case of the laborais less than 0.8, and the tory prototype, the modulation index is greater than 0.2 as shown in Fig. 9. duty ratio of the switch is about 0.0005, and the voltage converAlso, the parameter at 0.2 is 0.976. This means that the differsion ratio and the input ence between the voltage across the capacitor is 2.4%. Therefore, can be assumed to voltage source . In addition, the design be a voltage source charged with can be derived from (2) and expressed as equation of

Fig. 8. Voltage conversion ratio in the DCM buck converter.

where switching period; duty ratio; load resistance; modulation index. If the rated output voltage, the rated output current, and the allowed error of the output voltage are known, the proper value and modulation index can be determined of inductance from (4). IV. APPLICATIONS CONSIDERATION The SVS inverter has three important advantages compared to the NPC inverter. First, the output phase voltage is twice as high as that of the NPC inverter. This means that the SVS can generate twice the output power. Second, the dc offset voltage of the output is zero. This can make the power system more reliable and safer. This is very important especially for high power applications. Finally, the SVS inverter has no voltage unbalance problem. It can make the control algorithm simple to drive motor. These advantages for some applications are considered in the following section.

(3) (4)

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Fig. 9. Gate signal of switch

M.

A. Motor Drive System Conventional two-level PWM inverters and multilevel PWM inverters generate common-mode voltage or neutral shift effect within the motor windings. This common mode voltage may build up the motor shaft voltage through electrostatic couplings between the rotor and the stator windings and between the rotor and the frame [18]. Moreover, since the conventional inverters have dc offset voltage between ground and motor as shown in Fig. 10(a), the common mode neutral point voltage becomes higher and the motor line-to-ground voltage may be much higher than its rated line-to-neutral (phase) voltage. Therefore, the transformerless design of the drive with the conventional PWM inverter may cause the much larger common-mode leakage current to ow into the ground [18] and cause a high voltage stress on motor windings, which may deteriorate the motor insulation life [19], [20]. Although the isolation transformer can solve these problems, it increases the cost and reduces the efciency of the drive, which is undesirable, especially for high-power systems. In the case of the proposed SVS inverter, the neutral point of the motor stator windings can be grounded as shown in Fig. 10(b), and the motor line-to-ground voltage is identical to its phase voltage. Therefore, neutral shift effect disappears, and as long as the motor phase voltage is kept within its rated value during operation, the motor insulation will not be deteriorated. For example, a 400-V input voltage source can generate 200 V of the peak value of the phase voltage in the NPC inverter and a 200-V input voltage source can generate 200 V of the peak phase voltage in the proposed SVS inverter as shown in Table I. In this case, the phase voltages are the same. However, the maximum line-to-ground voltages of the NPC inverter are twice as high as those of the SVS inverter due to the dc offset voltage of the output. Since the motor stator is grounded, the line-to-ground voltage is the voltage stress of the motor insulator as shown in Fig. 11. Therefore, the voltage stress of the motor insulator in the NPC inverter is twice as high as that of the SVS inverter. In the case of the same input voltage source, the output phase voltage of the SVS inverter has twice as high as that of the NPC inverter as shown in Table II. In this case, the output voltage of

Fig. 10. Motor drive system: (a) NPC inverter and (b) SVS inverter.

TABLE I COMPARISON NPC INVERTER AND SVS INVERTER WITH SAME OUTPUT POWER

the SVS inverter is twice as high as that of the NPC inverter. However, the voltage stress of the motor insulator is the same. Therefore, since the output current of the SVS inverter is half of that of the NPC inverter with the same output power, the proposed SVS inverter has less conduction loss and higher efciency than the NPC inverter. Thus, since the proposed SVS inverter has desirable features such as high reliability, high efciency, and high safety, it is expected that the proposed SVS inverter is well suited for use in the motor drive systems. B. Power Conditioning System Recently, the importance of distributed energy generation and renewable energy sources (e.g., solar-cell or fuel-cell applications having batteries or supercapacitors) has been increased due to the exhaustion of fossil energy. The importance of the power conditioning system (PCS), which efciently transforms power from dc to ac, has also been increased. In general, renewable energy sources have low voltage sources. Therefore, to boost the voltage up to the grid levels, an additional power conversion system which consists of a dc/dc converter and transformer is required with the inverter. However, since a PCS is generally an individually owned single-phase system in the power range of up to 10 kW, a PCS requires low cost, high efciency, and reliability such as transformerless inverter. If the conventional inverter topologies which show undesirable

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Fig. 12. PCS: (a) single phase two-line type and (b) single phase three-line type.

Fig. 11. PMSM: (a) structures of PMSM and (b) structures of stator.

TABLE II COMPARISON NPC INVERTER AND SVS INVERTER WITH SAME INPUT VOLTAGE SOURCE

dc offset output voltage are applied to transformerless PCS, the electrical isolation between the inverter and the grid should be considered for safety. However, since the dc offset voltage of the SVS inverter output is zero, the proposed SVS inverter can be safely applied to a transformerless PCS. Two different types of PCS example circuits are shown in Fig. 12(a) and (b), respectively. Moreover, since the output voltage is twice as high as that of the NPC inverter, the proposed SVS inverter is suitable for applications with low input voltage sources such as battery cells, fuel cells, or solar cells. Thus, the SVS inverter is well suited for the transformerless PCS as it has many desirable features such as safety, high reliability, high efciency, and low cost. V. EXPERIMENTAL RESULTS The operational principles of the SVS inverter shown in Fig. 2 have been investigated by Pspice simulation and experimental results. For the three-level inverter drive, the sine-triangular wave modulation scheme was used to obtain a three-level PWM pattern. The laboratory prototype was fed with 200 VDC and employ a switching frequency of 9 kHz from a triangular carrier wave. This prototype uses a LC lter with a resistive

Fig. 13. Simulation results of the SVS inverter.

load of 50 . Figs. 13 and 14 show the simulated and experimental results of the phase voltages, line to line voltages, and load currents of the three-level voltage source inverter, respectively. As can be seen in Figs. 13 and 14, the peak value is 200 V and the peak value of the of the phase voltages is 400 V. These are twice as high as line to line voltage 2 those of the conventional NPC inverter. Therefore, the larger amplitude of the output voltage can be obtained compared with the conventional NPC inverter and it is well suited for an inverter with a low input voltage source. Moreover, since the phase and line voltage show three and ve levels, respectively,

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Fig. 14. Experimental results of the SVS inverter.

the multilevel waveform can be implemented by employing the interconnected modules without isolated dc sources or the voltage unbalance problem. Furthermore, the proposed multilevel SVS inverter can considerably reduce the voltage harmonics and output lter size. In addition, since the average value of the phase voltages to the ground during one period is zero, the neutral point can be connected to the ground and it can be applied to a transformerless grid connected photovoltaic (PV) and fuel cell power conditioning system. VI. CONCLUSION A new three phase three-level SVS inverter with zero neutral point potential is proposed. Its phase voltage and line to line voltage are twice as high as those of the conventional neutral-point-clamped PWM inverter and a three-level waveform can be achieved without the switch voltage unbalance problem. Therefore, it is well suited for an inverter with low input voltage such as a fuel cell, battery, or solar cell input. Furthermore, its average neutral point potential is zero. Therefore, the proposed SVS inverter can be widely applied to motor drive systems and transformerless grid connected power conditioning systems. REFERENCES
[1] J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multilevel inverters: a survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724738, Aug. 2002. [2] J.-S. Lai and F. Z. Peng, Multilevel converters-a new breed of power converters, IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509517, May/ Jun. 1996.

[3] F. Z. Peng, A generalized multilevel inverter topology with self voltage balancing, IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 611618, Mar./Apr. 2001. [4] B.-R. Lin, Analysis and implementation of a three-level PWM rectier/inverter, IEEE Trans. Aerosp. Electron. Syst., vol. 36, no. 3, pp. 948956, Jul. 2000. [5] C. Hochgraf, R. Lasseter, D. Divan, and T. A. Lipo, Comparison of multilevel inverters for static VAr compensation, in Proc. IEEE Conf. Ind. Appl. Soc., 1994, vol. 2, pp. 921928. [6] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523, Sep./Oct. 1981. [7] T. A. Meynard and H. Foch, Multi-level conversion: high voltage choppers and voltage-source inverters, in Proc. Power Electron. Spec. Conf., 1992, vol. 1, pp. 397403. [8] Z.-Y. Zhao, C.-J. Zhan, Y. Han, T. Xie, and L.-B. Zhao, Analysis on voltage unbalance between the inner and outer devices in three level IGBT converters, in Proc. Power Electron. Drive Syst. Int. Conf., 1999, vol. 1, pp. 218224. [9] S. Ogasawara and H. Akagi, Analysis of variation of neutral point potential in neutral-point-clamped voltage source PWM inverters, in Proc. Ind. Appl. Soc. Annu. Meeting, 1993, vol. 2, pp. 965970. [10] S. Alepuz, J. Salaet, A. Gilabert, J. Bordonau, and J. Peracaula, Analysis of neutral-point voltage balancing problem in three-level neutral-point-clamped inverters with SVPWM modulation, in Proc. IECON02, 2002, vol. 2, pp. 920925. [11] I. M. Salagae and H. du T. Mouton, Natural balancing of neutralpoint-clamped converters under POD pulsewidth modulation, in Proc. Power Electron. Spec. Conf., 2003, vol. 1, pp. 4752. [12] H. L. Liu and G. H. Cho, Three-level space vector PWM in low index modulation region avoiding narrow pulse problem, IEEE Trans. Power Electron., vol. 9, no. 5, pp. 481486, Sep. 1994. [13] Y. H. Lee, B. S. Suh, and D. S. Hyun, A novel PWM scheme for a three-level voltage source inverter with GTO thyristors, IEEE Trans. Ind. Appl., vol. 32, no. 2, pp. 260268, Mar./Apr. 1996. [14] G. H. Jung, G. C. Cho, S. W. Hong, and G. H. Cho, DSP based control of high power static VAR compensator using novel vector product phase locked loop, in Proc. IEEE Annu. Power Electron. Spec. Conf., 1996, vol. 1, pp. 238243. [15] J. S. Lai and F. Z. Peng, Multilevel convertersa new breed of power converters, IEEE Trans. Ind. Appl., vol. 30, no. 3, pp. 509559, May/ Jun. 1996. [16] K. R. M. N. Ratnayake, Y. Murai, and T. Watanabe, Novel PWM scheme to control neutral point voltage variation in three-level voltage source inverter, in Proc. IEEE Ind. Appl. Conf., 1999, vol. 3, pp. 19501955. [17] A. Rufer, An aid in the teaching of multilevel inverters for high power applications, in Proc. Power Electron. Spec. Conf., 1995, pp. 347352. [18] Z. Haoran, A. Von Jouanne, D. Shaoan, A. K. Wallace, and W. Fei, Multilevel inverter modulation schemes to eliminate common-mode voltages, IEEE Trans. Ind. Appl., vol. 36, no. 6, pp. 16451653, Nov./ Dec. 2000. [19] A. H. Bonnett, A comparison between insulation systems available for PWM-inverter-fed motors, IEEE Trans. Ind. Appl., vol. 33, no. 5, pp. 13311341, Sep./Oct. 1997. [20] W. Bin and F. A. DeWinter, Voltage stress on induction motors in medium-voltage (2300-6900-V) PWM GTO CSI drives, IEEE Trans. Power Electron., vol. 12, no. 2, pp. 213220, Mar. 1997.

Won-Sik Oh (S04) received the B.S. degree from Kyungpook National University, Daegu, Korea, in 2001 and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2003, where he is currently pursuing the Ph.D. degree in electrical engineering. His research interests are in area of power electronics and digital display driver system, including analysis, modeling, design and control of power converters, soft switching power converters, resonant inverters, distributed power system, photovoltaic power conditioning system (PVPCS), driving circuit for digital display, and backlight inverter for LCD TV. Mr. Oh is a member of the Korean Institute of Power Electronics (KIPE).

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Sang-Kyoo Han received the M.S. and Ph.D. degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2001 and 2005, respectively. For the next six months, he was a Post-Doctoral Fellow in KAIST where he developed digital display power circuits and preformed several research activities. Since September 2005, he has been with the Kookmin University, Seoul, Korea, as a Professor of electrical engineering and has worked for the Samsung Power Electronics Center (SPEC) as a Research Fellow. His research interests are in the areas of power electronics and digital display driver system, including analysis, modeling, design, and control of power converter, soft switching power converters, step-up power converters for electric drive system, multilevel converters and inverters, power factor correction, plasma display panel (PDP) driver, digital display driving circuit, and back light inverters for LCD TV. Dr. Han is a member of the Korean Institute of Power Electronics (KIPE).

Gun-Woo Moon (S92M00) was born in Korea in 1966. He received the B.S. degree from Han-Yang University, Seoul, Korea, in 1990 and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1992 and 1996, respectively. He is currently an Associate Professor in the Department of Electrical Engineering and Computer Science, KAIST. His research interests include modeling, design and control of power converters, soft-switching power converters, resonant inverters, distributed power systems, power-factor correction, electric drive systems, driver circuits of plasma display panels, and exible ac transmission systems. Dr. Moon is a member of the Korean Institute of Power Electronics (KIPE), Korean Institute of Electrical Engineers (KIEE), Korea Institute of Telematics and Electronics (KITE), and Korea Institute of Illumination Electronics and Industrial Equipment (KIIEIE).

Seong-Wook Choi (S05) received the B.S. degree in electrical engineering from Dankook University, Seoul, Korea, in 2002 and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2004, where he is currently pursuing the Ph.D. degree in electrical engineering. His research interests are in the areas of power electronics and digital display driver system, including analysis, modeling, design, and control of power converter, soft switching power converters, step-up power converters for electric drive system, multilevel converters and inverters, power factor correction, digital display driver systems, and EEFL back light inverters for LCD TV. Mr. Choi is a member of the Korean Institute of Power Electronics (KIPE).