EECT 6326 Analog IC Design

Introduction

Instructor: Prof. Hoi Lee

Department of Electrical Engineering The University of Texas at Dallas hoilee@utdallas.edu

Course Information

Prerequisite
EE 4340 / EECT 5340 (Senior Level: Analog IC Design)

Objective
To introduce the principles of analog integrated circuit design and to provide the circuit level analog IC design knowledge required in the analog IC design industry and research.

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Textbook and Reference Books

Textbook
Design of Analog CMOS Integrated Circuits, by Behzad Razavi, McGraw-Hill, 2001. ISBN: 0072380322.

Recommended
Analysis and Design of Analog Integrated Circuits, Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, John Wiley & Sons, Inc., 5th edition, 2009. ISBN: 0470245996. CMOS Analog Circuit Design, Phillip E. Allen and Douglas R. Holberg, Oxford University Press, 2nd edition, 2002. ISBN: 0-19-511644-5 Operational Amplifiers Theory and Design, Johan H. Huijsing, Kluwer. ISBN: 0792372840 Analog Design for CMOS VLSI Systems, Franco Maloberti, Kluwer Academic Publishers, 2001. ISBN: 0792375505.

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Coverage of Topics
Topics Gray 1 3 3 4 4 6 3 7 9 Handout Handout Handout Handout Razavi 2, 16 3 4 5 11 9 Handout 6 10 Handout Handout Handout Handout
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Review (1/14 1/30)

MOSFET & BJT Device Models Single-Stage Amplifier Differential Amplifiers Current Sources and Sinks References

Major Topics (2/4 5/1)

Opamp Design Input Offset Voltage Frequency Response Stability and Compensation Transient Responses Two-Stage Amplifier Design Hspice Tutorial (2/10 TA)

HW & Proj.
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Cadence Tutorial (2/10 TA)

Course Grading Policy

Course Grading Policy
Quiz Project Midterm Exam Final Exam 20% 20% 20% 40%. Any student scored 80/100 in the final examination will automatically get A.

Exams

Homework and Project

All the exams are closed book with an one-sided letter-sized notes allowed for Midterm Exam and a two-sided paper for the Final Exam. All grades become final one week after they are returned in class. Midterm: 3/6/13 class time Final: 5/10/13 2:00p.m. 4:45p.m. Homework will be assigned on a bi-weekly basis and be collected at the beginning of the class on the due date except the first homework. No late homework. The homework solution will be posted on the professors webpage. Some of the homework and the project require the use of cadence/analog artist design tools; tutorial will be given at the beginning of the semester. In order to use Cadence tools at UTD, a UTD UNIX account is required. It is OK to use Cadence tools at your workplace if preferred.

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Academic Honesty

It is the responsibility of the instructor to

encourage an environment where you can learn and your accomplishments will be rewarded fairly. Any behavior that compromises the Universitys rules of academic honesty will be reported to the Dean of Students. The penalty of academic dishonesty ranges from receiving F grade in this class to being expelled from the university.
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Attendance and Email Announcement

You are responsible for all course materials,

announcements, and notes, etc. made during our regular class meeting time. If you send email to ask for questions, please start with EECT 6326 **** in the title of the email.
Example 1: EECT 6326 Project submission Example 2: EECT 6326 Unable to attend class due to sickness Example 3: EECT 6326 Scope of midterm exam

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Professor Contact Information

Contact Information
Office: ECSN 4.918 Phone: (972) 883-4841 Email: hoilee@utdallas.edu Webpage: www.utdallas.edu/~hoilee

Office Hours
2:00pm 3:00pm on Mondays or by appointment This is the time I set aside just to help you - the students in EECT 6326 class.

TA and TA office hours - TBD.

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Class Information

All course materials including syllabus, notes,

etc will be distributed through UTD elearning
elearning.utdallas.edu (using netid and password to login)

No homework in the first week TA information will be updated in the second

week

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Analog & Mixed-Signal Integrated Systems

Power Input/Output Signals Modulated Signal Wireless Channel High-speed Data Wireline Communication Circuits DSP Power Management Wireless Communication Circuits Data Converter

Electrical/optical Data Links

Natural Signal
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Sensor Interface Circuits

Data Converter An IC System

H. Lee pg. 10

Related Analog Courses at UTD

Undergraduate Level
EE 3311 EE 4340

Graduate Level
EECT 5340 Analog IC Design and Analysis (Same as EE 4340) EECT 6326 Analog IC Design (Core) EECT 6378 Power Management Circuits (Elective) EECT 7326 Advanced Analog IC Design (Elective) EECT 7327 A/D & D/A Converters (Elective) EERF 6330 RFIC Design (Elective) EECT 6379 Energy Harvesting (offer in Spring 13) EECT 7v88 High Speed Data Communication Circuits (offer in Spring 13)

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DIGITAL CIRCUITS ARE ON OR OFF ANALOG DEALS WITH THE GRAY

Global use of products such as cell phones, digital

cameras, digital music players and satellite radios continues to grow. And more content, such as music, video and data, are being digitized to run on such devices. In order for digital devices to operate, they need chips that can take signals from the real world -such as sound, power and temperature -- and compress them into a format that can be understood by a computer as zeros and ones. The demand for many types of analog chips in the $32 billion-a-year analog market continues to grow. So does demand for these specialized designers. With digital engineers outnumbering analog ones by an estimated 200-to-1, one headhunter has even said recruiting analog engineers is like using a pig to sniff out truffles in the forest.
H. Lee pg. 12

Dennis Monticelli, Fellow at National in Santa Clara, quoted by MercuryNews http://www.siliconvalley.com/mld/siliconvalley/13493561.htm

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Analog Education

Analog chip design is highly collaborative -- passed

down from generation to generation, like artisans learning from master tradesmen. Analog engineers describe their apprenticeship much like the residency that doctors go through at a hospital. Because there are few automated tools in the field, they learn how to do chip layouts from being mentored and hearing the stories, tricks and mistakes of others. Many companies, such as Texas Instruments, the leader in the field, and others like National Semiconductors, Analog Devices, Maxim and Linear, sponsor programs at universities, and then recruit heavily from that pack of engineers.

MercuryNews, http://www.siliconvalley.com/mld/siliconvalley/13493561.htm H. Lee pg. 13

EE6326 Introduction

Introduction (1)

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Introduction (2)

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Introduction (3)

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Analog Design Flow

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Analog Design (1)

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Analog Design (2)

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Analog Design (3)

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Analog Design (4)

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Analog Design (5)

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Analog Design (6)

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Understanding Technology

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Analog Today

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Future of Analog

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Notation, Terminology and Symbology (1)

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Notation, Terminology and Symbology (2)

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Notation, Terminology and Symbology (3)

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Notation, Terminology and Symbology (4)

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Applications of Analog IC

Example of Analog IC Applications

Power management ICs for portable applications Low-dropout regulators:
Convert a time varying battery voltage to a regulated constant DC voltage for noise sensitive RF transceiver Involve amplifier design, voltage reference design, negative feedback concept, current mirrors and sinks, frequency responses and compensation, transient responses

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Why Power Management in Portable Devices? (1)

Battery-Operated Portable Devices Energy Sources Li-Ion Batteries

Long Battery Life, Small Size, Light Weight, & More Functions

NiMH /NiCd Batteries

But, Limited Battery Capacity

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Why Power Management in Portable Devices? (2)

Provide a regulated power source
Low Dropout Regulator (LDO) Switched-Inductor DC-DC Regulator (SMPC) Switched-Capacitor Power Converter (SCPC)

Energy Source

Power Management Circuits ( 1)

Analog Part
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Digital Part

RF Part

Interface Part
H. Lee pg. 37

Low Dropout Regulator for Portable Applications (1)

Vin

Error Amp Dynamically-Biased Shunt Feedback Buffer

Pass Device Vout Rf1 CL RL

Vbg

Rf2

0.35m standard CMOS

Low dropout regulator design

Key Achievements:
Developed dynamically-biased shunt feedback in the LDO to minimize output transient overshoots and undershoots under massive load step changes. A 20mV undershoot under load step changes of 200mA/100ns.
IEEE CICC 2006, IEEE JSSC Aug. 2007
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Low Dropout Regulator for Portable Applications (2)

Total Vout = 54mV

Vdo (V) JSSC 98 JSSC 00 JSSC 03 TCAS-I 04 JSSC 07 0.3 N. A. 0.2 N. A. N. A.

IL,max (mA) 50 200 100 160 200

Iq (mA) 0.023 0.03 0.038 0.025 0.02

Current (%) 99.5 N. A. N. A. N. A. 99.8

Vout (mV) 19 220 130 200 54

Tr (s) 1.8 1.1 2 2.75 0.27

CL (F) 4.7 1 10 2.2 1

ESR No Yes Yes No No

Tech. (m) 2.0 1.0 0.6 0.5 0.35 H. Lee

FOM (ns) 8.2 0.165 4.9 0.43 0.027 pg. 39

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