Register Transfer Languages Objectives At the end of the discussion, the student must be able to: differentiate a micro-operation

on from a macro instruction know the different implementations of data transfers To use the register transfer language to specify the behavior of any sequential digital system. Topics of Discussion Micro-operations and Register Transfer Language Using RTL to Specify digital Systems Specifications of Digital Components Specification and Implementation of Simple System More Complex Digital Systems and RTL Micro-operation and Register Transfer Language Format of micro-operation transfer of 1 bit data in a digital system Implementation of data transfer : X Y, Y Z Compact Notation of Data Transfer Conditions: Micro operations : X Y

Implementation of data transfer : X Y, Z Y

Implementations of data transfers : X 0 : X 1

a. Using multiplexer to select data input Group of bits can be referred to as ranges in RTL Examples: : X(3-1) Y (2-0) : X3 Y2 : X(3-0) X(2-0),X3 Micro operations that perform arithmetic, logical and shift operations on data.

b. Using as the data input

c. Using the CLR signal 4-bit Data Transfer : X Y

Operations Add Subtract Increment Decrement AND OR XOR NOT

Example X X+ Y X X - Y, or X X+Y'+1 XX+1 XX-1 X X Y or X XY XXY XX1 X /X or X X'

4 Basic Types of Shift micro-operations Linear Shift Circular Shift Arithmetic Shift Decimal shift Shift micro-operations with its corresponding notations Operations Linear Shift Left Linear Shift Right Circular Shift Left Circular Shift Right Arithmetic Shift Left Arithmetic Shift Right Decimal Shift Left Decimal Shift Right Notations shl(x) shr(x) cil(x) cir(x) ashl(x) ashr(x) dshl(x) dshr(x)

Using RTL to Specify Digital Systems Specifications of Digital Components

Data paths of the system to implement the RTL code using direct connections

Complete design of the system to implement the RTL code using direct connection

Modifications of conditions so they are mutually exclusive; CLRLD : QD LD: QD CLR: Q0 LDCLR: Q0 JK Flip-flop without a CLR input; RTL as follows; JK : QO JK : Q 1 JK : QQ Consider a system whose RTL code is given as follows: assume that j,o,h,n are mutually exclusive J : MA o : AY h : RM n : YR, MR

Complete design of the system to implement the RTL code using a bus and tri-state buffers.

 Complete design of the system to implement the RTL code using a bus and multiplexer

Modulo 6 Counter State table for the modulo 6 counter Present State U S0 S0 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S7 0 1 0 1 0 1 0 1 0 1 0 1 X X Next State S0 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S0 S0 S0 C 1 0 0 0 0 0 0 0 0 0 0 1 1 1 V2V1V0 000 001 001 010 010 011 011 100 100 101 101 000 000 000

Sample Problems Write the RTL code for the following transitions. All registers are 1-bit wide. Show the hardware to implement the RTL statements in one combined system. Control signals ensure that no more than one is active at any time. a. A: X X + Y b. B: X X + Y + 1 c. C: X X xor Y More Complex Digital Systems and RTL State diagram of modulo 6 counter

RTL for modulo-6 counter (S0 + S1 + S2 + S3 + S4 + S5)U: V V, C C (S0 + S1 + S2 + S3 + S4)U: V V+1, C 0 S5U: V0, C1 S6+S7: V0, C1 Final RTL: (S0 + S1 + S2 + S3 + S4)U: V V+1, C 0 S5U+ S6+S7 : V0, C1 Two Implementation of the RTL code for the modulo-6 a) using a counter b) using a register Hardware Implementation using Counter

Hardware Implementation of Mod-6 counter