VHDL PROGRAMMING

PROGRAM: Half Adder

library IEEE; use IEEE.std_logic_1164.all; Entity ha is port(a,b: in std_logic; s,ca: out std_logic); end ha; Architecture ha1 of ha is begin s<=a xor b; ca<=a and b; end ha1;

Expt. No. : 05(a) Date HALF ADDER AIM: To design the Half Adder using VHDL programming in MODEL SIM. COMPONENTS REQUIRED: Xilinx IDE, MODEL SIM. ALGORITHM: Step 1: Start the program by including the required Header Files. Step 2: Write the Architecture for processing a,b and assign S & Ca according to Half Adder expression. Step 3: Simulate it using Modelsim. Step 4: Check and verify the signals in the waveform. :

OUTPUT:

RESULT: Thus the Half Adder using VHDL programming in MODEL SIM was designed and verified successfully.

PROGRAM: Full adder

library IEEE; use IEEE.std_logic_1164.all; Entity fa is port(a,b,c: in std_logic; s,ca: out std_logic); end fa; Architecture fa1 of fa is begin s<= a xor b xor c; ca<=(a and b) or (b and c) or (c and a); end fa1;

Expt. No. : 05(b) Date FULL ADDER AIM: To design the Full Adder using VHDL programming in MODEL SIM. COMPONENTS REQUIRED: Xilinx IDE, MODEL SIM. ALGORITHM: Step 1: Start the program by including the required Header Files. Step 2: Write the Architecture for processing a,b,c and assign S & Ca according to Full Adder expression. Step 3: Simulate it using Modelsim. Step 4: Check and verify the signals in the waveform. :

OUTPUT:

RESULT: Thus the full Adder using VHDL programming in MODEL SIM was designed and verified successfully.

PROGRAM: Half Subtractor

library IEEE; use IEEE.std_logic_1164.all; Entity ha is port(a, b: in std_logic; diff, borr : out std_logic); end ha; Architecture ha1 of ha is begin diff<=a xor b; borr<= not a and b; end ha1;

Expt. No. : 06(a) Date HALF SUBTRACTOR AIM: To design the Half Subtractor using VHDL programming in MODEL SIM. COMPONENTS REQUIRED: Xilinx IDE, MODEL SIM. ALGORITHM: Step 1: Start the program by including the required Header Files. Step 2: Write the Architecture for processing a,b and assign d & br according to Half Subtractor expression. Step 3: Simulate it using Modelsim. Step 4: Check and verify the signals in the waveform. :

OUTPUT:

RESULT: Thus the Half Subtractor using VHDL programming in MODEL SIM was designed and verified successfully.

PROGRAM: Full subtractor

library IEEE; use IEEE.std_logic_1164.all; Entity fs is port(a,b,c: in std_logic; diff,borr: out std_logic); end fs; Architecture fs1 of fs is begin diff<=(a xor b xor c); borr<=((b and c) or (not a and (b or c))); end fs1;

Expt. No. : 06(b) Date FULL SUBTRACTOR AIM: To design the Full Subtractor using VHDL programming in MODEL SIM. COMPONENTS REQUIRED: Xilinx IDE, MODEL SIM. ALGORITHM: Step 1: Start the program by including the required Header Files. Step 2: Write the Architecture for processing a,b,c and assign d & br according to Full Subtractor expression. Step 3: Simulate it using Modelsim. Step 4: Check and verify the signals in the waveform. :

OUTPUT:

RESULT: Thus the Full Subtractor using VHDL programming in MODEL SIM was designed and verified successfully.

PROGRAM: Decoder
library IEEE; use IEEE.std_logic_1164.all; Entity dec is port (i: in bit_vector(1 downto 0); o: out bit_vector(3 downto 0)); end dec; Architecture dec1 of dec is begin o<= "0001" when i="00" else "0010" when i="01" else "0100" when i="10" else "1000"; end dec1;

Expt. No. : 07(a) Date DECODER AIM: To design the Decoder using VHDL programming in MODEL SIM. COMPONENTS REQUIRED: Xilinx IDE, MODEL SIM. ALGORITHM: Step 1: Start the program by including the required Header Files. Step 2: Assign the input & output according to Decoder expression. Step 3: Simulate it using Modelsim. Step 4: Check and verify the signals in the waveform. :

OUTPUT:

RESULT: Thus the Decoder of 2*4 using VHDL programming in MODEL SIM was designed and verified successfully.

PROGRAM: Multiplexer
library IEEE; use IEEE.std_logic_1164.all; Entity mux is port(a,b,c,d: in std_logic; s: in std_logic_vector(1 downto 0); o: out std_logic); end mux; Architecture mux1 of mux is begin o<= a when s= "00" else b when s= "01" else c when s= "10" else d; end mux1;

Expt. No. : 07(b) Date 4:1 MULTIPLEXER AIM: To design the 4:1 Multiplexer using VHDL code in MODEL SIM. COMPONENTS REQUIRED: Xilinx IDE, MODEL SIM. ALGORITHM: Step 1: Start the program. Step 2: Declare the entity. Step 3: Define the Architecture of the Entity. Step 4: In the Architecture of Multiplexer, call the components of all Entities. Step 5: Define port Map for each Entity. Step 6: Simulate it using Modelsim. Step 7: Check and verify the signals in the waveform. :

OUTPUT:

RESULT: Thus the 4:1 Multiplexer using VHDL programming in MODEL SIM was designed and verified successfully.

PROGRAM: Parallel Adder

--- LIBRARY DECLARATION --Library IEEE; use IEEE.std_logic_1164.all; ---- ENTITY DECLARATION ---Entity PA is port(A,B: in std_logic_vector(3 downto 0); S: out std_logic_vector(3 downto 0); ca: out std_logic); end PA; Architecture PA1 of PA is ----COMPONENT DECLARATION --component fa port(a,b,c: in std_logic; s,ca: out std_logic); end component; signal x: std_logic:='0'; signal c1,c2,c3: std_logic; begin ----- COMPONENT INSTATIATION --L0: fa port map(a=>A(0),b=>B(0),c=>x,s=>S(0),ca=>c1); L1: fa port map(a=>A(1),b=>B(1),c=>c1,s=>S(1),ca=>c2); L2: fa port map(a=>A(2),b=>B(2),c=>c2,s=>S(2),ca=>c3); L3: fa port map(a=>A(3),b=>B(3),c=>c3,s=>S(3),ca=>ca); end;

Expt. No. : 08(a) Date PARALLEL ADDER AIM: To design the Parallel Adder using VHDL programming in MODEL SIM. COMPONENTS REQUIRED: Xilinx IDE,MODEL SIM. ALGORITHM: Step 1: Start the program by including the required Header Files. Step 2: Write the Architecture for processing a,b,c and assign S & Ca according to Half Adder expression to get c1,c2,c3,x signals. Step 3: Simulate it using Modelsim. Step 4: Check and verify the signals in the waveform. :

SUB PROGRAM: Full Adder

library IEEE; use IEEE.std_logic_1164.all; Entity fa is port(a,b,c: in std_logic; s,ca: out std_logic); end fa; Architecture fa1 of fa is begin s<= a xor b xor c; ca<=(a and b) or (b and c) or (c and a); end fa1;

OUTPUT:

RESULT: Thus the Parallel Adder using VHDL programming in MODEL SIM was designed and verified successfully.

PROGRAM: Parallel Subtractor

library IEEE; use IEEE.std_logic_1164.all; entity ps is port( A,B: in std_logic_vector(3 downto 0); D: out std_logic_vector(3 downto 0); BOR: out std_logic); end ps; Architecture ps1 of ps is component fs port(a,b,c: in std_logic; diff, bor: out std_logic); end component; signal x: std_logic:='0'; signal b1,b2,b3: std_logic; begin L0: fs port map(a=>A(0),b=>B(0), c=>x, diff=>D(0), bor=>b1); L1: fs port map(a=>A(1),b=>B(1), c=>b1, diff=>D(1), bor=>b2); L2: fs port map(a=>A(2),b=>B(2), c=>b2, diff=>D(2), bor=>b3); L3: fs port map(a=>A(3),b=>B(3), c=>b3, diff=>D(3), bor=>bor); end;

Expt. No. : 08(b) Date PARALLEL SUBTRACTOR AIM: To design the Parallel Subtractor using VHDL code in MODEL SIM. COMPONENTS REQUIRED: Xilinx IDE,MODEL SIM. ALGORITHM: Step 1: Start the program. Step 2: Declare the entity. Step 3: Define the Architecture of the Entity. Step 4: In the Architecture of Multiplexer, call the components of all Entities. Step 5: Define port Map for each Entity. Step 6: Simulate it using Modelsim. Step 7: Check and verify the signals in the waveform. :

SUB PROGRAM:

Half subtractor
library IEEE; use IEEE.std_logic_1164.all; Entity ha is port(a, b: in std_logic; diff, borr : out std_logic); end ha; Architecture ha1 of ha is begin diff<=a xor b; borr<= not a and b; end ha1;

OUTPUT:

RESULT: Thus the Parallel Subtractor using VHDL programming in MODEL SIM was designed and verified successfully.