Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Pin name VBAT PC13-TAMPER PC14OSC32_IN(4) PC15OSC32_OUT(4) OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP

Type S I/O I/O I/O I O I/O I/O I/O I/O I/O S S I/O

Main function (after reset) VBAT PC13(5) PC14(5) PC15(5) OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0

Default

Remap

TAMPER-RTC OSC32_IN OSC32_OUT

ADC123_IN10 ADC123_IN11 ADC123_IN12 ADC123_IN13

15

PA1

I/O

PA1

16

PA2

I/O

PA2

17

PA3

I/O

PA3

WKUP/USART2_CTS(6) ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETR USART2_RTS(6) ADC123_IN1/TIM5_CH2 TIM2_CH2(6) USART2_TX(6)/ TIM5_CH3/ADC123_IN2/ TIM2_CH3 (6) USART2_RX(6)/ TIM5_CH4/ADC123_IN3 TIM2_CH4(6)

18 19 20

VSS_4 VDD_4 PA4

S S I/O

VSS_4 VDD_4 PA4

21 22

PA5 PA6

I/O I/O

PA5 PA6

23

PA7

I/O

PA7

24 25 26

PC4 PC5 PB0

I/O I/O I/O

PC4 PC5 PB0

SPI1_NSS(6)/DAC_OUT1 USART2_CK(6) ADC12_IN4 SPI1_SCK(6) DAC_OUT2 ADC12_IN5 SPI1_MISO(6) TIM8_BKIN/ADC12_IN6 TIM3_CH1(6) SPI1_MOSI(6) TIM8_CH1N/ADC12_IN7 TIM3_CH2(6) ADC12_IN14 ADC12_IN15 ADC12_IN8/TIM3_CH3 TIM8_CH2N

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N
1

27

PB1

I/O

PB1

ADC12_IN9 TIM3_CH4(6) TIM8_CH3N I2C2_SCL USART3_TX(6) I2C2_SDA USART3_RX(6)

TIM1_CH3N

28 29 30 31 32 33

PB2/BOOT1 PB10 PB11 VSS_1 VDD_1 PB12

I/O I/O I/O S S I/O

PB2/BOOT1 PB10 PB11 VSS_1 VDD_1 PB12

TIM2_CH3 TIM2_CH4

34

PB13

I/O

PB13

35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PB14 PB15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 PA13/JTMSSWDIO VSS_2 VDD_2 PA14/JTCKSWCLK PA15/JTDI

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O I/O

PB14 PB15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 FT JTMSSWDIO VSS_2 VDD_2 JTCKSWCLK JTDI

SPI2_NSS/I2S2_WS/ I2C2_SMBAl/ USART3_CK(6)/ TIM1_BKIN(6) SPI2_SCK/I2S2_CK USART3_CTS(6)/ TIM1_CH1N SPI2_MISO/TIM1_CH2N USART3_RTS(6) SPI2_MOSI/I2S2_SD TIM1_CH3N(6) I2S2_MCK/ TIM8_CH1/SDIO_D6 I2S3_MCK/ TIM8_CH2/SDIO_D7 TIM8_CH3/SDIO_D0 IM8_CH4/SDIO_D1 USART1_CK/ TIM1_CH1(6)/MCO USART1_TX(6)/ TIM1_CH2(6) USART1_RX(6)/ TIM1_CH3(6) USART1_CTS/CANRX(6) TIM1_CH4(6)/USBDM USART1_RTS/USBDP/ CANTX(6)/TIM1_ETR(6) PA13

TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4

PA14 PA15/SPI3_NSS/ I2S3_WS UART4_TX/SDIO_D2 UART4_RX/SDIO_D3 TIM2_CH1_ET R SPI1_NSS USART3_TX USART3_RX

2

51 52

PC10 PC11

I/O I/O

PC10 PC11

53 54 55

PC12 PD2 PB3/JTDO

I/O I/O I/O

PC12 PD2 JTDO

56 57 58 59

PB4/JNTRST PB5 PB6 PB7

I/O I/O I/O I/O

JNTRST PB5 PB6 PB7

UART5_TX/SDIO_CK TIM3_ETR/UART5_RX SDIO_CMD PB3/TRACESWO JTDO SPI3_SCK/I2S3_CK/ PB4/SPI3_MISO I2C1_SMBAl/ SPI3_MOSI/I2S3_SD I2C1_SCL(6)/ TIM4_CH1(6) I2C1_SDA(6)/ FSMC_NADV/ TIM4_CH2(6) TIM4_CH3(6)/SDIO_D4 TIM4_CH4(6)/SDIO_D5

USART3_CK

TIM2_CH2 / SPI1_SCK TIM3_CH1 / SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX

60 61 62 63 64

BOOT0 PB8 PB9 VSS_3 VDD_3

I I/O I/O S S

BOOT0 PB8 PB9 VSS_3 VDD_3

I2C1_SCL/ CANRX I2C1_SDA / CANTX

1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 is restricted: only one I/O at a time can be used as an output, the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 8. For devices delivered in LQFP64 packages, the FSMC function is not available.
3