SUB: EDA

Sub Code: EC702

Sem: 7th STREAM: ECE

Group A (Multiple Choice Type Questions) 1. Choose the correct alternatives for the following: i)What is another name of D.Gzaski chart? (a)Y Chart (b) Z chart ii.)Channel less Gate array is a sub type of (a) FPGA. (b) ASIC.

(c) Smith Chart. (d) Log Chart.

(c) PLD. (d) None of these.

iii.) Always interconnection will be done between neighboring modules means (a) Locality (c) Regularity. (b) Modularity (d) Synthesis. iv) Mead and Conway proposed which diagram among the following. (a) Stick Diagram. (c) Lambda Layout diagram. (b) Micron Layout diagram. (d) None of these. v) The model parameter LAMDA () in a MOS structure stands for (a) Flicker noise coefficient. (c) Transit time. (b) Channel Length modulation. (d) Transconductance. vi)In which PLD all the inputs and outputs are connected with programmable connection? (a) EPROM (b) PAL (c) PLA (d) FPGA vii) In which type of ASIC, the Cell size is variable ? (a) Full Custom (b) Standard Cell (c) Gate array (d) FPGA viii) Bypass register is needed for (a) Boundary Scan testing (c) Ad-hoc testing ix) K-L algorithm is used for (a) Partitioning (c) Floorplaning x) Channel density is related to (a) Partitioning (c) Floorplaning

(b) BIST (d) ATPG

(b) Placement (d) Routing

(b) Placement (d) Routing

xi) In the design rule the width of the well is in unit (a) 9 (b) 12 (c) 10 (d) 6

xii) Full form of PODEM is

a) path oriented decision making c) pxoximity ordinary decision making

b) path oriented data making d) none of these

xiii) Manufacturing lead time for full custom ASIC is a) 2 weeks b) 2 days c) 8 weeks d) 5 weeks xiv) In VHDL is a a) signal b) variable c) signal called assignment d) equal to sign xv) What is LUT? a) unit of ASIC c) unit of CPLD

b) small unit of FPGA d) a PLA

xvi) Programmable logic device (PLD) is a) fixed programmable b) Fabricated using custom specific layout c) quick design process d) all of these xvii) Which algorithm is most advantageous among these a) quadrature min cut algorithm b) bisection min cut algorithm c) slice and bisection algorithm d) normal placement algorithm xviii) This is the symbol for := a) signal b) variable c) both d) none of these xix) Generation and application is included in a) verification b) layout c) testing d) syntax check xx) Boundary Scan Cell includes a) Mux b) flip flop c) mux and flip flop d) none of these xxi) Which is automatic way of testing by generating test pattern a) ad-hoc testing b) scan based testing c) BIST d) BST xxii) Full form of VHDL is a) very high development language b) very high speed hardware description language c) very high speed integrated circuits hardware description language d) very high speed description language xxiii) For multi valued logic IEEE 1164 requires a) std_logic b) std_ulogic c) stdlogic d) std_vlogic xxiv) Step coverage is better for a) negative photoresist b) positive photoresist c) same for both d) DUV photoresist

xxv) A datapath is a collection of a) memory b) ALUs or multipliers c) ASIC d) Fpgas xxvi) Difference between CPLD and FPGA is a) architectural b) behavioral c) no difference d) in flexibility and architectural Group B (Answer any three) 2. a) What are the differences between Full- Custom, Semi-Custom and PLD?. b) What do you mean by VHDL? What is Concurrent Statement of VHDL? 3. Define the following: Layout of a CMOS NAND Gate. 4. What do you mean by stick diagram? Draw the stick diagram for {(A+B)C}/. 5. Write a VHDL program of a MOD-8 counter using generic statement. 6. Discuss the three different graph models which are commonly used in VLSI design. 7. Draw the Binary Decision Diagram (BDD), OBDD and ROBDD of the Boolean Expression f=(a+b)c. 8. Describe the Shanons expansion Theorem with a suitable example. Group C (Answer any three) 8. (a) What is the difference between SIGNAL and VARIABLE in the VHDL Program? (b) Discuss about the different styles of describing the Architecture in VHDL with suitable example. (c) Write a program of 4:1 MUX using CASE and WHEN-THEN statement. 9. (a) What is ASIC? Give the classification of ASIC. (b) Write the advantages and disadvantages of full custom ASIC. (c) Give some application of Full custom ASIC? (d) Distinguish between Channeled gate array and Channel less gate Array . (e) Describe the design flow of an ASIC Design. 10. (a) What do you mean by Stuck at fault?. (b) What is Roths Test Detect Algorithm? Describe it using a suitable example. (c) What is importance of DFT in ASIC Design? Explain the different DFT procedure with appropriate block diagram. (d) What are the differences between Testing and verification? 11. (a) Describe the Scheduling and Binding in High-level Synthesis using ASAP and ALAP algorithms, Sequencing Graph and DFG with a suitable example. (b) Consider the ONSET of the Boolean Function is in the Figure given bellow. Now optimize it by Two Level Optimization Method.

12. (a) What is the Min-Cut Algorithm. Describe the different types of Min-Cut algorithm. (b) Describe the Kernighan-Lin Algorithm for partitioning with a suitable example. (c) Optimize the System, described by the State Diagram given bellow.

12. (a) Describe the Sliceable, Non-Sliceable and Hierarchical Floorplaning using their corresponding Trees with a suitable example. (b) Describe the Spacial Routing, Global Routing and Detail Routing. (c) Design an XOR gate using LUT based FPGA. 13. Short Notes. (Answer any three) (a) CAD Tools (b) ATPG (c) Analog Design Automation (d) Minimize the Following Expression by Tabular Method. F=m(0,1,2,8,9,15,17,21,24,25,27,31). (e) IC design Flow using EDA Tools. (f) Typical design flow using VHDL. 14. a) What is Layout? Draw the layout of CMOS Inverter. What is FOX in IC fabrication? b) Implement a full adder in VHDL code using mixed style of Modelling. c) What are -based and -based design rules for the layout of VLSI circuits? For 0.5m process what is the value of ? According to the design rule, what will be the minimum width of diffusion region and metal interconnect lines? 15.a) Explain the n-well CMOS fabrication process with necessary diagrams. b) Draw the CMOS NAND gate and CMOS NOR gate using layout technique. c) Give the circuit and stick diagram of NMOS two input NOR gate. Explain the operation of the gate.