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MOS Transistor Capacitance

Gate Gate Source CGS CGD CGB CSB CDB CSB Drain Source CGS CGD CGB CDB Drain

VDD

VLSI Design

Dr. Bassel Soudan University of Sharjah

Gate Capacitance
CGB

OX

WL

tOX

= COX WL

Define Cpermicron = CoxL Typically about 2 fF/m

 Typically about 2 fF/m

Therefore, CGB = Cpermicron X W Realistically, there are additional capacitances. However, the above relationship is a polysilicon good approximation gate W of the gate t capacitance. SiO L
ox

n+

n+

gate oxide 2 (good insulator, = 3.9 )

ox 0

p-type body

VLSI Design

Dr. Bassel Soudan University of Sharjah

Diffusion Capacitance

CSB, CDB Undesirable, called parasitic capacitance Capacitance depends on area and perimeter
Comparable to CG for contacted diffusion CG for uncontacted Varies with process

VLSI Design

Dr. Bassel Soudan University of Sharjah

MOSFET Resistance

The resistance of a MOSFET transistor must be determined from the Shockley I-V relationships.
However, Ids(Vds, Vgs). Therefore, R the resistance to current moving from the drain to the source is:

I R = ds V ds
However,

Shockley models for MOSFET transistor are not accurate enough for modern transistors Too complicated for hand analysis
VLSI Design
Dr. Bassel Soudan University of Sharjah
6

Effective Resistance

Simplification: treat transistor as resistor

Replace with effective resistance R
Ids = Vds/R

R averaged across switching range of digital gate

Simulate the transistor driving a known capacitance and measure the time constant. Too inaccurate to predict current at any given time
But good enough to predict RC delay

VLSI Design

Dr. Bassel Soudan University of Sharjah

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4

RC Delay Model

Use equivalent circuits for MOS transistors

of 23 Ideal switch + capacitances and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C
The PMOS resistance should actually be (kn/kp)R

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Capacitance proportional to width Resistance inversely proportional to width

d kC d k s R/k g kC s kC g s k d kC g kC d s kC 2R/k

VLSI Design

Dr. Bassel Soudan University of Sharjah

RC Values

Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width Search This Document across many processes Values similar
Search Resistance Search History: Searching... R 6K * m Result 00 of 00 00 results for result for

in 0.6um process

Unit transistors p.

Improves with shorter channel lengths May refer to minimum contacted device (4/2 ) Or maybe 1 m wide device Doesnt matter as long as you are consistent

VLSI Design

Dr. Bassel Soudan University of Sharjah

Input Capacitance of the CMOS Inverter

The input capacitance of the CMOS inverter can be C = C as: C written +

in GN GP

= (WN + WP) Cpermicron

Cpermicron = COX X L:
COX the oxide capacitance which depends on the type of oxide used and is inversely dependent on the thickness of the oxide layer.
COX is typically in the range of ~700aF/m2
-18

L the length of the channel.

a stands for atto 10 .

VLSI Design

Dr. Bassel Soudan University of Sharjah

10

Example

Calculate the input capacitance for a CMOS inverter with the following characteristics:
COX = 690 aF/m2 WN / LN = 4m / 2m WP / LP = 8m / 2m

Using the expressions from above: Cin = (WN + WP) Cpermicron Cpermicron = L COX

Cpermicron = 2m X 690 aF/m2 = 1.38 fF/m Cin = (4m + 8m) X 1.38 fF/m Cin = 16.56 fF
VLSI Design
Dr. Bassel Soudan University of Sharjah
11

Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

2 Y 1

2 1

VLSI Design

Dr. Bassel Soudan University of Sharjah

12

Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

2C R 2C A 2 Y 1 2 1 R 2C Y C C

VLSI Design

Dr. Bassel Soudan University of Sharjah

13

Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

2C R 2C 2C Y 1 R C R C C C 2C

2 Y 1

2C

VLSI Design

Dr. Bassel Soudan University of Sharjah

14

8 Cmos Capacitance
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