Appendix

Projects for Graduate-Level Courses

P.1 INTRODUCTION To assist the student in understanding the course material and the instructor in evaluating students performance, a number of simulation based projects can be assigned. The titles of these projects are as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 12-Pulse Series-Type Diode Rectifier 18-Pulse SCR Rectifier Space-Vector Modulation Schemes for Two-level Voltage Source Inverter Multilevel CHB Inverter with Carrier-Based Modulation Techniques Three-Level NPC Inverter with Space-Vector Modulation IPD and APOD Modulation Schemes for Multilevel Diode Clamped Inverters Current Source Inverter with Space-Vector Modulation TPWM and SHE Schemes for Current Source Inverters Dual-bridge Current Source Rectifier VSI Fed MV Drive with Common-Mode Voltage Mitigation CSI Fed MV Drive with Common-Mode Voltage Mitigation High-Performance Induction Motor Drive with Field-Oriented Control

It is suggested that five to six projects be selected for a one-semester graduate course. The detailed instruction for the projects and their answers will be included in Instructors Manual. As an example, the instruction for Project 3 is given in the following text.
High-Power Converters and ac Drives. By Bin Wu 2006 The Institute of Electrical and Electronics Engineers, Inc.

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P.2 SAMPLE PROJECT Project 3Space Vector Modulation Schemes for TwoLevel Voltage Source Inverter
Objectives 1) To understand the principle of space vector modulation; and 2) To investigate the harmonic performance of the two-level voltage source inverter. Suggested Simulation Software Matlab/Simulink System Spefications Inverter Topology: Two-level voltage source inverter as shown in Fig. 6.1-1 Rated Inverter Output Power: 1 MVA Rated Inverter Output Voltage: 4160 V (fundamental voltage, rms) Rated Inverter Output Current: 138.8 A (fundamental, rms) Rated dc Input Voltage: Constant dc (to be determined) Load: RL load with a per-phase resistance of 0.9 pu and inductance of 0.31 pu, which gives the load impedance of 1.0 pu with a lagging power factor of 0.95. Note that the RL load is fixed for the inverter operating under various conditions. Switching Devices: Ideal switch (no power losses or forward voltage drops) Project Requirements Part A A.1 Determine the dc input voltage Vd that can produce a fundamental lineto-line voltage of 4160 V (rms) at the modulation index of ma = 1.0. A.2 Determine the value of load resistance ( ) and inductance (mH). Part B Develop a simulation program for the conventional SVM scheme using the seven-segment switching sequence given in Table 6.3-4. Run your simulation program for the tasks given in Table P.1. B.1 For each of the above tasks, draw waveforms (two cycles each) for the inverter line-to-line voltage VAB (V) and inverter output current iA (A). B.2 Plot the harmonic spectrum (0 to 60th harmonics) of vAB normalized to the dc voltage Vd and iA normalized to its rated fundamental component IA1,RTD (138.8 A). Find the THD of vAB and iA.

Appendix Table P.1 Simulation Task T.1 T.2 T.3 T.4 Simulation tasks for the conventional SVM scheme f1 (Hz) 30 30 60 60 ma 0.4 0.8 0.4 0.8 Ts (sec) 1/720 1/720 1/720 1/720

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Table P.2 Simulation Task T.5 T.6

Simulation tasks for the modified SVM scheme f1 (Hz) 30 60 ma 0.8 0.8 Ts (sec) 1/720 1/720

B.3 Analyze your simulation results and draw conclusions. Part C Modify your simulation program developed in Part B such that even-order harmonics in vAB can be eliminated. Use the switching sequence given in Table 6.3-5. Run your simulation program for the tasks given in Table P.2. C.1 For each of the above tasks, draw the waveforms for vAB and iA. C.2 Calculate harmonic spectrum and THD of vAB and iA. C.3 Find harmonic content of vAB versus ma for the inverter operating at f1 = 60 Hz and Ts = 1/720 sec. C.4 Analyze your simulation results and draw conclusions. Project Report The project report is composed of the following six parts: 1. Title page 2. Abstract 3. Introduction 4. Theory 5. Simulation results 6. Conclusions

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P.3 ANSWERS TO SAMPLE PROJECT

A.1 Vd = 5883 V A.2 R = 16.4 and L = 14.2 mH per phase B.1 Simulated Waveforms

Figure P.1

Waveforms of vAB and iA at f1 = 30 Hz.

Figure P.2

Waveforms of vAB and iA at f1 = 60 Hz.

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B.2 Harmonic Spectrum and THD

(a) ma = 0.4

Figure P.3

Harmonic spectrum and THD of vAB and iA at f1 = 30 Hz.

(a) ma = 0.4

Figure P.4

Waveforms of vAB and iA at f1 = 60 Hz.

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B.3 Summary The waveform of vAB is not half-wave symmetrical, i.e., f ( t) f ( t + ). Therefore, it contains both even and odd order harmonics. The THD of iA is much lower than that of vAB. This is due to the filtering effect of the load inductance. The voltage and current harmonics appear in sidebands whose frequency is centered around the sampling frequency (720 Hz) and its multiples (such as 1440 Hz). The fundamental voltage VAB1 is proportional to the modulation index ma. The THD of vAB decreases with the increase of ma, which is consistent with the THD curve in Fig. 6-3.7. The number of pulses Np per half cycle of the inverter fundamental frequency does not affect the THD significantly. For example, the THD of vAB in Figure P.1(a) with Np = 22 is 147.6% in comparison to 150.9% in Figure P.2(a) where Np = 12. The harmonic spectrum of vAB in Figure P.4(b) is very close to the measured spectrum in Fig. 6.3-6. C.1 Simulated Waveforms

Figure P.5

Waveforms of vAB and iA at ma = 0.8.

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C.2 Harmonic Spectrum and THD

(a) f1 = 30Hz

Figure P.6

Harmonic spectrum and THD of vAB and iA at ma = 0.8.

C.3 Harmonic Content

Figure P.3

Harmonic content (f1 = 60 Hz and Ts = 1/720, no even order harmonics).

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C.4 Summary The waveform of vAB is of half-wave symmetry, i.e., f ( t) = f ( t + ). Therefore, it does not contain any even order harmonics. The THD of vAB and iA in Figure P.6 is almost identical to that given in Figures P.3(a) and P.4(b), which implies that the use of the modified SVM for even order harmonic elimination does not affect the THD profile of the inverter. The harmonic spectrum of vAB in Figure P.6(b) is very close to the measured spectrum given in Fig. 6.3-10.