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# Layout Design

## Lecture 4 18-322 Fall 2003

Textbook: Design Methodology Insert A
[Portions adapted from J. P. Uyemura Introduction to VLSI Circuits and Systems, Wiley 2001.]

Transistor sizing Wires

## Homework 1: Due Thursday Homework 2: Out Thursday Lab 2: This week

Todays Overview
Physical structure of ICs
Design rules Basic gates layout

Stick diagrams
Basic rules Examples

Review: MOSFETs
Gate (G) No connection

G=0
Source Gate layer Conduction layer Drain Open switch

Source layer

Drain layer

Closed switch

G=1

G is responsible for the absence or presence of the conduction region between the drain and the source regions

VG
source diff

0V n+

## insulator drain diff

L W n+ Top view n+

n+
No electrons

p Side view

+
n+
electrons

electron channel

n+ n+ n+ p

Review: Manufacturing
2D top-down view How design engineers see the chip.

## 3D cross-section view How process engineers see the chip.

Design Rules
Interface between designer and process engineer
Clean separation between the process during wafer fabrication and the design effort
Permissible geometries -> DESIGN RULES

## Ways to do design rules

Scalable Design Rules Absolute measures

## Scalable Design Rules

CMOS scales
Implement something now, shrink it later Express all design rules in terms of a unit dimension Change the actual dimension of the unit, and the whole design shrinks Mead and Conway

Unit dimension: Minimum line width (2) In 1978, = 1.5 m (a.k.a. 3 micron technology) In 2003, = 0.065 m (a.k.a. 0.13 micron technology) Important Intellectual idea, not used in industry (but we will)

Transistor Layout
poly

Transistor

L W
3 2

## All distances are expressed in

Well boundary

Transistor Layout
5 4 2 2 Source Source to gate shortcirc L 2 Drain W 2 Non-catastrophic misalignment

= 0.5m -> A = 12.5m2

## Absolute Design Rules

It is hard to scale every aspect of design linearly The elegance of scalable CMOS isnt worth the cost Specify all dimensions in real units (m or nm) Currently (0.13 micron), there are THOUSANDS of design rules

## CMOS Process Layers

Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

Inverters
VDD VDD VDD

Vin

Vout

Vin

Vout

Vin

Vout

## Transistor sizing determines inverter fundamental properties!

Series/Parallel Connections
A A n+ n+ B n+ n+ A n+ B n+ n+ n+ p n+ B

Devices can share patterned regions; this may reduce the layout area or complexity!
A B
X

X
X

B
X

poly metal

Red Blue

n+/p+ Green

contact Black

NAND2
V DD

V DD NOT(AB) A B GND

B A

NOT(AB)

GND

V DD VDD

V DD NOT(AB) A B GND

B A

NOT(AB)

A and B

GND

GND

NOR2
V DD A NOT(A+B) B GND GND B NOT(A+B)
The output here is connected to one p-trans drain and two n-trans drains.

V DD

## NOR2 (alternate layout)

V DD V DD

A NOT(A+B) B GND

A B NOT(A+B)
The output here is connected to one p-trans drain and one n-trans drain.

GND

This is better!
Less drain area connected to the output . This results in a faster gate.

## Complex Logic Gates: OAI Gates

#1
2 A B C D A F B C A D B C 1 D

#2
2

F= NOT(A(B+C+D))

2

C A

2 VD D

C A

1 GND A B C D

2 VD D

C A

D F

1 GND A B C D

## Capacitance: Friend or Foe???

Foe: Slows down the output:
Big Capacitance More charge to to change voltage SLOWER!

## Friend: Stabilizes the Power Supply

Big Capacitance More charge to to change voltage More stable supply voltage!

#2
2 A

C 1

2 VDD A

C 1

GND A B C D

V DD V DD

## The output here has two output drain capacitances.

GND A B C D A B C D

GND

Right

Wrong

## Gate Design Procedure

Run VDD and GND in metal at top and bottom Run vertical poly for each gate input Order gates to allow maximum source-drain abutting Place max number of n-diffusions close to GND Place max number of p-diffusions close to VDD Make remaining connections with metal
Minimize metal usage

Overview
Physical structure of ICs
Design rules Basic gates layout

Stick diagrams
Basic rules Examples

Stick Diagrams
Introduced by Mead & Conway in the 80s Every line of a conduction material layer is represented by a line of a distinct color

## Logic Gates Design

Examples

Complex Functions
OUT = ABC + D
VDD A D B C
X X X X X V DD

OUT
X X X

OUT

A B
GND

D
C

Summary
Discussed
Design rules Basic gates layout Stick diagrams

## Need more practice on

Stick diagrams Layout (mostly in the lab)

Boolean function

## Preview: Modern ASIC Design

Designer Productivity is a big problem In 1978, people could draw transistors, now there are 100s of millions per chip New abstractions necessary: Cell Libraries Design Rules