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APPENDIX
Chapter 3
3.4(f) 3.5(c) 3.7(a) 3.9(c) 3.10(b) 3.11(d) 3.11(e) 3.14(a) 3.14(c) 3.15 3.17(b)
c(5)+ (AB)C
C 0(AB)
+ABC
BC
=z
(m)
ChaDter 4
4.1 4.3(c) 4.7 4.10 4.13
F=OF =__ BC AC + f=AOC ___ J ; = A B C , f; = C J;=B@C Add the 4-bit unsigned number to itself using full-adders.
fo=s
627
628
4.16
Z= 1
4.20
W=m9 For 4-Bit signed number, A A + 11 1 1, = A - 1, decrement by 1. A + 0 0 0 1 , = A + 1,incrementby 1. Manipulate C,, to accomplish the above.
ChaDter 5
qqg
Q
Tx = ; Ty = 1
Tie JK inputs to HIGH ; Clock is the T input. 5.13 B, = A , outputy = B 5.15 5.17(b) Jx = z, kx = y Jy = - ky = x + z 1, Jz =xy, kz = x DA= (A O x ) + %x5.19 Where x is the input DR= x(A O B) + ABx 5.20(c) 5.23 5.24(a)
J ,
73 = Q,Qo
= B,
K,
= BC,
QzQiQo
J,
= C,
K,= C, J,
1, K, = A + B
self correcting
ChaDter 6
6.4(a)
sign = 0, carry = 0, zero = 0, overflow = 0. sign = 1, carry = 0, zero = 0, overflow = 1. 20BE 6.6(a) Cb) (20BE) = 05, (20BF) = 02 6.13(a) 16,384 (b) 128 chips (c) 4 bits 6.18 Use the following identities: a 0a = 0 and a O 0 = a and ( a 06 ) 0a
(4
=b
ChaDter 7
Yes, it is possible Yes, it is possible Use four muxs. Manipulate inputs of the muxs to obtain the desired outputs. Use the tristate buffers at the outputs of the muxs. y=lxl If x7= 0, then y,.... y2yIyo - ....x2xlxo = x7 --_ else y7....y2y1yo x7....XZXlX0 + 1 =
629
7. (a)
s 15
xi
co
7.14
F 7.17 7.22(a) 7.25(a) 7.34(a) Product = 0000 0000 0000 01 00, Po = zT3, P , = T, L = P o +PI, d , = P , , d , =Po, d o = P l C0 = C I = T C~ = T C = rC = C = T O Z I 3 4 Savings = 34,304 bits
C 2= T~
c,
1
c,
0
c 2
1 1
c,
0 0
c o
0 0
; A AminusA ; A + Aex-or A
Make F=O (set c,,c, lc12 000) and set the zero flag to 1. to Execute JZ instruction.
ChaDter 8 8.5 8.6(a) 8.13 8.14 8.16 Memory Chip #1 ECOOH - EDFFH Memory Chip #2 F200H - F3FFH ROM Map: OOOOH - 07FFH RAM Map: 2000H - 27FFH 20 Maximum Directly Addressable Memory = 16 Megabytes; 14 unused address pins Available. (b) Virtual address Physical address 24 24 3784 I224 10250 page fault 30780 page fault (a) 4115 6 x 64 decoder Cache Tag Field = I-bit Cache Index Field = 12-bits Cache Data Field = 32-bits Cache word size = 36 bits.
630
8.27 8.28 8.37 8.39 8.41
2040
STAW
The above program assumes that the system supports delayed branch. ChaDter 9 9.4 9.6(a) 9.8 9.13 20642H Implied (AL)=5
XCHG MOV ADD HLT BL,BH AX, BX AX,CX
9.19
9.26
BCD2BIN
BC2BIN CONV
SEGMENT ASSUME C S :CONV PROC FAR MOV BX,4000H MOV CL,10 MOV DX, 0 MOV AL, [ B X ] MUL CL ADD DX,AX INC BX ADD DL, [ B X ] RE T ENDP ENDS END
9.27
MOV MOV OUT MOV BACK :
IN
63 1
S T A R T : DEC
LEDON: MOV
PORTB,AL
9.28 9.34
Port A = OlH, Port B = 03H, Port C = 05H, CNTRL = 07H 2732 ODD = 00001H,00003H, ...,01FFFH 2732 EVEN = 00000H,00002H, ...,01FFEH For 15 sec. delay: a count of 093 1H provides a delay of 20 msec; this loop needs to be executed 750 times.
ChaDter 10 TRAP occurs since odd address. 10.7 10.9(c) Privileged 10.13 $0000 0000 10.16 SWAP D1
MOVE EXT .L SWAP EXT. W DIVS JMP D 1 , DO DO D1 D1 D 1 , DO FINISH
FINISH
10.18
10.31 10.33
AS -= 0 ,
FC2FClFCO=-l LDS=I, UDS=O Memory map: even 2764 $000000,$000002,...,$003FFE odd 2764 $000001,$000003,...,$003FFF 68230 I/O map: PGCR = $004001, PADDR = $004005 PBDDR = $004007, PACR = $00400D PBCR = $00400F, PADR = $00401 1 PBDR = $004013
11.20
(ECX) = 2A157241H
632
11.22 11.33 11.35 11.39
ADD.L D3,DO ADDX.L D2,Dl FINISH JMP FINISH 1 1.45 *32-bit device: Byte data will be transferred via 68020 D,, - D, pins. *8-bit device: Byte data will be transferred via D,, - &,pins. 11.49 GPRO - GPR3 I 11.51(b) The PR bit in MSR is 1. 11.52(a The 32-bit contents of r2 and r3 are added; the result is stored in rl. The dot suffix
enables the update of the condition register.