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The Easy8051 v6 is compatible w ith 14-, 16-, 20-, 28-, 40-pin PLCC44 and PLCC32 MCUs. It comes w ith an AT89S8253. The board has a USB 2.0 programmer and many peripherals such as COG, port expander, MENU and 4x4 keypads etc. [more info]
Introduction
It has been more than 20 years since the first version of the 8051 microcontroller was launched. During that time it has undergone various upgrades and improvements. Today, the 8051 microcontroller is being manufactured across the globe by many manufacturers and under different names. Of course, the latest versions are by far more advanced than the original one. Many of them has the label 8051 compatible, 8051 compliantor 8051 family in order to emphasize their noble heritage. These tags imply that microcontrollers have similar architecture and are programmed in a similar way using the same instruction set. Practically, if you know how to handle one microcontroller belonging to this family, you will be able to handle any of them. In other words, several hundreds of different models are at your disposal. This book covers one of them called the AT89S8253, manufactured by Atmel. Why this particular one? Because it is widely used, cheap and uses Flash memory for storing programs. The last feature mentioned makes it ideal for experimentation due to the fact that program can be loaded and erased from it for many times. Besides, thanks to the built-in SPI System (Serial Programing Interface), the program can be loaded to the microcontroller even after embedding the chip in the target device.
mikroProg for 8051 is supported w ith mikroC, mikroBasic and mikroPascal compilers for 8051. You may also use mikroProg for 8051 as a
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2Kb of EEPROM Memory. Power supply voltage: 4-6V. Operating clock frequency: 0-24MHz. 256 bytes of internal RAM for storing variables. 32 input/output pins. Three 16-bit timers/counters. 9 interrupt sources. 2 additional power saving modes (low-power idle and power-down mode). Programmable UART serial communication. Programmable watchdog timer. Three-level program memory lock
The 8051 core combined w ith modern modules is popular in the past. With m ikroBasic you can quickly develop your projects. [more info]
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Port 2 (P2.0-P2.7) Whether configured as an input or an output, this port acts the same as Port 1. If external memory is used, the high byte of the address (A8-A15) comes out on the Port 2 which is thus used for addressing it. Port 3 (P3.0-P3.7) Similar to P1, Port 3 pins can be used as general inputs or outputs. They also have additional functions to be explained later in the chapter.
P O RT P I N P3.0 P3.1 P3.2 P3.3 P3.4 A L T ERNA T E F UNC T I O N RXD (serial input) TXD (serial output) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input)
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T1 (Timer 1 external input) WR (External data memory write signal) RD (External data memory read signal)
RST Logic one (1) on this pin causes the microcontroller to be reset. ALE/PROG In normal operation, the ALE pin is activated at a constant rate of 1/16 the oscillator frequency and can be used for external clocking and timing purposes. When external memory is used, a signal from this pin is used to latch the low byte of an address (A0-A7) from P0. During the process of writing a program to the microcontroller, this pin also serves as a control input. PSEN This pin provides a signal used for accessing external program memory (ROM). EA/VPP When this pin is connected to ground, the microcontroller reads program instructions from external program memory. If internal program memory is used, which is the common case, this pin should be connected to the positive power supply voltage (VCC). During the process of programming internal Flash mamory, this pin is supplied with +12V. XTAL 1 This is internal oscillator input. It is used for the purpose of synchronizing the operation of the microcontroller with some other circuit or for connecting external oscillator when used. XTAL 2 This pin is connected to internal oscillator output. Therefore, it is out of use when using external oscillator.
128 general-purpose registers; 128 memory locations reserved for SFRs. Even though only some of them are trully used, free locations shouldnt be used for storing variables; and 128 additional registers available for use (have no special purpose). Since they have the same addresses as SFRs, they are accessed by indirect addressing.
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EEPROM Memory
EEPROM is a special type of memory having features of both RAM and ROM. The contents of the EEPROM may be changed during operation, but remains permanently saved even after the loss of power. The AT89S8253 microcontroller has in total of 2K of EEPROM, that is 2048 locations.
Memory Expansion
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All mentioned above about ROM and RAM memory expansion remains in force when it comes to the AT89S8253 microcontroller as it is based on the 8051 core. In other words, both memories can be added as external chips with the capacity of up to 64Kb. The process of addressing is also the same as in the 8051 standard.
Types of addressing
Similar to all microcontrollers compatible with the 8051, there are two ways of addressing:
Direct addressing (for example: MOV A,30h); and Indirect addressing (for example: MOV A,@R0).
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As shown in the table above, each of these registers has its name and specific address in RAM. Unoccupied locations are intended for the future upgraded versions of the microcontroller and shouldnt be used. As their name suggests, these registers are mostly in control of one specific circuit within the microcontroller such as timers or SPI etc. and they will be discussed later in the book. This chapter covers only those SFRs controlling more than one circuit within the microcontroller.
Accumulator (ACC)
The accumulator, otherwise marked as ACC or A, belongs to the core registers of the 8051 microcontroller. Its contents is not modified.
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B register
The B register also belongs to the core registers of the 8051 microcontroller. Bits of this register are not modified. It is used during multiply and divide operations (MUL and DIV instructions) to store the operands upon which these operations are performed.
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comminication with peripheral environment which is carried out by sending data from registers to the corresponding pins and vice versa. They belong to the core registers of the 8051 microcontroller and their bits are not modified.
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DISALE
0 - ALE is activated at a constant rate of 1/6 the oscillator frequency. 1 - ALE is active only during execution of MOVX or MOVC instructions.
Intel_Pwd_Exit
0 - When the microcontroller is in Pow er Dow n mode, the program proceeds w ith execution on high-to-low transition (1-0). 1 - When the microcontroller is in Pow er Dow n mode, the program proceeds w ith execution on low -to-high transition (0-1).
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0 - The oscillator frequency (the XTAL1 pin) is divided by 2 before used as a clock (machine cycle lasts for 6 such periods). 1 - Quartz oscillator is used as a clock generator. This enables the quartz crystal of two times lower frequency (for example 6MHz instead of 12MHz) to be used for the same operating rate of the microcontroller. Data Pointers
Data Pointers are not true registers as they dont physically exist. They consist of two separate registers: DPH (Data Pointer High) and DPL (Data Pointer Low). All 16 bits are used for addressing external and internal EEPROM memory. The DPS bit of the EECON register determines the registers to be used as data pointers: DPS=0 -> Data pointer consists of DP0L and DP0H registers and is marked as DPTR0.
DPS=1 -> Data pointer consists of DP1L and DP1H registers and is marked as DPTR1.
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EECON register
Bits of the EECON register controls the operation of EEPROM memory:
WRTINH The WRTINH bit is read-only. When the power supply voltage is too low for programming EEPROM, hardware automatically clears this bit, which means that write to EEPROM cannot be completed or is aborted if in progress.
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0 - Write in progress (takes approximately 4mS). 1 - Write complete (data is written to EEPROM).
DPS
0 - Address for EEPROM write/read is stored in the DP0H and DP0L registers. 1 - Address for EEPROM write/read is stored in the DP1H and DP1L registers.
EEMEN
0 - Instruction MOVX is used for accessing external memory chip. 1 - Instruction MOVX is used for accessing internal EEPROM memory. If the register address is larger than 2K, the microcontroller will access external memory chip.
EEMWE When set, the EEMWE bit enables write to EEPROM using the MOVX instruction. After completing EEPROM write, the bit must be cleared from within the program. EELD When set, the EELD bit enables up to 32 bytes to be written simultaneously. The bit is set and the MOVX instruction writes data to EEPROM (buffer is loaded). The bit is cleared before writing the last data. When the last MOVX is executed, the entire buffer is automatically loaded to EEPROM for 4mS.
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PS2 0 0 0 0 1 1 1 1
PS1 0 0 1 1 0 0 1 1
PS2,PS1,PS0 These three bits are in control of the prescaler and determine the nominal time of the watchdog timer. If the program doesnt clear the WSWRST bit during that time, the watchdog timer will reset the microcontroller. When all three bits are cleared to 0, the watchdog timer has a nominal period of 16K machine cycles. When all three bits are set to 1, the nominal period is 2048K machine cycles. WDIDLE The WDIDLE bit enables/disables the watchdog timer in Idle mode:
0 - Watchdog timer is enabled in Idle mode (low-consumption mode). 1 - Watchdog timer is disabled in Idle mode.
DISRTO The DISRTO bit enables/disables reset of peripheral circuits connected to the RST pin:
0 - Watchdog controls the state of the input reset pin. At the moment of reset, this pin acts for a moment as an output and generates a logic one (1). It causes the microcontroller and all other circuits connected to the RST pin to be reset. 1 - Reset triggered by the watchdog timer doesnt affect the state of the reset pin. At the moment the watchdog timer resets the microcontroller, the reset pin remains configured as an input.
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HWDT The HWDT bit selects hardware or software mode for the watchdog timer:
0 - Watchdog is in software mode and can be enabled or disabled by the WDTEN bit. 1 - Watchdog is in hardware mode. To enable it, the sequence 1E/E1(hex) should be written to the WDTRST register. Only reset condition can disable the watchdog timer. In order to prevent the WCDT from resetting the microcontroller when the nominal time expires, the same sequence 1E/E1hex must be constantly repeated.
WSWRST When set, this bit resets the watchdog timer in software mode (bit HWDT=0). In order to enable the microcontroller to operate without being interrupted, this bit must regularly be cleared from within the program. After being set, the watchdog timer is cleared by hardware, counting starts from zero and the bit is automatically cleared. If the watchdog timer is in hardware mode, setting this bit has no effect on the watchdog timer operation. WDTEN The WDTEN bit enables/disables the watchdog timer in software mode (HWDT=0):
4.6 Interrupts
The AT89S8253 has in total of six interrupt sources, which means that it can recognize up to 6 different events that can interrupt regular program execution. Each of these interrupts can be individually enabled or disabled by setting bits of the IE register, whereas the whole interrupt system can be disabled by clearing the EA bit of the same register. Since this microcontroller has embedded Timer T2 and SPI (they don't fall under the 8051 Standard) which can generate an interrupt, it was necessary to make some changes in registers controlling interrupt system. Besides, there is a new interrupt vector (address 2B), i.e. program memory address from which the program proceeds with execution when the Timer T2 generates an interrupt. All these changes are made on the previously unused bits. This enables all programs written for the previous versions of the microcontrollers to be used in this one too without being modified. This is why the 8051-based microcontrollers are so popular.
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0 - UART and SPI interrupt disabled. 1 - UART and SPI interrupts enabled.
ET1 bit enables or disables Timer T1 interrupt:
0 - Interrupt on the INT0 pin disabled. 1 - Interrupt on the INT0 pin enabled.
ET0 bit enables or disables Timer T0 interrupt:
0 - Interrupt on the INT1 pin disabled. 1 - Interrupt on the INT1 pin enabled. Interrupt Priorities
When several interrupts are enabled, it may happen that while one of them is in progress, another one is requested. In such situations, the microcontroller needs to know whether to proceed with the execution of current interrupt routine or to meet a new interrupt request. For this reason, there is a priority list on the basis of which the microcontroller knows what to do. The previous versions of the microcontrollers differentiate between two priority levels defined in the IP register. As for the AT89S8253 microcontroller, there is an additional SFR register IPH which enables all the interrupts to be assigned 1 out of 4 priorities (excluding reset). Here is a list of priorities:
1. Reset. If a reset request arrives, all processes are stopped and the microcontroller restarts. 2. The high priority interrupt (3) can be disabled by reset only. 3. The low priority interrupt (2, 1 or 0) can be disabled by any high priority interrupt and reset.
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It is usually defined at the beginning of the program which one of the existing interrupt sources have high and which one has low priority level. According to this, the following occurs:
If two interrupt requests, at different priority levels, arrive at the same time then the higher priority interrupt is always serviced first. If the both interrupt requests, at the same priority level, occur one after another, the one which came later has to wait until routine being in progress ends. If two interrupt requests of equal priority arrive at the same time then the interrupt to be serviced is selected according to the following priority list : 1. External interrupt INT0 2. Timer T0 interrupt 3. External interrupt INT1 4. Timer T1 interrupt 5. Serial communication interrupt 6. Timer T2 Interrupt IP register (Interrupt Priority Register)
Bits of this register determine the interrupt source priority. PT2 Timer T2 interrupt priority:
0 - Priority 0 1 - Priority 1
PS Serial port interrupt priority:
0 - Priority 0 1 - Priority 1
PT1 Timer T1 interrupt priority:
0 - Priority 0 1 - Priority 1
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0 - Priority 0 1 - Priority 1
PT0 Timer T0 interrupt priority:
0 - Priority 0 1 - Priority 1
PX0 External interrupt INT0 priority:
PT2H Timer T2 interrupt priority PSH Serial port interrupt priority PT1H Timer T1interrupt priority PX1H External interrupt INT1 priority PT0H Timer T0 interrupt priority PX0H External interrupt INT0 Priority Bits of this register can be combined with appropriate bits of the IP register. This is how a new priority list with 4 interrupt priority levels (5 including reset) is obtained.
I P BI T 0 0 1 I P H BI T 0 1 0 I NT ERRUP T S Priority 0 (lowest) Priority 1 (low) Priority 2 (high)
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Priority 3 (highest)
Processing interrupt
When an interrupt request arrives, the microcontroller automatically detects the interrupt source and the following occurs:
1. Instruction in progress is ended; 2. The address of the next instruction to execute is pushed onto the stack; 3. Depending on which interrupt is requested, one of five vectors (addresses) is written to the program counter according to the table below:
I NT ERRUP T S O URC E IE0 TF0 IE1 TF1 RI, TI, SPIF TF2, EXF2 All addresses are in hex format J UM P A DDRES S 3h Bh 13h 1Bh 23h 2Bh
Appropriate subroutines processing interrupts are stored at these addresses. Instead of them, there are usually jump instructions specifying locations at which these subroutines reside. 4. When an interrupt routine is executed, the address of the next instruction to be executed is popped from the stack to the program counter and the program proceeds from where it left off.
Timer T2
Timer 2 is a 16-bit timer/counter installed only in new versions of the 8051 family. Unlike timers T0 and T1, this timer consists of 4 registers. Two of them, TH2 and TL2, are connected serially in order to form a larger 16-bit timer register. Like timers 0 and 1, it can
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operate either as a timer or as an event counter. Another two registers, RCAP2H and RCAP2L, are also serially connected and operate as capture registers. They are used to temporarily store the contents of the counter register. The main adventage of this timer compared to timers 0 and 1 is that all read and swap operations are easily performed using one instruction. Similar to T0 and T1, it has four different modes of operation to be described later in this chapter.
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This register contains bits controlling the operation of timer 2. TF2 bit is automatically set on timer 2 overflow. In order to detect the next overflow, this bit must be cleared from within the program. If bits RCLK and TCLK are set, overflow has no effect on the TF2 bit. EXF2 bit is automatically set when a capture or a reload is caused by a negative transition on the T2EX pin. It generates an interrupt (if enabled), unless the DCEN bit of the T2CON register is set. The EXF2 bit must be cleared from within the program. RCLK is receive clock bit which determines which timer is to be used as receive clock for serial port:
1 - T2 is used as receive clock for serial port. 0 - T1 is used as receive clock for serial port.
TCLK is transmit clock bit which determines which timer is to be used as transmit clock for serial port:
1 - T2 is used as transmit clock for serial port. 0 - T1 is used as transmit clock for serial port.
EXEN2 is timer 2 external enable bit used to include the T2EX pin in timer 2 operation:
1 - Signal on the T2EX pin affects timer 2 operation. 0 - Signal on the T2EX pin is ignored.
TR2 is timer 2 run control bit used to enable/disable timer 2:
1 - 16-bit register (T2H and T2L) counts pulses on the C/T2 pin (counter). 0 - 16-bit register (T2H and T2L) counts pulses from the oscillator (timer).
CP/RL2 is timer 2 capture/reload bit used to define transfer direction:
1 - If EXEN=1, pulse on the T2EX pin will cause a number to be transferred from counter to capture register. 0 - Under the same condition, signal on the T2EX pin will cause a number to be transferred from capture to counter register. Timer T2 in Capture mode
If the CP/RL2 bit of the T2CON register is set, timer 2 operates according to the figure below. This is so called Capture mode in which the value of the counter register (consisting of RCAP2H and RCAP2L) can be captured and copied to the capture register (consisting of RCAP2H and RCAP2L), thus not affecting the counting process. This is how it operates:
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1. First, it is necessary to write a number from which the counting starts to a 16-bit register (TH2+TL2). 2. Timer 2 is enabled by setting the TR2 bit of the TCON register. Each coming pulse increments the number stored in the 16-bit register by 1. When both registers are loaded (decimal number 65536), the first next pulse causes an overflow, reset occurs and counting starts from zero.
Settings:
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T2OE - Enables timer 2 to operate as independent clock generator. DCEN - When set, it enables counting in either direction- "up" and "down".
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As seen in figure above, unlike Capture mode, the contents of the capture register (RCAP2H, RCAP2L) is now copied in the opposite direction upon an overflow occurs, from capture (RCAP2H, RCAP2L) to counter register (TH2, TL2). Settings of Auto Reload mode are shown in the table below:
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All previously mentioned about timer 2 is in force only if the T2MOD register hasn't been changed, i.e. if DCEN = 0. Otherwise, timer/counter is enabled to count in either direction, which depends on the T2EX pin: T2EX = 0 Timer 2 counts down T2EX = 1 Timer 2 counts up
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On counting up, the whole procedure is similar to the previous mode with one exception referring to the function of the EXF2 bit. On counting down, an overflow occurs when values stored in the counter and capture registers match. It causes the TF2 bit as well as all bits of registers T2H and T2L to be set while the counter keeps on counting down: 65535, 65534,65533... In either case, the EXF2 bit is assigned a new function. When an overflow occurs, this bit inverts the signal and cannot be used for generating an interrupt anymore. Instead, it serves as supplementary bit (the 17th bit) of the counter register, making this counter virtually a 17-bit register.
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1. This formula works only if the internal oscillator is used as a clock generator (in this mode, clock is divided by 2, instead of 12) 2. Overflow has no effect on the TF2 bit and does not generate an interrupt. 3. Whether the EXEN2 bit is set or not, the T2EX pin logic state has no effect on the timer. It means that the T2EX pin can be used as an external interrupt source in this mode. 4. Timer should be disabled (TR2=0) prior to writing or reading from registers TH2 and TL2. Otherwise, an error in serial communication might occur. Timer T2 as a clock generator
As previously mentioned, timer T2 can also be used as a clock generator. In all previous examples, the P1.0 pin (marked as T2 in figures) is used as an alternative clock generator for this timer, i.e. it acts as an input. Besides, it can also output pulses. By using a 16MHz quartz crystal, the frequency of pulses it generates ranges from 61Hz to 4MHz with a 50% duty-cycle. To configure this pin as an output, the C/T2 bit of the T2CON register must be cleared, whereas the T2OE bit of the T2MOD register must be set. The TR2 bit enables the timer and the pin outputs rectangular waves the frequency of which ca be calculated using the formula below:
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Multiprocessor Communication
Multiprocessor communication (the SM2 bit of the SCON register is set) enables automatic address recognition by allowing the serial port to examine the adress of each incoming command. The process of writing a program is much easier therefore as the microcontrollers sharing the same interface don't have to check each address received via the serial port. Let's make it clear. Two special function registers, SADDR and SADEN, enable multiprocessor communication. Each device has an individual address that is specified in the SADDR register, while the so called mask address is written to the SADEN register. The mask address contains don't care bits which provide the flexibility to address one or more slaves at a time. In other words, it defines which bits of the SADDR register are to be used and which are to be ignored.
When the master wants to transmit data to one of several slaves, it first sends out an address byte which identifies the target device. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. After receiving the address byte, all slaves check whether it matches their address. The adressed slave clears its SM2 bit and prepares to receive the data bytes to come. The slaves that weren't addressed leave their SM2 bits set and ignores the coming data bytes. The most simple example is a mini-network comprising only 3 microcontrollers: Microcontroller A is the master and communicates with devices B and C.
Microcontroller B: SADDR = 1100 0000 SADEN = 1111 1101 Address = 1100 00X0 Microcontroller C: SADDR = 1100 0000
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Although both microcontrollers B and C are assigned the same address (1100 0000), the mask in register SADEN is used to differentiate between them. It enables the master to communicate with both of them separately or at the same time: If transmit address is 1100 0010, the data will be sent to slave device B. If transmit address is 1100 0001 the data will be sent to slave device C. If transmit address is 1100 0000 the data will be sent to both slave devices.
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side it must have voltage level 0. When the SS pin on the slave side is set, its SPI system is deactivated and the MOSI pin can be used as a general-purpose input.
As shown on the schematic, pins MISO and MOSI are configured differently in the master and slave device (as inputs or outputs), which is determined by the MSTR bit of the SPCR register. Knowing abbraviations makes connection easier: MISO - master in, slave out; MOSI - master out, slave in; SCK - serial clock; SS - slave select; Similar to many other circuits within the microcontroller, the SPI system can also be configured to operate in several modes.
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Data written to the SPI data register SPDR is automatically transferred to an 8- bit shift register. SPI clock generator is enabled and serial data appears on the MOSI pin. An initial delay may occur for the sake of synchronization with the main oscillator.
After sending one byte, the SPI clock generator stops, the SPIF bit (flag) is set, the received byte is transferred to the SPDR register and, if enabled, an interrupt is generated. Any attempt to write another byte to the SPDR register while byte transmit is in progress will cause the WCOL bit to be set. It indicates that an error has occured. However, the byte will be succesfully transmitted, while the new byte will be ignored, i.e. it will not be transmitted.
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While one byte transmit is in progress, the next byte to transmit may be written to the SPDR register. It will be immediately moved to buffer. In order to check whether data transmit is in progress, it is sufficient to check the logic state of the LDEN bit of the SPSR register. If this bit is set (Load Enable) and the WCOL bit is cleared, data transmit is in progress and buffer is empty so the next byte can be written to the SPDR register. How to select the right mode? If individual bytes are sent occasionally then there is no need to complicate- the best solution is the normal mode. If it is necessary to send a great amounts of data, it is better to use enhanced mode in which the clock oscillator is enabled as far as buffer is regularly loaded and the WCOL bit is set. In addition, no time is needed for synchronization and data is easily and efficiently transferred. The SPI system is under control of 3 special function registers. These are SPDR, SPSR and SPCR.
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SPIF Interrupt flag. Upon data transfer, this bit is automatically set and an interrupt is generated if SPIE=1 and ES=1. The SPIF bit is cleared by reading SPSR followed by reading/writing SPDR register. WCOL This bit is set in normal mode (ENH=0) if the SPDR register is written during data transfer is in progress. The write is premature and has no effect. It is called Write Collision. This bit is cleared in the same manner as the SPIF bit. The bit is set in enhanced mode (ENH=1) when buffer is full. It is indication that a new data is ready to be transmitted to the shift register. In enhanced mode, a new data can be written to buffer when the WCOL bit is set. In addition, the WCOL bit must be cleared. DISSO When set, this bit causes the MISO pin to float, thus enabling several slave microcontrollers to share the same interface. Normally, the first byte, called address byte, is received by all of them, but only one should clear its DISSO bit. ENH 0 SPI system operates in normal mode (without buffer). 1 SPI system operates in enhanced mode.
SPIE When this bit is set, the SPI system can generate an interrupt. SPE This bit enables SPI communication. When set, pins SS, MOSI, MISO and SCK are connected to the microcontroller pins P1.4, P1.5, P1.6 and P1.7. DORD Bit determines which bytes in serial communication are to be sent first:
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* not defined. It is usually MSB of previously received byte. Serial data format if CPHA=1
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* not defined. It is usually LSB of previously received byte. Two things are important to remember when configuring SPI system:
Master should be configured before slave. When writing bits to the SPCR register, the SPE bit enabling SPI should be set last, i.e. after setting all other parameters.
PCON register
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SMOD1 When set, this bit makes boud rate twice as high. SMOD0 Bit determines the purpose of the 7th bit of the SCON register:
0 Seventh bit of the SCON register has the function of SM0, i.e. selects mode of operation. 1 Seventh bit has the function of FE, i.e. detects errors. It is rarely used.
POF Bit is automatically set when the voltage level reaches maximum (must be higher than 3V) after powering on. It is used for detecting cause for reset (power on or restart condition after exiting Power Down mode). GF1 General purpose bit (available for use). GF0 General purpose bit (available for use). PD By setting this bit, the microcontroller is set in Power Down mode. IDL By setting this bit, the microcontroller is set in Idle mode.
If we neglect this detail, there is a risk that the program suddenly starts to perform unpredictably. In order to prevent it, it is necessary to take care of the following: If only registers R0-R7 from bank 0 are in use, everything is easily kept under control and program memory locations from 08h to 1Fh are available for use. If registers, otherwise having the same names, from some other bank are in use, you should be careful when using locations whose addresses are less than 20h because it can cause R registers to be erased. If bit-variables are not used in the program, program memory locations 20h-2Fh are available for use. If the program contains bit-variables, you should be careful when using these location in order not to change them accidentaly.
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By default, the data pushed onto stack occupy program memory locations starting from 08h. If the banks 1, 2 or 3 are in use, their contents will be certainly erased. For this reason, it is recommended to set the Stack Pointer value to be greater than 20h or even greater at the beginning of the program. SFRs are used for controlling the microcontroller operation. Each of them has its specific purpose and it should be observed. It means that they cannot be used as general purpose registers even in the event that some of their locations is not occupied. Instruction set, recognized by the microcontroller, contains instructions which can be used for controlling individual bits of registers at program memory location 20h-7Fh. Besides, individual bits of some SFRs (not all of them) can also be directly accessed. Addresses of these registers are divisible by 8. If memory is expanded by adding external RAM or ROM memory chip, ports P0 and P2 are not available for use regardless of how many pins are actually used for memory expansion. The DPTR register is a 16-bit register comprised of registers DPH and DPL which are 8-bit wide each. The DPTR register should be considered like that practically. For example, when pushing it onto the Stack, DPL should be pushed first, then DPH. When used, serial communication is under control of the SCON register. Besides, registers TCON and TMOD should be configured for this purpose as well since the timer T1 is mostly used for boud rate generation. When some of the interrupts is enabled, you should be careful because there is a risk that program starts to perform unexpectedly. When an interrupt request arrives, the microcontroller will execute instruction in progress, push the address of the first following location onto the stack (in order to know from where to continue) and jump to the specified interrupt routine address. When the routine has been executed, the microcontroller will pop the address from the stack and continue from where it left off. However... The microcontroller saves only the address to continue from after routine execution. What is usually neglected is the fact that the contents of many registers can be changed during routine execution. The program normally procedees with execution considering the changed registers correct if their original vaules haven't been saved, thus causing a total chaos. The worst thing is that this problem can be manifested anytime: at the moment or several days later (depending on the moment an interrupt occurs). Obviously, the only solution is to save the state of all important registers at the beginning of interrupt routine and to update these values before returning to the program. We are actually talking about the following registers:
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When some of the instructions for indirect addressing is used, you should be careful not to use them for accessing SFRs as the microcontroller ignores their addresses and accesses free RAM locations having the same addresses as SFRs. When UART system for serial communication is used, setting bits RI and TI of the SCON register generated the same interrupt. If such an interrupt is generated, it is first necessary to detect interrupt source (byte is sent, received or both). It is important to remember that the microcontroller only sets these bits so that they must be cleared from within the program. Otherwise, the program gets stuck and executes the same interrupt routine over and over again.
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P0
87
86
85
84
83
82
81
80
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Bit address
8F
8E
8D
8C
8B
8A
89
88
A UX R
C L KREG
DP 0 H
DP 0 L
DP 1 H
DP 1 L
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EEC O N
IPH
PC ON
S A DDR
S A DEN
S BUF
SP
SPCR
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S P DR
SPSR
RC A P 2 H
RC A P 2 L
TL0
TL1
TL2
T H0
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T H1
T H2
T M OD
T 2 M OD
W DT C O N
W DT C O N
VIL1
VIH
Input High-voltage
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VIH1
Input High-voltage on pins XTAL1 and RST Iol = 10mA, Vcc = 4.0V, Ta = 85C Ioh = -40mA, Ta = 85C Ioh = -25mA, Ta = 85C Ioh = -10mA, Ta = 85C Vin = 0.45V, Vcc = 5.5V, Ta = -40C 0.45V < Vin < Vcc
0.7 Vcc
VOL
Output High-voltage
VOH1
Output High-voltage when Pull-up resistors are enabled (Port P0 in External BUS mode, ports P1,2,3, pins ALE and PSEN)
IIL
Input leakage current (port P0, pin EA) Reset pull-down resistor I/O pin C apacitance
f = 1Mhz, Ta = 25C Normal mode: f = 12Mhz, Vcc = 5.5V Ta = -40C Idlle mode f = 12Mhz, Vcc = 5.5V Ta = -40C Vcc = 5.5V Ta = -40C Vcc = 4V Ta = -40C
25 mA 6.5 mA
100 A 40 A
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