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REF RC 2 SLEEP OUT2B LOAD SUPPLY 2 GND GND SENSE2 OUT2A STEP DIR MS1
1 2 3 4 5 6 7 8 9 10 11 12 VBB2
PWM TIMER
24
PFD
23 RC 1 22 RESET 21 OUT1B VBB1 LOAD 20 SUPPLY 1 19 18 17 16 TRANSLATOR & CONTROL LOGIC GND GND SENSE1 OUT1A
Dwg. PP-075-2
FEATURES
750 mA, 30 V Output Rating Satlington Sink Drivers Automatic Current-Decay Mode Detection/Selection 3.0 V to 5.5 V Logic Supply Voltage Range Mixed, Fast, and Slow Current-Decay Modes Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection
Part Number A3967SLB-T A3967SLBTR-T Pb-free* Yes Yes Package 24-Lead SOIC 24-Lead SOIC Packing 31 per tube 1000 per reel
* Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classification indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadline for receipt fo LAST TIME BUY orders: April 27, 2007. These variants include: A3967SLB and A3967SLBTR.
DAC + -
SENSE
RC1
23
PWM LATCH BLANKING MIXED DECAY
OUT1A
16
OUT1B
21
3 STEP 10
PWM TIMER
TRANSLATOR
SENSE1
CONTROL LOGIC
17
VBB2
SLEEP
ENABLE 15 VPF
24
PFD
2
OUT2B
4
RC2 + DAC
6 7 18 19
SENSE2
Dwg. FP-050-3A
Table 1. Microstep Resolution Truth Table MS1 L H L H MS2 L L H H Resolution Full step (2 phase) Half step Quarter step Eighth step
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright 2002, 2003 Allegro MicroSystems, Inc.
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ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 30 V, VCC = 3.0 V to 5.5V (unless otherwise noted)
Limits Characteristic Control Logic (contd) Mixed Decay Trip Point Ref. Input Voltage Range Reference Input Impedance Gain (Gm) Error (note 3) Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current TJ TJ VUVLO VUVLO ICC Outputs enabled Outputs off Sleep mode Increasing VCC PFDH PFDL VREF ZREF EG VREF = 2 V, Phase Current = 38.37% VREF = 2 V, Phase Current = 70.71% VREF = 2 V, Phase Current = 100.00% Operating 1.0 120 2.45 0.05 0.6VCC 0.21VCC 160 165 15 2.7 0.10 50 VCC 200 10 5.0 5.0 2.95 65 9.0 20 V V V k % % % C C V V mA mA A Symbol Test Conditions Min. Typ. Max. Units
* Operation at a step frequency greater than the specied minimum value is possible but not warranteed. 8 microstep/step operation. NOTES: 1. Typical Data is for design information only. 2. Negative current is dened as coming out of (sourcing) the specied device terminal. 3. EG = ([VREF/8] VSENSE)/(VREF/8)
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
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1.0
200
300
400
500
600
700
Dwg. GP-064-1A
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
Timing Requirements
(TA = +25C, VCC = 5 V, Logic Levels are VCC and Ground)
STEP
50%
C A B
MS1/MS2/ DIR/RESET
SLEEP
Dwg. WP-042
A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time) ..... 200 ns B. Minimum Command Active Time After Step Pulse (Data Hold Time) ............ 200 ns C. Minimum STEP Pulse Width ...................... 1.0 s D. Minimum STEP Low Time ......................... 1.0 s E. Maximum Wake-Up Time ......................... 1.0 ms
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*RJA = 35C/W on JEDEC standard High-K four-layer board per JESD 51-7. RJA = 50C/W on typical two-sided PCB with 1.3 square inches copper ground on each side. See also, Application Note 29501.5, Improving Batwing Power Dissipation.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
SLOW DECAY
70.7%
PHASE 1 CURRENT
70.7%
SLOW DECAY
70.7%
PHASE 2 CURRENT
70.7%
Dwg. WK-004-19
10
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
100% 70.7%
PHASE 1 CURRENT
70.7% 100%
SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY
100% 70.7%
PHASE 2 CURRENT
70.7% 100%
Dwg. WK-004-18
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay is between these two levels.
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11
SLOW DECAY
MIXED DECAY
SLOW DECAY
MIXED DECAY
MIXED DECAY
SLOW DECAY
MIXED DECAY
SLOW DECAY
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay is between these two levels.
12
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
SLOW DECAY
MIXED DECAY
SLOW DECAY
MIXED DECAY
MIXED DECAY
SLOW DECAY
MIXED DECAY
SLOW DECAY
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay is between these two levels.
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13
Terminal List Terminal Name REF RC2 SLEEP OUT2B LOAD SUPPLY2 GND SENSE2 OUT2A STEP DIR MS1 MS2 LOGIC SUPPLY ENABLE OUT1A SENSE1 GND LOAD SUPPLY1 OUT1B RESET RC1 PFD Terminal Number 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18, 19 20 21 22 23 24
Terminal Description Gm reference input Analog input for fixed offtime bridge 2 Logic input H bridge 2 output B VBB2, the load supply for bridge 2 Analog and power ground Sense resistor for bridge 2 H bridge 2 output A Logic input Logic Input Logic input Logic input VCC, the logic supply voltage Logic input H bridge 1 output A Sense resistor for bridge 1 Analog and power ground VBB1, the load supply for bridge 1 H bridge 1 output B Logic input Analog Input for fixed offtime bridge 1 Mixed decay setting
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
24
13
0.0125 0.0091
0.2992 0.2914
0.020 0.013
0.6141 0.5985
0.050
BSC NOTE 1 NOTE 3
0 TO 8
24
0.32 0.23
7.60 7.40
0.51 0.33
15.60 15.20
1.27
BSC NOTE 1 NOTE 3
0 TO 8
NOTES: 1. 2. 3. 4.
Exact body and lead configuration at vendors option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Supplied in standard sticks/tubes of 31 devices or add TR to part number for tape and reel.
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15
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Satlington is a registered trademark of Allegro MicroSystems, Inc. (Allegro), and Satlington devices are manufactured under U. S. Patent No. 5,684,427. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000