IMTC 2005 Instrumentation and Measurement Technology Conference Ottawa, Canada, 17-19 May 2005

Switched Capacitor Signal Conditioning for Push-Pull Type Capacitive Sensors

Boby George and V. Jagadeesh Kumar
Dept. of Electrical Engineering, IIT Madras, Chennai-600 036, India Phone: +91-44-22578419, Fax: +91-44-22578360, Email: vjkumar@ee.iitm.ac.in

Abstract A novel switched capacitor signal conditioning circuit is developed for differential capacitive sensors. The main advantage of the proffered m ethod lies in the fact that it accepts sensors possessing either linear or inverse characteristics and provides a linear output. Moreover, the output is dependent only on a pair of DC reference voltages and the transformation constant of the sensor. Hence increased linearity and accuracy is easily achieved by employing precision DC reference voltages. Results from the tests on a prototype elucidate the practicality of the proposed method. Keywords capacitive sensors, switched capacitor circuits, nonlinearity, signal conditioning.

differential capacitive sensors utilizing different circuit configurations have been proposed [1 - 5]. We now present a novel signal conditioning circuit using a switched capacitor integrator circuit. The main advantage of the present method lies in the fact that it can be used with sensors possessing either linear or inverse characteristics. In both cases, the output turns out to be linear. Since the sensitivity of the method is dependent only on a pair of DC reference voltages and the transformation constant, increased linearity and accuracy can be easily achieved by employing precision DC reference voltages. II. SWITCHED CAPACITOR SIGNAL CONDITIONING CIRCUIT The functional block schematic of the proposed signal conditioner is shown in Fig. 2. Switches S1, S2, S3, S4 and S5 are all single pole two way analog switches. Switches S1 and S2 are controlled by a high frequency clock having 50 % duty cycle and switch the capacitances C1 and C2 of the sensor between charge and discharge positions. Switches S3 and S4 are ganged and connected such that only one of the capacitors (C1 or C2) charge the feedback capacitance C at a given time. The circuit is essentially a relaxation oscillator with opamp OA working as a switched capacitor integrator, while switch S5 in conjunction with comparator OC provide necessary hysterisis and positive feedback required for oscillation. Let us assume that initially the integrator output is positive and increasing. The comparator output is high and for this condition, switches S3, S4 and S5 will be at position 1. In this condition, the charge in the capacitor C2 is transferred to the integrator capacitor C at the rate determined by the clock while the charge in C1 is discharged to ground. This condition prevails until the integrator voltage voi reaches +VR. As soon as voi becomes equal to +VR the comparator output will toggle. For this condition, switches S3, S4 and S5 will be at position 2. In this condition, the charge in the capacitor C1 is transferred to the integrator capacitor C and that in C2 is discharged to ground. The outputs of the integrator and the comparator are shown in Fig. 3. Since C1 is switched to +VR, the charge transferred from C1 will charge C in the opposite direction to that of C2 and hence the integrator capacitor voltage voi will decrease. This condition prevails until voi reaches -VR. As soon as voi becomes -VR, the comparator output will toggle again and switches S3, S4 and S5 will go back to position 1. Now the circuit will operate as explained in the first condition thus leading to sustained oscillation. During period TON and TOFF the integrator output will step

I. INTRODUCTION Differential capacitive sensors are widely used in the industry to measure various parameters such as pressure, displacement and force. The equivalent circuit of a typical differential capacitive sensor is shown in Fig. 1.

P C1 Q C2

Fig. 1. Equivalent circuit of a differential capacitive sensor

The variations in capacitances C1 and C2 are normally equal and opposite. Differential capacitive sensors, where the parameter that changes with respect to the physical quantity being sensed is either the area between the capacitor plates or the dielectric constant will possess a linear characteristic as given in equation (1).
C1 = C0 (1 kx) and C 2 = C0 (1 kx)

(1)

On the other hand, sensors utilizing the distance between the plates as transduction parameter will posses an inverse relationship as given in equation (2).
C1 = C0 1 1 and C2 = C0 (1 kx) (1 kx)

(2)

Here C0 is the nominal value of the sensor capacitances C1 and C2, k the transformation constant of the sensor and x is the physical quantity being sensed. Signal conditioning of

0-7803-8879-8/05/$20.00 2005 IEEE

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C2 C and VR 1 respectively. C C As shown in Fig. 3, the integrator output voltage voi ramps from VR to +VR and +VR to VR during TON and TOFF respectively. Hence,
through with a slope of VR
2C T and T ON = C H 2 2C T T OFF = C H 1

given in equation (2). Thus the output from the signal conditioning circuit is linear with respect to the change in the measurand even if the capacitance variation possesses an inverse characteristic. The effect of various circuit parameters on the sensitivity of the output is discussed next.
A. Effect of integrator capacitance C

(3)

where TH is the time period of the high frequency clock.

1 2

2
S3 C1

Integrator capacitor (C) plays a vital role as it influences the frequency of oscillation. The step change in the integrator output VON = VR
C2 C

C voi

during TON and VOFF = VR

C1 C

+VR

S2

during TOFF. VON=VOFF only when C1 equals C2.

OA
C2

OC
S5

-VR

S1 1 2

S4 2 +VR 1

-VR

CLOCK

L P
F

VO
Fig. 4. Voltage waveforms at the output of the integrator

Fig. 2. The functional block diagram of the proposed circuit.

+VR

voi

TON

TOFF

-VR
TH

C for TON may not C2 always be an integer. In such a case, integrator voltage voi will go beyond +VR as shown by the dotted lines in Fig. 4, and at the maximum it can reach (VR + VON). Thus, ON period becomes TON 1 = TON + TH . During TOFF, integrator will
The requisite number of clocks n ON = 2

Fig. 3. The voltage waveforms at the output of the integrator and input to the low pass filter.

take an additional time TA = C 2 TH to discharge VON. If,

either the ratio VON to VOFF or number of clocks for OFF period
n OFF = 2 C C1

C1

If we assume the cut off frequency of the low pass filter to be very low compared to the frequency of oscillations f [f=1/T, T = (TON + TOFF)] then its output can be expressed as
TON T 1 V0 = VR dt + VR dt T 0 T ON

is

fractional,

the

OFF

period

becomes TOFF 1 = TOFF + TA + TH . The ensuing error c in the output of the circuit is obtained as 2C1C2 C1 C = 100 % (C2 C1 ) 2CC2 + 2CC1 + C12 + 2C1C2 The presence of C in the denominator gives freedom for the
designer to reduce the error. For C = 10 5 the worst case
C0

TON TOFF V TON + TOFF R

(4)

By substituting for TON and TOFF in terms of C1, C2 and C as in equation (3), we will get: C C2 V0 = 1 V (5) C 2 + C1 R Substitution of equation (1) or (2) in equation (5) gives V0 = VR kx (6) The output of the low pass filter is linearly proportional to x and the proportionality constants are the reference voltage VR and the transformation constant k. The significance of the present method lies in the fact that equation (6) is valid even if the capacitive sensor possesses an inverse relationship as

error is found to be 0.01%.

B. Effect of reference voltages

Let the reference voltages +VR and -VR have errors of x% and y% respectively. Due to these errors TON and TOFF will deviate from ideal as illustrated in Fig. 5.

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Worst-case error will occur if x% and y% are either positive maximum or negative maximum. The waveform represented by the dotted line in Fig. 5 is the integrator output when x% and y% are at negative maximum. In this case, the ON and OFF durations will deviate from the true value.
(+VR + x%) +VR (+VR - x%)

( RON r ) =

(C1 C 2 )(C1 + C 2 C1e C 2 e )

2C1C 2 (e e )

100 %

where, =

TH = 2(R r)C . For a typical ON CMOS switch CD4053 with RON = 400 , r = 15 , C = 0.01 F and TH = 100 sec the worst-case error is found to be 0.01%.
TH and 2(R r)C ON

(-VR + y%) -VR (-VR - y%) T ON TON1 T OFF TOFF 1

D. Effect of Comparator Delay

Fig. 5. Voltage waveforms at the output of the integrator with the error in the reference voltages are accounted.

The resulting error in the output V R can be expressed as

V =
R

2C1C 2 x% + y% 100 % (C1 C 2 ) 100(C 1 + C 2 ) x% + y%

An ideal comparator that changes its state instantaneously is assumed while explaining the operation of the signal conditioning circuit. However, a practical comparator will take a delay time of seconds to change its state. The integrator output waveform incorporating a practical comparator with delay is shown by the dotted waveform in Fig. 7.

+VR

voi( 0 )

C. Effect of switch resistance

voi ( = 0 )
-VR

The ingrained ON resistances offered by S1, S2, S3 and S4 will introduce time constants on charging and discharging.
+VR

TON TON1

TOFF TOFF1

Fig. 7. Integrator output voltage in the presence of comparator delay,

-VR

TON1

T OFF 1

Fig. 6. The integrator voltage voi with the switch resistance bear in mind

Since C1 and C2 are normally small valued capacitances, the effect of ON resistances of S1 and S2 on the operation of the circuit is negligible. However ON resistances of S3 and S4 introduce exponential charge building as illustrated in Fig. 6. Assuming the ON resistance of S3 and S4 to be RON, the slope of the integrator output during ON period becomes TH and the slope during OFF period V 1 exp
ON

In this case, during LOW state of the comparator, the integrator output voltage voi will go beyond -VR. The additional voltage acquired by C for the time of has to be discharged during the HIGH state period of the comparator. Time taken ON to discharge this extra voltage C is ON = 2 TH . The comparator will again take seconds C 1 to change its state from HIGH to LOW. Thus, the new ON period is TON1 = TON + + ON . Similarly, the new OFF period

is TOFF1 = TOFF + + OFF ,

2R C ON

C where OFF = 1 . The error C 2 introduced in the output due to the delay in the comparator, is
= TH C1 + C 2 C 100 % .

is V

OFF 1 exp

ON resistance is (RON r) during TON and (RON r) during TOFF or vice versa. The influence of this unequal ON resistances can be accounted for by replacing the RON by (RON r) during TON and (RON r) during TOFF in the above discussion. For this condition, expression for percentage relative error in the output ( RON r ) can be derived as

TH . 2R ON C

The worst case error occurs if the

E. Effect of Opamp Bias Current

The input bias current - iB of the opamp will charge the integrator capacitor C in the same direction throughout the

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cycle. For each clock, the capacitor C will get a charge equal to ( i B TH ) Coulomb. However, by choosing the charging current to be several orders of magnitude higher than the bias current, the effect can be made negligible.
F. Effect of Stray Capacitances

waveforms are observed on an Agilent 54624A oscilloscope. The output is found to be linear for the entire range of 50% tested. The percentage error is computed for each reading and is plotted in Fig. 9. Worst-case error is found to be 0.03%. These results show the effectiveness of the proposed method.
0.03
0.02
0.01
% Error

Fig. 8 demonstrates the differential capacitive sensor C1 and C2 with all possible parasitic capacitances. CP0, CQ0 and CR0 are the capacitances between ground and nodes P, Q and R respectively. CPQ, CQR and CPR are the parasitic capacitances between P and Q, Q and R and P and R respectively.

0
-0.01

C PR

C P0

CQ 0

C R0

C1
C PQ
Q

C2
CQ R

-0.02
-0.03 -60

R
-40

-20

% kx

20

40

60

Fig. 8. Sensor capacitances C1 and C2 with all possible stray capacitances and cable capacitances

Fig. 9. Actual error obtained with the prototype circuit

The node Q is always connected to ground, thus the charging current through CQ0 is zero. The capacitances CPQ and CQR come in parallel with CP0 and CR0 respectively. Let the parallel combination of CPQ and CP0 be CP and that of CQR and CR0 be CR. The output of the signal conditioning circuit is derived for this condition as
C1 C 2 C P C R Vo = + C1 + C 2 + C s C1 + C 2 + C s

IV. CONCLUSION A high accuracy switched capacitor signal conditioning circuit is developed for differential capacitive sensors. The proposed method accepts sensors possessing linear as well as inverse characteristics and provides a linear output. Since the sensitivity of the circuit is determined only by a pair of DC excitation voltages, increased linearity and accuracy is easily achieved by employing precision DC reference voltages. Detailed analysis indicates that the errors introduced due to other circuit parameters are minimal. Tests on a prototype indicated that the worst-case error was less than 0.03%. Since the signal being processed by the low pass filter is a two level discrete one, it can be easily interfaced to a digital circuit and a digital output obtained. REFERENCES
[1] Mochizuki K., Watanabe K., Masuda T. and Katsura M., A Relaxation Oscillator-Based Interface for High-Accuracy Ratiometric Signal Processing of Differential Capacitance Transducers, IEEE Trans. on Instrum. Meas., Vol.IM-47, No. 1, Feb. 1998, pp 11-15. Mochizuki K., Masuda T. and Watanabe K., An interface circuit for highaccuracy signal processing of differential capacitance transducers, Proc. Instrum. Meas. Tech. Conf., 1996, pp 1200-1203. Matsumoto H., Shimizu H. and Watanabe K., A switched-capacitor charge-balancing analog to digital converter and its application to capacitance measurement, IEEE Trans. on Instrum. Meas., Vol. IM-36, No. 4, Dec. 1987, pp 873-878. Wang B., Kajita T., Sun T. and Temes G.C., High Accuracy Circuits for On-Chip Capacitance Ratio Testing and Sensor Readout, IEEE Trans. on Instrum. Meas., Vol. IM-47, No. 1, Feb. 1998, pp 16-20. Cao Y. and Temes G.C., High Accuracy Circuits for On-Chip Capacitance Ratio or Sensor Readout, IEEE Trans. Circuits Syst. II , Vol. 41, No. 9, Sep.1994, pp 637-639.

where C s = C P + C R 4C PR . This leads to an error in the

gain and introduces an offset in the output. III. EXPERIMENTAL SET-UP AND RESULTS The proposed scheme was implemented using commercially available ICs and tested. CD4053 CMOS switches were used for switches S1, S2, S3, S4 and S5. LF357 served as a comparator. The opamp is OP07. The reference voltages were obtained using reference diode LM385-2.5 and an opamp inverter. The clock frequency for the prototype was chosen to be 10 kHz. The output voltage is filtered with a Butterworth filter of order 2 and cut off 1 Hz. Two precision, variable capacitance boxes with an accuracy of 0.01 %, from F&G Neptun, Germany were used to simulate the differential capacitive sensor. The range of the capacitance box is 100-1100 pF, variable in steps of 10pF. The nominal values of the capacitances C1 and C2 were chosen to be 500 pF and the capacitances were varied over 250 pF. The output of the signal conditioning circuit was measured with a HP34401A 6-1/2-digit multimeter. The

[2] [3]

[4] [5]

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