IMPLEMENTATION OF MAC UNIT USING FPGA

AIM: To implement MAC unit using FPGA. SOFTWARE REQUIRED: Xilinx TOOLS REQUIRED: FPGA kit ALGORITHM: Step 1: Start the program. Step 2: Declare the input variables. Step 3: When x1=1 arithmetic operation. Step 4: When x1=0 logical operation. Step 5: Example:When x1=1,s1=1,s2=1 and s3=1 it gives invalidOutput using conditional operator.Step 6: Example:When x1=0,s1=1,s2=1 and s3=0 it gives 2sCompliment Output using conditional operator.Similarly for Everyother input values. Step 7: Stop the program. THEORY: In the majority of digital signal processing (DSP) applications thecritical operations usually involve many multiplications and/or accumulations. For real-time signal processing, a high speed and highthroughput Multiplier Accumulator (MAC) is always a key to achieve a high performance digital signal processing system. Inthe last few years, the main consideration of MAC design is to enhance

its speed. This is because; speedand throughput rate is always the concern of digital signal processingsystem. But for the epoch of personal communication, low power designalso becomes another main design consideration. This is because; batteryenergy available for these portable products limits the power consumption of the system. Therefore, the main motivation of this work is to investigatevarious VLSI Design and Implementation ofLow Power MAC Unit withBlock Enabling Technique. PROGRAM: module MAC(clk,rst,a,b,z); input clk,rst; input[2:0] a,b; output z; wire[5:0] w; multiplier U1(.a(a),.b(b),.p(w)); pipo U2(.RIN(w),.clk(clk),.rst(rst),.ROUT(z)); endmodule module multiplier(a,b,p); input[2:0] a,b; output[5:0] p;

wire[7:0] u; wire[1:0] su; wire[8:0]i; and(p[0],a[0],b[0]); and(u[0],a[1],b[0]); and(u[1],a[2],b[0]); and(u[2],a[0],b[1]); and(u[3],a[1],b[1]); and(u[4],a[2],b[1]); and(u[5],a[0],b[2]); and(u[6],a[1],b[2]); and(u[7],a[2],b[2]); hadd h1(.l(u[0]),.m(u[2]),.sum(p[1]),.cry(i[0])); hadd h2(.l(i[0]),.m(u[1]),.sum(su[0]),.cry(i[1])); hadd h3(.l(u[3]),.m(u[5]),.sum(su[1]),.cry(i[2])); hadd h4(.l(su[0]),.m(su[1]),.sum(p[2]),.cry(i[6])); hadd h5(.l(i[1]),.m(i[2]),.sum(i[5]),.cry(i[6])); or(i[7],i[5],i[4]); fadd f3(.d(i[7]),.e(u[4]),.cin(u[6]),.s(p[3]),.cout(i[8])); fadd f4(.d(i[8]),.e(i[6]),.cin(u[7]),.s(p[4]),.cout(p[5])); endmodule module pipo(RIN,clk,rst,ROUT); input[5:0] RIN; input clk,rst;output[5:0] ROUT; reg[5:0]ROUT; always @(posedge clk or negedge rst) begin if(!rst) begin ROUT<=6'b000000; end else begin ROUT<=RIN; end end endmodule module fadd(s,cout,d,e,cin); input d,e,cin; output s,cout; assign s=(d^e^cin); assign cout=((d&e)|(e&cin)|(d&cin)); endmodule module hadd(sum,cry,l,m); input l,m; output sum,cry;

wire sum,cry; assign sum=(l^m); assign cry=(l&m); endmodule RESULT: Thus the MAC unit was implemented using FPGA

DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING FPGA AIM: To implement a combinational circuits using FPGA. SOFTWARES REQUIRED: Xilinx. Modelsim.

TOOLS REQUIRED: FPGA kit. ALGORITHM: HALF ADDER: Step 1: Start the program. Step 2: Declare the input ports a, b. Step 3: Declare output ports s, c. Step 4:Begin the process using behavioral architecture. Step 5:.Assign s=ab. Step 6: Assign c=a.b. Step 7: End the process. FULL ADDER: Step 1: Start the program. Step 2: Declare the input ports a, b, cin. Step 3: Declare the output ports s, cy. Step 4: Begin the process using behavioral architecture. Step 5: assign s and cy value. Step 6: end the process. PROGRAM: HALF ADDER: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ha is Port ( a,b: in STD_LOGIC; s,c: out STD_LOGIC); end ha; architecture Behavioral of ha is begin s<=a XOR b; c<=a AND b; end Behavioral;

FULL ADDER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full is Port ( a,b,cin : in STD_LOGIC; s,cy : out STD_LOGIC); end full; architecture Behavioral of full is begin s<=a xor b xor cin; cy<=(a and b)or(b and cin)or(cin and a); end Behavioral; RESULT: Thus the combinational circuit was designed and implementedusing FPGA and its truth table was verified.

DESIGN AND IMPLEMENTATION OF ALU USING FPGA AIM To implement ALU using FPGA. SOFTWAREREQUIRED: ALGORITHM: Step 1: Start the program. Step 2: Declare the input variables. Step 3: When x1=1 arithmetic operation. Step 4: When x1=0 logicaloperation. Step 5: Example:When x1=1,s1=1,s2=1 and s3=1 it gives invalidOutput using conditional operator. Step 6: Example:When x1=0,s1=1,s2=1 and s3=0 it gives 2sCompliment Output using conditional operator. Similarly for Everyother input values. Step 7: Stopthe program. Xilinx. Modelsim.

PROGRAM: module a1(a,b,s1,s2,s3,x1,out); input[3:0]a,b; input s1,s2,s3,x1; output out; wire [7:0] out; wire [7:0] arith,log; wire [4:0] sum,diff;wire [7:0] prod,,squ; wire [3:0] comp1,comp2; wire [3:0] and1,or1; wire [3:0] sr1,sl1,not1,invalid; assign sum=a+b; assign diff=a-b; assign prod=a*b; assign squ=a^b; assign comp 1=~a; assign comp 2=~a+8b00000001; assign invalid=8b00000000; assign and 1=a&b; assign sr 1=a<<2; assign or 1=a | b; assign not 1=~a; assign sl 1=a>>2; assign out=x1?arith:log; assign arith =s1?(s2?(s3? invalid:comp 2):(s3? comp1:squ)):

(s2?(s3? invalid:prod)(s3? diff:sum)); assign log=s1?(s2? invalid:invalid):(s3? invalid:sl1)): (s2? invalid:sl1)):(s2?(s3? sr1:not)(s3? or1:and 1)); end module RESULT: Thus the ALU was designed and implemented using FPGA and its output was verified.