NANYANG TECHNOLOGICAL UNIVERSITY SCHOOL OF ELECTRICAL & ELECTRONIC ENGINEERING

EE2072 LABORATORY 2B Academic Year 2012/2013

Laboratory Manual

Module L221

Logic Circuit Simulation

Electronics Laboratory I S1-B3c-28

Name : Group : Date :

Revised: May 2012

Revised by: A/P Jong Ching Chuen

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Logic Circuit Simulation

1. Introduction Advance in technology has allowed highly complex digital electronic circuits to be designed. Circuits contain thousands and millions of logic gates are quite common. One of the challenges in designing these complex circuits is the verification of their functionality. In other words, the designers have to ensure that the circuits perform the intended functions. Logic simulation is one way to verify the functionality of digital circuits and is usually performed before the circuits are implemented in hardware. Logic simulation is the analysis of the functionality of a circuit at the logic gate level. Logic simulation is performed by using a software program called Logic Simulator. The simulator takes in a logic circuit in terms of a netlist or a schematic of logic gates and a set of values for the inputs of the circuit. It generates the evaluated results for the outputs of the circuit. In a logic simulator, a logic gate is treated as a black box modelled by a function whose variables are the input signals. The model does not contain any electrical information such as voltage and current. In the simulation, input signals are specified with some logic values such as 1, 0, unknown, or high impedance. The simulator will perform evaluation on the logic circuit and work out the logic values for the outputs. Both the inputs and outputs can be in either text format or graphical format in terms of waveforms. Combinational logic circuits are the circuits whose outputs depend on only the combinations of the current inputs. As for sequential circuits, their outputs at any time depend not only on the current inputs but also on the past sequence of the inputs that have been applied to the inputs. In other words, a sequential circuit has memory of past events.

2.

Objectives In this experiment, several logic circuits are to be simulated using a logic simulator from a company called Altera. The simulator is integrated in a design tool called MAX+plus II. The objectives are: (i) To capture the schematics of several logic circuits; (ii) To perform the logic simulation on the circuits; (iii) To verify the functions of the circuits using the logic simulator.

3.

Exercise 1: A Simple Logic Gate This exercise is to capture a schematic consisting of a 2-input NOR gate as shown in Figure 1 and to simulate the circuit.
a y b

Figure 1

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Procedure 1: Schematic Capture: (i) Start the simulator: In Windows, start MAX+plus II. (ii) Start the schematic capture editor: MAX+plus II -> Graphic Editor (This means Under the MAX+plus II menu, select Graphic Editor). (iii) Place a logic gate: Double click anywhere in the Graphic Editor. A Symbol window will appear. Select the primitive library by double clicking c:\maxplus2\max2lib\prim\. (iv) Select a nor2 gate from the Symbol Files or type its name in the symbol name box and press the OK button. (v) A 2-input NOR gate will appear in the Graphic Editor. (vi) Place two input ports and one output port (they are input and output in the symbol library respectively). (vii) Connect the input ports to the input pins of the NOR gate and the output pin to the output port by moving the cursor to the pin (pointer cursor changes to + cursor). Press and hold the left mouse button and drag the wire to the other connection point. (viii) Rename the pin names to the given names: a pin name can be changed by double clicking on the name and typing the new name. (ix) Save the schematic: File -> Save (Use nor as the file name for this exercise.) Circuit Compilation: (i) Set the current project: File -> Project -> Set Project to Current File. (ii) Start the compiler to compile the circuit for simulation: MAX+plus II -> Compiler. (iii) Prepare for functional simulation: Processing -> Functional SNF Extractor. (iv) Compile the schematic by pressing the start button. (v) Correct errors if any. Otherwise, close the compilation window. Input Waveforms: (i) Start the waveform editor: MAX+plus II -> Waveform Editor. (ii) Enter the input and output signals: Node -> Enter Nodes From SNF. (iii) Press the list button to list the inputs and outputs. (iv) Select all the input and output signals and press => button to select them. (v) Press the OK button. (vi) Select input signal a by clicking on it. (vii) Specify a waveform for a: Edit -> Overwrite -> Count Value. (viii) In the Overwrite Count Value window, give the following values: Starting Value = 0, Count Type = Binary, Increment By = 1 and Multiplied By = 1. (ix) Press the OK button. (x) Similarly, specify a waveform for input signal b with the value Multiplied by = 2. (xi) Save the file as nor.scf. Simulation: (i) Start the Simulator: MAX+plus II -> Simulator. (ii) Make sure the Simulation Input is nor.scf. (iii) Press the Start button to simulate the circuit. (iv) When simulation completed, press the Open SCF button to view the simulation results. (v) Observe the output waveforms and verify the simulation results.

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4.

Exercise 2: Latch and Flip Flop This exercise is to capture a schematic consisting of a D latch and two D flip flops as shown in Figure 2 and to simulate the circuit. D latch is level-triggered. As long as the clock signal is activated (high in this case), the input will appear at the output. On the other hand, the two D flip flops of Figure 2 are edge-triggered. One is triggered by the positive edge (or rising edge) of the clock signal and the other by the negative edge (or falling edge) of the clock signal. This exercise is to simulate the circuit and to observe the different functional behaviours of the latch and flip flops.
Q0
LATCH D ENA CLRN CLRN Q DFF D PRN DFF Q D

Q1
PRN

Q2

IN CLOCK

Figure 2 Procedure 2: Schematic Capture: (i) Close all the files and windows of Exercise 1. (ii) In MAX+plus II, open a new Graphic Editor file: File -> New (iii) To place a logic gate: Double click anywhere in the Graphic Editor and a Symbol window appears. Select the primitive symbol library by double clicking c:\maxplus2\max2lib\prim\. (iv) Select a latch from the Symbol Files or type its name in the symbol name box. (v) Place 2 D flip flops DFF and 1 inverter not in the Graphic Editor too. (vi) Complete the circuit according to Figure 2. (vii) Save the schematic with dff as the file name. Circuit Compilation: (i) Set the current project: File -> Project -> Set Project to Current File. (ii) Start the compiler to compile the circuit for simulation: MAX+plus II -> Compiler. (iii) Prepare for simulation: Processing -> Functional SNF Extractor. (iv) Compile the schematic. Input Waveforms: (i) Start the waveform editor. (ii) Enter the input and output signals. (iii) Change the simulation end time to 1.5s: File -> End Time. (iv) Set the simulation grid size to 50ns: Options -> Grid Size. (v) To view the complete window: View -> Fit In Window. (vi) Select input signal CLOCK by clicking on it. (vii) Specify a waveform for CLOCK: Edit -> Overwrite -> Count Value. (Or press the short cut button on the left hand side of the screen. To find out what the short cut buttons are, move the cursor over the buttons and read the message at the bottom of the window.)

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(viii) In the Overwrite Count Value window, give the following values: Starting Value = 1, Count Type = Binary, Increment By = 1 and Multiplied By = 3. (ix) Specify a waveform for input signal IN according to the following values: Time 050100- 250- 350- 400- 500- 550- 800- 950- 1300(ns) 50 100 250 350 400 500 550 800 950 1300 1500 Value 0 1 0 1 0 1 0 1 0 1 0 (To specify a value in a range, select the range with the cursor and press the short cut (x) buttons or for logic 0 and 1 respectively.) Save the file as dff.scf.

Simulation: (i) Start the Simulator. (ii) Make sure the Simulation Input is dff.scf. (iii) Press the Start button to simulate the circuit. (iv) When simulation completed, press the Open SCF button to view the simulation results. (v) Observe the output waveforms and verify the simulation results. (vi) Explain the different behaviours of the D latch and the D flip flops.

5.

Exercise 3: Full Adder This exercise is to capture the schematic of a full adder. A full adder has 3 inputs: two bits to be added and one carry input. It has 2 outputs: the sum of the 3 inputs and the carry output. Table 1 shows the truth table of a full adder and Figure 3 shows its logic circuit. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Ci 0 1 0 1 0 1 0 1 Table 1 S 0 1 1 0 1 0 0 1 Co 0 0 0 1 0 1 1 1

A S B

Ci

Co

Figure 3

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Procedure 3: (i) (ii) (iii) Capture the schematic of Figure 3 and save it with a file name fulladder.gdf. Compile the circuit and correct any errors. Prepare waveforms for simulating the circuit. The waveforms should cover all the combinations of the 3 inputs. This can be done by: Edit -> Overwrite -> Count Value, for each input with the value Multiplied by set to 1, 2 and 4. Simulate the circuit and display the output waveforms. Verify the logic function of the circuit.

(iv) (v)

6.

Exercise 4: A 4-bit Arithmetic Circuit Figure 4 shows a 4-bit arithmetic circuit constructed by cascading 4 full adder cells of Figure 3 and 4 XOR gates.
B0 A0 B1 A1 B2 A2 B3 A3

A B Ci

S Co

A B Ci

S Co

A B Ci

S Co

A B Ci

S Co

C4

S0

S1

S2

S3

Figure 4 Procedure 4(a): (i) (ii) (iii) (iv) Open the schematic of the full adder cell fulladder.gdf. Create a symbol of the cell: File -> Create Default Symbol. Close the file. Open a new file and capture the schematic of Figure 4. Note that the symbol of the cell appears in the Symbol Files list and it can be used as if it is a logic gate. (v) Save it with a file name arith4.gdf. (vi) Compile the circuit and correct any errors. (vii) Prepare waveforms for simulating the circuit. (viii) Simulate and verify the function of the adder by choosing some inputs and observing the outputs S3S2S1S0. (ix) What is the function of the input m? (x) What is the function of the circuit? (xi) How is the function of the circuit achieved? Procedure 4(b): (i) (ii) Open the schematic of the full adder cell arith4.gdf. Start the compiler: MAX+plus II -> Compiler.

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(iii)

Prepare for timing simulation by recompiling the circuit with the Functional SNF Extractor unselected: Processing -> Functional SNF Extractor; (iv) Start the compilation: Press Start Button. (v) Open the file arith4.scf. (vi) From time 0 to 200 ns, set m to 0, A3A2A1A0 to 1111 and B3B2B1B0 to 0001. (vii) From time 200ns onward, change the input B0 to 0. (viii) Save and Simulate. (ix) Zoom in to observe the outputs S3S2S1S0. (x) Press the right arrow button at the top left corner of the Waveform Editor window to move the reference line to the edge of the waveforms. (xi) Record the time for the rightmost edge of S3, S2, S1 and S0. (xii) Study the results and explain the behaviour of the arithmetic circuit.

7.

Exercise 5: An Asynchronous Counter This exercise is to capture a schematic of a 4-bit asynchronous counter as shown in Figure 5. The counter consists of 4 T flip flops TFF and counts from 0000 to 1111 when the input IN is 1. The SET input presets the outputs to 1 and the CLEAR input resets the outputs to 0. Both SET and CLEAR are active LOW signals.
SET IN
TFF T PRN TFF Q T PRN TFF Q T PRN TFF Q T PRN

CLOCK
CLRN CLRN CLRN CLRN

CLEAR Q0 Q1 Q2 Q3

Figure 5 Procedure 5: (i) (ii) (iii) (iv) (v) (vi) Capture the schematic of Figure 5 and save it with a file name asyn_counter.gdf. Compile the circuit for timing simulation and correct any errors. Prepare waveforms for simulating the circuit. Simulate the circuit and display the output waveforms. Verify the counting function of the circuit. Explain why this counter is asynchronous.

8.

Exercise 6: A Synchronous Counter To compare the difference of synchronous counters and asynchronous counters, a 4-bit synchronous counter shown in Figure 6 is to be simulated in this exercise. The synchronous counter also counts from 0000 to 1111 when IN is 1. The SET and CLEAR inputs have the same function as that for the asynchronous counter.

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Procedure 6(a): (i) (ii) (iii) (iv) Open a new file and capture the schematic of Figure 6. Save it with a file name syn_counter.gdf. Compile the circuit for timing simulation and correct any errors. Prepare waveforms for simulating the circuit. The waveforms should be the same as that for the asynchronous counter. (v) Simulate the circuit and display the output waveforms. (vi) Verify the counting function of the circuit. (vii) Explain why this counter is synchronous. (viii) What is the main different behaviour of the synchronous counter compared to the asynchronous counter? (ix) Explain the different behaviours between the asynchronous and the synchronous counter.
SET

TFF

IN

PRN

TFF Q T

PRN

TFF Q T

PRN

TFF Q T

PRN

CLRN

CLRN

CLRN

CLRN

CLOCK CLEAR Q0 Q1 Q2 Q3

Figure 6 Procedure 6(b): (i) The counter in Figure 6 is supposed to suspend the counting and hold its current value when IN = 0. However, due to a design error, it does not behave as expected. (ii) Simulate the circuit with different input values and find out what the error is. (iii) Correct the error and verify the corrected function. 9. Optional Exercise: A Random Sequence Counter Figure 7 shows a counter with an unknown counting sequence. This exercise is to find out the counting sequence by simulating the counter.
SET

TFF

IN

PRN

TFF Q T

PRN

TFF Q T

PRN

TFF Q T

PRN

CLRN

CLRN

CLRN

CLRN

CLOCK RESET Q0 Q1 Q2 Q3

Figure 7

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Procedure 7: (i) (ii) (iii) (iv) (v) Open the schematic of syn_counter.gdf and save it as x_counter.gdf: File -> Save As. Modify the schematic according to Figure 7 and save the file again. Compile the circuit and correct any errors. Prepare waveforms for simulating the circuit. Simulate the circuit and display the output waveforms. Try to start the counting with 0000 and then with 1111. (vi) What is the counting sequence of this counter? (vii) Explain how the counter produces this counting sequence. (viii) Simulate the circuit with the input IN set to 0 and 1 at different time. (ix) What are the counting sequences produced? (x) Explain why these counting sequences are produced. 10. References (i) (ii) (iii) John F. Wakerly, Digital Design: Principles and Practices, 4th ed., Pearson Prentice-Hall, 2007. (Text book for EE2004 Digital Electronics.) Steve Waterman, Digital Logic Simulation And CPLD Programming, Prentice Hall, 2000. (More exercises on logic simulation can be found in this book.) www.altera.com (Altera Max+plus II software can be downloaded from the above web site. Further readings can also be found there.)