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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012

1487

Buried Silicon-Germanium pMOSFETs:

Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling

Felice Crupi, Massimo Alioto, Senior Member, IEEE , Jacopo Franco, Paolo Magnone, Ben Kaczer, Guido Groeseneken , Fellow, IEEE, Jérôme Mitard, Liesbeth Witters, and Thomas Y. Hoffmann

Abstract— In t his paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the rst time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with

/metal gate stack, as well as on 45-nm Si pMOSFETs

with identical gate stack for comparison. In the reference SiGe technol ogy, an innovative technological solution is adopted that limits the SiGe material only to the channel region. The resulting SiGe device merges the higher speed of the Ge technology with the lo wer leakage of the Si technol ogy. Appropriate circuit- and system-level metrics are introd uced to identify the advantages

offered by SiGe technology in VLSI circuits. Analysis is performed

in t he context of next-generation VLSI circuits that fully exploit

circuit- and system-level techniques to improve the energy ef -

ciency through aggressive voltage scaling, other than low-leakage t echniques. Analysis shows tha t the SiGe technology has more

ef cient leakage-delay and dynamic energy-delay trade-offs at

nominal supply, compared to Si technology. Moreover, it is shown that the traditional analysis perf ormed at nominal supply actually underestimates the bene ts of SiGe pMOSFETs, since the speed advantage of SiGe VLSI circuits is further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benet from aggressive voltage scaling signi cantly more than Si circuits, thereby making SiGe devices a very promising alternative to Si transistors in next-generation VLSI systems.

a high-

to Si transistors in next-generation VLSI systems. a high- Index Terms— Aggressive voltage scaling, digital

Index Terms— Aggressive voltage scaling, digital circuits, emerging technologies, energy ef ciency, power-delay trade-off, Silicon-Germanium, VLSI.

Manuscript received July 06, 2010; revised February 02, 2011; accepted June

10, 2011. Date of publication July 22, 2011; date of current version June 14,

2012.

F. Crupi is with the Dipartimento di Elettronica, Informatica e Sistemistica

(DEIS), Università della Calabria, 87036 Rende, Italy. M. Alioto is with the Dipartimento di Ingegneria dell’Informazione (DII),

Università di Siena, 53100 Siena, Ital y, and also with the Berkeley Wireless Research Center, Electrical Engineering and Computer Science Department, University of California, Berkeley, CA 94704-1302 USA (e-mail: malioto@dii. unisi.it; alioto@eecs.berkeley.edu).

J. Franco and G. Groeseneken are with th e Interuniversity Microelectronics

Center (IMEC), 3001 Leuven, Belgium, and also with the Department of

Electrical Engineering (ESAT), Katholieke Universiteit Leuven, 3001 Leuven, Belgium.

P. Magnone is with the Advanced Research Center on Electronic Systems for

Information and Communication Technologies E. De Castro (ARCES), Univer-

sità di Bologna, 40125 Bologna, Italy.

B. Kaczer, J. Mitard, L. Witters, and T. Y. Hoffmann are with the Inter-

university Microelectronics Center (IMEC), 3001 Leuven, Belgium. Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org.

Dig ital Object Identi er 10.1109/TVLSI.2011.2159870

I. I NTRODUCTI ON

T WO major technological breakthroughs have enabled the enhancement of the performance and the en ergy

efciency of sub-100-nm CMOS VLSI circuits [1], [2]. The rst one was the introduction of the strain e ngineering since the 90-nm technology node, which allowed for dramatically boosting the performance thanks to t he higher channel mobility. The second one was the introduction o f the high-k metal gate stack since the 45-nm technology no de, which is highly ben- e cial in terms of energy efcienc y thanks to the suppression of the gate leakage. In order to su stain the trends indicated by the ITRS roadmap, other techn ological breakthroughs are expected below the 22-nm tec hnology generation. A possible technological solution is t he use of high-mobility material as

replacement of Si for the device channel. Germanium-based and III-V materials are cu rrently under extensive investigation by the device community w hile the circuit and system com- munity is waiting for res ponse. Consequently, the results on high-mobility materials available in the literature focus on the device features and d o not provide enough information on the suitability for VLS I implementations. Energy efciency iss ues are progressively pushing for more aggressive voltage scaling and ner granularity to improve performance-per-watt (e.g., laptop computers, portable media players) [3]–[5]. Clearly, the energy efciency bene ts most from ultra-dyna mic voltage scaling (UDVS) when performance exhibits a low d egradation under a given voltage reduction, whereas dynami c and leakage power exhibit a large reduc- tion [6]–[8]. In particular, the performance/power reduction obtained wit h UDVS is strongly dependent on the adopted tech- nology and th e design approach at circuit and system level [9], [10]. This means that the assessment of emerging technologies as candida te replacements of Si devices for next-generation VLSI circ uits must be carried out under the realistic scenario where UDV S and low-leakage techniques are extensively employe d [11]. Recently the same authors proposed a novel evaluation methodo logy that aims to ll this gap between device char- acteri zation and VLSI systems by extracting circuit- and system -level features from pure on-wafer experimental mea- surem ents of a newly developed technology. This methodology was ap plied to Germanium pMOSFETs very recently [12]. This meas urement-based methodology permits to perform an early asse ssment of the technology well before having a complete

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012

design kit. This approach does not require 2-D/3-D device simulations, which are not well calibrated for semiconductors different from Si. Our analysis in [12] showed that although VLSI circuits with Ge pMOSFETs overcome their Si counter- parts in terms of speed, some technological issues need to be solved especially for red ucing the junction leakage. In this paper, we adopt and extend the above approach to buried SiGe channel pMOSFETs [13]–[18]. An interesting study on the potential advantages of SiGe devices for VLSI cir- cuits based on theoretical simula tions has been reported in [19]. However, experimental analysis of nanometer SiGe transistors would be more reliable and hence preferable to simulations, which are based on simplifying assumptions and do not ac- count for process non-idealities. In this paper, the potential of SiGe technology for VLSI logic circuits is explored through an experimental evaluation at 45-nm technology generation. In particular, two main goals will be pursued. The rst is to understand the speed advantage offered by SiGe technology in the context of VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efciency (e.g., UDVS, power gating). The second purpose is to show that the SiGe technology offers an excellent leakage-delay trade-off, since it can merge the higher speed of the Ge technology with the lower leakage of the Si technology. This paper is structured as follows. SiGe pMOSFETs are reviewed in Section II, where details of the fabrication of the considered devices are provided. Various gures of merit for performance at circuit level are introduced in Section III to compare SiGe and Si technologies from a speed perspective. In Section IV, this performance improvement is traded off for lower power consumption, and the efciency of dynamic-en- ergy delay and leakage-delay trade-off is analyzed under the adoption of aggressive voltage scaling. Finally, conclusions are drawn in Section V.

II. A DOPTED S I G E T ECHNOLOGY AND B ASIC P ROPERTIES OF

S I G E P MOSFET S

Devices were fabricated at IMEC using 300 mm (100) Si wafers. Fig. 1(a) and (b) shows the cross-sectional sketch and image of the nal device. A thin compressively strained

layer is epitaxially grown onto a relaxed Si buffer.

This strain effect is expected to be bene cial for the mobility [20]. On top of this SiGe layer, a thin Si cap is grown. A detailed description of the epi-process can be found else- where [21], [22]. The Si cap is needed to avoid SiGe oxidation

causing an increase of interface defects

during gate stack

fabrication which starts with a very thin wet chemical oxide.

On top of this

deposited using atomic layer deposition (ALD). Finally a metal gate is deposited. Due to the valence band offset between the SiGe and the Si [see Fig. 1(c)] inversion channel holes are con- ned in the SiGe layer, which therefore behaves as a quantum well for holes. This causes the Si cap thickness to lower the inversion capacitance as compared to the accumulation capac- itance. It is then necessary to report the capacitance-equiva-

lent thickness in inversion

are

the capacitance-equiva- lent thickness in inversion are interfacial layer (IL), 2 nm of , which was
the capacitance-equiva- lent thickness in inversion are interfacial layer (IL), 2 nm of , which was
the capacitance-equiva- lent thickness in inversion are interfacial layer (IL), 2 nm of , which was

interfacial layer (IL), 2 nm of

thickness in inversion are interfacial layer (IL), 2 nm of , which was estimated to be

, which was estimated to be

1.65 nm. Channel width and physical gate length were 90 and 45 nm, respectively.

and physical gate length were 90 and 45 nm, respectively. Fig. 1. (a) Cross-sectional TEM image
and physical gate length were 90 and 45 nm, respectively. Fig. 1. (a) Cross-sectional TEM image

Fig. 1. (a) Cross-sectional TEM image of SiGe pMOSFET. (b) Cross-sectional sketch. (c) Band diagram in inversion. Channel holes are con ned in the SiGe quantum well due to valence band offset toward the Si layers. The Si cap addi- tionally displaces channel holes, therefo re lowering the inversion capacitance.

For comparison purposes, we characterized a second set of standard Si channel devices with identical dimensions and gate

stack.

worth to emphasize that, although having the same gate stack, Si

devices show a lower

channel devices: as mentioned a bove, this is due to the impact

devices: as mentioned a bove, this is due to the impact was estimated as 1.31 nm

was estimated as 1.31 nm for these devices. It is

as compared to thethe impact was estimated as 1.31 nm for these devices. It is of the SiGe of

as 1.31 nm for these devices. It is as compared to the of the SiGe of

of the SiGe

of

the thin Si cap acting as an additional displacement for holes

in

the latter case. The device measurements were done at wafer-level using

a

semiconductor characterizat ion system based on multiple

Keithley 2602 instruments. For the typical investigated the ITRS roadmap [1] indicates that the supply voltages are

,
,

in the range

quirements (high-performance or low-power). In this work, we

1 V. The SiGe and Si

0.147 V

and

maximum transconductance method [23]. Since the threshold voltage in the SiGe process is not optimized and is signicantly different with respect to Si devices, in order to perform a fair comparison, we shifted the I-V curves in such a way to equalize

0.33 V for both SiGe

the threshold voltages

0.357 V, respectively, as found by applying the

devices have different threshold voltages,

choose the intermediate value

–1.2 V based on the technology re-different threshold voltages, choose the intermediate value and Si devices. 1 In Fig. 2 we report

the intermediate value –1.2 V based on the technology re- and Si devices. 1 In Fig.
the intermediate value –1.2 V based on the technology re- and Si devices. 1 In Fig.
the intermediate value –1.2 V based on the technology re- and Si devices. 1 In Fig.
the intermediate value –1.2 V based on the technology re- and Si devices. 1 In Fig.
and Si devices. 1 In Fig. 2 we report the drain current as a function
and Si devices. 1
In Fig. 2 we report the drain current as a function of
gate voltage overdrive
measured in Si and
SiGe pMOSFETs at (a) low
and (b) high
. The
on-current
achieved for
1 V and
667 mV for the Si (SiGe)
device is 684
A
m (705
A
m), hence at fi rst glance the

on-current advantage of SiGe devices is negligible. However, this result is not representative of practical cases, and a more

1 For example, this can be easily done by adjusting the work function of the gate by selecting a proper metal or by inserting a cap layer between the high-k dielectric and the metal gate.

CRUPI et al.: BURIED SILICON-GERMANIUM P MOSFET S

CRUPI et al. : BURIED SILICON-GERMANIUM P MOSFET S Fig. 2. Measured drain current versus gate

Fig. 2. Measured drain current versus gate voltage overdrive in Si and SiGe

1 V. The on-current im-drain current versus gate voltage overdrive in Si and SiGe . Si and SiGe pMOSFETs at

. Si and SiGe

pMOSFETs at (a)

provement observed at low

pMOSFETs exhibit the same sub-threshold slope (see insets).

pMOSFETs exhibit the same sub-threshold slope (see insets). 50 mV and (b) at is strongly reduced

50 mV and (b) at

is strongly reduced at high

(see insets). 50 mV and (b) at is strongly reduced at high fair performance comparison will

fair performance comparison will be presented in the next

section. On the other hand, at low

), and reaches

1.78

. This observation suggests a

improvement is signi cantly higher (1.41

the SiGe on-currentsuggests a improvement is signi fi cantly higher (1.41 after normalizing by mobility enhancement up to

is signi fi cantly higher (1.41 the SiGe on-current after normalizing by mobility enhancement up to
is signi fi cantly higher (1.41 the SiGe on-current after normalizing by mobility enhancement up to

after normalizing by

cantly higher (1.41 the SiGe on-current after normalizing by mobility enhancement up to about 80%. It

mobility enhancement up to about 80%. It is worth noting that the reduction of the speed advantage at higher voltages is a common property of all high-mobility materials. The physical reason is that at high longitudinal elds the carrier velocity tends to saturate and the speed advantage of high-mobility materials is signi cantly reduced. In the following section we will show how the improvement in several speed gures of merit at circuit and system level is actually between the speed improvement at high voltages and that of low voltages. As highlighted in the insets of Fig. 2, SiGe devices exhibit the same sub-threshold slope (SS) values as Si pMOSFETs. It is im- portant to underline that the SiGe pMOSFETs used in this work do not suffer from the high junc tion leakage of Ge devices re- ported in [12], thanks to the proposed architecture which limits the use of SiGe material only to the channel layer. Moreover, the drain-induced barrier lowering (DIBL) coefcients of the SiGe and Si technologies are very close as well (see Table I).

Note that the slightly higher

FETs is simply because equalizing the

maximum transconductance method does not guarantee exactly

the same

in devices with the same SS , and also because of

the strong dependence of

matic perspective, since the main leakage parameters (SS and DIBL coefcient) are almost equal for SiGe and Si devices, we conclude that the leakage in SiGe pMOSFETs is actually very similar to that of Si devices. These observations bring us to the conclusion that the proposed buried SiGe pMOSFETs merge the higher speed of the Ge technology with the lower leakage of the Si technology.

Ge technology with the lower leakage of the Si technology. measured in SiGe pMOS- extracted with

measured in SiGe pMOS-

lower leakage of the Si technology. measured in SiGe pMOS- extracted with the . From a

extracted with the

the Si technology. measured in SiGe pMOS- extracted with the . From a more prag- on

. From a more prag-

in SiGe pMOS- extracted with the . From a more prag- on the 1489 TABLE I
in SiGe pMOS- extracted with the . From a more prag- on the 1489 TABLE I

on the

1489

TABLE I

D EVICE P ARAMETERS OF SiGe AND Si pMOSFETs

TABLE I D EVICE P ARAMETERS OF SiGe AND Si pMOSFETs TABLE II F IGURES OF

TABLE II

F IGURES OF M ERIT E XPRESSING THE A DVANTAGES OF SiGe

O VER Si pMOSFETs

E XPRESSING THE A DVANTAGES OF SiGe O VER Si pMOSFETs As a further advantage, we

As a further advantage, we have recently reported that the proposed SiGe devices exhibit remarkably reduced negative- bias temperature instability an d lower 1/f noise with respect to their silicon counterparts [17], [18].

III. S PEED P OTENTIAL OF VLSI C IRCUITS W ITH S I G E P MOSFET S U NDER A GGRESSIVE V OLTAGE S CALING

In this section, we evaluate the performance improvement offered by the SiGe pMOSFET for a reference inverter gate (see Section III-A) and for more c omplex logic gates containing stacked transistors (see Section III-B). In both cases, we assume that the load is dominated by the gate capacitance (i.e., the con- sidered logic gate is driving nearby cells). All comparisons are

performed by equalizing the threshold voltage

are performed by equalizing the threshold voltage 0.33 V and the supply voltage for both SiGe

0.33 V

and the supply voltage for both SiGe and Si technologies. The main results are summarized in Table II.

A. Analysis of Reference Inverter Gate

The speed bene ts brought by SiGe devi ces can be intuitively

between

the on-current and gate capacitance of SiGe normalized to the

and

. The normalization of the drain current for the gate

has been simply obtained by multiplying

the drain current for the capac itance-equivalent thickness in

inversion

, whereas a

signi cantly smaller improvement (down to 1.28) is obtained

at high

. In the following, practical cases where a large

provement (up to 1.91) is observed at low

. From this gure the largest speed im-

grasped by inspecting Fig. 3, where the ratio

speed im- grasped by inspecting Fig. 3, where the ratio Si counterpart is plotted as a

Si counterpart is plotted as a function of voltages

- capacitance
-
capacitance
speed im- grasped by inspecting Fig. 3, where the ratio Si counterpart is plotted as a
speed im- grasped by inspecting Fig. 3, where the ratio Si counterpart is plotted as a
speed im- grasped by inspecting Fig. 3, where the ratio Si counterpart is plotted as a
speed im- grasped by inspecting Fig. 3, where the ratio Si counterpart is plotted as a

1490

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012

INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012 Fig. 3. Ratio of bias voltages, low

Fig. 3. Ratio of

bias voltages,

low

improvement observed at low in the DIBL behavior.

and
and

between SiGe and Si pMOSFETs as a function of the

. The large speed improvement observed at

(up to 1.91) is strongly reduced at higha function of the . The large speed improvement observed at (down to 1.28). The speed

observed at (up to 1.91) is strongly reduced at high (down to 1.28). The speed is
observed at (up to 1.91) is strongly reduced at high (down to 1.28). The speed is

(down to 1.28). The speed

is due to differences

and high

bene t can be achieved will be identi ed and discussed by introducing appropriate gures of merit. An extremely simple gure of merit expressing the speed ad- vantage of SiGe over Si is

of merit expressing the speed ad- vantage of SiGe over Si is (1) is de fi

(1)

is de ned as the MOSFET current . To better understand the impact

where the on-current

when

of UDVS, the gure of merit in (1) obtained from experimental

measurements was plotted in Fig. 4(a) versus

. This gure

clearly shows that

tends to increase at low voltages, i.e., SiGe circuits have a larger performance advantage when the supply voltage is aggressively scaled. In particular, the sp eed improvement in (1) is 1.30 at

600 mV. It is worth empha-

is always greater than one and

at 600 mV. It is worth empha- is always greater than one and 1 V and
at 600 mV. It is worth empha- is always greater than one and 1 V and
at 600 mV. It is worth empha- is always greater than one and 1 V and
at 600 mV. It is worth empha- is always greater than one and 1 V and

1 V and 1.41 at

worth empha- is always greater than one and 1 V and 1.41 at Fig. 4. Advantage
worth empha- is always greater than one and 1 V and 1.41 at Fig. 4. Advantage

Fig. 4. Advantage of SiGe pMOSFETs with respect to Si devices in terms of

(a) on-current, (b) delay time, and (c) rise time as a function of for different
(a) on-current, (b) delay time, and (c) rise time as a function of
for different
numbers of stacked devices
. In all cases, the speed improvement of SiGe
pMOSFETs increases with decreasing
and with increasing
. As ex-
pected,
is larger than
, which is slightly larger than
.

minimum-sized transistor, and

the considered cell), the gate delay can be expressed as

the driving strength ofand the considered cell), the gate delay can be expressed as sizing that since this speed

sizing that since this speed improvement is a consequence of reducing the longitudinal electric eld (roughly proportional to

), it emerges when we reduce the supply bias for a fi xed xed

channel length

techniques. On the other hand, this advantage does not apply to

the case of the

(i.e., channel length) scaling, because in this case the longitu- dinal eld is almost the same. The gure of merit in (1) is based on the evaluation of the on-current at maximum voltage, hence it is not necessarily re- alistic since transistors actually experience large voltage varia- tions during the output transition of a generic logic gate. As a more rigorous measure of speed, let us evaluate the inverter gate delay by using the actual on-current that is delivered by the tran- sistor during the output transition. In particular, assuming that the load is dominated by the input capacitance of the subsequent

reduction associated with the technology

, as in the case of circuits which exploit UDVS

(2) To fairly compare a generic SiGe and Si logic gate, let us assume the
(2)
To fairly compare a generic SiGe and Si logic gate, let us assume
the same driving strength in (2), as well as the same fan-out and

size of the loading gates (i.e., the same

gure of merit

of SiGe over Si technology results to

). Hence, the resultingfi gure of merit of SiGe over Si technology results to that evaluates the speed advantage

that evaluates the speed advantage

). Hence, the resulting that evaluates the speed advantage (3) . Observe that all pa- rameters
). Hence, the resulting that evaluates the speed advantage (3) . Observe that all pa- rameters

(3)

. Observe that all pa-Hence, the resulting that evaluates the speed advantage (3) rameters in (3) can be derived directly

rameters in (3) can be derived directly from device measure- ments, as required by our evaluation approach. As expected

from the larger speed advant age of SiGe devices at lower

the

value. In

particular, SiGe technology offers a 1.3

speed advantage at

600

is slightly higher than the corresponding

which is plotted in Fig. 4(b) versus

than the corresponding which is plotted in Fig. 4(b) versus 1 V and a 1.44 ,

1 V and a 1.44

,
,

value increases at lower supply voltage and

1 V and a 1.44 , value increases at lower supply voltage and speed improvement at
1 V and a 1.44 , value increases at lower supply voltage and speed improvement at

speed improvement at

increases at lower supply voltage and speed improvement at logic gates, the load capacitance can be
increases at lower supply voltage and speed improvement at logic gates, the load capacitance can be

logic gates, the load capacitance can be expressed as

being

the equivalent number of

driven transistors (it accounts for both the fan-out and the size of the transistors of the loading gates). By modeling the transistor

(e.g., a minimum inverter) and

,
,
By modeling the transistor (e.g., a minimum inverter) and , the input (gate) capacitanc e of

the input (gate) capacitanc e of a reference logic gate

, the input (gate) capacitanc e of a reference logic gate as a current source delivering

as a current source delivering a current

(gate) capacitanc e of a reference logic gate as a current source delivering a current (being

(being

the current delivered by a
the current delivered by a

CRUPI et al.: BURIED SILICON-GERMANIUM P MOSFET S

mV. This means that SiGe technology offers a signicant speed

advantage at nominal

ence a smaller degradation when

to Si technology. This is a very nice feature of SiGe circuits in

the context of next-generation VLSI systems with UDVS, and

is again explained by the great er SiGe mobility enhancement at

low longitudinal elds. As a further interesting aspect related to the performance of VLSI circuits that is traditiona lly neglected, let us compare the rise time of SiGe and Si inverters. This comparison gives infor- mation on the speed improvement in the output transition of a logic gate. For example, the rise time is very important in the case of local clock buffers (i.e., driving the clock of a clock do- main), since their rise time denes the local clock slope, which strongly impacts the energy-del ay trade-off in clock domains [24]. To comparatively evaluate the rise time of SiGe and Si

circuits, let us resort to a procedure that is similar to that used

to derive (3), which leads to the following gure of merit ex-

pressing the advantage of SiGe over Si

gure of merit ex- pressing the advantage of SiGe over Si , and its performance tends

, and its performance tends to experi-

of SiGe over Si , and its performance tends to experi- is scaled down, compared (4)

is scaled down, compared

its performance tends to experi- is scaled down, compared (4) where it was considered that the

(4)

where it was considered that the transistor current determines the output transition from 10% to 90% of the supply voltage.

for the reference tech-

nologies. From this gure, the rise time bene ts from the adop- tion of SiGe technology even more than the gate delay. This can be intuitively explained by considering that the rise time

is affected more by currents at low voltages, since the output

voltages varies up to 90% of

titatively, SiGe technology exhibits a rise time improvement

by 1.45

at

600 mV. This means that in general SiGe inverters have

signi cantly sharper transitions compared to Si counterparts, other than having a faster respon se (i.e., lower delay). In turn, sharper output edges in SiGe circuits keep the delay of subse- quent gates and their short-circuit power smaller, other than per- mitting to downsize buffers for a targeted signal slope (thereby reducing their dynamic and leakage consumption, which is ben- e cial in the local distribution of the clock within a clock do- main [24]).

(4) is plotted in Fig. 4(c) versus

a clock do- main [24]). (4) is plotted in Fig. 4(c) versus , instead of 50%.
a clock do- main [24]). (4) is plotted in Fig. 4(c) versus , instead of 50%.

, instead of 50%. More quan-

atis plotted in Fig. 4(c) versus , instead of 50%. More quan- 1 V, and an

plotted in Fig. 4(c) versus , instead of 50%. More quan- at 1 V, and an

1 V, and an even better improvement is

achieved at lower voltages, reaching a remarkable 1.56

is achieved at lower voltages, reaching a remarkable 1.56 B. Extension to Complex Gates In general,
is achieved at lower voltages, reaching a remarkable 1.56 B. Extension to Complex Gates In general,

B. Extension to Complex Gates

In general, transistor stacking in complex gates leads to

a degradation of the on-current. Since the proposed SiGe

pMOSFETs show the same leakag e behavior (in terms of SS and DIBL) of their Si counterparts, the following comparative analysis is focused on the on-c urrent degradation associated with the transistor stacking. Si nce stacked transistors were not available for direct measurem ents, we applied an appropriate numerical procedure which allows for extracting the bias point

as a func-

tion of

of the stacked transistors from measurements of

on a single pMOSFET [12]. As

shown in Fig. 4(a), a signi cantly lower degradation associated with the transistor stacking is observed in SiGe pMOSFETs. In

1 V is 1.30, 1.50,

particular, the speed improvement at

In 1 V is 1.30, 1.50, particular, the speed improvement at , and 1491 1, 2,

, andIn 1 V is 1.30, 1.50, particular, the speed improvement at 1491 1, 2, and 3,

V is 1.30, 1.50, particular, the speed improvement at , and 1491 1, 2, and 3,
V is 1.30, 1.50, particular, the speed improvement at , and 1491 1, 2, and 3,

1491

1, 2,

and 3, respectively. This improv ement is clearly a consequence

of the reduction in

transistors is adopted. An even larger advantage is obtained by considering the joint effect of bias supply voltage reduction and transistor stacking. For example, the speed improvement

. As shown

reaches 1.70 at

in Figs. 4(b) and (c), this adva ntage further increases if we

consider the gures of merit instead of the simplistic gure of merit

the

and

provement over Si technology.

, i.e., SiGe technology has a 74% speed im-

and 1.62 for a number of stacked transistors

a 74% speed im- and 1.62 for a number of stacked transistors when a larger number
a 74% speed im- and 1.62 for a number of stacked transistors when a larger number

when a larger number of stacked

of stacked transistors when a larger number of stacked 600 mV and and , . For

600 mV andof stacked transistors when a larger number of stacked and , . For example, 600 mV

and , . For example, 600 mV
and
,
. For example,
600 mV
number of stacked 600 mV and and , . For example, 600 mV reaches a remarkable

reaches a remarkable 1.74 at

IV. ENERGY/P OWER -D ELAY T RADE -O FF IN S I G E VLSI

C IRCUITS U NDER A GGRESSIVE V OLTAGE S CALING

In Section III, it was shown that SiGe circuits exhibit a signi cant speed advantage over Si circuits at same threshold voltage and supply voltage. In this section, this performance improvement is traded off for l ower consumption, and SiGe and Si leakage are compared at is o performance in the context of systems with aggressive voltage scaling. The resulting advantage in terms of dynamic and leakage consumption is discussed in Sections IV-A and I V-B, respectively. The main results are summarized in Table II.

A. Dynamic Energy-Delay Trade-Off and Voltage Scaling

Let us consider the case where th e performance improvement offered by SiGe technology is traded off for lower power con- sumption by reducing the SiGe supply voltage to achieve the same gate delay as the Si counterpart, assuming both technolo- gies have the same threshold voltage as in Section III. The re-

sulting supply voltage

the same gate delay as the Si counterpart powered by voltage

) is plotted in Fig. 5.the same gate delay as the Si counterpart powered by voltage As expected, from this fi

As expected, from this gure the SiGe circuit voltage

at same performance

is typically 20–30% lower than

of the SiGe circuit leading tovoltage at same performance is typically 20–30% lower than (i.e., such that (slightly higher for circuits

typically 20–30% lower than of the SiGe circuit leading to (i.e., such that (slightly higher for

(i.e., such that

lower than of the SiGe circuit leading to (i.e., such that (slightly higher for circuits with
lower than of the SiGe circuit leading to (i.e., such that (slightly higher for circuits with

(slightly higher for circuits with a higher number of stacked transistors). More in detail, the SiGe voltage reduction tends to

be smaller when

the delay becomes more sensi tive to voltage reductions. The above discussed SiGe voltage reduction at iso-perfor- mance is clearly bene cial in terms of dynamic energy. More speci cally, assuming again that the capacitance at the output of an inverter is dominated by the gate capacitance, the dynamic

power can be expressed as

derivation of (3), let us adopt the gure of merit

expresses the dynamic power at iso -performance (or energy) ad- vantage of SiGe compared to Si

is closer to the threshold voltage, since-performance (or energy) ad- vantage of SiGe compared to Si . Similarly to the that (5)

compared to Si is closer to the threshold voltage, since . Similarly to the that (5)

. Similarly to the

that

to the threshold voltage, since . Similarly to the that (5) where cuits matching the same

(5)

where

cuits matching the same delay as the Si counterpart powered

with a supply

. As shown in Fig. 6, SiGe technology al-

lows a remarkable dynamic power saving that increases by in-

creasing

600 mV and 1.98 (2.21)

. More quantitatively, the dynamic energy is re-saving that increases by in- creasing 600 mV and 1.98 (2.21) duced by a factor 1.64

duced by a factor 1.64 (1.71) at

is the resulting supply voltage of the SiGe cir-by in- creasing 600 mV and 1.98 (2.21) . More quantitatively, the dynamic energy is re-

the dynamic energy is re- duced by a factor 1.64 (1.71) at is the resulting supply
the dynamic energy is re- duced by a factor 1.64 (1.71) at is the resulting supply

1492

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012

INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012 Fig. 5. Supply voltage of SiGe pMOSFETs

Fig. 5. Supply voltage of SiGe pMOSFETs required to match the gate delay of the Si counterpart as a function of supply voltage of Si pMOSFETs for dif-

. The SiGe supply voltage reduction

increases when increasingof Si pMOSFETs for dif- . The SiGe supply voltage reduction ferent numbers of stacked devices

ferent numbers of stacked devices

increases when increasing ferent numbers of stacked devices and . Fig. 6. Advantage of SiGe in
increases when increasing ferent numbers of stacked devices and . Fig. 6. Advantage of SiGe in

and

.
.
when increasing ferent numbers of stacked devices and . Fig. 6. Advantage of SiGe in terms

Fig. 6. Advantage of SiGe in terms of dynamic energy versus Si supply voltage (SiGe supply set to match performance) for different numbers of stacked devices

. at
.
at

. The stronger re-

duction at high supply voltages could appear contradictory to

the higher

voltage. However, this trend can be explained by considering again that the delay becomes more sensitive to voltage reduc- tions when the voltage is reduced. Anyway, the above results clearly show that SiGe circuits bene t from aggressive voltage

scaling much more than Si counterparts, as

. This

considerable improvement in the energy efciency is highly bene cial in today’s and future sy stems-on-chip operating in a power limited regime [25]. As additional bene t of the reduced supply voltage of SiGe circuits, a signi cant improvement in their reliability is expected [17]. It is worth noting that a 4- to 6-fold reduction in the dynamic power of SiGe devices was re- ported in a previous study based on theoretical simulations [19]. This higher value could be ascribed to the higher bias voltage of 2.5 V used in [19].

improvement observed at lower supply

1 V for

V used in [19]. improvement observed at lower supply 1 V for B. Leakage-Delay Tradeoff and
V used in [19]. improvement observed at lower supply 1 V for B. Leakage-Delay Tradeoff and
V used in [19]. improvement observed at lower supply 1 V for B. Leakage-Delay Tradeoff and

B. Leakage-Delay Tradeoff and Voltage Scaling

The reduced supply voltage enabled by SiGe circuits at iso-performance can also provide a signi cant reduction in leakage power. In general, the leakage power in a technology

is the

subthreshold leakage current of a minimum-sized inverter,

evaluated at

. The resulting gure of

is meaningfully expressed by

. The resulting fi gure of is meaningfully expressed by where and Fig. 7. Advantage of

where

resulting fi gure of is meaningfully expressed by where and Fig. 7. Advantage of SiGe in
resulting fi gure of is meaningfully expressed by where and Fig. 7. Advantage of SiGe in

and

fi gure of is meaningfully expressed by where and Fig. 7. Advantage of SiGe in terms
fi gure of is meaningfully expressed by where and Fig. 7. Advantage of SiGe in terms

Fig. 7. Advantage of SiGe in terms of leakage power versus Si supply voltage (SiGe supply set to match performance).

merit

SiGe over Si technology results to

match performance). merit SiGe over Si technology results to that evaluates the leakage power reduction of

that evaluates the leakage power reduction of

results to that evaluates the leakage power reduction of (6) Assuming the scenario where SiGe and

(6)

Assuming the scenario where SiGe and Si devices have the same threshold as in Section III and the SiGe supply is scaled to match the Si performance (as discussed at the be- ginning of Section IV-A), the resulting gure of merit in (6) is plotted in Fig. 7. From this gure, SiGe technology allows for a considerable reduction o f leakage power, which is even larger than the dynamic power saving and ranges from 1.65

to 3.36 when

reduction is in part due to the leakage reduction resulting from the voltage reduction through the DIBL effect [i.e., the

factor

reduction itself [i.e., the factor

speci cally, the ratio

ranges from 1.45 to 2.55 (from 1.14 to 1.32), hence the leakage power reduction is mainly due to the leakage current reduction (thanks to DIBL effect) rather than the voltage reduction itself. Observe that the leakage power reduction in Fig. 7 increases by

increasing

the previous subsection. The above results permit to evaluate the intrinsic advantage in ter ms of leakage of SiGe technology in VLSI circuits, as no low-l eakage technique was accounted for. However, practical applica tions always require the adop- tion of techniques to keep leak age under control. In particular power gating is the most popular technique, since it is effective and can be easily integrated in automated design ows [5]. In power gating schemes, a sleep transistor with high threshold is introduced to cut off a circuit from its power rail during the standby mode [5]. To compar e the effectiveness of this technique in SiGe and Si circuits, we made two assumptions. First, the (higher) threshold of the sleep transistor was set so that the intrinsic leakage of the sleep transistor is lower than that of transistors within log ic gates by a decade (i.e., the threshold voltage of the sleep tr ansistor is increased by a value corresponding to the subthreshold slope in V/dec, as compared to transistors in logic gates with standard threshold). Second,

the width

maximum voltage drop (which degrades the effective supply

voltage seen by logic gates) in active mode to 5% of

of the sleep transistor was sized to keep its

for the same reasons that were discussed in

to keep its for the same reasons that were discussed in ranges from 600 mV to

ranges from 600 mV to 1.2 V. This

in (6)], and in part to the voltage

in (6)]. More
in (6)]. More
same reasons that were discussed in ranges from 600 mV to 1.2 V. This in (6)],
same reasons that were discussed in ranges from 600 mV to 1.2 V. This in (6)],
same reasons that were discussed in ranges from 600 mV to 1.2 V. This in (6)],
same reasons that were discussed in ranges from 600 mV to 1.2 V. This in (6)],
.
.

CRUPI et al.: BURIED SILICON-GERMANIUM P MOSFET S

CRUPI et al. : BURIED SILICON-GERMANIUM P MOSFET S Fig. 8. Leakage reduction inactive pMOSFETs as

Fig. 8. Leakage reduction

inactive pMOSFETs as a function of the simultaneously active gates

SiGe devices allow a larger leakage reduction (by a factor 1.4) with respect to their Si counterparts.

when sleep transistors are used to drive 100

counterparts. when sleep transistors are used to drive 100 . Clearly, the maximum voltage dr op
.
.

Clearly, the maximum voltage dr op depends on the current that is drawn by the logic gates, which is in turn set by the maximum number of logic gates that switch simultaneously. Intuitively, power gating is expected to be mo re effective in SiGe circuits, as compared to Si counterparts. Indeed, SiGe sleep transistors have a signi cantly greater driving capability compared to Si counterparts, especially considering that their source-drain

). Hence,counterparts, especially considering that their source-drain voltage is quite low (a few percentage points of SiGe

voltage is quite low (a few percentage points of

SiGe sleep transistors can be made smaller compared to Si counterparts under the same voltage drop requirement, thereby reducing the overall leakage. To achieve quantitative results, we assumed for simplicity that a sleep transistor is conn ected to 100 minimum-sized in-

verters (with width

sistor sizing and leakage calculations by progressively varying

the number

to 50. In each case, the procedure described in [12] was adopted

must be 5.9In each case, the procedure described in [12] was adopted (8) times larger than . The

(8) times larger than

. The smallerin [12] was adopted must be 5.9 (8) times larger than to keep the voltage drop

to keep the voltage drop on

the SiGe (Si) sleep transistor below the 5% of

area of SiGe sleep transistors is justi ed by the above qualitative considerations. The resulting leakage reduction offered by SiGe

compared with Si technology is plotted in Fig. 8 versus From this gure, power gating in SiGe circuits is more effective in reducing leakage by a factor 1.4 with respect to Si devices,

. Thisreducing leakage by a factor 1.4 with respect to Si devices, and this advantage is basically

and this advantage is basically independent of

advantage adds up to the considerably lower intrinsic leakage power of SiGe technology that was discussed above.

leakage power of SiGe technology that was discussed above. ). Then, we repeated the sleep tran-

). Then, we repeated the sleep tran-

was discussed above. ). Then, we repeated the sleep tran- of simultaneously switching gates from 10

of simultaneously switching gates from 10

to evaluate leakage. Analysis showed that

gates from 10 to evaluate leakage. Analysis showed that . V. C ONCLUSION AND R EMARKS
.
.

V. C ONCLUSION AND R EMARKS

In this work, we have analyzed the potential of high-mobility Silicon-Germanium (SiGe) pMOSFETs from the perspective of VLSI logic circuits exploiting aggressive dynamic voltage scaling. The study is based o n experimental measurements

performed on 45-nm SiGe pMOSFETs with a high-

/metal

gate stack having capacitance-equivalent thickness in inversion of 1.65 nm and, for comparison purposes, also on 45-nm Si pMOSFETs with identical gate stack. Thanks to an innovative technological solution that limits the SiGe material only to the channel region, the proposed buried SiGe pMOSFETs exhibit the same leakage as their Si coun terparts, thus overcoming the

same leakage as their Si coun terparts, thus overcoming the 1493 main problem of conventional Ge

1493

main problem of conventional Ge pMOSFETs which suffer from excessively high junction leakage [12]. This study brings us to two main conclusions. The rst one is that by evaluating the speed performance at the maximum supply voltage, as is typically done in the early assessment of a new technology, the bene ts of SiGe pMOSFETs are strongly underestimated . Indeed, SiGe technology offers a 30% speed improvement at nominal voltage, and an even higher advan- tage at lower supply voltages (44% at 600 mV). Hence, SiGe VLSI circuits bene t from ultra-dynamic voltage scaling much more than Si circuits. This is a key advantage from the perspec- tive of next-generation VLSI systems with aggressive dynamic voltage scaling. It is worth noting that the higher speed advan- tage at lower voltages is a common property of all high-mo- bility materials. The reason is that at high longitudinal elds the carrier velocity tends to saturate and the speed advantages of high-mobility materials are signi cantly reduced. Further- more, SiGe buffers generate much sharper edges (by up to 56%), which is bene cial from both the perfo rmance and consumption point of view (for example, this is very useful for local clock buffers). Interestingly, SiGe pMOSFETs show a lower on-current degradation when considering st aked transistors. Therefore, an even larger advantage is obtained by considering the joint

effect of bias supply voltage reduction and transistor stacking.

For example, the speed improvement reaches 1.74 at

600 mV and

that synthesis tools will tend to use high fan-in SiGe standard cells more frequently than Si technology. As a consequence, the composition of SiGe standard cell libraries is expected to be different from Si libraries, as higher fan-in cells must be included to take full advantage of the above feature. The more frequent adoption of high fan-in cells is well known to be advantageous from an energy efciency point of view [26]. The second conclusion is that SiGe technology offers a re- markably better power-delay trade-off for VLSI circuits with respect to their Si counterparts . In addition to the above-men- tioned SiGe speed advantages ob tained at similar leakage con- ditions, it was shown that SiGe technology exhibits a signi cant

power saving at iso-p erformance by approp riately reducing the SiGe supply voltage. For example, the dynamic (static) power

saving is 1.98

feature, leakage suppression through power gating with SiGe pMOSFETs is more effective tha n in Si circuits by a factor 1.4, as the former technology tends to reduce the size of sleep tran- sistors under the same requirements. To our knowledge, the reported advantages of the buried SiGe pMOSFETs for VLSI logic circuits overcome the ones reported for other high-mobilit y technologies (like Ge tech- nology), which suffer of excessive leakage penalty, thus suggesting that SiGe pMOSFET is a promising candidate for the next generations of CMOS VLSI circuits.

candidate for the next generations of CMOS VLSI circuits. . From a design perspective, this means
candidate for the next generations of CMOS VLSI circuits. . From a design perspective, this means

. From a design perspective, this means

CMOS VLSI circuits. . From a design perspective, this means (2.95 ) at 1 V. As

(2.95

VLSI circuits. . From a design perspective, this means (2.95 ) at 1 V. As a

) at

circuits. . From a design perspective, this means (2.95 ) at 1 V. As a further

1 V. As a further interesting

R EFERENCES

[1] “International Technology Roadmap for Semiconductors,” [Online]. Available: http://public.itrs.net [2] H.-S. P. Wong, “Beyond the conventional transistor,” IBM J. Res. De- velop., vol. 46, no. 2/3, pp. 133–168, 2002.

1494

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 8, AUGUST 2012

[3] A. Chandrakasan, W. Bowhill, and F. E. Fox , Design of High-Perfor- mance Microprocessor Circuits . New York: IEEE Press, 2001. [4] A. Chandrakasan et al., “Technologies for ultradynamic voltage scaling,” Proc. IEEE , vol. 98, no. 2, pp. 191–212, Feb. 2010. [5] S. G. Narendra a nd A. Chandrakasan , Leakage in Nanometer CMOS Technologies . New York: Springer, 2006. [6] B. Calhoun and A. Chandrakasan, “Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering,” IEEE J. Solid-State Circuits , vol. 41, no. 1, pp. 238–245, Jan. 2006. [7] M. E. Sinangil, N. Verma, and A. Chandrakasan, “A recon g- urable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in

65 nm CMOS,” IEEE J. Solid-State Circuits , vol. 44, no. 11, pp.

3163–3173, Nov. 2009. [8] M.-E. Hwang, A. Raychowdhury;, K. Keejong, and K. Roy, “A

8 FIR lter in

130 nm technology,” in Proc. IEEE Symp. VLSI Circuits , 2007, pp. 154–155. [9] Z. Bo, D. Blaauw, D. Sylvester, and K. Flautner, “Theoretical and

practical limits of dynamic voltage scaling,” in Proc. DAC , 2004, pp.

85 mV 40 nW process-tolerant subthreshold 8

DAC , 2004, pp. 85 mV 40 nW process-tolerant subthreshold 8 868–873. -ratio modulation for ultra-dynamic

868–873.

-ratio

modulation for ultra-dynamic voltage scaling,” in Proc. DATE , 2007, pp. 1–6. [11] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, “Leakage-delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.

16, no. 2, pp. 232–245, Feb. 2010. [12] P. Magnone, F. Crupi, M. Alioto , B. Kaczer, and B. De Jaeger, “Un- derstanding the potential and the limits of Germanium pMOSFETs for VLSI circuits from exper imental measurements,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 10.1109/TVLSI.2010.2053226 .

[13]

N. Collaert, P. Verheyen, K. De Meyer, R. Loo, and M. Caymax, “High- performance strained Si/SiGe pMOS devices with multiple quantum wells,” IEEE Trans. Nanotechnol. , vol. 1, no. 4, pp. 190–194, Dec.

[10]

M.-E. Hwang, T. Cakici, and K. Roy, “Process tolerant adaptive

Hwang, T. Cakici, and K. Roy, “Process tolerant adaptive 2002. [14] N. Collaert, P. Verheyen, K.

2002.

[14] N. Collaert, P. Verheyen, K. De Meyer, R. Loo, and M. Caymax, “In-

uence of the Ge-concentration and RTA on the device performance ofstrained Si/SiGe pMOS devices,” in Proc. Eur. Solid-State Device Res. Conf., 2002, pp. 263–266. [15] P. Majhi, P. Kalra, R. Harris, K. J. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B. J. Cho, S. Banerjee, W. Tsai, H. Tseng, and

R. Jammy, “Demonstration of high-performance PMOSFETs using

quantum wells with high- /metal-gate stacks,”

using quantum wells with high- /metal-gate stacks,” [16] IEEE Electron Device Lett. , vol. 29, no.
using quantum wells with high- /metal-gate stacks,” [16] IEEE Electron Device Lett. , vol. 29, no.

[16]

IEEE Electron Device Lett., vol. 29, no. 9, pp. 99–101, Sep. 2008.

S. H. Lee, P. Majhi, J. Oh, B. Sassman, C. Young, A. Bowonder, W.-Y. Loh, K.-J. Choi, B.-J. Cho, H.-D. Lee, P. Kirsch, H. R. Harris, W. Tsai,

S. Datta, H.-H. Tseng, S. K. Banerjee, and R. Jammy, “Demonstration of pMOSFETs with CHANNELS,
S.
Datta, H.-H. Tseng, S. K. Banerjee, and R. Jammy, “Demonstration
of
pMOSFETs with
CHANNELS,
HIGh
, and controlled Short Channel Effects

(SCEs),” IEEE Electron Device Lett., vol. 29, no. 9, pp. 1017–1020, Sep. 2008. [17] J. Franco, B. Kaczer, M. Cho, G. Eneman, and G. Groeseneken, “Im- provements of NBTI reliability in SiGe p-FETs,” in Proc. Int. Reliab. Phys. Symp., 2010, pp. 1082–1085.

[18]

J. Franco, B. Kaczer, G. Eneman, J . Mitard, A. Stesmans, V. Afanas’ev,

T.

Kauerauf, P. J. Roussel, M. Toledano-Luque, M. Cho, R. Degraeve,

T.

Grasser, L.-Å. Ragnarsson, L. Witters, J. Tseng, S. Takeoka, W.-E.

Wang, T. Y. Hoffmann, and G. Groeseneken, “6

pMOSFET with optimized reliability

NBTI lifetime target at ultra-thin EOT,” in IEDM Tech. Dig. , 2010, pp.

: Meeting the

EOT,” in IEDM Tech. Dig. , 2010, pp. : Meeting the EOT Si0.45Ge0.55 70–73. [19] A.

EOT Si0.45Ge0.55

70–73.

[19] A. Sadek, K. Ismail, M. A. Armstrong, D. A. Antoniadis, and F. Stern, “Design of Si/SiGe heterojunction complementary metal-oxide-semi- conductor transistors,” IEEE Trans. Electron Devices , vol. 43, no. 8, pp. 1224–1232, Aug. 1996. [20] C. Claeys, E. Simoen, S. Put, G. G iusi, and F. Crupi, “Impact strain

engineering on gate stack quality and reliability,” Solid-State Electron. , vol. 52, pp. 1115–1126, 2008. [21] R. Loo, C. Walczyk, P. Verheyen, R. Rooyackers, F. E. Leys, G. En- eman, D. Shamiryan, P. P. Absil, T. Delande, A. Moussa, H. Bender,

C. Drijbooms, L. Geenen, M. Caymax, J. W. Weijtmans, R. Wise, V.

Machkaoutsan, P. Tomasini, C. Arena, J. McCormack, S. Passefort,

H. Sorada, A. Inoue, B. C. Lee, S. Hyun, S. Jakschik, and S. Godny,

“Selective epitaxy of Si/SiGe to improve pMOS devices by recessed

source/drain and/or buried SiGe channels,” ECS Trans. , vol. 3, no. 7,

pp. 453–465, 2006.

[22] A. Hikavyy, R. Loo, L. Witters, S. Takeoka, J. Geypen, B. Brijs, C. Merckling, M. Caymax, and J. Dekoster, “SiGe SEG growth for buried channel p-MOS devices,” ECS Trans. , vol. 25, no. 7, pp. 201–210,

2009.

[23] D. K. Schroder, Semiconductor Material and Device Characteriza-

tion. New York: Wiley, 1998.

[24] M. Alioto, E. Consoli, and G. Palumbo, “Flip-op energy/performance versus clock slope and impact on the clock network design,” IEEE Trans. Circuits Syst. I, Reg. Papers , vol. 57, no. 6, pp. 1273–1286, Jun.

2010.

[25] B. Nikolic, “Design in the power-limited scaling regime,” IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 71–83, Jan. 2008.

Low-Voltage/Low-Power Integrated Circuits and Systems, E. Sánchez- Sinencio and A. G. Andreou, Eds. Piscataway, NJ: IEEE Press, 1999.

[26]

A. G. Andreou, Eds. Piscataway, NJ: IEEE Press, 1999. [26] Felice Crupi received the M.S. degree

Felice Crupi received the M.S. degree in elec-

tronic engineering from the University of Messina, Messina, Italy, in 1997 and the Ph.D. degree from

the University of Firenze, Firenze, Italy, in 2001.

Since 2002, he has been with the Dipartimento

di Elettronica, Informatica e Sistemistica, Univer-

sità della Calabria, Rende, Italy, as an Associate Professor of electronics . Since 1998, he has been a repeat Visiting Scientist with the Interuniversity Micro-Electronics Center (IMEC), Leuven, Bel- gium. In 2000, he was a Visiting Scientist with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. His main research interests include reliability of C MOS devices, modeling and simulation of CMOS devices, electrical charact erization techniques for solid state electronic devices, the design of ultra l ow noise electronic instrumentation and the design of extremely low power CMOS circuits. He has authored and coauthored over 70 pape rs published in peer-r eviewed journals and over 50 papers published in international conference proceedings. His publications have been cited more than 700 times and his h-index is equal to 14 (Scopus’s source). Prof. Crupi serves or served as a technical program committe member of the IEEE International Electron Devices Me eting (IEDM), and the IEEE Interna- tional Reliability Physics Symposium ( IRPS). He has been the Coordinator of international research projects in th e eld of semiconductor devices and circuits.

in th e fi eld of semiconductor devices and circuits. Massimo Alioto (M’01–SM’07) was bo rn

Massimo Alioto (M’01–SM’07) was bo rn in Brescia, Italy, in 1972. He received the Laurea degree in electronics engineerin g and the Ph.D. degree in electrical engineering from the Univer- sity of Catania, Catania, Italy, in 1997 and 2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dell’Informazione (DII), the Un iversity of Siena, Siena, Italy, as a Research Associate and in the same year as an Assistant Professo r. In 2005, he was ap- pointed Associate Professor of Electronics, and was engaged in the same faculty i n 2006. In the summer of 2007, he was a Visiting Professor at EPFL, Lausanne , Switzerland. In 2009–2011, he held a Visiting Professor position with BW RC, UCBerkeley, Berkeley, CA, investigating on next-generation ultra-lo w power circuits and wireless nodes. In 2011, he also holds a Visiting Professo r position with University of Michigan, investigating on technique for resilien cy in near-threshold processors and ultra-low power circuits. Since 2001 he has been teaching undergraduate and graduate courses on advanced VLSI digital design, microelectronics and basic electronics. He has authored or co-a uthored 170 publications on journals (60, mostly IEEE Transactions) an d conference proceedings. Two of them are among the most downloaded TVLS I papers in 2007 (respectively, 10th and 13th). He is co-author of the book Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and S CL Digital Circuits (Springer, 2005). His primary research interests include ultra-low power VLSI circuits and wireless nodes,

sub-

efcient on-chip power converters for sub-

W operation, modeling/design of

W cryptograph ic circuits, ultra-low standby power SRAMs, highly

ic circuits, ultra-low standby power SRAMs, highly variability-tol erant low-leakage VLSI CMOS cir cuits,
ic circuits, ultra-low standby power SRAMs, highly variability-tol erant low-leakage VLSI CMOS cir cuits,

variability-tol erant low-leakage VLSI CMOS cir cuits, circuit techniques for emerging techno logies. He is the director of the Electronics Lab at University of Siena (site of Arezzo). Prof. Alioto is a m ember of the HiPEAC Network of Excellence. He is the Chair of the “ VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society, for which he was also Distinguished Lecturer in 200 9-2010 and member of the DLP Coordinating Committee in 2011–2012. He i s regularly invited to give t alks and tutorials to academic institutions , conferences, and companies throughout the world. He serves or

CRUPI et al.: BURIED SILICON-GERMANIUM P MOSFET S

has served as a member of various conference technical program committees (ISCAS, ICCD, PATMOS, ICM, ECCTD, CSIE) and Track Chair (ISCAS, ICCD, ICECS, ICM). He was Technical Program Chair of the conference ICM 2010. He serves as Associate Editor of the IEEE T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI) S YSTEMS , as well as of the Microelec- tronics Journal , the Integration–The VLSI journal , the Journal of Circuits, Systems, and Computers, the Journal of Low Power Electronics and Applica- tions and the ACM Transactions on Design Automation of Electronic Systems . He was Guest Editor of the Special Issue “Advances in Oscillator Analysis and Design” of the Journal of Circuits, Systems, and Computers (2010), and Technical Program Chair for the ICM 2010 Conference.

Jacopo Franco received the B.Sc. and M.Sc. degrees in electronic engineering from the University of Cal- abria, Calabria, Italy, in 2005 and 2008, respectively. He is currently pursuing the Ph.D. degree in the re- liability group of imec and at the Katholieke Univer- siteit Leuven, Leuven, Belgium, on the topic “Inter- face stability and reliability of Ge and III-V transis- tors for future CMOS applications”. His M.Sc. thesis was developed at imec, Leuven, Belgium, and it is related to reliability issues in ad- vanced Silicon and Germanium MOSFETs. He has authored or co-authored over 30 publications. Mr. Franco was a recipient of the IEEE SISC Ed Nicollian Award for the Best Student Paper in 2009.

SISC Ed Nicollian Award for the Best Student Paper in 2009. Paolo Magnone received the B.S.

Paolo Magnone received the B.S. and M.S. degrees in electronic engineering from the University of Cal- abria, Rende, Italy, in 2003 and 2005, respectively, and the Ph.D. degree in el ectronic engineering from the University of Reggio Calabria, Italy, in 2009. In the period 2006–2008, he joined for one year the Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium, within the “Advanced PROcess Technologies for Horizontal Integration” Project (Marie Curie Actions), where he worked on parameters extraction and matching analysis of FinFET devices. He was a Postdoctoral Researcher with the University of Calabria from 2009 to 2010. He is currently with the ARCES Center, Univer- sity of Bologna. His research interests include the electrical characterization, electrothermal simulation and modeling of semiconductor devices, and the numerical simulation of photovoltaic silicon solar cells.

numerical simulation of photovoltaic silicon solar cells. Ben Kaczer received the M.S. degree in physical electronics

Ben Kaczer received the M.S. degree in physical electronics from Charles U niversity, Prague, Czech Republic, in 1992 and the M.S. and Ph.D. degrees in physics from The Ohio State University, Columbus, in 1996 and 1998, respectively. He is a Senior Reliability Scientist with IMEC, Leuven, Belgium. In 1998, he joined the reliability group of IMEC, Leuven, Belgium, where his activ- ities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric lms, planar and multiple-gate FETs, circuits, and characterization of Ge/III-V and MIM de- vices. He has authored or co-authored over 250 journal and conference papers. Dr. Kaczer received the OSU Presidential Fellowship and support from Texas Instruments, Inc. for his Ph.D. research on the ballistic-electron emission mi- croscopy of SiO2 and SiC lms. He was a recipient of three Best and one Out- standing Paper Awards at IRPS and the Best Paper Award at IPFA. He has pre- sented invited papers and tutorials at sev eral international conferences. He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, and WoDiM Conferences. He is currently serving on the IEEE T. Electron Dev. Ed- itorial Board.

serving on the IEEE T. Electron Dev. Ed- itorial Board. 1495 Guido Groeseneken (F’05) received the

1495

Guido Groeseneken (F’05) received the M.Sc. degree and the Ph.D. degree in applied sciences from the KU Leuven, Belgium, in 1980 and 1986, respectively. In 1987, he joined the R&D Laboratory, IMEC, Leuven, Belgium. He is responsible for research in reliability physics for deep submicrometer CMOS technologies and in nanotechnology for post-CMOS applications. From October 2005 until April 2007, he was responsible for the Post CMOS Nanotechnology program within IMEC’s core partner research pro- gram. Since 2001, he is a Professor with the KU Leuven, where he is Program Director of the Master in Nanoscience and Nanotechnology and coordinating a European Erasmus Mundus Master Program in nanoscience and nanotech- nology. He has made contributions to the elds of non-volatile semiconductor memory devices and technology, reliability physics of VLSI-technology, hot carrier effects in MOSFET’s, time-dependent dielectric breakdown of oxides, Negative-Bias-Temperature Instability effects, ESD-protection and -testing, plasma processing induced damage, electrical characterization of semiconduc- tors and characterization and reliab ility of high k dielectrics. Recently he has also interest in such as carbon nanotubes for interconnect applications, tunnel FET’s for alternative nanowire devices, etc. Dr. Groeseneken became an IMEC Fellow in 2007. He has served as a technical program committee member of several international scientic con- ferences, such as IEDM, ESSDERC, IRPS, SISC, and EOS/ESD Symposium. He has authored or co-authored over 500 publications in international scientic journals and in international conference proceedings, 6 book chapters, and 10 patents in his elds of expertise.

chapters, and 10 patents in his fi elds of expertise. Jérôme Mitard received the Ph.D. degree

Jérôme Mitard received the Ph.D. degree in micro- electronic engineering from the Polytechnic Univer- sity School of Marseille, Marseille, France, in 2003. For three years, he acted as an STMicroelectronics assignee with “Commissariat Energie Atom- ique–Laboratoire d’électronique et de technologie de l’information”, Grenoble, France, where he was deeply involved in the electrical characterization of hafnium-based dielectrics with metal gate for sub-70-nm complementary metal–oxide–semicon- ductor (CMOS) technologies. After his Ph.D. in microelectronics at Micro and Nanotech nologies Campus Center, Grenoble, France, he joined the Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium, as a device researcher, where he is currently working on the integra- tion of high-mobility substrates for the sub-22-nm CMOS node.

of high-mobility substrates for the sub-22-nm CMOS node. Liesbeth Witters received the B.Sc. and M.Sc. degrees

Liesbeth Witters received the B.Sc. and M.Sc. degrees in chemical engi neering from Katholieke Universiteit Leuven, Leuven, Belgium and ENSPM, Paris, France in 1992 and 1993, respectively. From 1994 to 1995, she did graduate research work at the Civil Engineering Department, Uni- versity of California, Irvine. In 1995, she joined Rockwell Semiconductor Systems, later Conexant, in Newport Beach, CA, where she worked as a CMP Process Development Engineer. In 2001, she joined IMEC, Leuven, Belgium, as a BiCMOS Process Integration Engineer. Since 2 004 she has been working on different applications in the CMOS Process Integration Department.

applications in the CMOS Process Integration Department. Thomas Y. Hoffmann received the Ph.D. degree from Lille

Thomas Y. Hoffmann received the Ph.D. degree from Lille University, Villeneuve d’Ascq, Lille, France, in 2000. He joined Intel Corporation’s Research and De- velopment Group, Hillsboro, OR, as a Technology Computer-Aided Design Engineer for sub-90-nm technologies. In 2004, he moved to Intel’s Tech- nology Development Group as a Device Engineer for 45-nm process development. In 2005, he joined Interuniversity Microelectronics Center, Leuven, Belgium, to lead the electrical characterization group for advanced silicon technologies. In 2009, he became the Director of the Front-End-of-Line Logic and D ynamic Random Access Memory Devices Research Program. He has authored or coauthored approximately 50 technical papers for publication in journals a nd presentations at conferences.

authored or coauthored approximately 50 technical papers for publication in journals a nd presentations at conferences.