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2/19/13

ASIC-System on Chip-VLSI Design: Clock Gating

ASIC-System on Chip-VLSI Design

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Clock Gating
Clock tree consume more than 50 % of dynamic power. The components of this power are: 1) Power consumed by combinatorial logic whose values are changing on each clock edge 2) Power consumed by flip-flops and 3) The power consumed by the clock buffer tree in the design. It is good design idea to turn off the clock when it is not needed. Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted.

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RTL clock gating works by identifying groups of flip-flops which share a common enable control signal. Traditional methodologies use this enable term to control the select on a multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flipflop with clock enable capabilities. RTL clock gating uses this enable signal to control a clock gating circuit which is connected to the clock ports of all of the flip-flops with the common enable term. Therefore, if a bank of flip-flops which share a common enable term have RTL clock gating implemented, the flip-flops will consume zero dynamic power as long as this enable signal is false. There are two types of clock gating styles available. They are: 1) Latch-based clock gating 2) Latch-free clock gating.

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Latch free clock gating


The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on which flip-flops are triggered). Here if enable signal goes inactive in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or generate multiple clock pulses. This restriction makes the latch-free clock gating style

asic-soc.blogspot.com/2008/04/clock-gating.html

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2/19/13

ASIC-System on Chip-VLSI Design: Clock Gating

inappropriate for our single-clock flip-flop based design.

PIC18F Series Microcontroller The design uses the PIC18F series microcontroller. All the control functionalities of the system are built around this. Upgradeability is th... Clock Gating Clock tree consume more than 50 % of dynamic power. The components of this power are: 1) Power consumed by combinatorial log... Temperature controller using Microchip PIC16F877A Microcontroller In continuously monitoring the surrounding temperature of industrial applications Temperature Monitoring Control System play v... Power Planning There are two types of power planning and management. They are core cell power management and I/O cell power management . In former one VDD... Physical Design Questions and Answers I am getting several emails requesting answers to the questions posted in this blog. But it is very difficult to provide detailed answer ... Clock Tree Synthesis (CTS) The goal of CTS is to minimize skew and insertion delay. Clock is not propagated before CTS as shown in Figure (1). Figure (1) Ideal clock b... Transition Delay and Propagation Delay Transition Delay Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %( 80%) of its maximum ...

Latch free clock gating

Latch based clock gating


The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style.

Latch based clock gating

Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low power technique. Advantage of this method is that clock gating does not require modifications to RTL description.

References
[1] Frank Emnett and Mark Biegel, Power Reduction Through RTL Clock Gating, SNUG, San Jose, 2000 [2] PrimeTime User Guide You might also like: Power Gating Clock Definitions Power Gating Low Power Techniques: Clock Gating
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8 comments:
Anonymous November 4, 2008 at 10:59 PM Mention that one has to use negative-level sensitive latch for a posedge flop design. So I would prefer you indicating a bubble infront of

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latch Reply

Murali

November 5, 2008 at 9:36 AM

you are right......... thanks for the observation ! Reply

Anonymous December 30, 2008 at 5:17 AM So how does the timing between the neg-edge latch and the pos-edge flop look like ? I am not sure if it's a half-cycle path or a full cycle path. Can you please clarify if possible. Reply

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Another ASIC Designer January 16, 2009 at 3:03 PM Or use a pos-edge flip-flip instead of a latch. (For gating pos-edge clocked flip-flops.) Then you don't have to use latches, which can make DFT harder in some cases. Reply

Anonymous June 25, 2010 at 5:20 PM If someone is not using Library available hard cell for clock gating , and writing it's own code for the same , how will the user make sure for timing analysis for this ?? How to define constraints for the same. ??? Reply

vijay September 3, 2010 at 1:15 AM Can timing diagrams for latch based gating be included too? The bubble on the latch has also not been included? Reply

Anonymous February 4, 2011 at 12:38 AM Hi Murali, Nice explanation. Why your latch & flip flop symbols are same ? Can you please update the latch symbol. Reply

Anonymous April 15, 2012 at 9:43 PM I believe it is not good practice to use the triangle symbol on the input to a level-sensitive latch. The triangle denotes edge-triggered, which is correct for the main, master-slave flip flops, but the glitch-removing latch is a transparent one. Reply
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