Topic10 Introduction To The Analog To Digital Subsystem On The Freescale MC9S12X.

Topic Video 10
Analog: Its not all digital these days...
10
Monday, 2 November 2009
Analog to Digital Conversion

The analog subsystem is crucial in any embedded application. The real world is analog, not digital. So converting the real world into a form the processor can understand is very important. The analog to digital subsystem is responsible for converting an analog signal into a digital representation.

An Analog to Digital converter can transform analog signals into a digital word that the processor can understand. This digital word can vary in size depending on the particular A/D subsystem. Word sizes supported by A/D subsystems 8 bit 10 bit 12 bit 16 bit 24 bit 32 bit
The A/D subsystem allows the possible range of input analog voltages to be limited using two reference voltages: VRH (Highest possible input voltage) Any input voltage higher than this value will result in the highest possible digital word value. VRL (Lowest possible input voltage) Any input voltage lower than this value will result in the lowest possible digital word value (zero).
Analogue to Digital Conversion

So if the lowest digital token (zero) represents VRL, and the highest digital token represents VRH. Then any voltage within this range would follow a linear relationship.
Relationship digital token and input analog voltage if VRH=5V, VRL=0V, and AD word size is 8 bits.
What is the relationship?

If we have a xed word size and a know voltage range we can work it out. If we have a word size of 8 bits then we can represent 256 different numbers (256 different voltages between VRL and VRH). The voltage difference between each digital number is =(VRH - VRL) / (2word_size-1)
If we had an 8 bit A/D, where VRL = 0 V and VRH = 5V, then =(5-0)/(28-1) =5/255 =0.01960 Volts =19.6mV
The relationship between analog input voltage (Vi) and the resulting digital token (Dt) is Dt =
,Vi < VRL ,VRL Vi VRH ,Vi > VRH
(Vi-VRL)/
Max

Exercise
Assume an A/D system with a 12 bit word size and VRH and VRL set to 3V and 1V respectively, calculate
and the digital token values for the following voltages,

1.89Volts 2.4Volts 4.5 Volts

Exercise (Answers)
=(VRH-VRL)/2word_size - 1 =(3-1)/(212-1) =2/4095 =0.000488 Volts =488Volts
10

Exercise (Answers)
Dt =
(Vi-VRL)/
Max
1.89V since it is greater than VRL and less than VRH would be Dt = (Vi-VRL)/ = (1.89-1)/0.000488 = 1823
11

Exercise (Answers)
Dt =
(Vi-VRL)/
Max
2.4V since it is greater than VRL and less than VRH would be Dt = (Vi-VRL)/ = (2.4-1)/0.000488 = 2868
12

Exercise (Answers)
Dt =
(Vi-VRL)/
Max
4.5V since it is greater than VRH would be Dt = 212-1 = 4095
13
Aside: Digital 2 Analog
14
How is it done?
Vi
S/H
Comparator
D/A
Dt
Weights Array Control Logic
Init Reset
Clock Shift Register
There are many ways of converting analog signals into digital tokens. The most common method used in micro-controllers is the successive approximation approach.
15
How is it done?
Vi
S/H
Comparator
D/A
Dt
Init Reset
Clock 100 Shift Register
3 bit example assuming VRH = 5V and VRL = 0V

Monday, 2 November 2009 16
How is it done?
3.8V Vi S/H
Comparator
D/A
Dt
Init Reset
Clock 100 Shift Register

How is it done?
3.8V Vi S/H
Comparator
D/A
Dt
100 Weights Array
Control Logic Init Reset Clock 100 Shift Register

How is it done?
3.8V Vi S/H
Comparator
2.5V
D/A
Dt
100 Weights Array

How is it done?
3.8V Vi S/H
Comparator
2.5V
D/A
Dt
100 Weights Array
1

How is it done?
3.8V Vi S/H
Comparator
D/A
Dt
100 Weights Array

How is it done?
3.8V Vi S/H
Comparator
D/A
Dt
110 Weights Array

How is it done?
3.8V Vi S/H
Comparator
3.75V
D/A
Dt
110 Weights Array

How is it done?
3.8V Vi S/H
Comparator
3.75V
D/A
Dt
110 Weights Array
1

How is it done?
3.8V Vi S/H
Comparator
D/A
Dt
110 Weights Array

How is it done?
3.8V Vi S/H
Comparator
D/A
Dt
111 Weights Array

How is it done?
3.8V Vi S/H
Comparator
4.375V
D/A
Dt
111 Weights Array

How is it done?
3.8V Vi S/H
Comparator
4.375V
D/A
Dt
111 Weights Array
0

How is it done?
3.8V Vi S/H
Comparator
4.375V
D/A
Dt
111 Weights Array
0

How is it done?
3.8V Vi S/H
Comparator
4.375V
D/A
Dt 110
Weights Array
0

On-Chip A/D Subsystem
The MC9S12XDP512 contains two (S12ATD10B8CV3) 8 channel 10 bit successive approximation A/D subsystems. The external reference voltages VRH and VRL are set to 5V and GND respectively on the Adapt9S12X board. It also has external trigger pins, that can be used to initiate a sampling of the analog inputs. A bit like the IRQ interrupt pin, but specically for the A/D subsystem.
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Bus Clock
Clock Prescaler Trigger Mux
ATD clock
ATD10B8C
On-Chip A/D Subsystems

A/D Sampling Clock Pre-scaler A/D Triggering Mechanism
ETRIG0 ETRIG1 ETRIG2 ETRIG3 (See Device Overview chapter for availability and connectivity)
Mode and Timing Control
Sequence Complete Interrupt
ATDCTL1
ATDDIEN
PORTAD VDDA VSSA VRH VRL Successive Approximation Register (SAR) and DAC
Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7
AN7 AN6
Components of the Successive Approximation A/D converter Result Registers
+ Sample & Hold 1 1 Analog Comparator
AN5 AN4 AN3 AN2 AN1 AN0 MUX
Figure 5-1. ATD Block Diagram
Analog Multiplexer
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The physical interface

Analog input pins of the A/D subsystem are labelled AN0-AN15. The pins AN0-AN15 can be used as general purpose digital input when the A/D subsystem is not in use.
ATD0
ATD1
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The Programmers Model
All interaction with the AD subsystems is done via there I/O register sets.
ATDxCTL0 ATDxCTL1 ATDxCTL2 ATDxCTL3 ATDxCTL4 ATDxCTL5 ATDxDRXH ATDxDRXL ATDxSTAT0 ATDxSTAT1 ATDxDIEN ATDxPTAD
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Controlling the A/D

The 6 control registers of the A/D allow you to congure the A/D in the way that is suitable for your application. Following is an in-depth look at these registers.
ATDxCTL0 ATDxCTL1 ATDxCTL2 ATDxCTL3 ATDxCTL4 ATDxCTL5
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Controlling the A/D

ATDxCTL0
0 0 0 0 0 WRAP2 WRAP1 WRAP0
WRAP2-WRAP0
Channel number to wrap from. When doing multiple conversions this register denes when the analog multiplexer should switch back to AN0 (or AN8). It will switch back to AN0 (or AN8) after sampling the channel dened in this register.
25
Controlling the A/D

ATDxCTL1
ETRIGSEL
ETRIGCH2
ETRIGCH1
ETRIGCH0
ETRIGSEL
0 - Selects a analog input channel as the triggering source. 1 - Selects one of the triggering channels as the triggering source.
ETRIGCH2-ETRIGCH0
This number represents the triggering source.
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Controlling the A/D

ATDxCTL2
ADPU AFFC AWAI
ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACIF
ADPU (ATD Power Up) 0 disable subsystem 1 enable subsystem It takes approximately100useconds for the analog circuits stabilize. Once the subsystem is powered all registers are reset to there default state. AFFC (ATD Fast Flag Clear All) 0 means ATD ag clearing operates normally (A read to ATDSTAT0 and the appropriate result register is required to clear the corresponding CCF ag).
1 means only a read to the result register is required to reset the CCF ag.
Controlling the A/D

ATDxCTL2
ADPU AFFC AWAI
ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACIF
AWAI (ATD Wait Mode) 0 continues to run when in wait mode 1 doesnt run when in wait mode ETRIGLE 0 means edge triggered 1 means level triggered ETRIGP (work in combination with ETRIGLE) 0 means falling edge or low level 1 means rising edge or high level
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Controlling the A/D

ATDxCTL2
ADPU AFFC AWAI
ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACIF
ETRIGE 0 means disable external trigger 1 means enable external trigger ASCIE (ATD Sequence Complete Interrupt Enable) 0 disable ATD interrupt (default) 1 enable ATD interrupt ASCIF (ATD Sequence Complete Interrupt Flag 0 = No ATD interrupt occurred 1 = An ATD interrupt occurred.
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Table 5-7. ATDCTL3 Field Descriptions (continued)
Controlling the A/D

Field 2 FIFO Description
ATDxCTL3
0 S8C S4C
Result Register FIFO Mode If this bit is zero (non-FIFO mode), the A/D conversion results map into registers based on the conversion sequence; the result of the rst conversion appears in the rst resul the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conv sequence; sequential conversion results are placed in consecutive result registers. In a continuously conversion sequence, the result register counter will wrap around when it reaches the end of the resu le. The conversion counter value (CC2-0 in ATDSTAT0) can be used to determine where in the resu le, the current conversion result will be placed. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clea conversion counter even if FIFO=1. So the rst result of a new conversion sequence, started by writin ATDCTL5, will always be place in the rst result register (ATDDDR0). Intended usage of FIFO mode is c conversion (SCAN=1) or triggered conversion (ETRIG=1). Finally, which result registers hold valid data can be tracked using the conversion complete ags. Fast mode may or may not be useful in a particular application to track valid data. 0 Conversion results are placed in the corresponding result register up to the selected sequence len 1 Conversion results are placed in consecutive result registers (wrap around at end).
S2C
S1C
FIFO
FRZ1
FRZ0
S8C-S1C Sets the number of conversions that should take place.

S8C 0 0 0 0 0 0 0 0 1 S4C 0 0 0 0 1 1 1 1 X S2C 0 0 1 1 0 0 1 1 X S1C 0 1 0 1 0 1 0 1 X
10 FRZ[1:0]
Background Debug Freeze Enable When debugging an application, it is useful in many cases to ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD wil to a breakpoint as shown in Table 5-9. Leakage onto the storage node and comparator reference capac compromise the accuracy of an immediately frozen conversion depending on the length of the freeze
Table 5-8. Conversion Sequence Length Coding

Number of Conversions per Sequence 8 1 2 3 4 5 6 7 8
Table 5-9. ATD Behavior in Freeze Mode (Breakpoint)
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Controlling the A/D

ATDxCTL3
0 S8C S4C S2C S1C FIFO FRZ1 FRZ0
FIFO Denes the behavior of the results registers. 0 means the results are stored in the corresponding registers. 1 means the results are stored in consecutive registers (wrap around at ATDDR15). FRZ1-FRZ0 Sets the behavior in freeze mode (halted during debugging).
31
Controlling the A/D

A/D Clock selection and Sampling Time
The time it takes for a sample to be performed can be programmed from 18 to 32 ATD clock cycles. Further more, the ATD clock frequency can be programmed using the prescaler bits (PRS4-PRS0) to produce an ATD clock in the range of 500 kHz to 2 MHz. ATDxCTL4
SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
SRES8 Sets the word size of the A/D. 0 means a 10 bit word size for the result. 1 means an 8 bit word size for the result.
32
Controlling the A/D

ATDxCTL4
SMP1-SMP0 (Sample time select) Set the length of time for sampling the analog input. Using these two bit you set how long the sample and hold circuit can charge.
33
Controlling the A/D

ATDxCTL4
PRS4-PRS0 (ATD Clock Prescaler) Set the frequency of the ATD clock. The relationship between the ATD clock and the Bus Clock (8MHz) is shown below
34
Controlling the A/D

ATDxCTL5
DJM DSGN SCAN MULT 0 CC CB CA
DJM (Result Register Data Justication) 0 means left justied. 1 means right justied. DSGN (Result Data Register Signed or Unsigned) 0 means unsigned data representation in Result Register. 1 enable signed data representation in Result Register.
35
Controlling the A/D

ATDxCTL5
DJM+DSGN
36
Controlling the A/D

ATDxCTL5
SCAN (Continuous Conversion Sequence Mode) 0 means single conversion sequence. 1 means continuos operation. MULT (Multi-channel sample mode) 0 means sample only one channel. 1 means sample across several channels.
37
SRES8 1 1 1 0 0 0
DJM 0 0 1 0 0 1
DSGN 0 1 X 0 1 X
Description and Bus Bit Mapping 8-bit / left justied / unsigned bits 815 8-bit / left justied / signed bits 815 8-bit / right justied / unsigned bits 07 10-bit / left justied / unsigned bits 615 10-bit / left justied / signed bits 615 10-bit / right justied / unsigned bits 09
Controlling the A/D

Table 5-15. Left Justied, Signed, and Unsigned ATD Output Codes
Input Signal VRL = 0 Volts VRH = 5.12 Volts Signed 8-Bit Codes 7F 7F 7E Unsigned 8-Bit Codes FF FF FE 81 80 7F Signed 10-Bit Codes
ATDxCTL5
DJM
Unsigned 10-Bit Codes
DSGN
5.120 Volts 5.100 5.080 2.580 2.560 2.540
SCAN
MULT
7FC0 7F00 7E00 0100 0000 FF00
CC
FFC0 FF00 FE00 8100 8000 7F00
CB
CA
CD-CA (Analog Input Channel Select Code) Select the analog Input. 81 0100 8100 01 0.020 0000 8000 00 80 0.000 A write to this register will start the conversion process.
Table 5-16. Analog Input Channel Select Coding
CC 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
01 00 FF
38
Result Registers
ATDxDRXH & ATDxDRXL
The result of the A/D conversion are stored in the appropriate result register. Since the A/D has a 10 bit word size the result is stored a 16 bit result register made up of ATDxDRxH:ATDxDRxL in which the result is either right or left justied. The results be read when the conversion is completed, this is signalled b either an A/D interrupt being triggered or the SCF bit in ATDxSTAT0 is set.
ATDxDRXH
ATDxDRXL
39
Status of the A/D

Finding out what the AD is doing is as simple as looking at the values in the two status registers.
ATDxSTAT0 ATDxSTAT1
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Status of the A/D
ATDxSTAT0
SCF 0 ETORF FIFOR 0 CC2 CC1 CC0
SCF
0 means a conversion in progress 1 means all conversions are complete ETORF 0 means no external trigger overrun has occurred. 1 means an external trigger overrun has occurred. FIFOR 0 means no FIFO overrun has occurred. 1 means a FIFO overrun occurred.
CC2 CC0
Channel number that just completed a conversion.

41
Status of the A/D
ATDxSTAT1
CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 CCF7
CCF7-CCF0
0 means conversion number X is yet to completed. 1 means conversion number X has completed.
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Using AN0-AN15 for Digital Input...

IEN7
Each analog input pin can be individually switch from analog input to digital input using the ATDxDIEN register. ATDxDIEN
IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0
IENX
0 means the corresponding pin is used for analog input. 1 means the corresponding pin is used for digital input.
43
Using AN0-AN15 for Digital Input...

PTAD7
The digital byte can be read from the ATDxPTAD register. ATDxPTAD (ATD1PTAD or ATD0PTAD0)
PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
44
Using the A/D
There are two modes of operating the A/D system
Polled Mode, or Interrupt Mode
45
Polled Mode

Using polled mode requires the use of a spin lock. Firstly the A/D system is congured as required: It is enabled, the type and number of conversion congured, the triggering type setup and the interrupts are disabled. The conversion process is started by writing the desired value to ATD0CTL5. The program then needs to wait until the conversion is complete before reading the result. The SCF ag in the ATD0STAT0 register is set once the conversion is complete. So it will require a spin lock like SPIN: BRCLR ATD0STAT0,$80, SPIN
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Polled Mode
Example
mainloop: SpinLock: JSR InitAD MOVB #$00, ATD0CTL5 BRCLR ATD0STAT0,$80,SpinLock LDD .... Spin InitAD: BRA Spin MOVB #$80,ATD0CTL2 ; Turn on A/D Subsystem LDX #820 DBNE OFF X,* ; Delay a minimum of 100us MOVB #$E0,ATD0CTL2 ; Turn on A/D Subsystem,External Trigger and Interrupts MOVB #$08,ATD0CTL3 ; One conversion, FIFO off MOVB #$60,ATD0CTL4 ; Set Max sample time, 10 bit and Fast ATD Clock RTS ATD0DR0H
47
Interrupt Mode
As with polled mode, the A/D system is congured as required:
It is enabled, the type and number of conversion congured, the triggering type setup and the interrupts are enabled. The conversion process is started by writing the desired value to ATD0CTL5.
The program then needs to wait until the conversion is complete before reading the result. However it can continue on to another task and doesnt need to wait for the result. The ISR will take care of processing the result for it once i is ready.
48
Interrupt Mode
Example
MOVB #$F7,IVBR mainloop: Spin InitAD: JSR InitAD MOVB #$00, ATD0CTL5 BRA Spin MOVB #$80,ATD0CTL2 ; Turn on A/D Subsystem LDX #820 DBNE X,* ; Delay a minimum of 100us MOVB #$E2,ATD0CTL2 ; Turn on A/D,External Trigger OFF and Interrupts ON MOVB #$08,ATD0CTL3 ; One conversion, FIFO off MOVB #$60,ATD0CTL4 RTS ATDISR: LDD .... RTI ORG $FFD2 DC.W ATDISR ; Set up Interrupt Vector Table ; ATD Vector ATD0DR0H ; Set Max sample time, 10 bit and Fast ATD Clock
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Topic10 Introduction To The Analog To Digital Subsystem On The Freescale MC9S12X.

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Topic Video 10

Analog: Its not all digital these days...

Monday, 2 November 2009

Analog to Digital Conversion

Monday, 2 November 2009

Analog to Digital Conversion

Monday, 2 November 2009

Analog to Digital Conversion

Monday, 2 November 2009

Analogue to Digital Conversion

Monday, 2 November 2009

What is the relationship?

Monday, 2 November 2009

What is the relationship?

Monday, 2 November 2009

What is the relationship?

,Vi < VRL ,VRL Vi VRH ,Vi > VRH

Monday, 2 November 2009

What is the relationship?

and the digital token values for the following voltages,

1.89Volts 2.4Volts 4.5 Volts

What is the relationship?

=(VRH-VRL)/2word_size - 1 =(3-1)/(212-1) =2/4095 =0.000488 Volts =488Volts

Monday, 2 November 2009

What is the relationship?

,Vi < VRL ,VRL Vi VRH ,Vi > VRH

Monday, 2 November 2009

What is the relationship?

,Vi < VRL ,VRL Vi VRH ,Vi > VRH

Monday, 2 November 2009

What is the relationship?

,Vi < VRL ,VRL Vi VRH ,Vi > VRH

4.5V since it is greater than VRH would be Dt = 212-1 = 4095

Monday, 2 November 2009

Aside: Digital 2 Analog

Monday, 2 November 2009

Clock Shift Register

Monday, 2 November 2009

Clock 100 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

Clock 100 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

Control Logic Init Reset Clock 100 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

Control Logic Init Reset Clock 100 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

3 bit example assuming VRH = 5V and VRL = 0V

Control Logic Init Reset Clock 010 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

Control Logic Init Reset Clock 010 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

Control Logic Init Reset Clock 010 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

3 bit example assuming VRH = 5V and VRL = 0V

Control Logic Init Reset Clock 001 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

Control Logic Init Reset Clock 001 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

Control Logic Init Reset Clock 001 Shift Register

3 bit example assuming VRH = 5V and VRL = 0V

3 bit example assuming VRH = 5V and VRL = 0V

3 bit example assuming VRH = 5V and VRL = 0V

3 bit example assuming VRH = 5V and VRL = 0V