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A CMOS Voltage Controlled Oscillator and Frequency Tripler for 22 27 GHz Local Oscillator Generation
Pei-Kang Tsai, Chih-Yu Liu, and Tzuen-Hsi Huang, Member, IEEE
AbstractThis letter presents a CMOS voltage-controlled oscillator (VCO) and frequency tripler integration for 2227 GHz local oscillator (LO) generation. An 8 GHz wideband VCO provides the fundamental and second harmonic signals which are directly fed into the frequency tripler for frequency mixing. The tripler generates an output frequency in the range of 2227 GHz. This integration is implemented and fabricated using a 0.18 2 . The measured CMOS process. The total chip area is 0.66 frequency tuning range (FTR) of the VCO increases from 7.28 to 9.11 GHz as the tuning voltage increases from 0 to 1.8 V. The output frequency range of the tripler covers a wide band of 5.5 GHz (22.4%) ranging from 21.83 to 27.33 GHz. Overall, the core circuits of this integration consume 11.1 mW. At a frequency offset of 1 MHz from the centre frequency, the measured phase noises of the VCO and frequency tripler are and , respectively. The calculated gure of merit with frequency tuning range . T is


101 dBc Hz


112 dBc Hz 185 4 dBc Hz

Index TermsFrequency tripler, integration design, local oscillator (LO), millimeter-wave, voltage-controlled oscillator (VCO), wideband.

frequency range. For the frequency multiplier design, a nonlinear differential amplier has been used as a frequency tripler in [3]; however, it suffers from high power consumption and poor sub-harmonic rejection. Quadrature VCO (QVCO) with frequency doubler using pinchoff clipping has been proposed in [4], but QVCO usually consumes more chip area and dc power. A Gilbert cell mixer has been used as frequency doubler [5], but it has many input ports directly connected to the VCO output nodes. The mixer will cause overloading of capacitive parasitics that degrades the FTR directly. This letter presents the direct combination of a VCO with a frequency tripler for a 2227 GHz LO generation. Unlike the circuit topology in [6], the power consumption can be saved without inserting a buffer stage between the VCO and the mixer. The second harmonic in the common node of the cross-coupled pair is peaked with shunt-peaking technique [7]. Shunt-peaking at second harmonic can improve the phase noise in VCO [7] which leads to low phase noise in frequency tripler output. II. CIRCUIT DESIGN Fig. 1(a) shows the function block diagram of our proposal. The second harmonic of the VCO output frequency is obtained and peaked at the common node of the cross-coupled pair with shunt-peaking technique. By mixing the differential and ) with the second harmonic fundamental signals ( ) can be produced at the ( ), two frequency terms ( output nodes of an inductive-loaded differential mixer. The inductor load ( ) as well as the parasitic capacitance of the mixer acts as a bandpass lter (BPF) that peaks at frequency and lters out the fundamental frequency ( ). By doing so, it accomplishes the desired frequency tripling. The proposed circuit is shown in Fig. 1(b). To widen the operation frequency range and improve the phase noise performance after frequency tripling, the VCO itself needs a wide tuning range as well as good phase noise. The capacitance tuning ratio of a VCO can be expressed as (1) and are the maximum and minimum where varactor capacitances, respectively, and is the xed parasitic capacitance. It derives from (1) that the frequency tuning range can be maximized by either increasing the varactor capacitance or decreasing the parasitic capacitance. Nevertheless, a higher varactor capacitance generally results in degradation of the quality factor of the LC-tank. Therefore,

I. INTRODUCTION HE demand for wideband transceivers has increased rapidly with the development of millimeter-wave (mm-wave) systems such as the 60 GHz wireless personal area network (WPAN) [1] and radar systems [2]. The wideband mm-wave phase-locked loop (PLL) is an important building block in wideband transceivers. The voltage-controlled oscillator (VCO) and the rst-stage frequency divider of a prescaler in a mm-wave PLL are the most critical to the broadband operation among all building blocks in the PLL. The combination of a low-frequency VCO and a frequency multiplier to achieve the desired mm-wave source had been widely adopted for broadband PLL applications [3][6]. In general, MOS varactors can have a wider tuning capability and a better quality factor when they are operating at comparatively low frequencies. The trade off between the tuning range and phase noise of a VCO at low mm-wave frequency range will become easier than that are operated at high mm-wave

Manuscript received May 01, 2011; revised June 29, 2011; accepted July 19, 2011. Date of publication August 15, 2011; date of current version September 02, 2011. The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: n2896135@mail.ncku.;; Color versions of one or more of the gures in this letter are available online at Digital Object Identier 10.1109/LMWC.2011.2163060

1531-1309/$26.00 2011 IEEE



Fig. 1. (a) Function block diagram and (b) the circuit schematic of the proposed VCO and frequency tripler integration.

in our VCO design, the NMOS-only cross-coupled pair ( ) is adopted for negative resistance generation. Such an NMOS-only structure introduces fewer parasitic capacitance as compared to the CMOS structure or the PMOS-only ) structure. Accumulation-type MOS varactors ( ratio are used to provide the appropriate ) at 8 GHz. The (401 fF/144 fF) with a good quality factor ( is 1.62 nH with a quality factor of 13.6 at 8 GHz. inductor This particular topology requires a lower operation frequency (i.e., 7.39 GHz) for achieving an output signal ranging from 2227 GHz. Therefore, it has a greater possibility of attaining the tuning range specication of the VCO as compared to that of a VCO directly operated around the 24 GHz band. The phase noise can be optimized according to the operation frequency range at around 8 GHz instead of 24 GHz, in which the passive components have a better quality factor. The common node , which in this VCO core provides the output voltage and the parasitic is peaked by a resonator composed of capacitance connected to the source ends of the cross-coupled pair ( ). This shunt-peaking for second harmonic can also improve phase noise of VCO by noise ltering [7]. A common source buffer is also integrated to drive the 50 instrument load when taking measurements. A single-balanced mixer is employed as the frequency tripler. As shown in Fig. 1(b), this mixer includes an RF transconductance stage ( ), an LO switch pair ( ), an output inductor ( ), and a latch transistor pair ( ). The latch transistor pair is designed for IF switching enhancement. resonates with the total parasitic capacitance The inductor ( ) contributed by the switching stage, latch transistor pair, resonator acts as a BPF that and output buffers. This provides a high load impedance of three times the VCO frequency and lters out other unwanted signals. Finally, to facilitate measurement, output buffers with a two-stage conguration are also integrated to drive the instrument load. III. EXPERIMENTAL RESULTS The photograph of the complete integrated circuit is shown in Fig. 2. The VCO core consumes 3 mW at a supply voltage of 0.9 V and the frequency multiplier consumes 8.1 mW at 1.2 V. The total chip area is 0.72 mm 0.91 mm. As shown in Fig. 3, the measured tuning ranges and phase noises at 1 MHz offset

Fig. 2. Vhip photograph of the proposed circuit.

Fig. 3. Simulation and measured results of tuning range and phase noise versus the tuning voltage of the proposed circuit.

over the entire tuning range (from 0 to 1.8 V) are compared with the simulation results. Fig. 4 shows the output power of the frequency tripler ( ) as well as that of the sub-harmonics ) from the output over the entire frequency range. ( and After calibrating the cable loss, the power level of the tripler to . The power frequency ( ) ranges from suppression of the VCO frequency ( ) at the output is even better than 18 dB in the worst case. The phase noises of the VCO core and frequency multiplier were measured by a signal source analyzer set (Agilent E5052B + E5053A). Fig. 5 shows . At a frequency offset the measured phase noise at of 1 MHz from the center frequency, the phase noise of the whereas that of the frequency tripler is VCO is . The noise degradation of 11 dB is close to the theoretical value of 9.5 dB estimated for the tripler frequency multiplication. Table I compares the performance of our proposed design with previously reported works. A VCO in [8] has the widest tuning range; however, its power consumption is quite high. The transformer-based current-reused VCO [9] has a wide tuning




Fig. 4. Measured power levels of the tripler frequency (3f ) and the sub-harmonic signals (2f and f ) at the frequency tripler output.

Fig. 5. Measured phase noises of the VCO and the frequency tripler at V 0 V.

[1] A. M. Niknejad and H. Hashemi, mm-Wave Silicon Technology 60 GHz and Beyond. New York: Springer Science+ Business Media, LLC, 2007, ch. 1, pp. 124. [2] I. Gresham et al., Ultra-wideband radar sensors for short-range vehicular applications, IEEE Trans. Microw. Theory Tech., vol. 52, no. 9, pp. 21052122, Sep. 2004. [3] M. Danesh, F. Gruson, P. Abele, and H. Schumacher, Differential VCO and frequency tripler using SiGe HBTs for the 24 GHz ISM band, in IEEE RFIC Symp. Dig., Jun. 2003, pp. 277280. [4] S. Ko, J. -G. Kim, T. Song, E. Yoon, and S. Hong, K- and Q-bands CMOS frequency sources with X-band quadrature VCO, IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp. 27892800, Sep. 2005. [5] G. Bu, A. R. Tavakoli, and K. Entesari, A 24 GHz indirect VCO in 0.18 m CMOS technology, in Proc. Microw. Integr. Circuits Conf., Oct. 2008, pp. 7174. [6] G. Huang and V. Fusco, A 94 GHz wide tuning range SiGe bipolar VCO using a self-mixing technique, IEEE Microw. Wireless Compon. Lett., vol. 21, no. 2, pp. 8688, Feb. 2011. [7] E. Hegazi, H. Sjland, and A. A. Abidi, A ltering technique to lower LC oscillator phase noise, IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 19211930, Dec. 2001. [8] K. Kwok and J. R. Long, A 23-to-29 GHz transconductor-tuned VCO MMIC in 0.13 m CMOS, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 28782886, Dec. 2007. [9] Y.-H. Kuo, J.-H. Tsai, and T.-W. Huang, A 1.7-mW, 16.8% frequency tuning, 24-GHz transformer-based LC-VCO using 0.18-m CMOS technology, in IEEE RFIC Symp. Dig., Jun. 2009, pp. 7982. [10] J. Kim, J. O. Plouchart, N. Zamdmer, R. Trzcinski, K. Wu, B. J. Gross, and M. Kim, A 44 GHz differentially tuned VCO with 4 GHz tuning range in 0.12 m SOI CMOS, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 416417.

range and low power consumption; however, it has higher phase noise, possibly because of the low quality factor of the varactors at 24 GHz. Among the previous works that integrate a VCO and a frequency multiplier [3][6], our design has the widest tuning . range as well as the best IV. CONCLUSION CMOS process, we have successfully Using a 0.18 presented a compact integration design consisting of a widetuning VCO and a wideband frequency tripler for a 2227 GHz LO generator. The integration of a VCO core with a tripler without inter buffer stages can save the power consumption. MOS varactors operated at a lower frequency (8 GHz) have wider tuning capabilities but less quality factor degradation, and peaking the second harmonic of VCO with shunt-peaking technique [7] can also improve phase noise. Therefore, the designed VCO core can be optimized with a wider tuning range and better phase noise performance, resulting in high performance frequency tripler and overall circuit [10]. Finally, of this proposal for mm-wave LO applications is . calculated to be a remarkable value of