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A Modied Three-phase Four Wire UPQC Topology with Reduced DC-link Voltage Rating
Srinivas Bhaskar Karanki, Nagesh Geddada, Student Member, IEEE, Mahesh K. Mishra, Senior Member, IEEE, B. Kalyan Kumar, Member, IEEE

AbstractThe Unied Power Quality Conditioner (UPQC) is a custom power device, which mitigates voltage and current related power quality issues in the power distribution systems. In this paper, an UPQC topology for applications with non-stiff source is proposed. The proposed topology enables UPQC to have a reduced DC-link voltage without compromising its compensation capability. This proposed topology also helps to match the DClink voltage requirement of the shunt and series active lters of the UPQC. The topology uses a capacitor in series with the interfacing inductor of the shunt active lter and the system neutral is connected to the negative terminal of the DC-link voltage to avoid the requirement of the fourth leg in the Voltage Source Inverter (VSI) of the shunt active lter. The average switching frequency of the switches in the VSI also reduces, consequently the switching losses in the inverters reduce. Detailed design aspects of the series capacitor and VSI parameters have been discussed in the paper. A simulation study of the proposed topology has been carried out using PSCAD simulator and the results are presented. Experimental studies are carried out on three-phase UPQC prototype to verify the proposed topology. Index TermsAverage switching frequency, DC-link Voltage, UPQC, Hybrid topology, Non-stiff source.

I. I NTRODUCTION With the advancement of power electronics and digital control technology, the renewable energy sources are increasingly being connected to the distribution systems. On the other hand, with the proliferation of the power electronics devices, non-linear loads and unbalanced loads have degraded the power quality (PQ) in the power distribution network [1]. Custom power devices have been proposed for enhancing the quality and reliability of electrical power. Unied Power Quality Conditioner (UPQC) is a versatile custom power device which consists of two inverters connected back-toback and deals with both load current and supply voltage imperfections. UPQC can simultaneously perform as shunt and series active power lters. The series part of the UPQC is known as Dynamic Voltage Restorer (DVR). It is used to maintain balanced, distortion free nominal voltage at the load. The shunt part of the UPQC is known as Distribution STATic Compensator (DSTATCOM) and it is used to compensate load reactive power, harmonics and balance the load currents
Copyright (c) 2009 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to pubs-permissions@ieee.org. This work is supported by Department of science and Technology, India under the project grant SR/S3/EECE/048/2008. The authors are with the Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai-36, India. Email: balu.karanki@gmail.com, nagesh.mselectrical@gmail.com, mahesh@ee.iitm.ac.in, bkalyan@ee.iitm.ac.in.

thereby making the source current balanced and distortion free with unity power factor. Voltage rating of DC-link capacitor largely inuences the compensation performance of an active lter [2]. In general the DC-link voltage for the shunt active lter has much higher value than the peak value of the line to neutral voltage. This is done in order to ensure a proper compensation at the peak of the source voltage. In [3], the authors mentioned about the current distortion limit and loss of control limit, which states that the DC-link voltage should be greater than or equal to 6 times the phase voltage of the system for distortion free compensation. When the DC-link voltage is less than this limit, there is insufcient resultant voltage to drive the currents through the inductances so as to track the reference currents. The primary condition for reactive power compensation is that the magnitude of reference DC-bus capacitor voltage should be higher than the peak voltage at the point of common coupling (PCC) [4]. Due to the above mentioned criteria, many researchers have used a higher value of DC capacitor voltage based on applications [5][13]. Similarly, for series active lter the DC-link voltage is maintained at a value equal to the peak of the line to line voltage of the system for proper compensation [14][18]. In case of the UPQC, the DC-link voltage requirement for the shunt and series active lters is not the same. Thus, it is challenging task to have a common DC-link of appropriate rating in order to achieve satisfactory shunt and series compensation. The shunt active lter requires higher DClink voltage when compared to the series active lter for proper compensation. In order to have a proper compensation for both series and shunt active lter, the researchers are left with no choice rather than to select common DC-link voltage based on shunt active lter requirement. This will result in over rating of the series active lter as it requires less DC-link voltage compared to shunt active lter. Due to this criterion, in literature, a higher DC-link voltage based on the UPQC topology has been suggested [19][22]. With the high value of DC-link capacitor, the Voltage Source Inverters (VSIs) become bulky and the switches used in the VSI also need to be rated for higher value of voltage and current. This in turn increases the entire cost and size of the VSI. To reduce the DC-link voltage storage capacity, few attempts were made in literature. In [23], [24], a hybrid lter has been discussed for motor drive applications. The lter is connected in parallel with diode rectier and tuned at 7th harmonic frequency. Although an elegant work, the design is specic to the motor drive application and the reactive power

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compensation is not considered, which is an important aspect in UPQC applications. In case of the three-phase four wire system, neutral clamped topology is used for UPQC [25], [26]. This topology enables the independent control of each leg of both the shunt and series inverters, but it requires capacitor voltage balancing [27]. In [21], four leg VSI topology for shunt active lter has been proposed for three-phase four wire system. This topology avoids the voltage balancing of the capacitor, but the independent control of the inverter legs is not possible. To overcome the problems associated with the four leg topology, in [28], [29], the authors proposed a T-connected transformer and three-phase VSC based DSTATCOM. However, this topology increases the cost and bulkiness of the UPQC because of the presence of extra transformer. In this paper, an UPQC topology with reduced DC-link voltage is proposed. The topology consists of capacitor in series with the interfacing inductor of the shunt active lter. The series capacitor enables reduction in DC-link voltage requirement of the shunt active lter and simultaneously compensating the reactive power required by the load, so as to maintain unity power factor, without compromising its performance. This allows us to match the DC-link voltage requirements of the series and shunt active lters with a common DC-link capacitor. Further, in this topology the system neutral is connected to the negative terminal of the DC bus. This will avoid the requirement of the fourth leg in VSI of the shunt active lter and enables independent control of each leg of the shunt VSI with single DC capacitor. The simulation studies are carried out using PSCAD simulator and detailed results are presented in the paper. A prototype of three-phase UPQC is developed in the laboratory to verify the proposed concept and the detailed results are presented in this paper. II. C ONVENTIONAL AND P ROPOSED T OPOLOGIES OF UPQC In this section, the conventional and proposed topology of the UPQC are discussed in detail. Figure 1 shows the power circuit of the neutral clamped VSI topology based UPQC which is considered as the conventional topology in this study. Even though this topology requires two DC storage devices, each leg of the VSI can be controlled independently and tracking is smooth with less number of switches when compared to other VSI topologies [27]. In this gure, vsa , vsb and vsc are source voltages of phases a, b and c, respectively. Similarly, vta , vtb and vtc are terminal voltages . The voltages vdvra , vdvrb and vdvrc are injected by the series active lter. The three-phase source currents are represented by isa , isb and isc , load currents are represented by ila , ilb and ilc . The shunt active lter currents are denoted by if a , if b , if c and iln represents the current in the neutral leg. Ls and Rs represent the feeder inductance and resistance, respectively. The interfacing inductance and resistance of the shunt active lter are represented by Lf and Rf respectively and the interfacing inductance and lter capacitor of the series active lter are represented by Lse and Cse respectively. The load constituted of both linear and nonlinear loads as shown in this

gure. The DC-link capacitors and voltages across them are represented by Cdc1 = Cdc2 = Cdc and Vdc1 = Vdc2 = Vdc , respectively and the total DC-link voltage is represented by Vdbus (Vdc1 + Vdc2 = 2Vdc ). In this conventional topology, the voltage across each common DC-link capacitor is chosen as 1.6 times the peak value of the source voltages as given in [27]. Figure 2 represents the equivalent circuit of the proposed VSI topology for UPQC compensated system. In this topology the system neutral has been connected to the negative terminal of the DC bus along with the capacitor Cf in series with the interfacing inductance of the shunt active lter. This topology is referred to as modied topology. The passive capacitor Cf has the capability to supply a part of the reactive power required by the load and the active lter will compensate the balance reactive power and the harmonics present in the load. The addition of capacitor in series with the interfacing inductor of the shunt active lter will signicantly reduce the DC-link voltage requirement and consequently reduces the average switching frequency of the switches. This concept will be illustrated with analytic description in the following section. The reduction in the DC-link voltage requirement of the shunt active lter enables us to the match the DC-link voltage requirement with the series active lter. This topology avoids the over rating of the series active lter of the UPQC compensation system. The design of the series capacitor Cf and the other VSI parameters have signicant effect on the performance of the compensator. These are given in the next section. This topology uses a single DC capacitor unlike the neutral clamped topology and consequently avoids the need of balancing the DC-link voltages. Each leg of the inverter can be controlled independently in shunt active lter. Unlike the topologies mentioned in the literature [21], [25], [26], [30], this topology does not require the fourth leg in the shunt active lter for three-phase four wire system. The performance of this topology will be explained in detailed in the following section. III. D ESIGN OF VSI PARAMETERS The parameters of the VSI need to be designed carefully for better tracking performance. The important parameters that need to be taken into consideration while designing conventional VSI are Vdc , Cdc , Lf , Lse , Cse and switching frequency (fsw ). The design details of the VSI parameters for the shunt and series active lter are given in [31], [32]. Based on the following equations the parameters of the VSIs are chosen for study. A. Design of shunt active lter VSI parameters Consider the active lter is connected to an X kVA system and deals with 0.5X kVA and 2X kVA handling capability under transient conditions for n cycles. During transient, with an increase in system kVA load, the voltage across each DC-link capacitor (Vdc ) decreases and vice versa. Allowing a maximum of 25% variation in Vdc during transient, the differential energy (Ec ) across Cdc is give by Ec = [Cdc (1.125Vdc )2 (0.875Vdc )2 ] 2 (1)

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vsa N vsb vsc

isn

Rs Rs Rs

Ls Ls Ls

isa isb isc

vt

vdvra
vdvrb vdvrc

vla PCC vlb vlc

ila ilb ilc

Rla Rlb Rlc

Lla Llb Llc

iln

Cse Lse

Cse Lse

Linear load

Cse Lse Lf Saa Sbb Scc Vdc

i fn

ifa Lf Rf

ifb Lf Rf

ifc

Rnl Lnl
Non-linear load

Cdc
n'

Sa

Sb

Sc

Rf

S'aa

S'bb

S'cc

S'a

S'b

S'c

Vdc

Cdc

Fig. 1.

Equivalent circuit of neutral clamped VSI topology based UPQC.

vsa N vsb vsc

isn

Rs Rs Rs

Ls Ls Ls

isa isb isc

vt

vdvra
vdvrb vdvrc

vla PCC vlb vlc

ila ilb ilc

Rla Rlb Rlc

Lla Llb Llc

iln

Cse Lse Rsw

Cse Lse Rsw

Linear load

Cse Lse Rsw Saa Sbb Scc Vdbus S'aa S'bb S'cc Sa Sb Sc

Cf Lf Rf

Cf Cf ifa ifb ifc Lf Rf Lf Rf

Non-linear load

Rnl Lnl

Cdc
i fn

S'a

S'b

S'c

Fig. 2.

Equivalent circuit of proposed VSI topology for UPQC compensated system (Modied Topology).

The change in system energy (Es ) for a load change from 2X kVA to 0.5X kVA is Es = (2X X/2)nT. (2)

as 1.6 in the study. m= 1 1 fswmin /fswmax (4)

Equating 1 and 2, the DC-link capacitor value is given by Cdc = 2(2X X/2)nT . (1.125Vdc )2 (0.875Vdc )2 (3)

where, Vm is the peak value of the source voltage, X is the kVA rating of the system, n is number of cycles and T time period of each cycle. An empirical study has been carried out for various values of interfacing inductance values with the variation of the DC-link voltage in [31], with Vdc = mVm and it is found that m = 1.6 gives fairly good switching performance of the VSI. The approximate relationship between m and minimum (fswmin ), maximum switching frequency (fswmax ) is obtained by analysis of the VSI in [31] and this is given below. For switching frequency variation approximately from 6 kHz to 10 kHz, the value of m is 1.58, which is taken

Based on this, the shunt interfacing inductance has been derived taking into consideration of the maximum switching frequency and is given below [31] mVm Lf = (5) 4h1 fswmax where k1 (2m2 1) h1 = fswmax . (6) k2 4m2 Where, h1 is the hysteresis band limit, k1 and k2 are proportionality constants. B. Design of series active lter VSI parameters In order to make the series active lter system a rst order system, a resistor is added in series with the lter capacitor, referred as switching band resistor (Rsw ) [32].

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The rms value of the capacitor current can be expressed 2 as Ise = Iinv Il2 . Iinv is the series inverter current rating and Il is the load current. The capacitor branch current is divided into two components - a fundamental current Ise1 , corresponding to the fundamental reference voltage (Vref 1 ) and a switching frequency current Isw , corresponding to the band voltage (Vsw ). The DVR voltage and the current of the capacitor are given by, Vdvr = Ise =
2 2 Vref 1 + Vsw 2 Ise1

TABLE I S YSTEM PARAMETERS

System Quantities System voltages Feeder impedance Linear Load Non-linear Load Shunt VSI parameters Series VSI parameters Series interfacing transformer PI controller gains Hysteresis band

2 Isw

Values 230 V (line to neutral), 50 Hz Zs = 1 + j3.141 Zla = 34 + j47.5 , Zlb = 81 + j39.6 , Zlc = 31.5 + j70.9 three-phase full bridge rectier load feeding a R-L load of 150 -300 mH Cdc = 2200 F, Lf = 26 mH, Rf = 1 Vdbus = 2 Vdc = 1040 V (Conventional), Vdbus = 560 V(Proposed) Cse =80 F, Lse = 5 mH Rsw = 1.5 1:1, 100 V and 700 V A Kp = 6, Ki = 5.5 h1 = 0.5 A, h2 = 6.9 V

Vref 1

h2 Vsw = Isw Rsw = 3 Ise1 = Ise1 Xse1 = 2f1 Cse

(7)

where h2 is the hysteresis band voltage. The resistance (Rsw ) and the capacitance (Cse ) values are expressed in terms of band voltage vsw and rated references voltage (Vref 1 ) respectively and are given by Rsw = Cse h2

Isw 3 Ise1 = Vref 1 2f1

(8)

non linear components of currents are very rare and most of the electrical loads are combination of the linear inductive and non-linear loads. Under these conditions the proposed topology will work efciently. The design of the value of Cf is carried out at the maximum load current, i.e., with the minimum load impedance to ensure that the designed Cf will perform satisfactorily at all other loading conditions. If Smax is the maximum kVA rating of a system and Vbase is the base voltage of the system, then the minimum impedance in the system is given as Zmin =
2 Vbase = |Rl + jXl | (say). Smax

The interfacing inductor Lse has been designed based on the switching frequency of the series active lter and is given by Lse (Vbus )Rsw = 4fswmax h2 (9)

(10)

where Vbus is the total DC-link voltage across both the DClink capacitors. A design example is illustrated for a rated voltage of 230 V line to neutral and the DC-link voltage reference (Vdcref ) of the conventional VSI topology has been taken as 1.6 Vm for each capacitor [27], [31]. The hysteresis band (h1 ) is taken as 0.5 A. From equation (5) the interfacing inductance (Lf ) is computed to be 26 mH. The base kVA rating of the system is taken as 5 kVA. Using equation (3), Cdc is computed and found to be 2200 F. The rated series VSI voltage is chosen as 50% of the rated voltage i.e. the maximun injection capacity of the series active lter is 115 V . The hystersis band (h2 ) for series active lter is taken as 3% of the rated voltage i.e 6.9 V . The maximun switching frequency of the IGBT based inverter is taken as 10 kHz. The series active lter current rating is choosen as 8 A and the rated load current as 7 A. Using the equations (7) to (9), the lter capaciotr Cse , the band resistor Rsw and interfacing inductance Lse are calcluated to be 80 F, 1.5 and 5 mH respectively. The system parameters are given in Table I for the conventional VSI topology. C. Design of Cf for the proposed VSI topology The design of the Cf depends upon the value to which the DC-link voltage is reduced. In general, loads with only

In order to achieve the unity power factor, the shunt active lter current needs to supply the required reactive component of the load current i.e., the fundamental imaginary part of the lter current should be equal to the imaginary part of the load current. The lter current and load current in a particular phase are given below I f ilter = Vinv1 Vl1 Rf + j(Xlf Xcf ) Vl1 Rl + jXl (11) (12)

I load =

where, Xlf = 2f Lf , Xl = 2f Ll , Xcf =1/ 2f Cf and f is the supply frequency of fundamental voltage. Neglecting the interfacing resistance and equating the imaginary parts of the the above equations gives (13) Vl1 Xl Vinv1 Vl1 (Xlf Xcf ) = 2 Rl + Xl2 (Xlf Xcf )2 (13)

where, Vinv1 and Vl1 are the line to neutral rms voltage of the inverter and the PCC voltage at the fundamental frequency respectively. The fundamental component of inverter voltage in terms of DC-link voltage is described in [33], is given as below Vinv1 = 0.612Vdc . 2 3 (14)

In general, if the lter current (If ) ows from the inverter terminal to the PCC, the voltage at the inverter terminal should

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be at a higher potential. Due to this reason, in conventional VSI topologies, the DC-link voltage is maintained higher than the voltage at the PCC. Equations (15) and (16) give the KVL along the lter branch for conventional topology and the proposed modied topology respectively. uVdc vl = Lf 1 Cf dif + Rf if dt (15)

dif + Rf if dt (16) dif (uVdc vcf ) vl = Lf + Rf if dt Where, u attains values of 1 or -1 depending on the switching of the inverter. In (16), the fundamental voltage across the capacitor (vcf 1 ) adds to the inverter terminal voltage (uVdc ) when the load is inductive in nature. This is because, when the load is inductive in nature, the fundamental of the lter current leads the voltage at the PCC by 90o for reactive power compensation and thus the fundamental voltage across the capacitor again lags the fundamental lter current by 90o . Therefore, the fundamental voltage across the capacitor will be in phase opposition to the voltage at the PCC. Thus, the fundamental voltage across the capacitor adds to the inverter terminal voltage. This allows us to rate the DC-link voltage at lower value than conventional design. The designer has a choice to choose the value of DClink voltage to be reduced, such that the LC lter in the active lter leg of each phase offers minimum impedance to the fundamental frequency and higher impedance for switching frequency components. In the modied topology along with the series capacitor in the shunt active lter, the system neutral is connected to the negative terminal of the DC bus capacitor. This will introduce a positive DC voltage component in the inverter output voltage. This is because, when the top switch is ON, +Vdbus appears at the inverter output and 0 V appears when the bottom switch is ON. Thus the inverter output voltage will have DC voltage component along with the AC voltage. The DC voltage is blocked by the series capacitor and thus the voltage across the series capacitor will be having two components, one is the AC component, which will be in phase opposition to the PCC voltage and the other is the DC component. Whereas, in case of the conventional topology the inverter output voltage varies between +Vdc when top switch is ONand Vdc when the bottom switch ON. Similarly when a four leg topology is used for shunt active lter with a single DC capacitor, the inverter output voltage varies between +Vdbus and Vdbus . Therefore, these topologies does not contain any DC component in the inverter output voltage. The modied topology contains only one DC capacitor as the neutral is directly connected to the negative terminal of the DC bus, thus it avoids the need of balancing of capacitor voltages, which is a major disadvantage of the neutral clamped topology [6], [34]. Since the neutral wire is directly connected to the negative terminal of the DC bus, the necessity of fourth leg in the inverter is avoided. In case of the four leg based VSI topology, independent control is not possible. In (uVdc if dt) vl = Lf

the modied topology, the three legs of the shunt active lter are independently controlled and this results in the automatic tracking of the neutral current. Thus, the modied topology has the advantage of both the neutral clamped topology and four leg inverter topology. From the system parameters mentioned in Table I, phase-a load impedance is chosen as Zmin . The DC bus voltage is chosen to be 560 V for the modied topology, such that it matches with the DC-link voltage requirement of the series active lter (peak of the line to line voltage). Using equation (13), the value of the the capacitor (Cf ) is obtained to be 65 F. IV. G ENERATION OF R EFERENCE C OMPENSATOR C URRENTS UNDER U NBALANCED AND D ISTORTED VOLTAGES In this work, the load currents are unbalanced and distorted, these currents ow through the feeder impedance and make the voltage at terminal unbalanced and distorted. The series active lter makes the voltages at PCC balanced and sinusoidal. However, the voltages still contains switching frequency components and they contains some distortions. If these terminal voltages are used for generating the shunt lter current references, the shunt algorithm results in erroneous compensation [35]. To remove this limitation of the algorithm, + + fundamental positive sequence voltages vla1 (t), vlb1 (t) and + vlc1 (t) of the PCC voltages are extracted and are used in control algorithm for shunt active lter [35]. The expressions for reference compensator currents are given in (17). In this equation, Plavg is the average load power, Ploss denotes the switching losses and ohmic losses in actual compensator and it is generated using a capacitor voltage PI controller. The term Plavg is obtained using a moving average lter of one cycle window of time T in seconds. The term is the desired phase angle between the source voltage and current. i a = ila i = ila f sa
+ + + vla1 + (vlb1 vlc1 ) (Plavg + Ploss ) + 1 + + v + + (vlc1 vla1 ) (Plavg + Ploss ) i b = ilb i = ilb lb1 f sb + 1 + + v + + (vla1 vlb1 ) (Plavg + Ploss ) i c = ilc i = ila lc1 f sc + 1 (17)

where, =
j=a,b,c

+ (vlj1 )2 , = tan/ 3

The above algorithm gives balanced source currents after compensation irrespective of unbalanced and distorted supply. The reference voltages for series active lter are given as
vdvri = vli vti

i = a, b, c

(18)

where vli represents the desired load voltages in three-phases and vdvri represents the reference series active lter voltages.

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Once the reference quantities and the actual quantities are obtained from the measurements, the switching commands for the VSI switches are generated using hysteresis band current control method [36]. Hysteresis current controller scheme is based on a feedback loop, generally with two-level comparators. The switching commands are issued whenever the error limit exceeds a specied tolerance band h. Unlike the predictive controllers, the hysteresis controller has the advantage of peak current limiting capacity apart from other merits such as extremely good dynamic performance, simplicity in implementation and independence from load parameter variations. The disadvantage with this hysteresis method is that the converter switching frequency is highly dependent on the AC voltage and varies with it. The switching control law for shunt active lter is given as If if a i a + h1 then bottom switch is turned ON whereas f top switch is turned OFF (Sa = 0, Sa = 1) If if a i a - h1 then top switch is turned ON whereas f bottom switch is turned OFF (Sa = 1, Sa = 0) similarly the switching commands for series active lter is given as If vdvra vdvra + h2 then bottom switch is turned ON whereas top switch is turned OFF (Saa = 0, Saa = 1) If vdvra vdvra - h2 then top switch is turned ON whereas bottom switch is turned OFF (Saa = 1, Saa = 0) The control circuitry for both the topologies is same and is shown in Fig. 3. Only six switching commands are to be generated. These six signals along with the complementary signals will control all the 12 switches of the two inverters.
vt abc * vdvr abc
i
* f abc

10.0 5.0

ila

ilb

ilc

Current (A)

iln

0.0 -5.0

-10.0 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

(a)
400 300 200

vta

vtb

vtc

Voltage (V)

100 0 -100 -200 -300 -400 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

(b) Fig. 4. Simulation results before compensation (a) Load currents (b) Terminal voltages.

vdvr abc
Hysteresis controller Inverter gating circuit

vl*abc

saa sbb scc sa sb sc

i f abc
Vdc bus
* dc bus

Reference current generation using eqn. (17)

vlabc

Positive sequence extraction

vl abc
il abc

PI controller

Ploss

Plavg

Power calculation using moving average filter (MAF)

Fig. 3.

Control block diagram for UPQC.

V. S IMULATION R ESULTS In order to validate the proposed topology, simulation is carried out using graphic-driven simulation software PSCAD. The same system parameters which are given Table I with additional Cf for a desired DC-link voltage are used to carry out simulation studies. The simulation results for both the conventional topology and the proposed modied topology are presented in this section for better understanding and comparison between both the topologies. The load currents and terminal (PCC) voltages before compensation are shown in Fig. 4. The load currents are unbalanced and distorted as shown in Fig. 4(a), the terminal voltages are also unbalanced and distorted because these load

currents ow through the feeder impedance in the system as shown in Fig. 4(b). Figure 5 gives the simulation results of the UPQC using conventional VSI topology. The DC-link voltages across the top and bottom DC-link capacitors are shown in Fig. 5(a). Using PI controller the voltage across both DC capacitors are maintained constant to a reference value of 520 V as shown in the gure. The source currents after compensation are balanced and sinusoidal as shown in Fig. 5(b). The voltage across the interfacing inductor in phase-a is shown in Fig. 5(c). The peak to peak voltage across the inductor is 1040 V. The three-phase shunt compensator currents are depicted in Fig. 5(d). Figure 5(e) represents the compensation performance of the series active lter. A sag of 50% is considered in all phases of the the terminal voltages for 5 cycles, which start from 1.9 seconds and ends at 2.0 seconds. The compensated DVR voltages and load voltages after compensation are shown in the same gure. The load voltages are maintained to the desired voltage using series active lter. The simulation results with the modied topology are shown in Fig. 6 and Fig. 7. In this topology The value of the capacitor (Cf ) in the shunt active lter branch is chosen to be 65 F and total DC bus voltage is maintained at 560 V . The voltage across the series capacitor in phase-a (vcf a ) and the phase-a load voltage (vla ) are shown in Fig. 6(a). From this gure it is clear that the voltage across the capacitor is in phase opposition to the terminal voltage. According to (16), the voltage across the capacitor adds to the DC-link voltage and injects the required compensation currents into the PCC. The inverter output voltage in leg-a is shown in Fig. 6(b). The inverter output voltage varies between 0 V and +Vdbus , which will introduce a DC component along with the AC components. Fast Fourier Transformer (FFT) for the voltage across the series capacitor (vcf a ) and inverter output voltage (vinva ) has been applied. The rms value of the fundamental and the DC components are shown in Fig. 6(c) for both vcf a and vinva . The same DC component will be reected across

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600 400

500 400

Vdc1
Voltage (V)

vla

vcfa

300 200 100 0 -100 -200 -300 -400 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Voltage (V)

200 0 600 400 200 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

Vdc 2

Time (s)

Time (s)

(a)
600

(a)
10.0 5.0

vinva

isa

isb isn

isc
Voltage (V)

500 400 300 200 100 0 1.9800 1.9850 1.9900 1.9950 2.0000

Current (A)

0.0 -5.0

-10.0 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

(b)
300

Time (s)

vcfadc
vcfa

(b)
Voltage (V)
900 600 300

200 100

vcfafund
vinvdc

vinda

300 200 100 0

Voltage (V)

0 -300 -600 -900 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

vinva
0.0 1.0 2.0 3.0 4.0

vinvfund
5.0

Time (s)

(c)
Time (s)

(c)
10.0 5.0 0.0 -5.0 -10.0

i fa

Fig. 6. Simulation results with modied topology (a) Voltage across series capacitor and load voltage in phase - a (b) Inverter output voltage in leg - a of shunt active lter (c) FFT of the voltage across series capacitor and inverter output voltage.

Current (A)

10.0 5.0 0.0 -5.0 -10.0 10.0 5.0 0.0 -5.0 -10.0 1.9600

i fb

i fc
1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

(d)
500 250 0 -250 -500

vta

vtb

vtc

Voltage (V)

300 150 0 -150 -300 500 250 0 -250 -500 1.860 1.880 1.900

vdvra

vdvrb

vdvrc

vla

vlb

vlc

1.920

1.940

1.960

1.980

2.000

2.020

2.040

Time (s)

(e) Fig. 5. Simulation results using conventional topology (a) DC capacitor voltages (top and bottom) (b) Source currents after compensation (c) Voltage across the interfacing inductor in phase-a of the shunt active lter (d) Shunt active lter currents (e) Terminal voltages with sag, DVR injected voltages and load voltages after compensation.

the series capacitor voltage (vcf a ) as shown in the Fig. 6(c). The DC bus voltage (Vdbus ) is shown in Fig. 7(a). The source currents after compensation using modied topology are shown in Fig. 7(b). The load voltages are maintained to the desired voltage using series active lter. The voltage across the inductor is shown in Fig. 7(c), the peak to peak voltage is 560 V, which is far lesser than the voltage across the inductor using conventional topology. As the voltage across inductor is high in case of conventional topology , the rate of rise of lter dif current dt will be higher than that of modied topology. This will allow the lter current to hit the hysteresis boundaries at a faster rate and increases the switching, whereas in modied topology the number of switchings will be less. Thus, the average switching frequency of the switches in the proposed topology will be less as compared to conventional topology. Since the average switching is less, the switching loss will also decrease in modied topology. Figure 7(e) represents the compensation performance of the series active lter. The shunt compensator currents are displayed in Fig. 7(d), which are identical to the currents obtained using conventional topology. A sag of 50% is considered in all phases of the the terminal voltages for 5 cycles, which start from 1.9 seconds and ends at 2.0 seconds. The compensated DVR voltages and load voltages after compensation are shown in the same gure. One more advantage of having less voltage across the inductor is that the hysteresis band violation will be less. This

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TABLE II THD OF S OURCE C URRENTS AND T ERMINAL VOLTAGES

Voltage (V)

600 500 400 300 200 100 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

Vdbus

THD (%) isa isb isc vla vlb vlc

Without Compensation 9.2 11.7 12.75 5.99 5.86 6.17

Conventional Topology 2.96 3.20 2.55 1.48 1.59 2.10

Modied Topology 1.59 2.19 1.31 1.12 1.24 1.58

Time (s)

(a)
10.0 5.0

TABLE III AVERAGE S WITCHING F REQUENCY OF THE I NVERTER S WITCHES ( K H Z )

Voltage (V)

isa

isb

isc

Leg

a b c

Shunt active lter Conventional Modied Topology Topology 3.96 3.10 4.12 2.44 3.95 2.98

Series active lter Conventional Modied Topology Topology 8.10 6.80 8.30 7.20 8.40 7.40

0.0 -5.0

isn

-10.0 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

(b)

will improve the quality of compensation and Total Harmonic Distortion (THD) reduces in the proposed topology. Similarly, the switching in the series active lter also reduces marginally as the DC-link voltage is reduced. The THD of the source currents and load voltages before and after compensation in all the three-phases are given in Table II. Table III gives the average switching frequency in each leg of the inverter. This clearly shows the modied topology performance is better than the conventional topology with a less DC-link voltage, reduction in switching operation and regular tracking of reference compensator currents. VI. E XPERIMENTAL S TUDIES The efcacy of the proposed scheme is veried with experimental studies. A DSP-based prototype of the three-phase UPQC has been developed in the laboratory. The system parameters UPQC are the same as given in Table I, with the source voltage rms value of 100 V. The experimental set up uses the SEMIKRON build two pulse inverters for realizing the series lter voltages and shunt lter currents. Two DSPs TMS320F2812 are used to process the data in digital domain. The signal and logic level consist of Hall effect voltage and current transducers, signal conditioning and protection circuits along with isolated DC power supplies. The threephase power quantities (voltages and currents) are converted to low level voltage signals using Hall effect voltage and current transducers. In the experimental set-up, the voltage is scaled down from 500 V range to 5 V range and a current of 10 A in the power network is converted to 5 V using the Hall effect voltage and current transducers respectively. These signals are further conditioned using signal conditioning circuit and given to the DSPs. The DSPs also receive a signal from the synchronizing circuit to realize reference quantities in time domain. The DSP is connected to the host computer through a parallel port. C codes are written in the DSP using code composer studio, CCS V3.3. The control algorithm in the DSP generates switching pulses to the VSI. The switching commands generated by the DSPs are issued through its general purpose input and output port. These pulses are then

400 300 200

vinda

Voltage (V)

100 0 -100 -200 -300 -400 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

(c)
10.0 5.0 0.0 -5.0 -10.0

i fa

Current (A)

10.0 5.0 0.0 -5.0 -10.0 10.0 5.0 0.0 -5.0 -10.0 1.9600

i fb

i fc
1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

(d)
500 250 0 -250 -500

vta

vtb

vtc

Voltage (V)

300 150 0 -150 -300 500 250 0 -250 -500 1.860 1.880 1.900

vdvra

vdvrb

vdvrc

vla

vlb

vlc

1.920

1.940

1.960

1.980

2.000

2.020

2.040

Time (s)

(e) Fig. 7. Simulation results using modied topology (a) DC capacitor voltages (b) Source currents after compensation (c) Voltage across the interfacing inductor in phase-a of the shunt active lter (d) Shunt active lter currents (e) Terminal voltages with sag, DVR injected voltages and load voltages after compensation.

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ila ilb ilc

10 A/div

Vdbus
vsa
vsb

500 V/div 200 V/div

iln

4 A/div

vsc

(a) (a)
vta
152 V/div
200 V/div

vdvra vdvrb

vtb
vdvrc

vtc

(b) (b)
vla

Fig. 8. Experimental results (a) Load currents before compensation (b) Terminal voltages before compensation.

vlb
200 V/div

vlc

passed through the blanking circuit to include a dead time in order to prevent short circuit of the capacitor through switches in the same VSI leg. The blanking circuit also receives STOP signals from the protection circuit to ensure safe operation of the set-up, in case of any abnormality in the system. The blanking circuit output pulses are given to the VSI through the driver circuit. ELGAR SW5500M SmartWave AC power source is used to generate the required voltage wave shapes to conduct experimental studies. In this experimental studies, both the conventional and proposed topologies are developed and experiments are performed for comparison. For the conventional topology, the DC-link voltage for each capacitor is maintained to 225 V (1.6 vm ). The DC-link voltage for each capacitor is taken as 125 V for the modied topology, such that the series capacitor value is 65 F same as simulation studies from equation (13). The load currents and the terminal voltages before compensation are shown in Fig. 8. The source and load currents are same before compensation and they are distorted and unbalanced. The terminal voltages are also distorted because of the feeder impedance. The THD of the source currents and terminal voltages before compensation are given in Table IV.
TABLE IV THD OF S OURCE C URRENTS AND T ERMINAL VOLTAGES

vsa

(c)
4 A/div

i fa i fb i fc

(d)
isa
10 A/div

isb
isc

isn

4 A/div

(e) Fig. 9. Experimental results using conventional topology (a) DC bus voltage (Vdbus ) and source voltages with 50% sag (b) Series active lter injected voltages (c) Load voltages after compensation (d) Shunt lter currents (e) Source currents after compensation.

THD (%) isa isb isc vla vlb vlc

Without Compensation 10.85 13.47 14.68 5.25 5.74 5.64

Conventional Topology 4.45 3.75 3.20 3.05 3.95 3.10

Modied Topology 3.45 2.80 2.70 2.60 3.60 2.70

The experimental results with the conventional topology are shown in Figs. 9(a)-9(e). The three-phase source voltages with 50% sag and the DC bus voltage are shown in Fig. 9(a). PI

controller is used to maintain the DC-link voltage at 225 V across each capacitor for the source voltage rms value of 100 V. The series active lter injected voltages are given in Fig. 9(b). The load voltages after compensation are shown in Fig. 9(c) along with the phase-a source voltage. The sag in the source voltages are mitigated by the series active lter injected votlages and the load voltages are maintained to the desired voltage. The lter currents which are injected into the PCC to make the source currents balanced and sinusoidal are shown in

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Fig. 9(d). The source currents after compensation are shown in Fig. 9(e). The source currents are balanced and sinusoidal, though the switching frequency components are still present. The load voltage and the voltage across the the series capacitor in phase-a for the neutral clamped topology with series capacitor is shown in Fig. 10(a). Both the voltages are in phase opposition with respect to each other as explained earlier. The same waveforms for the modied topology are shown in Fig. 10(b) and it can be observed that the voltage across the series capacitor contains the DC component and also in phase opposition to the load voltage (vla ). The performance of these two topologies will be same except the voltages across the series capacitor and inverter output voltage differ, so the results for the modied topology are discussed in this paper.

Vdbus
vsa

500 V/div 200 V/div

vsb vsc

(a)
200 V/div

vdvra vdvrb
vdvrc

v (50 V/div) cfa

(b)

vla (100 V/div)

vla
200 V/div

vlb vlc

(a)

vsa

(c)

vcfa

100 V/div
4 A/div

i fa

vla

200 V/div

i fb i fc

(b) Fig. 10. Load voltage and voltage across series capacitor in phase - a (a) Neutral clamped topology (b) Modied topology. (d)
10 A/div

The experimental results with the proposed modied topology are shown in Figs. 11 and 12. The compensation performance of the UPQC in phase-a with the modied topology is shown in Fig. 11. The gure clearly shows the simultaneous performance of the shunt and series active lter of the UPQC by compensating the load current and maintaining the load voltage to the desired value during voltage sag duration.
vsa
vla isa
200 V/div

isa isb
isc isn

(e) Fig. 12. Experimental results using modied topology (a) DC bus voltage (Vdbus ) and source voltages with 50% sag (b) Series active lter injected voltages (c) Load voltages after compensation (d) Shunt lter currents (e) Source currents after compensation.

ila

10 A/div

Fig. 11. Compensation performance of the UPQC in phase-a using modied topology.

The DC-link voltage across the DC capacitor is maintained at 250 V as mentioned earlier. The source voltages with sag and the DC bus voltage are shown in Fig. 12(a). The series

active lter injected voltages are represented in Fig. 12(b). The load voltages after compensation are shown in Fig. 12(c), they are balanced and sinusoidal. The sag in the source voltages are mitigated by the series active lter injected voltages with a reduced DC-link voltage. The shunt lter currents are shown in Fig. 12(d). The source currents after compensation are shown in Fig. 12(e), they are balanced and sinusoidal. The voltage across the interfacing inductor in phase-a is shown in Fig. 13, the peak to peak voltage across the

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200 V/div

TABLE V AVERAGE S WITCHING F REQUENCY OF THE I NVERTER S WITCHES ( K H Z ) Leg Shunt active lter Conventional Modied Topology Topology 1.80 1.35 1.95 1.60 2.25 1.8 Series active lter Conventional Modied Topology Topology 4.5 3.90 4.65 4.05 4.80 4.15

vinda

a b c (a)
200 V/div

vinda

(b) Fig. 13. Voltage across the interfacing inductor in phase-a (a) Neutral clamped topology (b) Modied topology.

The proposed method is validated through simulation and experimental studies in a three-phase distribution system with neutral clamped UPQC topology (conventional). The proposed modied topology gives the advantages of both the conventional neutral clamped topology and the four leg topology. Detailed comparative studies are made for the conventional and modied topologies. From the study, it is found that the modied topology has less average switching frequency, less THDs in the source currents and load voltages with reduced DC-link voltage as compared to the conventional UPQC topology.

interfacing inductor in the proposed topology is 140 V which is less than the conventional topology voltage of 250 V. As the voltage across inductor is high in case of conventional dif topology , the rate of rise of lter current dt will be higher than that of proposed topology. This will allow the lter current to hit the hysteresis boundaries at a faster rate and increases the switching, whereas in proposed topology the number of switchings will be less. Thus, the average switching frequency of the switches in the proposed topology will be less as compared to conventional topology. Since the average switching is less, the switching loss will also decrease in proposed topology. One more advantage of having less voltage across the inductor is that the hysteresis band violation will be less. This will improve the quality of compensation and Total Harmonic Distortion (THD) will be less in the proposed topology. The THD comparison of the source currents and the terminal voltages after compensation are given in Table IV. The average switching frequencies are compared in Table V. From the table it is clear that the average switching frequency of the shunt and series inverters with proposed topology has been reduced. The switching losses in the inverter has been calculated using the procedure given in [37]. The percentage reduction in switching power losses by using proposed topology are 53% and 56% for shunt and series active lters respectively. From the experimental results, the modied topology gives a reduced THDs both in the source currents and terminal voltages with a reduced DC-link voltage along with reduction in average switching frequencies. VII. C ONCLUSIONS A modied UPQC topology for three-phase four wire system has been proposed in this paper, which has the capability to compensate the load at a lower DC-link voltage under non-stiff source. Design of the lter parameters for the series and shunt active lters are explained in detail.

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Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
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Srinivas Bhaskar Karanki received his B. Tech. degree from Acharya Nagarjuna University, Guntur, India in 2007. He has completed his Ph.D. in Electrical Engineering Department from IIT Madras, India in 2012. His areas of interest include power quality, power electronic devices, and power electronics applications in power systems.

Nagesh G (S11) received his Bachelor of Technology degree from J.N.T.U Kakinada, India, in 2004, the M.S. degree from the Indian Institute of technology Madras in 2009 and presently pursuing Ph.D. in Indian Institute of Technology Madras, Chennai, India. His areas of interests include custom power devices, power electronics applications to power systems and control systems.

Mahesh K. Mishra (S00-M02-SM10) received the B.Tech. degree from the College of Technology, Pantnagar, India in 1991, the M.E. degree from the University of Roorkee, Roorkee, India, in 1993, and the Ph.D. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 2002. He has teaching and research experience of about 20 years. For about ten years, he was with the Electrical Engineering Department, Visvesvaraya National Institute of Technology, Nagpur, India. Currently, he is a Professor in the Electrical Engineering Department, Indian Institute of Technology Madras, Chennai. His interests are in the areas of power distribution systems, power electronics, and control systems. Dr. Mahesh is life member of the Indian Society of Technical Education (ISTE).

B. Kalyan Kumar (M07) received his Bachelor of Technology from J.N.T.U Hyderabad, India. He received his master and doctoral degree from Indian Institute of Technology kanpur in the year 2003 and 2007 respectively. He is at present working as Assistant Professor in Indian Institute of Technology Madras, India. His areas of interests includes power quality, power system dynamics and FACTS.

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