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Modied Hybrid Symmetrical Multilevel Inverter

Daniel Korbes, Samir Ahmad Mussa

Power Electronics Institute (INEP) Federal University of Santa Catarina (UFSC) Florian polis, Santa Catarina o Email: {korbes,samir}

Domingo Ruiz-Caballero
Department of Electrical Engineering Ponticia Universidad Catolica de Valparaiso Brasil Av, 2147 - Valparaso, Chile Email:

AbstractEven more the needs of efciency and productivity are required in industrial processes. Medium and high voltage inverter topologies are used in high scale industrial processes to achieve these goals. This work presents two variants of a modied hybrid symmetrical multilevel inverter topology based in [8] using Half Bridge commutation cells, proper to use in medium voltage levels. These topologies are able to create a 7-level phase-voltage waveform and a 13-level line-voltage waveform. A reduction in the number of switches and isolated sources is achieved when compared to traditional multilevel topologies, specially the cascaded topologies. A low power prototype was assembled using a programmable device (FPGA) and a modular platform developed to test new topologies.

I. I NTRODUCTION According the title of [1], The Age of Multilevel Converters Arrives. Every time high power appliances are required, the multilevel topologies are the best choice. Switches voltage isolation easily matches with the required specications, lots of control technique are available and easily extendible for multilevel inverters, the results are as expected - lower THDs, reduction on EMI, robusteness and reliability due to modularity - when compared to non-multilevel ones. Classic multilevel topologies, widely spread in literature and industrial appliances, are the Neutral Point Clamped (NPC) studied in [2] and [3], Flying Capacitor (FC) as seen in [4] and [5], and the Cascaded Topologies (CHB) shown in [6] and [7]. All these topologies have their pros and cons. Some of these are shown in table I. Based on previous works ([8] and [9]) this paper brings a modied hybrid multilevel inverter. Is known that all VSI are step-down converters. As show in [8] the topology originates from a Buck commutation cell. When cascaded with another Buck cell and imbricated in a full bridge, it generates the topolgy shown in g. 1(a). Points a and b are the connection points of a double Buck cell and a Full Bridge cell. This topology is able to create a 5-level phase-voltage waveform and 9-level line-voltagem. This cell, now called main cell, could be cascaded with half-bridge cells, as illustrated in g. 1(b) and 1(c). These topologies now creates a 7-level phase-voltage waveform and 13-level line-voltage, using fewer switches then the other topologies and with a reduced number of DC sources when compared to CHB topology. Compared to the classic multilevel topologies one could enumerate these main features:

Fewer isolated DC sources than CHB; Medium level of modularity, could be divided in two modules; Medium design complexity, due to input transformers; As CHB, power sharing is a control concern; Medium fault tolerance. Usually high power inverters works with lower switching frequency, commonly 500Hz, than low power ones (15kHz) to prevent high efforts on switches and due to characteristics of its power semiconductors (GTOs, thyristors, IGCTs). These topologies allows relatively high switching frequencies, around 1800Hz for high power inverters, due to lower voltage efforts and so on lower dV/dt across switches and possibility of use of modern switches, as IGBTs. Although, real inverters using these topologies should use a high power and high voltage level switch, as IGCTs, in the Full Bridge cell, because these switches are subjected to 3E voltage. Finally, experimental results were shown using a 3kW prototype. This prototype were created using 4 modular boards developed for generic multilevel inverter tests.

II. S INGLE - PHASE T OPOLOGY As described, this topology was born from a Buck commutation cell. The topology in single-phase conguration is shown in g. 1(b) and 1(c). Both are capable to create a 7level phase-voltage waveform and 13-level line-voltage using the same number of switches and DC sources. To create a 7-level phase-voltage the inverter cascade DC sources using switching states. As shown in table II, for each desired voltage level there are a different switching state, based on the topology of g. 1(b). To create negative voltage levels, a full bridge cell is used to invert polarity. With appropriate switching sequence those three positive levels become negative and so the 7-level waveform is created. Regardless modulation techniques used, switches Sx can work in high frequency (for high power drives around 1.5 kHz) but and in complementary pairs (S1 and S2, S3 and S4, S5 and S6) according to the proper modulation. Switches SPx also works in complementary pairs (SP1 and SP4, SP2 and SP3), but in low frequency (from 10 to 90 Hz considering traction application). This characteristic (switches working in complementary pairs) is necessary due to connections of each leg to DC

978-1-4577-1216-6/12/$26.00 2012 IEEE


TABLE I C OMMON MULTILEVEL TOPOLOGIES PROS AND CONS . NPC Clamping Diodes Low Low Voltage balancing Difcult FC Additional capacitor High Medium (capacitors) Voltage setup Easy CHB Isolated DC sources High High (input transformer) Power sharing Easy

Specic requirements Modularity Design complexity Control concerns Fault tolerance

S3 E S4 a SP 1 VL Load SP 2


(Current circulate through diodes)

SP 4

S5 E S6

SP 3 b

S3 , S6 S1 + S3 , S3 + S6 S1 + S3 + S6

iL < 0 S4 + S5 S2 + S5 , S4 S2 , S5
(Current circulate through diodes)


E S2 S3 E S4 SP 1 VL Load SP 2 S1

SP 4

S5 E S6

SP 3

The three-phase topology is created in the same way as dened in [9]. To create a Y-connection, one pole of VL in each phase is connected as a common point and the other pole is applied to the load. In the other hand a Delta connection could be created connecting one pole of each phase to one pole of another. In these congurations one can apply the Clark Transform and generate a vector map, as shown in g. 2. For a 7-level phase-voltage topology, this map shows 127 unique vectors. In total these topologies have 343 vectors. These redundant vectors should be used to balance the bus voltage in voltage sources.
V ector M ap in

S3 E S4 SP 1 VL Load SP 2

SP 4

3 2 1

S5 E S6

SP 3

V 0

S7 E S8

2 3 4 4 3 2 1 0 1 2 3 4

Fig. 1.

Origin (a) and proposed topologies - (b) and (c) for this paper Fig. 2.

Vector map in .

sources. If a pair of switches conducts at the same time the DC source connected to this pair is shorted, an unacceptable condition. This is called a prohibited switching state. In this paper, the modulation simulated in this inverter are the PD-PWM (Phase Disposition) and PD-CSV PWM (Phase Disposition - Centered Space Vector) techniques . All carriers are in-phase and compared to a senoidal reference (PD-PWM) and to a computed modulated waveform (PD-CSV PWM), based on a sinusoidal waveform, as described on [10].

The modulation strategy used in this inverter is the same that is used in the single-phase topology. In the three-phase topology a 13-level phase-voltage waveform can be obtained. Illustrated in g. 3, there is an 11-level phase-voltage waveform. This result was achieved using PD-PWM technique without over modulation as described in [9]. The computed modulated waveform, carriers and phasevoltage are illustrated also in g. 3. The parameters used in this simulation were: Switching frequency 1860 Hz, output power


500 W, Power Factor 0.85, frequency: 60 Hz, input voltage 100 V, modulation index: 0.9. IV. M ODULATION Were simulated and compared two diffent modulation techniques. Based on shift-level carriers, the In-Phase Modulation (PD-PWM), and a technique that emulate a Space Vector Modulation (SVM) called PD-CSV PWM. PD-PWM requires 6 triangular carriers and a senoidal reference and create a 13-level line-voltage waveform. Although, Vab , as showed in g. 3 just have 11 levels. This result is explained due to modulation index of 0.9. For 13-level waveform modulation index should be 1.
600 400 200 0 -200 -400 -600


~ ~

( a)

T HD : 15 . 37%




0 0.1
~ ~

( b)

T HD : 12. 73%





0 0 5.0



10.0 Frequency (kHz)



Fig. 5. Frequency spectrum and line-voltage THD. (a)PD-PWM and (b)PDCSV PWM


0 0.002 0.004 0.006 0.008 Time (s) 0.01 0.012 0.014 0.016

Fig. 3.

Line voltage Vab , carriers and modulator waveforms for PD-PWM

For PD-CSV PWM technique a reference waveform is calculated based in a sinusoidal waveform. This calculated waveform is showed in g. 4 according algorithm described in [9], with modulation index 0.9.
600 400 200 0 -200 -400 -600

Due to high number of switches, comparators and trigger signals involved in this topology, actually none DSP or microcontroller have enough embedded hardware and software solutions become too complex. One available solution that uses a single programmable device was a FPGA. The prototype employs an ALTERA Cyclone 3 development kit to create the sinusoidal reference and triangular carriers waveforms for SPWM with all hardware description made in AHDL. The modulation technique used here was the PD-PWM




Fig. 6.

Prototype assembled for topology test.

-4 0 0.002 0.004 0.006 0.008 Time (s) 0.01 0.012 0.014 0.016

Fig. 4. PWM

Line voltage Vab , carriers and modulator waveforms for PD-CSV

These waveforms obtained from PD-PWM and PD-CSV PWM had its frequency spectrum as showed in g. 5. Both graphics were normalized for fundamental frequency peak amplitude.

Were developed a generic power module board in which lots of topologies could be created and tested. Figure 6 brings a picture of this power module board. Are necessary two of these power modules board to assemble a single-phase inverter of the proposed topology. Each module are composed of four half-bridge commutation cells that could be arranged according the tested topology. For experimental results following parameters were used: Switching frequency: 1860Hz


Bus voltage: 75V Load: Resistive: 45 Inductive: 45 + 76mH Load frequency: 60Hz Modulation index: 1

0.1 0.08

~ ~

T HD : 13. 10%



Figures 7 and 8 showed experimental results using PDPWM. A 7-level phase-voltage with resistive load in g. 7 and a 13-level line-voltage with high inductive load in g. 8. Both pictures brings the bus voltage and the load current.


0 0 5.0 10.0 Frequency (kHz) 15.0 20.0

Fig. 9. form.

Frequency spectrum and line-voltage THD for experimental wave-

VI. C ONCLUSION These topologies are capable to work as medium or even high voltage drives, with low and high inductive loads. The generated line voltage waveform achieves the basic requirements like low common mode voltage generation and shifted frequencies to harmonics of the switching frequency, as side bands of these harmonics. Compared to usual topologies, listed at table I, these proposed topologies are similar to CHB, but use fewer components and isolated sources for a same output waveform. The use o PD-PWM is encouraged due to simplicity and low THD in line-voltage waveform.
Fig. 7. Waveforms for PD PWM. (a)Bus Voltage, (b)Phase voltage with resistive load and (c)Load current.

[1] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, The age of multilevel converters arrives, Industrial Electronics Magazine, IEEE, vol. 2, pp. 28-39, 2008. [2] A. Nabae, I. Takahashi, and H. Akagi, A New Neutral-Point-Clamped PWM Inverter, IEEE Transactions on Industry Applications, vol. IA-17, pp. 518-523, 1981. [3] R. H. Baker, Switching Circuit, U.S Patent nr 4210826 to Exxon Research and Engineering Co., 1980. [4] T. A. Meynard and H. Foch, Multi-level conversion: high voltage choppers and voltage-source inverters, in Power Electronics Specialists Conference, 1992. PESC 92 Record., 23rd Annual IEEE, 1992, pp. 397403 vol.1. [5] L. Jih-Sheng and P. Fang Zheng, Multilevel converters-a new breed of power converters in Industry Applications Conference, 1995. Thirtieth IAS Annual Meeting, IAS 95., Conference Record of the 1995 IEEE, 1995, pp. 2348-2356 vol.3. [6] R. H. Baker and H. Lawrence, Electric Power Converter, U.S. Patent nr 3867643, 1975. [7] B. Wu, High-Power Converters and AC Drives. Hoboken, New Jersey: John Wiley and Sons, 2006. [8] D. A. Ruiz-Caballero, R. M. Ramos-Astudillo, S. A. Mussa, and M. L. Heldwein, Symmetrical Hybrid Multilevel DC/AC Converters With Reduced Number of Insulated DC Supplies, IEEE Transactions on Industrial Electronics, vol. 57, pp. 2307-2314, 2010. [9] G. Carmona, R. Ramos, D. Ruiz-Caballero, S. A. Mussa, and T. Meynard, Symmetrical hybrid multilevel Dc-Ac converters using the PD-CSV modulation, in Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE, 2008, pp. 3327-3332. [10] B. P. McGrath, D. G. Holmes, and T. Lipo, Optimized space vector switching sequences for multilevel inverters, IEEE Transactions on Power Electronics, vol. 18, pp. 1293-1301, 2003.

Fig. 8. Waveforms for PD PWM. (a)Bus Voltage, (b)Line voltage with inductive load and (c)Load current.

Calculated THD for this experimental Vab waveform one can obtain a result close to the simulated one, 13.10%. This is showed also in g. 9 where the frequency spectrum is ilustrated. Again the results are normalized using the fundamental frequency peak amplitude.