Digital Design Using VHDL

Using Xilinxs Tool for Synthesis and ModelSim for Verification Part (IV) Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA

Session Four Outline

Time Delay Modeling State Machine Top-Down Design Example

Delay Moding
VHDL support delay modeling for signals only but not variables. Two types of delay modeling are supported in VHDL: Inertia Delay: The new assigned value will take place, if the signal value is persistence for the specified delay time Transport Delay: The assigned values will take place after the delay. Time Delay Modeling is used for simulation Only to MIMIC or simulate actual circuits. Example

A<= B AND C after 20ns;

A <= transport B AND C after 30 ns;

Sequential Circuits

Sequential Circuits: The output has a feedback path to the input. The output of the present cycle or time is the input of the next time. The output occurs in sequence. Sequential primitives: Latches, Flipflops, Registers, Counters, RAMS

Combinational

Sequential

Sequential Circuit

If a process is used to implement a sequential circuits, the following guidelines as used:

The sensitivity list contains the process inputs and feedback outputs Create variables to perform the actual algorithm Appends the variables to output signal, which may trigger the process.

Sequential Circuit: Example 8-bit Register

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity my_reg is Port ( RES, Load, clk : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0)); end my_reg; n
D D Q Latch Load RES

Architecture Behavioral of my_reg is begin data_out <= B"0000_0000" after 10ns when res = '1' else data_in after 20ns when (load ='1' and rising_edge(clk)); End Behavioral;

FINTE State Machine (FSM)

Finite State Machine (FSM): A dynamic system with finite number of conditions states, inputs and outputs. The outputs of the finite state machine are a functions of the inputs and the current state present state (PS). The Next State (NS) or the state transition is a function of the current state, the inputs and/or outputs. There are two types of FSM: Mealy State Machine: The output is a function of the present state and the input Moor State Machine: The output is only a function of the present state.
Logic

D Latch

FINTE State Machine (FSM)

The implementation of state machine in hardware requires two typed of circuits

Filp-Flops or Latches block used to hold the value of the present state. Combinational Circuit Block used to compute the Next States and the output.

Logic

D Latch

FINTE State Machine (FSM)

In VHDL states assignment may be of enumeration type for minimum number of latches, but it can be an array of bits for other type of assignments. There are several VHDL coding styles to support FSM Most popular and robust for synthesis is the Two Process FSM One process is used to design the combinational logic circuit, and the other one to code the next state assignment (Latches).
Input PS Combinational Process Output (Mealy Machine) NS

NS Clock

State Assignment Process

PS Output (Moore Machine)

EXAMPLE FINTE State Machine (FSM)

The following state machine detects a 010 sequence in a bit stream

RUN=1

1 State0 0 1/0 0
0

PS State 0 State 1 State2 State3

NS Input=0 State 1 State 1 State3 State1

NS Input=1 State 0 State 2 State0 State2

Output Valid 0 0 0 1 State3 1

0 0 State1 0 1

State2 0

EXAMPLE FINTE State Machine (FSM)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity my_3_bit_sequence is Port ( clk, RUN, input : in std_logic; valid : out std_logic ); end my_3_bit_sequence;
PS State 0 State 1 State2 State3 NS Input=0 State 1 State 1 State3 State1 NS Input=1 State 0 State 2 State0 State2 Output Valid 0 0 0 1

EXAMPLE FINTE State Machine (FSM)

architecture Behavioral of my_3_bit_sequence is type state_type is (state0, state1, state2, state3); signal P_state, N_state : state_type; Create two intermediate Signal valid_i: std_logic:='0'; signals. N_state for the input of the Latch and P_state for the Begin output of the latch. State_process: process(clk,run) begin This is the present state assignment. if (rising_edge(clk) and run = '1') then On the clock all scheduled next P_state<=N_state; states become present state. valid <= valid_i; end if; end process state_process; Create enumeration type for each state

EXAMPLE FINTE State Machine (FSM)

comb_process:process(P_state, run, input) begin
if (run='0') then N_state <= state0; elsif (RUN='1' ) then

CASE P_state is when state0 => valid_i <='0';

if (input = '0') then N_state<= state1; else N_state <= state0; end if;

when state1 => valid_i<='0';

if (input = '0') then N_state <= state1; else N_state <= state2; end if;

when state3 => valid_i<='1'; if(input = '0') then N_state <= state1; else N_state <= state2; end if; when others => valid_i<= '0'; N_state <= state0; end case; end if; end process comb_process; end Behavioral;

Top-Down Design Example Design:

Very efficient Utilizes library reuse
Specification System Sub-system

Register

Gate

Transistor

Top-Down Design Example Design:

1- Specifications We will design simple calculator that will either add or multiply two 32-bit numbers
a 32 Add Mult b 32 64

Specification System Sub-system

Register

Gate

Transistor

Top-Down Design Example Design:

Sub system Design: 1- Multiplier 2- Adder a 3- Mux
32

Specification System
b

Sub-system
32

Register
Add 64

Gate
Mult

Transistor

Top-Down Design Example Design:

Register Level Design: 1- Multiplier Multiplier is embedded within Xilinx
Specification System Sub-system

Register

Gate

Transistor