CSCE 3730 Reconfigurable Logic

FPGA Architecture
Dr. Song Fu song.fu@unt.edu http://www.cse.unt.edu/~song/csce3730
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HD Memory Architecture

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Memory operation
Address is divided into row, column.
Row may contain full word or more than one word.

Selected row drives/senses bit lines in columns. Amplifiers/drivers read/write bit lines.

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Row Decoders
Decode row using NORs:

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ROM
ROM core is organized as NOR gates pulldown transistors.

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Static RAM (SRAM)

Core cell uses six-transistor circuit to store value. Value is stored symmetricallyboth true and complement are stored on crosscoupled transistors. SRAM retains value as long as power is applied to circuit.

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SRAM Core Cell

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SRAM Core Operation

Read
precharge bit and bit high; set select line high from row decoder; one bit line will be pulled down.

Write
set bit/bit to desired (complementary) values; set select line high; drive on bit lines will flip state if necessary.

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Definitions
Field Programmable Device (FPD)
a general term that refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured insystem. Another name for FPDs is programmable logic devices (PLDs).
Source: S. Brown and J. Rose, FPGA and CPLD Architectures: A Tutorial, IEEE Design and Test of Computer, 1996
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Classifications
PLA a Programmable Logic Array (PLA) is a relatively
small FPD that contains two levels of logic, an ANDplane and an OR-plane, where both levels are programmable

PAL a Programmable Array Logic (PAL) is a relatively

small FPD that has a programmable AND-plane followed by a fixed OR-plane

SPLD refers to any type of Simple PLD, usually either a

PLA or PAL

CPLD a more Complex PLD that consists of an

arrangement of multiple SPLD-like blocks on a single chip.

FPGA a Field-Programmable Gate Array is an FPD

featuring a general structure that allows very high logic capacity.
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Programmable Logic Array (PLA)

Programmable AND Plane Programmable OR Plane

Programmable Node Un-programmed Connect Disconnect X Y O1 O2 O3 XY XY XY XY

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O4

X Y X X Y Y
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Programmable Logic Array (PLA)

Programmable AND Plane Programmable OR Plane
YZ XZ XYZ XY

XY+YZ XZ+XYZ

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Programmable Array Logic (PAL)

Programmable AND Plane Fixed OR Plane

O1

O2

O3

O4

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PAL with Logic Expanders

Programmable AND Plane Fixed OR Plane

Logic expanders
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PLA vs PAL
PLAs are more flexible than PALs since both AND & OR planes are programmable in PLAs. Because both AND & OR planes are programmable, PLAs are expensive to fabricate and have large propagation delay. By using fixed OR gates, PALs are cheaper and faster than PLAs. Logic expanders increase the flexibilities of PALs, but result in significant propagation delay. PALs usually contain D flip-flops connected to the outputs of OR gates to implement sequential circuits. PLAs and PALs are usually referred to as SPLD.
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Complex PLD
A CPLD comprises multiple PAL-like blocks on a single chip with programmable interconnect to connect the blocks. CPLD Architecture
I/O block I/O block
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I/O block

PAL-like block

PAL-like block

Programmable interconnect I/O block

PAL-like block

PAL-like block

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Altera MAX CPLD

I/O Cell

LAB (Logic Array Block)

LAB LAB LAB LAB LAB LAB LA (local array)

Chip-wide interconnect

Macroccell

Each LAB contains 16 macrocells

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Macrocell of Altera MAX CPLD

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Field-Programmable Gate Array

FPGA consists of an array of programmable basic logic cells surrounded by programmable interconnect. FPGA Structure
Programmable interconnect

Logic cell

I/O Cell

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FPGA vs CPLD
Capacitance
SPLDs Equivalent gates 0 ~ 200 CPLDs 200 ~ 12,000 FPGAs 1000 ~ 1,000,000

Applications
CPLDs
1. Implement random glue logics or 1. replace circuits previously implemented by multiple SPLDs Circuits that can exploit wide AND/OR gates, and do not need a very large number of flip-flops are good candidates for implementation in CPLDs.

FPGAs
FPGAs can be used in various applications: prototyping, FPGAbased computers, on-site hardware re-configuration, DSP, logic emulation, network components, etc.
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2.

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Elements of an FPGA Fabric

Logic. Interconnect. I/O pins.
IOB LE IOB IOB LE LE

interconnect LE LE LE LE LE LE

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Terminology
Configuration: bits that determine logic function + interconnect. Combinational logic block (CLB): logic element (LE). Lookup table (LUT): SRAM used for truth table. I/O block (IOB): I/O pin + associated logic and electronics.

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IOB

IOB

IOB LE

LE

Logic Element
Programmable:
Input connections. Internal function. Typically 4 inputs.

LE

interconnect LE LE LE LE LE LE

Coarser-grained than logic gates. Generally includes register. May provide specialized logic.
Adder carry chain.
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LE Example
Lookup table:
a 0
a b
0010

b 0 1 0 1

out
0 0 1 0 1 0 0 1
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0
out

memory
1001

1 1

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Programmable Wiring
Organized into channels.
Many wires per channel.

Connections between wires made at programmable interconnection points. Must choose:

Channels from source to destination. Wires within the channels.

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Programmable Wiring Paths

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Programming Technologies
SRAM
Can be programmed many times. Must be programmed at power-up.

Antifuse
Programmed once.

Flash
Similar to SRAM but using flash memory.

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