COMPUTER PROGRAMMING I ( (TA C162) )

Lecture 12 Storage Elements g

Todays Agenda
Basic Storage Elements
R-S Latch D Latch Register Memory

Thursday, February 11, 2010

Biju K Raveendran@BITS Pilani.

R-S Latch: Simple Storage Element

R is used to reset or clear the element
Set it to zero

S is used to set the element

Set it to one

If both R and S are one, output could be either zero or one

quiescent (or quiet) state -- Holds its previous value Note: if a is 1 b is 0 and vice versa 1, 0,
Thursday, February 11, 2010 Biju K Raveendran@BITS Pilani. 3

R=S=1

R-S Latch Summary

Holds previous value in latch

S = 0, R 1 R=1
Set value to 1

R = 0, S = 1(Set) (Se )
Set value to 0 (Reset)

R=S=0
Both outputs equal one Final state determined by electrical properties of gates t Dont do it!

Thursday, February 11, 2010

Biju K Raveendran@BITS Pilani.

Gated D Latch
It consists of the R S latch and two additional R-S gates that allows the latch to be set to value of D but only when the switch WE is on. WE stands for write enable enable. If WE is off, then value saved in the latch remains unchanged unchanged..

Thursday, February 11, 2010

Biju K Raveendran@BITS Pilani.

Gated D-Latch
Two inputs: D (data) and WE (write enable)
when WE = 1, latch is set to value of D
S = NOT(D), R = D

when WE = 0, latch holds previous value

S=R=1

Thursday, February 11, 2010

Biju K Raveendran@BITS Pilani.

Register
Usually we have to deal with values consisting of more the one bit. Important to be able to store these larger number of bits as self-contained units. Register is a structure that stores a number of bits, taken together as a unit A four-bit register is made up of four gated D latches. l t h
Thursday, February 11, 2010 Biju K Raveendran@BITS Pilani. 7

A register stores a multi-bit value multi bit value.

We use a collection of D-latches, all controlled by a common WE. When WE = 1, n-bit value D is written to register.

Register

Thursday, February 11, 2010

Biju K Raveendran@BITS Pilani.

Notation for sequence of bits

Q[3:0] Q[3] Q[2] Q[1] Q[0] Q[l:r] bit l to bit r, from left to right g Examples:
A[15:12] [ ] A[8:4] A[15:0] [ ]

A = 0101001101010101 A[14:9] = 101001

Thursday, February 11, 2010

15

A[2:0] = 101
9

Biju K Raveendran@BITS Pilani.

Memory
Is made up of a large number of locations. Each location is uniquely identifiable. Each location has ability to store a value. The unique identifier associated with each memory l location i called as it address. ti is ll d its dd

Thursday, February 11, 2010

Biju K Raveendran@BITS Pilani.

10

Address

Address Space & Addressability

Unique identifier associated with each memory location

Address Space
Total number of uniquely identifiable locations (usually a power of 2) With N bits; we can uniquely identify 2N locations

Addressability
Number of bits stored in each memory address location (e.g., byte-addressable or word-addressable)

Example: 16 M Byte Memory (24 bit Address line)

Address Space ???
16 x 220

Addressability = ???
(1 Byte)
Thursday, February 11, 2010 Biju K Raveendran@BITS Pilani. 11

Memory
We can build a memory
a logical k m array of stored bits.

Address Space: number of locations ( (usually a power of 2) y p )

k = 2n locations

Addressability:
number of bits per location m bits
Thursday, February 11, 2010 Biju K Raveendran@BITS Pilani. 12