Beruflich Dokumente
Kultur Dokumente
Author
Jamil Kawa R&D Group Director, Synopsys, Inc
Introduction
With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar FETs (also called planar CMOS) as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic power, intra-die variability, and retention voltage for SRAMs. FinFET devices have a significantly more complex topology than planar FET devices. In addition, their design features and characteristics are quite different, creating many questions for designers. For example, `` How much of the cumulative experience in planar FET design is applicable and transferrable to FinFET design? Can design flows and methodologies painstakingly developed over tens of years be reused? Or are we dealing with a radical change in design methodology? `` EDA tools ready for this transition? To what extent can they be ready, given the industrys Are limited experience with FinFET as a device? `` Given the complex device models of the FinFET and of its associated parasitics, can designers (and analog designers in particular) rely on such device models as good predictors for designing robust circuits? The list of questions goes on and all represent relevant issues that have to be addressed by foundries and EDA companies to minimize or avoid design pitfalls and costly iterations. A superficial view of the custom design flow, especially as far as the design implementation steps are concerned, could lead one to conclude that the transition from planar FET to FinFET will be seamless and transparent to the designer. But the impact the FinFET device has on the design flow can be quite significant. What does that mean for the designer? Most likely, a longer and steeper learning curve than what is typical in a transition from one planer technology node to the next, as shown in Figure 1. In fact, the learning curve has already been expanding with each new planar node as a result of new lithography artifacts such as restricted design rules (RDR) and double patterning. The jump in complexity with FinFET is even more pronounced.
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Figure 3: FinFET
The most important geometric parameters of a FinFET are its height (HFIN), its width or body thickness (Tsi), and its channel length (Lg). Figure 4 demonstrates those parameters. The effective electrical width of a FinFET is the planar width/body thickness Tsi plus twice the fin height HFIN.
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A simplified representation of the key stages in the process of manufacturing FinFET structures is shown in Figures 5, 6, and 7. The definition of the active device areas is shown as the blue mandrels, or temporary supporting structures. The fins (red) are formed by etching the mandrels (Figure 5). Then a cut mask is used to remove the unwanted parts of the structure (Figure 6) leaving the final pattern (Figure 7). Given that FinFET technology will be implemented at 20-nm or smaller geometries, double patterning techniques will be needed for all critical layers. A spacer double patterning is usually the preferred technique for patterning the fins.
Figure 5: Mandrels
At any one technology node, the FinFET has several advantages over its planar counterpart including (but not limited to): `` Very good electrostatic control of the channel. The channel can be choked off more easily. FinFETs boast a near-ideal sub-threshold behavior (associated to leakage), something thats not easy to achieve in planar technology without considerable design effort. `` Greatly reduced short channel effects (an effect that takes place when the channel length is the same order of magnitude as the depletion-layer widths of the source and drain junction, making the specific transistor behave differently from standard longer channel transistors). The short channel effects in planar technology are complex and give rise to a large impact on gate length variations and therefore on electrical performance. `` High integration density, or 3D. Thanks to the vertical channel orientation of FinFETs, they deliver more performance per linear W than planar even after the isolation dead-area between the fins is taken into account. `` Smaller variability, especially variability resulting from random dopant fluctuation primarily due to doping-free channels. Also, variability associated with line-edge roughness (LER), the random deviation of gate line edges from the intended ideal shape, which results in non-uniform channel lengths, is lower in FinFETs y Undoped or lightly doped channel: much lower dopant concentrations are necessary in the channel region. y Gate definition: the gate is defined from the top of the fin. The dominant part of the gate is defined by etching processes, which have very low LER
For SRAM design, optimizing the beta () ratio of a bit-cell is more difficult as W is quantized, and the flexibility in L as a tuning parameter is limited. Practically speaking, a of 1 or 2 are the two available choices. That in turn translates to the need for more advanced assist techniques to enhance SRAM yield. A less tangible yet crucial challenge, especially for the analog designer, is the close association between physical layout and circuit behavior. It is an iterative, painstaking process with no alternative (yet). This has to do with the complex parasitics of the FinFET device. Using a model to design and simulate and then fine-tune the finished circuit after the layout is extracted might not work. The discrepancy between the model-generated circuit and the realized one might be too wide to bridge with minor adjustments. This is an area where enhancements in tools and an extended experience in design is critical to minimize the impact of this issue. Finally, a physics-based challenge is the reliability concerns in the form of NBTI and PBTI aging that alters the behavior of the device. Experience in the area for FinFET devices is also crucial for design success.
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The TCAD part includes elaborate and extensive front-end 3D simulation and modeling of the device behavior. In the area of process modeling, the high-aspect ratio etching/deposition (topography) of FinFETs poses an added depth of analysis. Traditionally in TCAD, these processes have not been modeled, and have just been approximated geometrically. With the higher aspect ratio etching/deposition steps, there is growing interest in physical simulation of topography. 2D process modeling can be used for the fin generation process, but to really capture more complex behavior and proximity effects, 3D simulation is needed. In the area of device modeling, device simulation needs to capture effects of new surface orientation, surface scattering effects, quasi-ballistic transport, and corner effects. Mobility models need to adapted and recalibrated. Also, TCAD tools perform accurate 3D modeling of the FinFET device that addresses layout proximity effects, topology and architecture stress dependencies, as well as electromigration. It usually has its direct links to the RC extraction engine and to the BSIM spice modeling arm of the simulators.
An example of critical 3D simulations is that of stress profiles for various layout patterns and STI etch patterns. Layout dependency of mobility (stress induced) is a known phenomenon in planar CMOS that is more exacerbated in FinFET due to the 3D nature of fins and the STI etch profile. The proximity of adjacent fins, or lack thereof for end of line fins, and the depth of the etch (STI) between them are two critical parameters in FinFET.
Nested FinFET
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SPICE Models: The traditional SPICE models used for planar devices dont work sufficiently well. Berkeley provides a BSIM-CMG (common multi-gate) model that is able to model FinFETs (double-gate, multi-gate) as well as gate all around (GAA) devices, which are transistors with the channel completely surrounded by the gate, for example nanowires or pillar transistors. Also, new reliability concerns such as NBTI / PBTI call for accurate aging and end-of-life (EOL) models that accurately reflect the behavior of devices under specific bias conditions over specified time spans. Device Model (Parasitics): The FinFET parasitics device model is significantly more complex than its planar counterpart. A typical FinFET device model is shown in Figure 10.
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RC Circuit Parasitics Models: Efficient yet accurate RC models are needed to handle the increasingly more complex parasitics associated with FinFET-based circuits.
OPC/LITHO: Patterning and corresponding challenges from an OPC/MDP point of view are not expected to be fundamentally different from planar patterning, apart from the fin generation process, which is currently seen as generating a corrugated substrate. Spacer patterning is preferential, since the fins are sensitive to thickness variations. Support of DPT coloring and decomposition compliance checking is no different than that of all advanced nodes using DPT. From a physical layout perspective, FinFET design has a disproportionate number of RDR. Lithography is only one reason for the RDR. The fin patterning/formation process, with the high aspect ratio etches and the fragility of the fins under the high stress necessary for mobility enhancements, are further factors driving towards high restrictions. Layout & Design Database Tools: Existing schematics and layout tools must be enhanced and rearchitected with maximum productivity in mind. It must be a design rule-driven layout platform that dynamically interacts with simulators and with verification and data preparation tools. The tools must concurrently check hundreds of rules in real-time and provide error visualization. Extraction, Simulation, and Verification: With the exception of simulation packages that can efficiently handle aging and EOL simulations, there are no major changes impacting the extraction, simulation, and verification part of the EDA ecosystem for FinFETs. However, given the dramatic increase in the complexity of device and of parasitics models, efficient yet accurate extraction, simulation, and verification techniques are needed to handle the dramatically larger databases. Low Power Design: FinFET technology will extend the available options for power system designers by providing more options for performance versus leakage tradeoffs. FinFET-based design will have more on-chip power gating and wider use of dynamic voltage frequency scaling (DVFS) as designers strive to maximize performance per mW. Current techniques and design flows will evolve to accommodate this. FinFET technology provides a performance advantage at any operating voltage. As shown in Figure 11, this advantage is even wider at lower supply voltages, making FinFET technology ideal for low power and low operating voltage applications.
37% Faster
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Figure 11: Intels 22nm tri-gate technology showing the wider performance advantage at lower VDD *Source Mark Bhor, Intel, 2011
So, while it may appear there is hardly any change in the back-end of the EDA eco-system for FinFET design, the truth is that significant enhancements have been introduced to all the associated engines to efficiently and accurately handle the disproportionately larger databases back-end tools have to handle.
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