MANIPAL INSTITUTE OF TECHNOLOGY

DEPARTMENT OF Electronics and576 104 Manipal Karnataka Communication Engineering

COURSE PLAN Department Subject Semester & branch Name of the faculty No of contact hours/week : Electronics and Communication Engg : DSD HDL (ECE 206) : IV ECE : GP, SD, SKT : 4 hours/week Assignment portion Assignment no. 1 2 3 Test portion Test no. 1 2 Submitted by: Mr.Guruprasad Topics L1 L22 L23 L43 Topics L1 L16 L17 L34 L35 L50
(A constituent college of Manipal University, Manipal)

(Signature of the faculty) Date: Approved by:

(Signature of HOD) Date:

(Page 1 of 5)

MIT/GEN/F-05/R0

At the end of this course, the student will be able to: CO1: CO2: CO3: CO4: CO5: CO6: CO7: CO8: Discuss the architecture of hardware programmable devices like PLDs, PLAs and PALs. Describe the types of ASIC and their design methodologies. Discuss the architectural features of FPGAs Design digital circuits using FPGAs Discuss various testing methodologies employed in digital design Perform testing of designed module - both combinational and sequential circuits. Write and analyze the VHDL code for given design using structural, data flow and behavioral modeling styles and compare them. Write and analyze programs for test benches for the given design using VHDL.

L.No. L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15

Topics Digital System implementation using ROMs and PROMs. Digital System implementation using PLAs Digital System implementation using PLAs Digital System implementation using PALs Full-custom, semi-custom, standard cell based. Programmable ASICs PLDs, CPLDs, MPGAs, FPGAs and ASIC design flow. ACTEL- logic modules and Implementation of digital circuits using ACTEL logic modules Implementation of digital circuits using ACTEL logic modules XILINX- logic module and digital circuits using XILINX logic modules ALTERA- logic module and Implementation of digital circuits using ALTERA logic modules Programming Technology: anti fuse, SRAM and EPROM Programmable I/O cells. Programmable Interconnect of ACTEL ACT Programmable Interconnect of Xilinx LCA and ALTERA Max 9000 Testing Combinational Circuit:-Fault Table with examples

(Page 2 of 5)

MIT/GEN/F-05/R0

L16 L 17 L18 L19 L20 L 21 L22 L23 L24 L25 L26 L27 L28 L29 L 30 L 31 L 32 L 33 L 34 L 35 L 36 L 37 L 38 L 39 L40 L41 L42 L43 L44 L45 L46 L47 L48 (Page 3 of 5)

Boolean difference method with properties. Path Sensitization with examples and its failure. D-Algorithm- Introduction to D-Cubes, D-algebra, D-Algorithm fault propagation with examples. PODEM with example Fault-collapsing technique Observability and controllability Testing sequential circuits: sequential test methods, iterative test generator Design-for-test(DFT) methods: DFT guidelines for combinational circuits Critical path ,DFT methods like scan path, Boundary scan etc. DFT methods like Signature Analysis, BILBO and BIDCO. Y-chart, Different domains and levels of abstractions Types of synthesis, steps involved in synthesis, Digital modeling using HDLs. VHDL modeling concepts-syntax, entities and architectures VHDL object types, Data types: scalar data types with examples, Composite Data types with examples. File data types with examples, Access data types with examples. Behavioral Modeling: process statement, sequential statements-if, case, loop, next, exit, assert, wait, null. Examples Behavioral Modeling examples of Combinational circuits - Full-adder, Full-Subtractor, MUX, DEMUX, Encoder, D-FF, JKFF, State machines. Behavioral Modeling examples of sequential circuits -, D-FF, JKFF, State machines. Structural modeling with examples Structural modeling with examples Data flow modeling with examples Data flow modeling with examples Mixed modeling with examples Procedures with examples. Functions with examples. Packages and use clauses Configurations, pre-defined and user defined attributes Generics and Test benches Case studies Case studies Introduction to Verilog HDL Verilog v/s VHDL, behavioral Verilog modeling Structural and dataflow modeling

MIT/GEN/F-05/R0

References: [1]M.J.S.Smith (1997),Application Specific ICs, Addison Wesley. [2]Alexander Miczo(1987) , Digital logic testing and simulation , John Wiley & Sons. [3]C.H.Roth (1998) , Digital System Design using VHDL , PWS . [4]Peter Ashenden (1996) , The Designers Guide to VHDL, Morgan Kaufmann Publisher. [5]Douglas Perry (1998) , VHDL , McGraw Hill International. [6]J.Bhaskar (2002) , VHDL Primer , 3rd edition, Addison Wesley Longman Singapore Pvt Ltd. [7]Samir Palnitkar (2001) , Verilog HDL , Pearson Education Asia.

(Page 4 of 5)

MIT/GEN/F-05/R0