Design of Feedback Loop in Unity Power Factor AC to DC Converter

James B. Williams

Apollo Computer Inc. 330 Billerica Road Chelmsford, MA 01824

Abstract
In certain applications it is desirable to convert the utility AC voltage to a DC voltage is such a way as to present a unity power factor load. A common means of doing this is a circuit consisting of a bridge rectifier followed by a boost converter. Various control schemes for this boost converter are discussed in this paper including their tradeoffs as to power factor, output voltage transient regulation , and cost of implementation. A nonlinear regulation band circuit is presented which has a favorable combination of properties.

Basic Control Circuit

Figure 2 shows a simple block diagram for a control circuit. In this figure the value of K is derived from the difference between Vout. the output voltage, and Vref, the desired value of the output voltage. The dynamics of this derivation are described by F(s). Vin is defined as the rectified line voltage. It is sensed at the plus output of the bridge rectifier. Vin is multiplied by K to generate a signal Icmd which is the commanded input current. A minor loop with feedback gain G(s) compares Icmd with the actual input current and controls the duty ratio, D,of the boost converter switch. On a time averaged basis
Iout = Iin (1-D),

Introduction
In the workstation market there is a demand for more computing power requiring more electrical power. At the same time it is a surprisingly strong selling factor to allow use of power from a standard 120 volt wall outlet. Customers are understandably reluctant to rewire offices with nonstandard outlets. Not only does this represent extra cost, but any time the workstation is moved, the rewiring must be repeated. A power supply with unity power factor input is an important step in addressing this need. With unity power factor, a 20 amp., 120 volt outlet can supply 1920 watts. This includes 80% derating as required for safety agency approval. With 70% power factor, as is common with switching power supply inputs, this number is reduced to 1344 watts. The approach we use to implement unity power factor is a bridge rectifier followed by a boost converter as shown in figure 1. This serves as an AC to DC power converter. The DC output is fed to DC to DC converters to power the workstation. The subject of this paper is the design of the control circuitry for this boost converter. The control circuit used in this scheme must do two things. In order to maintain unity power factor, the input current must be controlled to be some constant K times the input voltage. In order to regulate the output voltage, this constant K must be changed in response to line and load changes. If this loop is coupled too tightly, K will vary due to the normal output ripple, and cause distortion in the input current waveform. If the loop is coupled too loosely (the loop crossover frequency in too low) the the response of the output voltage to line and load transients will be poor. and

(Eq. 1)

Vin-L(dIin/dt) = Vout (1-D).

(Eq. 2)

L is the value of the inductor. These two equation can be combined to eliminate (1-D) : ( Vin - L(dIin/dt) ) Iin = Vout Iout. (Eq. 3)

The current regulation minor loop containing G(s) has a loop gain which depends on Vout but not on Vin or Iin (or Iout). Since Vout does not change very much and this loop contains no right half plane zeros, its crossover frequency can be high compared to the main loop. From now on the minor loop will be ignored and it will be assumed that Iin equals Icmd. Equation 3 can now be rewritten as Iout = Icmd ( Vin - L(dIcmd/dt) ) / Vout. (Eq. 4)

To rewrite equation 4 in a linear incremental form, the following notation will be used. Italics will represent the incremental value and boldface will represent the operating point around which the value is perturbed.
Iour = I c m d (Vin-L(d1cmdldt)) / Vout Icmd L(dIcmd/dt) / Vout - Icmd (Vin-L(dIcmd/dt)) Vout / Vout

0 . %

5)

Equation 5 assumes that Vin looks like a voltage source and has no incremental value. dIcmd/dt is specifically assumed to have an operating point not necessarily zero.

959
CH2721-9/89/0000-0959 51.00 1 9 8 9 IEEE

Power Stage

T h e load is constant power with power equal to P. (P is constant with respect to Vout. It is not in general constant over time.) The KCL equation for the output voltage is as follows.
Iout = C(dVout/dt)

+ PlVout

(Eq. 6 )

C is the value of the output capacitor. Equation 6 can be linearized around the operating point as follows.
IOUC = C(dV0utldt) -

P V O UI~ VOUG

0%. 7)

Combining equation 7 with equation 5 gives the following. C(dVout/dt) - P Vout / Vout2 = Icmd (Vh-L(d1cmdldt)) / Vout - Icmd L(dIcmd/dt) / Vout - Icmd (VIn-L(dIcmd/dt)) Vouf / Vout2 Rearranging terms in equation 8 gives the following. Vout [Icmd(Vin-L(dIcmd/dt)) - P]/Vout2 + (dVout/dt) C = Icmd (Vln-L(dIcmd/dt))/Vout - (dlcmdldt) L Icmd / Vout

circuit common

(Eq. 8)

Figure 1

0%.

9)

Equation 9 can be rewritten in the frequency domain as follows.

Vout

= -Icmd (S-wz)/(s+wp) [L Icmd / (Vout c ) ]

(Eq. 10)

Basic Control Circuit

r;""
input current sense

The pole, wp , occurs at a low frequency compared to the loop dynamics; in fact it oscillates back and forth between positive and negative values at the output ripple frequency. There is very little loss of accuracy by assuming wp is equal to zero, so the equations which will be used for the power stage, including the current control minor loop, are equations 11, 12, and 13.
Vout = -Icmd (S-Wz)/S [L Icmd / (Vout c ) ]

I " '

(Eq. 11)

Vout = Icmd (l-s/wz)/s (Vin-L(dIcmd/dt)) / (Vout C)

(Eq.12)
Wr

= (VIn-L(dIcmd/dt)) / (L Icmd)

(Eq. 13)

I -

Equations 11 and 12 are equivalent. The overall regulation loop gain, H(s), in figure 2 can now be calculated.
H(S) = F(s) Vin (1-s/wz)/s (Vin-L(dIcmd/dt)) / (Vout C)

circuit common

0%. 14)
If we make F(s) equal to a constant, FO. the loop crossover frequency, ucr, can be calculated as follows.

Figure 2
960

W C I

= Fo Vin(rms)' / (Vout C)

(Eq. 15)

VIn(rms)' is the square of the RMS line voltage. This is substituted for the instantaneous value of Vin to give an average value over the line cycle. The dependence of the loop crossover on the square of the R M S line voltage is highly undesirable since we would like this converter to operate over a range of 90 to 264 volts. This would entail a spread of more than eight to one in the loop gain, which turns out to be a critical parameter.

Modified Basic Circuit

Figure 3 shows a modified control scheme whereby the square of the RMS line voltage is divided out of the loop gain. This corresponds to the circuit described in the Pioneer patent [ l ] . Now ~ c =r FO / (Vout C ) . and the stability criterion is F < (Vout C ) / (L Icrnd Vin(rrns)*). This circuit was simulated O to investigate the relationship between the loop crossover frequency, the input power factor, and the load transient response. The results are listed in table 1. What is shown is a clear tradeoff between input power factor and transient response. The reason that the power factor deteriorates when the loop gain is increased is that the loop tries to regulate out the normal output ripple and in so doing distorts the input current waveform.

Notch Filter Circuit

A logical approach to this problem is to add a notch filter in after the divider to eliminate the ripple which looks like a sine wave at twice the line frequency. This is shown in figure 4. The simulation results show that this approach works well. However in order to get these good results it is necessary to have a high Q notch with the center frequency tuned exactly. If the filter is detuned or the Q is lowered, the performance starts to degrade rapidly. Given that we want our converter to operate at 50 or 60Hz, and we dont want to maintain tight tolerances on component values, this approach was rejected. The circuit which was simulated with a notch filter tuned to 120Hz with a Q of 10, and a loop crossover frequency of 80Hz.

Modified Basic Control Block Diagram

Notch Filter Control Block Diagram

Power Stage

VOUt

Constant Power Load

cmd

I
notch filter

RMS Detector

t
Figure 3

r F< l
JI
Vrer

Figure 4

961

Sample & Hold Circuit

An alternative which accomplishes the same thing is illustrated in figure 6. A sample and hold has been added in the feedback path as shown. The signal into the multiplier is sampled at twice the line freqyency (this is equal to the output ripple frequency). This removes any ripple at the sampling frequency. Because of the sample and hold circuit, stability analysis is best done in discrete time rather than continuous time. As a first step, equation 12 is simplified by assuming than oz is infinite.
Vout = I c m d

Ant1 = A n [l - F h I (Vout C)] O + E n [FO wf h / (Vout C)]

(Eq. 2 9

Bntl = An [-h + 0.5 FO hz / (Vout C)] + Bn [l - 0.5 F Of h2 / ( V O UC)] O ~

(Eq. 26)

The closed loop poles in the z domain are exactly the eigenvalues of the state transition matrix. If we let E = F h / (Vout C), then O the state transition matrix is as follows.

11s (Vln-L(dIcmd/dt)) / (Vout C)

(Eq. 16)

The gain from the input of the multiplier, K, to Vout is

Vout =

K 11s Vln (Vin-L(dIcmd/dt)) / (Vout C).

(Eq.17)

I
9 - (2
E = 1.5

1
h z - h
l-horW2 I

By averaging over one half line cycle this is simplified to The characteristic equation of this matrix is
Vout = K

USVin(rms)2 / (Vout C).

(Eq.18)

-E-h

wf E12) z

+ (1 + h ~f

E12

- E)

= 0. (Eq. 27)

If h is the sampling period, which is equal to one half line cycle, and Vn is the output voltage at the n'th sampling instant, the following equation can be written.
V n t l = Vn

+h

(Kn - Keq) Vln(rms)2/(Vout C)

(Eq. 19)

Kn is the value of K after the n'th sampling instant and Keq is the value of K which will yield equilibrium for the given input voltage

The requirement for stability is that both roots of this equation have absolute values less than one. Optimum stability is achieved when both roots are zero. In this case the impulse response is finite; the response to any transient excitation dies out in two sampling periods. This optimum stability condition is achieved when the following hold. (Eq. 28) (Eq. 29) (Eq. 30)

and output connected load power. If the feedback gain F(s) is set to a constant value, FO, which is equal to (Vout C)/h, then the last equation can be rewritten as follows.
Vntl

= Vref

- Keq h Vln(rms)2/(Vout C) - P h /(Vout C)

o = 2 / (3 h) f (Eq. 20)
F = 1 . 5 Vout C / h O

The value of Keq is (P / Vin(rms)2) SO

V n t l = Vref

(Eq. 21)

The stability can be seen to be optimal is the sense that any perturbation dies out in one sampling period. The static voltage regulation is less than optimal, however, in that the output voltage deviates from the desired value, Vref, by an amount proportional to the load power. The static load regulation can be made optimal by adding a dominant pole and a compensating zero in the feedback gain, F(s). If we let F(s) = FO (s+wf)/s then a closed form solution can be derived.

Kn = [FO ~f
Ant1 = A n

Bn - FO A n ] / Vin(rmsI2

(Eq. 22) (Eq. 23)

+ h Vln(rrns)Z /

(Vout C) Kn

BntJ = Bn - h An - 0.5 h2 Vin(rms)2 / (Vout C) K n (Eq. 24)

In these equations Kn is the value of K after the n'th sampling instant, A n is the value of Vout at the n'th sampling instant, and Bn is the value of the state variable associated with F(s) at the n'th sampling instant. h is the sampling period. Substituting equation 22 into 23 and 24 gives the following.

This circuit was simulated using the feedback parameters derived in equations 29 and 30. The simulation waveforms show rapid recovery from load transients after the next sampling period, however there is considerable deviation in the output voltage during the half cycle between the time of the load transient and the time of the next sampling. The results are listed in table 1. This illustrates a general principle in that adding a dominant pole and a compensating zero in the feedback path improves the static voltage regulation, but does so at the expense of the peak to peak voltage excursions under large transient conditions. It is the latter which is most important in our application because the DC to DC converters which follow this converter will provide the ultimate regulation. It is therefor important only to make sure that the output of the AC to DC converter does not go outside the allowed input range of the DC to DC converters. The simulation outputs which follow show the transient response of the sample and hold circuit. The first simulation has a dominant pole and compensating zero. The second has a constant feedback gain, FO. The simulations were run with an input line voltage of 120 volts at 60Hz. The output voltage is 340 volts DC nominal. The load is cycled from 100 watts to 1800 watts and back to 100 watts. In each "oscilloscope" the top trace is the output voltage minus the nominal output voltage. The bottom trace is the input line current.

962

Sample & Hold Control Block Diagram

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Regula tion Band Circuit

The regulation band circuit outlined in figure 7 is an attempt to improve upon the preceding circuits. The previous circuit contains a multiplier, a squarer, a divider, and a sample and hold. In this circuit this has been reduced to a single multiplier together with some op. amps. In this circuit the input current is regulated to be some multiple, K, of the input voltage. As long as the output voltage remains within a defined regulation band, K is held constant. This band is made large enough to include the maximum expected output ripple. If the output voltage goes out of this regulation band, K is varied in such a way as to rapidly return the output voltage into the regulation band. After the output voltage has been regulated back into the acceptable range, K is set to a value slightly different than it was before the output voltage left this range. In this way K eventually reaches an equilibrium value which keeps the output voltage in the regulation band. The stability problem can be broken into two parts. The first involves causing the output voltage to return to the regulation band quickly whenever it falls outside. The second involves finding an equilibrium value for K which will keep the output voltage within the regulation band. In the first case, it is desirable to cross over the loop at some frequency below the right half plane zero, wz. Unfortunately wz varies all over the place depending on the operating point. It has no lower or upper bound. What is bounded, however, is the gain of the boost stage at frequencies above wz. This is the gain from Icmd to VOUI. Equation 11 shows that the magnitude

Transient response with constant gain.

Figure 5

963

of this gain is [ L Icmd I (Vout C) ] and the maximum value this can take is [ L Imax / (Vouc C) ] where Imax is the current limit So by making the feedback gain equal point. to [aVout C / (L Imax) 1, we are guaranteed that the loop will cross over at at most a times the right half plane zero frequency, where a is a circuit parameter whose value is less than one. Because there is a multiplication by Vin in the feedback path, a minor loop through attenuator B is used. This stabilizes the feedback path gain to AIB (assuming the transconductance amplifier has high gain), and allows optimum transient response independent of Vin. When the transconductance amplifier is in the active region,the combination of the transconductance amplifier, the op. amp. stage, and the multiplier acts in effect as a big op. amp. whose gain is determined by the feedback and is independent of the forward gain. The loop gain now floats up and down along with the right half plane zero, wz, maintaining a constant ratio with it, and it is not necessary to use a divider to divide out the R M S line voltage. The second part of the stability problem is a little more difficult to get a handle on. Let K = K + K where K is the value of K which would yield equilibrium in the output voltage, and K is the increment by which K differs from K. Vout will drift upwards at a rate of K Vin(ev) / C. Eventually Vout will hit the upper limit of the regulation band. At this point there will be a bump in K as the output voltage is regulated back to within the regulation band. There will be a corresponding bump in Icmd. The area under the bump in Icmd will be C A V where A V is the difference between where the output voltage ends up, and where it would have been had K held constant. The area under the bump in K is C A V / Vin' where Vin' is the value of Vin during the bump. The net change in K from before the bump to after the bump is
AK =

containing the op. amps. contains no switching elements, its cross over frequency can be moderately high (tens of kilohertz) and is determined by the open loop gain of the op. amps.

Regulation Band Circuit Block Diagram

vout

Power Stage Current output Command Voltage Input

<

Icmd

U @ -L 7l l
Attenuator Attenuator

< -

high limit-

C A V I Vin' I (RI C ) f.

(Eq. 31)

This corresponds to the change in the voltage across capacitor Cr. One can argue that the maximum value expected for A V is equal to the upward drift rate of Vout times tcyc where tcyc is the time span of one cycle of the output ripple (or one half line cycle), and that Vin' is approximately equal to Vin(av). This gives
AV

limit V High Gain Transconductance Amplifier with Dead Band

Vin

Figure 7

tcyc K Vin(av) I C,

(Eq. 32)

and
AK

tcyc K I (Rt C ) f.

(Eq. 33)

In theory by making (Rf greater than tcyc. K should move toCf) wards, but not overshoot its equilibrium value each time Vout bumps into the limit. However both breadboard and simulation show that (RfC ) should be made equal to one or two full line f f cycles. Fortunately the penalty for making (Rf C ) larger is only that it takes longer for the distortion of the input current waveform to subside after a line or load transient. Interestingly, because of the minor loop containing B, the stability does not depend on the values of R and Cf, f only on their product. Figure 9 shows a simplified implementation of this circuit. The transconductance amplifier is implemented with two op. amps. and two diodes. When the output voltage is in the regulation band, both diodes are off and zero current flows into the next stage. When the output voltage goes out of the regulation band, one of the diodes turns on and the incremental gain of the transconductance amplifier is the open loop gain of the op. amp. divided by the resistance coupling it to the next stage. Since the minor loop

964

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constant power load

input current sense

Icmd
Font
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Vref

2Nn Rb

8.52

Figure 8

The above simulation output shows the response of the regulation band circuit when subjected to an output load change from lOOW to 1800W and back to 1OOW. The top trace is the output voltage and the bottom trace is the input current. The distortion in the input current waveform can be seen dying out a few cycles after the transient.

Figure 9

Nonzero Line Impedance

All the analysis done so far assumes that Vin is an ideal voltage source. In reality the source impedance is not zero, is not necessarily known, and has some significant effects on stability. In addition the converter generally has some EM1 filtering. One way to approach this is to include some line impedance, Zline, in the circuit equations and solve again for stability. This however gives some very complicated expressions which are not very enlightening. A much better approach is to view the entire converter as a block in a feedback loop. The input to this block is an incremental line voltage and the output is the resultant incremental current. The gain of this block is Yin, the closed loop input admittance. The other block has a gain of -2line. The input to this block is the incremental current drawn by the converter, and the output is the resultant incremental voltage on the line.

965

Yin

= K (l/(KLs)

+ H(s))

/ (1

+ H(s))

(Eq. 35)

In this equation H(s) is the loop gain of the minor current regulating loop. In particluar Incremental Line Voltage H(s) = G(s)Vout / (Ls) . (Eq. 36)

Closed Loop Input Admittance

There is an interesting geometric interpretation of the phase associated with Yin illustrated by the following diagram.

Incremental Current into Converter

Figure 10
How can we stabilize this feedback loop if we don't know the value of Zline? If Zline is an arbitrary function of frequency then we can't, so it is necessary to make some assumptions about Zline. In particular we can assume that Zline is passive in nature. The can be stated in a number of equivalent ways: Zline is not capable of supplying power at any frequency; the real part of Zline is positive at all frequencies: the phase shift associated with Zline is always between -90" and +90". The line is being modeled as a Thevenin circuit with an ideal voltage source is series with an impedance. (It is important to distinguish that although the impedance is incapable of supplying power at any frequency, the voltage source can and does supply power at the line frequency.) This is a reasonable assumption since Zline is made up of the R's, L's, and C's of the distribution network which are themselves passive. The way to stabilize this loop is to pick some frequency, wx, and make sure that below that frequency lYin Zlinel is less than one, and above that frequency Yin has a positive real part. This guarentees that above o x the total phase shift around the loop is less than 180". Unfortunately it is not possible in general to make sure that Yin has a positive real part at all frequencies above wx by means of control circuit design. The alternative is to add a damping network across the input line of the converter. This damping network consisting of a resistor and a capacitor in series. The admittance of this network, Yrc, is then added to the existing input admittance of the converter. By selecting the resistor and capacitor of the damping network, the real part of its admittance, Re[Yrc] = (UR) (w R C)2 / [(w R C)2 + 11. (Eq. 34) Unfortunately in this case Yin has a negative real part at all frequencies, so for stability we have to rely on keeping IYinl smaller than l/IZlinel . From equation 37 it can be seen with a little algebra that
IYinl < 1 / (w

Figure 11
The three points shown are plotted in the complex plane. The angle, 8,is the phase angle of the closed loop input admittance, Yin. Yin would only have a negative real part when H(s) lies in the shaded circle. Since below the crossover frequency H(s) will have a phase lag between 0" and 180", H(s) will always be below the real axis in the complex plane. The only part of the shaded circle which extends below the real axis is inside the unit circle. Therefore Yin will only have a negative real part at frequencies above crossover. This allows for passive damping with a relatively small resistor and capacitor. If one of the diodes in the circuit in figure 9 is on, then Yin can be approximated as follows.
Yin = (1/L) / [s (1 - Imax /(aIcmd)) - Wz]

(Eq. 37)

a is a circuit parameter which was previously defined. With reference to the circuit in figure 9,
Q

= (RblRa) (L Imax) / (Vout C)

(Eq. 38)

can be selected such that when added to the input admittance of the converter, it results in a combined Yin with positive real part at frequencies above wx. Referring to the circuit in figure 9, the control circuit has two different topologies depending on whether one of the diodes connected to the outputs of the op. amps. is on. In the case where the diodes are off, the circuit is simplified by assuming the input bridge rectifier can be ignored incrementally, and that the energy storage capacitor looks like a voltage source. K becomes a constant and Yin can be approximated as follows.

Lx)

(Eq. 39)

where Lx is defined as follows.

Lx = L (1-a)/a

(Eq. 4 0 )

966

This is to say that the magnitude of the input admittance, (Yinl, is less than that of an inductor with inductance Lx. This gives some design guidance in that if the magnitude of the line impedence is assumed to be less than that of a 1mH inductor (over some frequency range), and Q is chosen such that Lx is 2mH then the design is reasonably safe (over that frequency range). The above gives some insight into the problem, but does not constitute a complete solution. This problem is perhaps better addressed empirically by measuring the closed loop input admittance with a network analyzer. To do this the circuit must run with a DC input, which it will, and one of the diodes in the control circuit must be shorted to measure stability in that mode. The appropriate R and C values for the damper circuit can be calculated from the measured data. These measurements must be repeated at different combinations of input line voltage and current since the worst case conditions will be different for each different frequency.

TABLE 1
The simulations were run with a state space averaged model of the power stage with a 1mH inductor and a 1000bF output capacitor. The line voltage was a constant 120V RMS at 60Hz. The output voltage was regulated to a nominal voltage of 340V DC. The power factor was determined at a load of 1800W. The output transient response was measured by cycling the load from lOOW to 1800W and back repeatedly. The difference between the maximum and minimum value of the output voltage was determined. I t is listed as AV. CIRCUIT Mod. basic circuit. Figure 3 lOHz gain-bandwidth Mod. basic circuit. Figure 3 20Hz gain-bandwidth Mod. basic circuit. Figure 3 40Hz gain-bandwidth Notch filter circuit. Figure 4 Sample&Hold. Figure 6 Constant feedback gain. Sample&Hold. Figure 6 Dom. pole, comp. zero Regulation Band. Figure 7 POWER FACTOR 99.6%
AV

done at the expense of additional circuit complexity as an RMS detector, a squarer, and a divider are added. The resultant circuit allows the designer to trade off input power factor against output transient voltage regulation by selecting the loop crossover frequency. The last three circuits allow a theoretical power factor of unity since none of the output ripple voltage is fed back. The sample and hold circuit is probably the least attractive because it has the highest circuit complexity and relatively poor transient response. The notch filter circuit had the best overall performance but presents some practical difficulties in implementation. The notch must have a high Q and be tuned to exactly the ripple frequency in order to be effective. This means either tight component tolerances together with some selection mechanism for differing line frequencies, or some complex active tracking filter. The regulation band circuit gives excellent performance and is the simplest to implement (except the basic control circuit). The transient response almost as good as any circuit examined. In all of these circuits a choice must be made whether the voltage feedback gain is constant or contains a dominant pole and compensating zero. The pole-zero approach gives better static output voltage regulation. but the constant gain approach gives better worst case response to large load changes.

References
Josh Mandelcorn and Bruce Wilkinson, Unity Power Factor Power Supply, US Patent number 4677366. Discussions with Bob Mammano. Bob Neidorff, and Lloyd Dixon of Unitrode Integrated Circuits Corporation. W. Rippel, Optimizing Boost Chopper Charger Design, Powercon 6 1979 Record. pp. D1-1 - D1-20. T. S. Latos and D. J. Bosack, A High Efficiency 3kW Switchmode Battery Charger, in Power Electronics Specialists Conference Record 1982, pp. 34 1-353. Martin Schlecht and Brett Miwa, Active Power Factor Correction for Switching Power Supplies, in IEEE Trans acfions on Power Elecfronics, Vol. PE-2, No. 4. Oct. 1987, pp 273-281.

88.9V

98.9%

46.4V

96.6%

30.0V

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Summary
Five different control circuits were investigated. I have referred to them by the following names: the basic control circuit, the modified basic control circuit, the notch filter circuit, the sample and hold circuit, and the regulation band circuit. The basic control circuit suffers from input current waveform distortion and reduced power factor at high input line voltage, and reduced output transient voltage regulation at low input line voltage. The modified basic control circuit addresses this problem by compensating for input line voltage variations in the feedback loop gain. This is

967