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The V7 TAI Logic Module can hold designs up to 180M ASIC gates with up to 9 Xilinx Vitex-7 2000T FPGA devices on a single board. In addition to our existing USB2.0 port for our popular runtime features such as FPGA download, programmable clock generations and self-test, the new V7 TAI Logic Module now supports these runtime features through Ethernet cable so you can control your FPGA hardware remotely. S2C has also added many new runtime features such as I/O voltage settings and clock frequency read backs through software control.
V7 TAI Logic Module Configuration Product Type Target Devices ASIC Logic Gates (Max) FPGA Memory DDR3 SO-MIDD slot DDR2 SO-MIDD slot External User I/O (Samtec) Inter-FPGA Nets Total SerDes Transceivers Quad 4 * 7V2000T 80M 180Mbits 2 2 1,440 192 * 6 48 GTX Dual 2 * 7V2000T 40M 90Mbits 1 1 1,200 530 32 GTX SingleA 1 * 7V2000T 20M 45Mbits 1 N/A 840 N/A 16 GTX SingleB 1 * 7V2000T 20M 45Mbits N/A 1 840 N/A 16 GTX
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Runtime Software
All S2C V7 TAI Logic Modules are shipped with our state-of-art TAI Player Pro Runtime software for FREE. You can exercise full control over the S2C TAI Logic Modules from Linux or Windows machines through the USB or Ethernet ports without being a hardware expert.
Control hardware through USB2.0 or Gigabit Ethernet ports Download designs to FPGA conveniently from TAI Player Pro software Make SD card for standalone FPGA download Run Self-Test for all I/O, interconnections and clocks Select global clock sources and program on-board programmable clock frequencies Reset hardware or re-download to FPGA remotely through software Monitor on-board voltage, current and temperature Read back on-board global clock frequencies Adjust I/O voltages through software Adjust fan speed settings through software
The optional Full version of TAI Player Pro Compile & Debug Software dramatically reduces your SoC prototyping effort particularly for designs that require partitioning across multiple FPGAs. With a straightforward graphical user interface, you can perform prototype verification within a fraction of the time it would take over a conventional design flow. TAI Player Pro encapsulates and works seamlessly with Xilinx tool set and third party tools, including synthesis, place and route, and debug. RTL-level probes are set up prior to synthesis step so that the signal names can be retained throughout the compile flow even when designs are partitioned across multiple Virtex-7 FPGAs.
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Dedicated I/O
Dedicated I/O
Dedicated I/O
Dedicated I/O
Dedicated I/O
Dedicated I/O
J1A 120
J1B 120
J1C 120
J2B 120
J2A 120
F2 F2
124
Differential I/O
V7-2000T
4GTX J5 4GTX Debug I/O 192 Debug I/O 192
V7-2000T
4GTX J6 4GTX 192+2GTX
8GTX+12 8GTX+12
J3X
Differential I/O
124
V7-2000T
192+2GTX
V7-2000T
F3
F4
120 J4B
Dedicated I/O
F3
124
120 J4A
Dedicated I/O
120 J4C
Dedicated I/O
120 J3C
Dedicated I/O
120 J3B
Dedicated I/O
120 J3A
Dedicated I/O
03
Differential I/O
F2
Differential I/O
F1
F2
124
J1X
Dedicated I/O
GTX I/O
Debug I/O
Power Modules
LM Controller
Giga-Ethernet port to PC
USB Interface to PC
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High Speed Transceivers Each FPGA has 16 Gigabit Transceivers with up to total of 32 Gigabit Transceivers Gigabit Transceiver can run up to 6.6Gbps through high speed differential connectors
Ease- of-Use Flexible & Powerful I/O Each FPGA can access up to 988 external I/O 360 dedicated I/O per FPGA 480 shared net and I/O between two FPGA 50 direct interconnections between two FPGA Dedicated I/O voltage can be adjusted to 1.2V, 1.5V, 1.8V through runtime software in GUI Multiple FPGA configuration options through Gigabit Ethernet Port, USB2.0 Port, JTAG and SD Card Less than 3 seconds per FPGA per configuration through SD Many new Runtime features including setting I/O Voltage, read hardware status through software User Test Area - LEDs, Push Buttons, Switches and GPIO Headers for testing and debugging High Performance Up to 60W power for each FPGA Equal trace length for I/Os from same I/O connector Pro-tested DDR2 memory at up to 666 Mbps and/or DDR3 memory at up to 1200Mbps Design Implementation TAI Player Pro supports design partition across multiple FPGAs Design Debug Set probes at the RTL level and bring the signals to the top level Use many off-the shelf pre-tested daughter boards
Dierential I/O
Shared I/O
Dierential I/O
Shared I/O
J1T/J1B 8GTX+12
Dedicated I/O
8GTX+12
J10
8GTX+12 50
120
DDR2 SO-DIMM
DDR3 SO-DIMM
F1
V7-LX2000T
120 124
F2
V7-LX2000T
124 120
120
Dedicated I/O
120
J9
120
J4
Dedicated I/O
Shared I/O
Shared I/O
Dedicated I/O
05
Dedicated I/O
480
Dedicated I/O
8GTX+12
J3
Dedicated I/O
Shared I/O
GTX I/O
2 Oscillator Sockets
LM Controller
USB Interface to PC
Giga-Ethernet port to PC
Power Module
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Corporate Headquarters
S2C Inc. 1754 Technology Drive, Suite 206 San Jose, CA 95110, USA Tel: +1 408 213 8818 Fax: +1 408 213 8821
Regional Oces
S2C (Shanghai) Co., Ltd Rm. 15J, World Plaza, 855 Pudong South Road Shanghai 200120, China Tel: +86 21 6887 9287 Fax: +86 21 6887 9289 Local Hotline: 400 8888 427 S2C Shenzhen Branch S2C Beijing Branch Rm. 2102, Building 1, Taiyangyuan, Dazhongsi East Road Haidian District, Beijing 100098, China Local Hotline: 400 8888 427 Unit 1311, 13F, Changhong Science & Tech Building , South 12 road, Southern District, High-tech Zone Local Hotline: 400 8888 427 S2C Taiwan 5F-5, No.65. Gaotie 7th Rd., Zhubei City Hsinchu County 302, Taiwan Tel: +886 3 667 5782 Fax: +886 3 667 5783
S2C, TAI, Prototype Ready and ProtoBridge are trademarks of S2C, Inc. Xilinx, Virtex and ChipScope are trademarks of Xilinx, Inc. All other tradenames and trademarks are the property of their respective owners. CB012913