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Phase-LOCKED loops (PLLs) finds wide application in areas such as communications, wireless systems, digital circuits, and disk

drive electronics.

A. Why PLL ? Two factors account for the use of PLL: 1. The demand for higher performance and lower cost in electronic systems. 2. The advance of integrated-circuit technologies in terms of speed and complexity.

B. Applications of PLL Applications of PLL: 1. Jitter Reduction Jitter manifests itself as variation of the period of a waveform, a type of corruption that cannot be removed by amplification and clipping even if the signal is binary. 2. Skew Suppression In high-speed digital systems, a system clock, CKs, enters a chip from a printed-circuit (PC) board and is buffered (in several stages) to sharpen its edges and drive the load capacitance with minimal delay. The principal difficulty in such an arrangement is that the on-chip clock typically drives several nanofarads of device and interconnects capacitance, exhibiting significant delay with respect to CKs. The resulting skew reduces the timing budget for on-chip and interchip operations.

3. Frequency Synthesis Many applications require frequency multiplication of periodic signals. 4. Clock Recovery In many systems, data is transmitted or retrieved without any additional timing reference. In optical communications, for example, a stream of data flows over a single fiber with no accompanying clock, but the receiver must eventually process the data synchronously. 5. Clock Distribution

The clock distribution is usually balanced so that the clock arrives at every end point simultaneously. One of those end points is the PLL's feedback input.

Speak about phase noise: origin Frequency-domain counterparts of jitter are sidebands and" phase noise". As illustrated in Figure5a, sidebands are deterministic components that do not have a harmonic relationship with the main component Wc (also called the "carrier"); in most cases of interest, they are quite close to Wc, i.e., Wm Wc. Sidebands are specified with their frequency and their magnitude relative to that of the carrier. In contrast to sidebands, phase noise arises from random frequency components (Fig. 5b). To quantify phase noise, we consider a unit bandwidth at a frequency offset w with respect to Wc, calculate the total noise power in this bandwidth, and divide the result by the power of the carrier (Fig. 6). Phase noise is expressed in terms of dBc/Hz, the letter "c" indicating the normalization of the noise power to the carrier power, and the unit Hz signifying the unity bandwidth used for the noise power.

PLL Components

Loop Parameters 1. 2. 3. 4. 5. Type and order Loop bandwidth : Defining the speed of the control loop Transient response : Like overshoot and settling time Steady-state errors : Like remaining phase or timing error Output spectrum purity : Like sidebands generated from a certain VCO tuning voltage ripple 6. Phase-noise: Defined by noise energy in a certain frequency band (like 1MHz offset from carrier). Highly dependent on VCO phase-noise, PLL bandwidth. 7. General parameters: such as power consumption, supply voltage range, output amplitude, etc.

Loop Dynamics in Looked State The above analysis provides insight into the "tracking" capabilities of a PLL. If the input frequency changes slowly, its variation can be viewed as a succession of small narrow steps, during each of which the PLL behaves as in Figure13.

It is important to note that in the above example the loop locks only after two conditions are satisfied: 1. wout has become equal to win 2. The difference between and

has settled to its proper value.

In lock, the input and output frequencies are equal but the phase error not be zero. Tracking range = lock range Acquisition range = capture range

PFD 1. Mixing: Has superior noise performance due to the fact that it operates on the en-tire amplitude of the input and VCO signals, rather than quantizing them to 1 bit. Balanced mixers are best suited for PLL applications in the microwave frequency range as well as in low noise frequency synthesizers. Furthermore, non-idealities in the circuit implementation of the mixer result in responses that are far from linear. 2. XOR If one uses signals so large that the amplifiers saturate, the output signals stop looking like sinusoids and start looking like Walsh functions (rectangular signals). One advantage of such a phase detector is that the loop gain is now independent of input signal amplitude. Furthermore, an XOR phase detectors response can have a larger linear range than a sinusoidal detector (mixer).

The disadvantage is that the linearity of the baseband response is affected by the relative duty cycles of the input and VCO signals. 3. Phase-Frequency Detector An extremely popular phase detector is the combination of the tri-state phasefrequency detector (PFD) with a charge pump. The action of the charge pump is to alleviate any loading of the phase detector in driving the rest of the circuit. This allows the response to be smoother than without the charge pump. 4. A Linear Clock Phase Detector (Hogge) 5. A Bang-Bang Clock Phase Detector (Alexander) The Bang-Bang phase detector is unique among the detectors presented here in that its baseband behavior is never linear. Instead, the detector acts as a relay over the region from to While the nonlinear behavior of the detector is a disadvantage, it has advantages for high speed clock data recovery applications over the Hogge detector

TSPC [True Single-Phase Clock] : Positive Edge 19 transistor Operation range of the PFD is over 1.4 GHZ Deadzone < 20 ps Low phase sensitivity errors Phase and frequency error detection range is not limited Independent of duty cycle of input signal Error detection ranges of PFD is only limited to to The high speed operation is accomplished with the proposed PFD because the PFD structure has no feedback network to reset the flip-flop The power consumption is reduced half conventional PFD because the switching of PFD is occurred in only one flip-flop

If the phase difference between the phase detector controlling signals, narrow pulses are required at the output. Due to finite rise and fall times, such narrow pulses cannot activate the charge pump, so the average output current will not follow input phase. This region is called the dead zone and occurs primarily due to a difference in rise time between the latch outputs in Figure 6.38 and the reset path delay.