LPGD

A Low-Power Design Methodology/Flow and its Application to the Implementation of a DCS1800-GSM/DECT Modulator/Demodulator
(ESPRIT 25256)
Generalized Low Power Design Flow N. Zervas1, S. Theoharis1, D. Soudris2, C.E. Goutis1, and A. Thanailakis2 1 Univerisity of Patras (UP), 2 Democritus University of Thrace (DUTH) Editor: UP Type: Report LPGD Id: LPGD/WP2/UP/D1.3R1 CEC Identifier: EP25256/ UP/D1.3.R1 Document Version: 1 Status: Deliverable Confidentiality: Public Actual Date: January 27, 1999 Contractual Date: December 31, 1998 WorkPackage: WP1 Keywords: logic-level power estimation, RT-level exploration Abstract: The purpose of the present report is to present a computer
aided exploration tool, the use of which will help to reduce the time and effort spend during register transferlevel power exploration. Part of this tool is a zero-delay gate-level power estimator based on a novel probabilistic method. The rest of this tool is actually a plug in for the Mentor Graphics framework and provides an easy way to perform power/area explorations at the Register Transferlevel.

Title: Author(s):

Copyright 1999 INTRACOM UP DUTH

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History
Date Version 1 Comments Deliverable

January 27, 1999

Purpose /Scope
The purpose of the present report is to describe a new computer aided design power exploration tool. The power estimation can be done during the logic level or register-transfer level design of a certain application. More specifically, the logic level exploration and estimation is performed by a zero-delay gate-level power estimator, which is based on a novel probabilistic method. The second part of this tool is actually a plug-in for the Mentor Graphics framework and provides an easy way to perform power/area explorations at the RT (Register Transfer)level. The main target of this tool was to accelerate the design process reducing the time and effort spending for register transfer-level exploration. The new CAD tool verified and refined during the design procedure of GMSK/GFSK modulator/demodulator. A certain register-transfer level power exploration example from LPGD project is provided. The proposed power exploration tool is available upon request. A User License Agreement between University of Patras and User should be signed.

Reference Documents
[1] [2] [3] M. Perakis, D. Soudris, C. Goutis and A. Thanailakis, Low Power Architecture Design of GSM/DECT Algorithms, Report D3.3R1 of the LPGD project (ESPRIT 25256), Dec. 1998 H. Mizas, D. Soudris, S. Theoharis, G. Theodoridis, Structure of the Low-Power Design Flow Report D1.2R1 of the LPGD project (ESPRIT 25256), June 1998 S. Theoharis, G. Theodoridis, D. Soudris, and C. Goutis, Logic Level Power Estimator, Deliverable D3.3S1 of the LPGD project (ESPRIT 25256), Dec 1998

Purpose/Scope

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TABLE OF CONTENTS
1 2 Introduction............................................................................................................................................. 6 Power estimation problem formulation................................................................................................... 6 2.1 Zero-delay and real delay models ....................................................................................................... 6 3 Supported power estimation methods ..................................................................................................... 7 3.1 Simulation-based approach ................................................................................................................ 7 3.2 Probabilistic approach........................................................................................................................ 7 3.3 Supported power estimation methods: Discussion............................................................................... 8 4 Exploration flow .................................................................................................................................... 10 5 CAEX tool description........................................................................................................................... 11 5.1 Required inputs................................................................................................................................ 11 5.2 Internal operation............................................................................................................................. 13 6 An RT-level exploration example.......................................................................................................... 14 7 Conclusions-Discussion.......................................................................................................................... 15 References ..................................................................................................................................................... 16

List of Figures FIGURE 1: THE EXPLORATION FLOW FIGURE 2: MAIN MENU OF THE EXPLORATION TOOL FIGURE 3:CELL LIBRARY SELECTION FIGURE 4: OPTIMIZATION STEP SELECTION FIGURE 5: OPTIMIZATION TYPE SELECTION FIGURE 6: CLOCK FREQUENCY SELECTION FIGURE 7: OPTIMIZATION EFFORT SELECTION FIGURE 8: OPTIMIZATION EFFORT SELECTION FIGURE 9: FIRST PHASE OF INTERNAL OPERATION FIGURE 10: SECOND PHASE OF INTERNAL OPERATION FIGURE 11: THE STRUCTURE OF THE CAEX SOFTWARE List of tables TABLE 1: CIRCUIT CHARACTERISTICS TABLE 2: POWER ESTIMATION RESULTS. TABLE 3: THE RESULT OF THE CA EXPLORATION 10 11 11 12 12 12 12 12 13 14 17 9 9 15

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Introduction

The requirement for long battery life at the wide spread portable communication systems forces the designers to take into consideration apart from the two traditional parameters, area and speed, and a third one, the power consumption [1, 2, 3]. Also, reasons related with power problems oblige the designers to tend at systems that dissipate less power. Thus there is a great need for CAD tools that will assist the exploration through the various level of the design flow. In this document a CAEX (Computer Aided EXploration) tool developed in the University of Patras is presented. This tool provides two alternative ways for power estimation at the logic level, one of which is a based on a novel zero-delay probabilistic power estimation method [6]. The rest of this tool is actually a plug-in for the Mentor Graphics framework and provides an easy way to explore at the RT (Register Transfer)-level. The aim is to provide designers (regardless of their experience) with an easy way to explore using CAD. This is achieved by hiding from the user the insignificant CAD-related details. This tool interprets the simple information given by the user to powerful scripts that control the various CAD tools involved at each step of the RT-level exploration flow. The input fed to the tool is a RT-level description (VHDL-source) of the circuit under consideration and the tool produces estimates for both power consumption and area. The motivation of the development of this CAEX-tool is to provide designers with a tool that will help them to select among alternative RT-level architectures of the same system or among alternatives RT-level components architectures in terms of area and power. The rest of this document is organized as follows: in section two the power estimation problem is formulated. In section three the supported by the CAEX tool under consideration power estimation methods are presented and compared while in section four the target exploration flow is presented. In section five the operation of the CAEX tool is described. Finally in section six an example taken from the LPGD project, in which this CAEX-tool was used is provided.

Power estimation problem formulation

The power dissipated in a CMOS circuit can be classified as static power and dynamic power dissipation. The dynamic power dissipation forms the dominant part of the total power and thus only this component of the power consumption is taken under consideration. The dynamic power dissipated by a CMOS combinatorial circuit can be expressed by the well-known formula:
2 Power = Cload i Vdd f Ei i =1 N

(1)

where C loadi is the load capacitance at node i, Vdd is the power supply voltage , f is the frequency and Ei is the activity factor at node i. The power estimation methods reported in this document actually estimate the activity factor. Capacitance estimates can be acquired by using CAD tools reports or by using a simple capacitance estimation formula. According to this formula the capacitance of a node with fan-out n is: C = Cgi + k n where Cg i is the input gate capacitance of the i-th input that is driven by this node
i =1 n

and k is a capacitance factor (in pFs) for a specified technology. For a given supply voltage the power estimate is usually expressed in W per MHz.

2.1

Zero-delay and real delay models

There are two main approaches to the power estimation. The distinguishing factor is the model used for the delays of the circuit components. According to the first approach the circuit components are considered to have zero delay. The first approach uses the delays of the circuit components in order to estimate each nodes activity. This way, also spurious transitions are taken into account. More precisely in the case of zero delay model it is assumed that the combinational circuit is a part of a synchronous sequential circuit, which means that its inputs can switch synchronously with the clock, performing at most one transition at time t=0 during the clock period [0.T). Moreover, an applied input signal is considered as ideal step pulse without any voltage drops at circuit nodes, while its width is greater or equal to the inertial gate delay.

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The power estimation problem of a combinational logic circuit, under zero- delay gate model can be stated as follows: Given the gate level description of a combinational circuit with n inputs and m outputs and assuming that the time between two successive applied input vectors is greater or equal to the settling time of the circuit, estimate the average power consumption of the circuit for an input vector stream through the calculation of its average switching activity. In the case of real-delay model a node is permitted to perform more than one transition during a clock period. The power estimation problem of a combinational logic circuit, under real-delay gate model can be stated as follows: Given the gate level description of a combinational circuit with n inputs and m outputs and taking into account the gate delays and assuming that the time between two successive applied input vectors is greater or equal to the settling time of the circuit, estimate the average power consumption of the circuit for an input vector stream through the calculation of its average switching activity.

Supported power estimation methods

In this section the two power estimation methods supported by the CAEX tool developed in University of Patras are presented. The first one is based on simulation and uses real time delay models, while the second one is a novel zero delay probabilistic power estimation method. Both methods takes as input a logic-level description of the circuit and an input vector set. Since the power consumption is depend on the input vectors their selection in terms of number and probabilistic characteristics is very crucial for the purpose of power estimation.

3.1

Simulation-based approach

The term f Ei of equation 1 is actually the frequency of node transition from logic 1 to logic 0, which is equal to the ratio of number of node transition from logic 1 to logic 0 divided by the total number of vectors: f Ei = f 1 0 = # transitions1 0 i # vectors (2)

(1)(2) Power =

N VDD 2 Cload i # transitions1 0 i # vectors i =1

(3)

Hence calculating the number of transitions from logic 1 to logic 0 for each node by simulation and given the load capacitance of each node can perform the power estimation. Simulation-based power consumption estimation can be used either under zero-delay model either under real-delay model.

3.2

Probabilistic approach

In recent years many researchers have suggested probabilistic methods for estimating the power consumption in digital CMOS circuits [4,10,11]. In particular, Devadas et al [10] used the symbolic simulation and Ordered Binary Decision Diagrams (OBBDs) [12] to calculate the switching activity. However, this method exhibits high computational complexity and the spatial correlation of the input signals are not included. Schneider et al [11] presented a method using Markov chain theory, Reduced OBBDs, temporal and structural correlation. However, it has been assumed that the primary inputs are independent and spatially uncorrelated. Marculescu et al [4] based on the research work reported in [5], on OBDDs, and on Markov chain theory suggested two accurate probabilistic methods. However, these methods are characterized by large computational complexity. In [8] a novel method for estimating the switching activity of logic level networks, is introduced. The proposed method belongs to the class of probabilistic approaches and provides highly accurate switching activity values in smaller time interval than existing methods. It has as inputs the static and transition probabilities, and data correlation of the primary inputs and the exact structure of a logic network, which consists of the zero-delay modeled basic logic gates, e.g. AND, OR, and NOT. The accuracy of the proposed method comes from the fact that spatial, temporal, and structural correlation of the signals at all logic levels are taken into account. The small time cost results from the fact that the computational complexity in terms of multiplications of the introduced method is reduced significantly. More specifically, a set of new formulas for calculating the switching activity of basic logic gates is derived. Their corresponding complexities in terms of multiplications have been
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computed by a series of formally proven lemmas. A novel algorithm for propagation of the appropriate transition coefficients and calculation of the switching activity values of a logic network is introduced. A CAD tool has been developed, using the proposed method. The experimental results for certain benchmark circuits indicate that the proposed method exhibits remarkably reduced computational complexity comparing to logic circuits in [4]. Here, it should be stressed that the proposed method does not use OBDDs. The CAEX tool under discussion here includes an activity estimator based on this probabilistic approach for power estimation [8]. The probabilistic activity estimator take as input the transition probabilities and the data correlation of the primary inputs as well as the structure of the logic network. Initially, the estimator performs a pre-processing of the logic network. Specifically, the pre-processing includes: i) the identification of the type and immediate inputs of each gate, ii) levelization of the circuit, iii) derivation of the Correlation List, L f , of each node f of the logic circuit, and iv) the determination of the necessary (i.e. subset) transition coefficients. It should be stressed that the Correlation List contains all the signals and their pairwise TCs, which are necessary for the calculation of the switching activity of the node f. The next step is to calculate and propagate the TCs as well as to compute the switching activity. To reduce the computational complexity, a Permitted Level of Correlation, C, is defined by the user. A Permitted Level specifies the number of the previous levels, whose the correlations of their signals must be considered for the calculation of the switching activity of a node f. The whole estimation procedure in an algorithmic form follows: function switching_activity_estimation ( F, X, C) -- F = logic circuit, X = set of primary inputs, -- C = permitted level of correlation begin for each gate f F : 1. find the type of gate f 2. find the level of gate f 3. derive the Correlation List L f 4. specify the proper TCs of the pairs in L f for each level i for each gate f F : calculate the transition probability E ( f ) for each pair of signals in level i : pre-compute the marked TCs return switching activities E ( f ) end function switching_activity_estimation;

3.3

Supported power estimation methods: Discussion

Obviously a power estimation method that takes into account glitching activity is more accurate than a method that ignore this type of transitions. Thus the real-delay simulation-based power estimation, is always more accurate that the zero-delay probabilistic power estimation. However the comparison between the zero-delay simulation-based power estimation and the zero delay probabilistic power estimation here proposed does not indicate significant differences in terms of accuracy. On the other hand the later method for power estimation is much quicker than simulation. The difference in the time spend for power estimation becomes larger as the size (in terms of number of primitives cells or transistors) of the circuits increases. However for circuits of few hundreds of gates this difference is negligible (few seconds). Hence the simulation-based power estimation in the case of relatively small circuits should be performed but for larger circuits the probabilistic approach must be preferred. Subsequently the two zero-delay supported power estimation methods supported by the CAEX tool under consideration are compared in terms of time and accuracy. Benchmark circuits have been used in order to do this (see table 1). In table 2 the time spend for estimation using the proposed zero delay probabilistic power estimation method and the zero-delay simulation-based power estimation method. Also in table 2 the power estimates acquired by the two methods are illustrated. For the technology mapping step, a general library of primitive gates of up to 4 primary inputs, is used. All power
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estimations are measured in W with 20 MHz clock frequency and 5V power supply. The maximum logic depth of each circuit is selected for the circuit partitioning. For a signal x, we define as Real Node Error the quantity Err(x) = Eeff (x) Eeff (x) Eeff (x) , where Eeff (x ) is the real effective switched capacitance of signal x and Eeff (x ) is the estimated effective capacitance. The effective switched

capacitance is calculated by the product of the switching activity E(x) and the total capacitance load of the node x, Cx=FxCg, where Fx is the fan-out of this node and Cg = 0.05 pF is a typical input gate capacitance. For comparison reasons, a random vector set of 100000 vectors is generated for each benchmark circuit. Circuit C1355 C1908 C2670 C3540 C499 C6288 C7552 C880 alu4 cu des f51m rca16 vda # Inputs # Outputs # Gates 41 32 180 33 25 205 233 64 422 50 22 817 41 32 176 32 32 1491 207 107 1154 60 26 221 14 8 543 14 11 104 256 245 2437 8 8 83 33 17 112 17 39 391 Table 1: Circuit characteristics # Levels 15 21 20 34 17 73 21 22 35 14 17 10 49 16

The power consumption differences between each method and switch level simulator are depicted in table 2. In particular, the columns TOTAL represent the total error of the total power dissipation for the specific input vector set, the columns MEAN is the mean error, while the columns MAX contain the maximum error for these power estimations. Table 2 shows the real errors in power estimation (%) of the proposed method. The average total error is about 1.173 % while the corresponding average mean and maximum error values are 6.277 % and 147.5 % respectively. In the column labeled Power the total power dissipation for each benchmark circuit in W is reported. Finally in columns Simulation and Probabilistic the run time for the simulation based (QUICKSIM II) and the run time for the proposed probabilistic power estimation method are reported. Power Simulatio Probabilistic (sec) (W) n TOTAL (sec) 6,73 0,65 14424 0,550 C1355 6,99 0,69 1666 0,084 C1908 9,65 5,03 3411 0,986 C2670 7,98 2,14 5181 1,485 C3540 5,98 0,63 1418 0,388 C499 9,10 3,66 10788 4,500 C6288 1,33 6,98 7603 1,766 C7552 7,93 0,94 1416 0,685 C880 8,18 0,96 2891 3,238 alu4 3,04 0,25 471 1,623 Cu 2,30 12,74 12995 0,427 Des 2,81 0,22 486 0,384 f51m 2,89 0,46 721 0,100 rca16 3,21 0,75 1742 0,204 Vda 5,580 2,579 4658 1,173 Average Table 2: Power estimation results. Circuit Error MEAN 1,999 5,805 7,829 11,695 1,948 12,156 7,315 3,345 17,103 4,752 3,389 4,016 0,791 5,734 6,277 MAX 50,509 257,282 404,698 323,997 19,871 373,587 127,482 42,032 145,190 48,141 142,249 73,082 6,409 50,524 147,504

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Exploration flow

In this section the steps followed during CAD exploration at the architectural-level are described. In the first step the circuit is described using a HDL. The HDL description of the design is first has to pass compilation. The task implemented by logic-synthesis is the mapping the latest description to an interconnection of primitive components (cells) that are contained into a cell-library. The cell-library contains the information about the cells of a particular technology (such as cell functionality, input capacitance, output delay etc). The designer has to choose among the available cell-libraries should in this step. Sequentially the designer feed the optimization option to the optimizer usually provided with the synthesis tool. Most synthesis tool provide an area estimate at this point, based on area characterization of the cells and to simple formulas in order to predict the area occupied by the interconnections. The output so far is an optimized (in terms of the circuit quality factors) logic-level description, together with a rough area estimate. The next step is to estimate power consumption. In order to do that, input vectors have to be generated and also the capacitance for each node has to be extracted. Given input vectors and capacitance, switching activity is estimated using toggle simulation or probabilistic analysis. With toggle simulation the circuit is simulated taking into account the cell delays provided by the cell-library. Probabilisticbased activity estimation tries to propagate the input statistics through the logic network. After power estimation a loop-back is possible if the power or area constraints are not satisfied.
Behavioral or RT description (VHDL source) Compilation
Cell Library

Synthesis
Optimization Options

Area Estimate

Logic-Level Description

Capacitance Estimation Vector Generation Input Vetcors

ToggleSimulation

Probabilistic Analysis

Switching Activity Estimation

Power Estimate

Figure 1: The exploration flow It has to be stressed here that currently this design-flow is far away from the touch button approach, in the sense that the CAD tool requires input from the designer relatively frequently. More precisely after the completion of design flow step by the CAD-tool the designer have to feed the inputs for the next step into the same or another CAD-tool. In order to avoid the time wasted waiting in frond of the monitor for the tool to prompt that it has finished and for feeding inputs experienced designers usually write scripts that partially automate this procedure. However familiarity with the not so easy to use CAD tools is necessary in order to write scripts or even follow this exploration flow. Finally it must be stressed that this CAEX-tool should not be used as a power cost function in cases where the effect of a large number of transformations must be evaluated. This is due to the relatively large time required for each iteration, since each iteration includes time-consuming synthesis step. As stated earlier in this document the aim of this tool is to help a designer to select among alternative RTPublic Page 10

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level architectures of the same system or among alternatives RT-level components architectures in terms of area and power.

CAEX tool description

In this section a CAEX (Computer Aided Exploration) tool developed in University of Patras, is analytically described. This tool target to minimize the time and effort spend during architectural (or RT-level) exploration. This achieved through the minimization of the interaction steps between the CAD framework and the designer. In other words the designer is provided with a tool that receives inputs at the first step, proceed to the further steps with no further interaction and finally produce the required output. This is what called here the press button approach. Additionally CAD-tool depended details (like descriptions formats, report formats, instructions format etc) are hidden from the user. The only things that are pre-required in order to use this CAEX tool is the abstract knowledge of the design-flow and the ability to write in an HDL. Thus it can also be used for educational reasons. Furthermore this software was designed to be a plug-in for the Mentor Graphics framework and can be extended to also support other vendors CAD frameworks (like Synopsis, Cadence etc.). Input to this CAEX tool is a register-transfer level description of the circuit. The format of the input circuit can be in any HDL format. This CAEX tool currently supports only VHDL, but with some minor changes it can accept and other standard input formats (Verilog, PLA, EQU, KISS etc).

5.1

Required inputs

This tool was designed to implement all the steps included in the exploration flow previously described in a discrete way (one by one) or all at once (press button approach) as shown in figure 2 where the main menu of the CAEX tool is illustrated. When the press button approach is selected at the first step all the needed information to perform the various steps must be fed to the tool. In figures 2-8 the related menus are illustrated. At first the destination technology (cell-library) is chosen (fig. 3). 1. 2. 3. 4. 5. 6. 7. 8. Create new library Delete existing library Compile new design Synthesize new design Estimate power Execute the whole flow Change configuration Exit

Enter your choice Figure 2: Main menu of the exploration tool SYNTHESIS OPTIONS Destination Technology 1. 2. 3. 4. 5. es2_07 es2_10 ams_08 ams_06 Return to main menu

Enter your choice Figure 3:Cell library selection

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Sequentially the number of optimization steps, the type of each step and the optimization effort is selected (fig.4-). The number of optimizations steps is fragmented in order to fragment also the time spend on optimization. SYNTHESIS of design: test_design How many optimizations steps (default=1, max=4) Figure 4: Optimization step selection The types (area and time) of optimization supported are imposed by the Autologic II. The aim of area optimization is to come up with smallest in terns of area possible circuit while the aim of time optimization is to reduce the critical path of the circuit in order to operate properly for a given clock frequency. So in the case of time optimization also the clock frequency should be determined. Optimization step 1: Type 1. 2. 3. Area Time Return to main menu Figure 5: Optimization type selection Optimization step 1: Clock frequency Enter the clock frequency (ns) Figure 6: Clock frequency selection The optimization effort actually determines the quality of the optimization result but also is strongly related to the time spend for optimization; the larger the optimization effort is the longer the time required for optimization becomes. Optimization step 1: Effort 1. 2. 3. 4. Low Medium (default) High (not recommended) Return to main menu Figure 7: Optimization effort selection The next step is to choose among simulation-based and probabilistic power estimation method (fig. 8). Additionally the user must define weather the power estimation must be performed using sample application data or data generated by the CAEX tool. If sample application data are available the file name and the location path must be given. Otherwise the tool based on to the number of inputs proposes a sufficient large number of input vectors to be generated. However the user can define a different number of input patterns. Power Estimation Method 1. 2. 3. 4. Simulation-based (real-delay) Simulation-based (zero-delay) Probabilistic (zero-delay) Return to main menu

Enter your choice

Enter your choice

Enter your choice Figure 8: Optimization effort selection

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5.2

Internal operation

The internal operation of the CAEX tool is analyzed in this section. After the input are defined scripts that will lead the operation of the synthesis tool (ALUI) and the logic-level toggle simulator (QuickSim) are generated. The RT-level description of the circuit is fed to the logic-synthesis tool. The logic-synthesis and the optimization tasks are implemented with respect to the option selected at the beginning of the process and contained in a generated script. The optimized logic-level description (net-list) of the design under consideration is extracted in the EDDM format (internal net-list format of Mentors Graphics). A converter to SLIF format transforms this description in order to feed the probabilistic power-estimation tool. Also a capacitance file is generated (pre-layout estimation of capacitance).
Behavioral or RT description (VHDL source) Compilation

ALUI
Netlist generation Initial Netlist Optimization step 0

ALUI script

...
Optimization step n Cap. estimation

Optimized Netlist (EDDM) Format converter Optimized Netlist (SLIF)

Cap. file

Figure 9: First phase of internal operation

So far the circuit has been synthesized. In order to proceed to the next step of the exploration flow (namely node activity estimation) input data are needed. With respect to the choice made in the first step the CAEX tool will use sample application data (in that case the user has already defined the name and location path of the file containing this data) or will generate the required data. In the later case the VHDL description of the circuit is fed to a parser in order to define the name, type and size of the inputs. This information is fed to a procedure for the input pattern generation (in-house tool). This way five different types of input data are generated: Equal All: Static probability (Pi) for each bit equals bit activity (Ei) equals 0.5 Non-temporal: Static probability of each bit is random (in the region between 0 and 1) and the activity is given by the following equation: Ei= Pi=0 Pi=1 Temporal: Both static probability and activity are random LFSR: Static probability (Pi) for each bit equals bit activity (Ei) equals 0.5 but the vectors are generated in a deterministic way, which introduces low spatial correlation. Highly Correlated: The vectors are highly spatial correlated (eg. Counter stream)

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Totally nine hundred thousand input vectors are produced for each circuit, three hundred thousand for each type of input data and stored to a vector file. This file is a binary file, which contains the applied input vectors to the circuit. Also an equivalent DO file is produced in order to use the same input vector set with the QuickSim switch level simulator of Mentor Graphics framework. If simulation-based power-estimation was selected in the first step the generated DO input vector file is used with the QuickSim switch level simulator and the switching activity of every circuit node is reported. If the probabilistic approach is selected then the in-house estimation tool After the pre-processing steps, namely the input vector analysis and the reconvergence structural analysis, the probabilistic values of the inputs are propagated using the reported models, and the switching activity of every node in the circuit is calculated. In the final step the CAEX tool calculates power consumption by multiplying the switching activities of every node by the corresponding capacitance (equation 1).

VHDL source

Parser Inputs name & size Vector generation

DO file genrator DO file QuickSim QSIM script

Toggle simulation Act.file generation

Input Vetcors

Prob. Act. Estimator

Input prob. values extraction Reconvergance struct. analysis Prob. values propagation

Act. file Cap. file

Power Calculator

Power Estimate

Figure 10: Second phase of internal operation The tool discussed here was used for the LPGD project both as power estimator and as an exploration tool.

An RT-level exploration example

In this section an example of RT-level exploration performed using the CAEX-tool is given. A critical part of the implementation of the algorithm used in the LPGD project [7] is the evaluation of the following function: Angle = Arc tan(Q / I ) , where Q, I and Angle are 6-bit signals. Due to the small word length of the input streams, a look-up table (LUT) implementation is chosen. A direct approach would give a LUT of 2 6 2 6 8 = 32Kbits. The properties of the trigonometric functions are used in order to reduce the LUT size. By ignoring the signs of I and Q, only the 64 out of the 256 angles are stored in the LUT, i.e. the angles that belong to the first quadrant. The signs are no longer used for the addressing of the LUT, therefore the size of the LUT can be 25 2 5 6 = 6Kbits. The signs of I and Q are used after the access to the LUT, in order to place the angle to the correct quadrant.
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So far it is obvious that the later approach for the implementation of the Arctan function was more effective in terms of both power and area. But also another alternative is feasible: The LUT size can be further reduced by exploiting the following trigonometric property: If one stores only the arctan values for angles corresponding to Cartesian co-ordinates where Q<I (i.e. angles in the range [0, pi/4) ), then the values for angles in the range (pi/4, pi/2] can be obtained by swapping I and Q and using the following identity: arctan(Q/I)= pi/2 - arctan (I/Q), I0, Q0. Now the arctan LUT has a size of n2 n 2 n (n=25), in order to store only the arctan values for Q<I. 2 In order to access the LUT as a single-dimension array, a simple addressing scheme is used: LUT_address (Q,I) = (Q^2 - Q)/2 + I 25 25 2 5 5 = 2400 bits. Since only angles in the range [0, pi/4) are stored, the final LUT size is 2 The question now is which of the two alternatives (6k-bit LUT or 2400-bit LUT + addressing + logic) is the more power and area effective. In order make a decision a VHDL source was written for both possible implementations. For the implementation of the LUT a multiplexer tree with set inputs was used. The CAEX tool was used in order to estimate power and area of the two alternative implementations of the Arctan function. The same inputs were fed to the tool for both of them. The es2-07m cell-library was used for mapping. Real-delay simulation-based power estimation was preferred since the size of the circuits was relatively small, and thus the time overhead comparing to the probabilistic estimation would be small. Two hundred thousand input vectors taken from sample application data was fed to the power estimation. The results of the comparison are illustrated in table 3. It must be stressed that the time spend for this comparison was less than fifteen minutes (excluding time spend for the writing of the VHDL sources). Taking under consideration that the press button approach was used, the actual time spend by the designer was just the time needed for feeding the inputs and reading the outputs, which is less than one or two minutes.

Description Implementation 1 Implementation 2 1k6 bits LUT

Power (mW/MHz) 1,743

Area (mm2) 0,508 0,101

0,278 4805 bits LUT, indexing, logic Table 3: The result of the CA exploration

Conclusions-Discussion

A CAD tool for performing power exploration at the register-transfer and logic level was presented in this report. The development of such tool comes from: i) the need for low power implementation of GSM/DECT algorithms and ii) the need of industrial partner for a power estimation tool, which can use Mentor Graphics routines. More specifically, since the DECT receiver was a very critical module and its architectural level exploration was complicated for deriving power-efficient design due to the DECT algorithm characteristics, the developed CAEX tool assisted the power exploration task. Also, the design, i.e. power exploration, of two critical blocks of DECT receiver (Automatic Frequency Correction and Symbol Timing Estimation & Slot Synchronisation) should be done at lower design level. For that purpose, we developed a logic level power estimator [8]. Concerning the industrial partner, its design flow starts from the specifications level or architecture level (i.e. RT) and the design optimisation criteria were mainly the area and performance. Thus, the need for power exploration was critical. The CAEX has as input the (structural) VHDL description of the considered module and estimates the associated power consumption. Also, an interesting feature is that the RT-tool can plug-in Mentor Graphics environment, without any demand for specific information of Mentor tools from the designer

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aspect. Thus, the designer can spend more effort to find or use architectural level transformations. For each architecture alternative, employing the environment of CAEX, we performed power exploration. The CAEX tool here described was developed for the needs of LPGD project. Explorations mainly concerning the selection of RT-level components were carried out using this tool. For demonstration reasons, we provide a certain example from the LUT design of the DECT receiver. Also, it was used for the exploration made for the implementation of the FIRs included in the LPGD [9]. It was proved to be a very useful tool the use of which significantly reduced the effort required for this short of exploration.

References
[1] A.P. Chandrakasan, S. Sheng, and R.W. Brodersen, Low Power Digital CMOS Design, in IEEE J. of Solid State Circuits, pp. 473-484, April 1992. [2] A.P. Chandrakasan, R. Mehra, M. Potkonjak, J. Rabaey, and R.W. Brodersen, Optimizing Power Using Transformations, in IEEE Trans. On CAD, pp. 13-32, Jan. 1995. [3] D. Singh, J. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T. Mozdzen, Power Conscious CAD Tools and Methodologies: A Perspective, in Proc. of IEEE, vol. 83, no. 4, pp. 570-594, April 1995. [4] R. Marculescu, D. Marculescu, and M. Pedram, Logic Level Power Estimation Considering Spatiotemporal Correlations, in Proc. of IEEE Int. Conf. on Computer Aided Design, 1994, pp. 294-299. [5] Ercolani, M. Favalli, M. Damiani, P. Olivio, and B. Ricco, Estimate of Signal Probability in Combinational Logic Networks, in Proc. of First European Test Conference, 1989, pp. 132-138. [6] S. Theoharis, G. Theodoridis, D. Soudris, and C. Goutis, A New Method for Switching Activity Estimation of Logic Level Networks, in Proc. of 7th Int. Workshop Power and Timing Modelling, Optimization and Simulation (PATMOS 97), Sept. 8-11, Louvain-la-Neuve, Brussels, pp. 131140, 1997. [7] M. Perakis, D. Soudris, C. Goutis and A. Thanailakis, Low Power Architecture Design of GSM/DECT Algorithms, Deliverable Report LPGD/WP3/UP/D3.3R1 (ESPRIT 25256), Dec. 1998. [8] S. Theoharis, G. Theodoridis, D. Soudris, and C. Goutis, Logic Level Power Estimator, Deliverable Report LPGD/WP3/UP/D3.3S1 (ESPRIT 25256), Dec. 1998. [9] Report Mizas FIR [10] Devadas, K. Kreutzer, and J. White, Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation, in IEEE Trans. on CAD, vol. 11, no. 3, March 1992, pp. 373-383 [11] Schneider, U. Schlictman, and B. Wurth, Fast Power Estimation of Larger Circuits, in IEEE Design & Test of Computers, Spring 1996, pp. 70-78 [12] Brayant, Graph-Based Algorithms for Boolean Function Manipulation, in IEEE Transactions on Computers, vol. C-35, August 1986, pp. 677-691

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Appendix A
vhdl_dir comp_name lib_name

configure
vhdl_dir comp_name lib_name

create_lib creates working directory maps to working directory

comp_name

lib_name lib_name input_number

compile_comp syntax qvhcom command compile vhdl source

compiled component comp_name lib_name

input_vectors Vector Generator

in_vec_file

Vector_compaction synth_comp print alui commands

vec_file

Autologic
cap_file area report synthesized component

comp_name

comp_name

vec_file

comp_name

sim_estimate
in_arr input_number act_file

calculate_power repair_cap_file
cap_file

pob_estimate parser
pipe file

init_array
input_number

calculate power (cap_file x act_file)

initialize in_arr * EDDM2SLIF

vec_file in_arr input_bits comp_name power

Input Vector Analyzer Probabilistic Power Estimator

act_file

print_qsim_script
qsim script

DVE

QUICKSIM

qsim_file

repair_qsim_file
act_file

Figure 11: The structure of the CAEX software

In this appendix the structure of the CAEX software is reported. The CAEX tool was realized using ANSI C. As shown in figure 11 there are eight major routines. The routine called configure is responsible for the initialization of the environment-related variables (sources directory, circuit file name and working directory name) and receives all the required inputs (cell-library name, optimization options, vector generation related options) to proceed for the press button approach. The routine create_lib creates a working directory and maps to it. The compile_comp routine creates and executes a script for the compilation (Qvhcom tool of the Mentor Graphics framework) the specified design
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(comp_name variable) and reports the number of errors occurred during compilation. The synth_component routine writes and executes a script for the synthesis and optimization steps (Autologic II is invoked) with respect to the option given by the call of the configure routine. The output of the latest routine is the capacitance and area reports extracted by Autologic II and a logic level description of the synthesized and optimized circuit in EDDM format. The prob_estimate routine is called for probabilistic activity estimation and sim_estimate for the simulation-based activity estimation. For both cases in the first step a parser is invoked that finds the number and size of the circuits inputs. This information is needed in order to produce the input vector file. In the next step the in-house tool for vector generation is invoked if sample application data are not available. The input vectors are then compacted by the vector_compaction routine. In the case that probabilistic switching activity estimation was chosen in the first step the EDDM format is converted to SLIF. Sequentially the input vector analysis and the reconvergence structural analysis are performed, while in the last step the probabilistic values of the inputs are propagated using the reported models, and the switching activity of every node in the circuit is calculated and reported to the activity file. In the case that simulation based activity estimation was chosen in the first step, scripts for the invocation of DVE (Design View-point Editor) and QuickSim are extracted and executed. DVE produces additional information needed in order the QuickSim to be able to perform simulation for the circuit prior being in EDDM format. The QuickSim produces the qsim_file which contains the activity for each node. In the final step the calculate_power routine is called the aim of which is to calculate the power using equation 1. The repair_qsim_file and repair_cap_file routines are responsible to make the formats of the reports for capacitance from Autologic II and activity from QuickSim compatible.

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