Beruflich Dokumente
Kultur Dokumente
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1-373
Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
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1-374
Course Roadmap
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1-375
Course Roadmap
Combinatorial Circuits
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1-376
Course Roadmap
Combinatorial Circuits
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1-377
Course Roadmap
Combinatorial Circuits
Sequential Circuits
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1-378
Course Roadmap
Combinatorial Circuits
Logic Circuits with gates Logic Circuits with memory Specific Specific Specific Specific functions functions functions functions
Sequential Circuits
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1-379
Course Roadmap
Combinatorial Circuits
Logic Circuits with gates Logic Circuits with memory Specific Specific Specific Specific functions functions functions functions
Sequential Circuits
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1-380
Shift Register
Q0 Q1 Q2 Q3 Q4 Q5 Q6
SI
SO
Clk
Present State Q0 Q1 Q2 Q3 Q4 Q5 Q6
Input SI
Output S0=Q6
SI
N-bit S/R SO
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1-381
SI
SO
Clk
Q0 Q1 Q2 SI
N-bit S/R SO
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1-382
Clk
D0 D1 D2 N-bit S/R Q0 Q1 Q2
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004
SI
SO
Clk P/S
D0 D1 D2
QN-1
1-384
Tandem S/Rs
Serial registers
Clock
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1-385
Inputs
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1-386
Inputs
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1-387
S SI I N-bit S/R SO
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1-388
Output Mapping
S SI I N-bit S/R SO
SI=1 SI=1
1BCDE
SI=0 SI=1
ABCDE
SI=0
0BCDE
SI=0
1-389
Input Data
Descrambled Data
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1-390
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1-391
Course Roadmap
Combinatorial Circuits
Logic Circuits with gates Logic Circuits with memory Specific Specific Specific Specific functions functions functions functions
Sequential Circuits
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1-392
Inputs
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1-393
Inputs
State-to-state transitions follow a counting sequence Inputs (if any) may be used to set counting range, direction, starting point
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1-394
Counters
Binary Ripple Counter
1 Clock 1
Clock A
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1-395
Counters
Binary Ripple Counter
1 Clock 1
Clock A B
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1-396
Counters
Binary Ripple Counter
1 Clock 1
Clock A B C
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1-397
Counters
Binary Ripple Counter (idealized)
1 Clock 1
Clock A B C 000 111 011 101 001 110 010 100 000 111 011 101 001 110
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1-398
Counters
Binary Ripple Counter (more realistic)
1 Clock 1
Clock A B C 000 111 011 101 001 110 010 100 000 111 011 101 001 110
100 110
{
111
{
101
{
100 110
110
111
101
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1-399
Cascading Counters
1 Clock
T Q
Clock Q0
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1-400
Cascading Counters
1 Clock
T Q
T Q
Clock Q0
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1-401
Cascading Counters
1 Clock
T Q
T Q
T Q
Clock Q0 Q1
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1-402
Cascading Counters
1 Clock
T Q
T Q
T Q
T Q
Clock Q0 Q1 QN
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1-403
Cascading Counters
1 Clock
T Q
T Q
T Q
T Q
Clock Q0 Q1 QN
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1-404
FJAR(A,B,C) 1
FJBR(A,B,C) 1
FJBR(A,B,C) 1
Clock
FKAR(A,B,C) 1
FKBR(A,B,C) 1
FKBR(A,B,C) 1
FJAS(A,B,C) 1
FJBS(A,B,C) 1
FJBS(A,B,C) 1
FKAS(A,B,C) 1
FKBS(A,B,C) 1
FKBS(A,B,C) 1
Clock
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
1-405
Synchronous Counters
BCD Counter: State table
0001 0010 0011 0100
Present State 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
0000
0101
0110
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1-406
Synchronous Counters
BCD Counter: J-K inputs
DC 00 BA 00 01 11 10 DC 00 01 11 10 BA 00 01 11 10
0010 0001 0011 0100
X KA
0000
JA
01 11 10 00
0101
1001
00 01 11 10
X KB
Present State Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
1-407
JB
01 11 10 00
00 01 11 10
X KC
JC
01 11 10 00
J-K operation: 0 0 0 X
1 0 1 X
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
00 01 11 10
X KD
1 0
X 1 X 1 1 0
JD
01 11 10
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004
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Synchronous Counters
BCD Counter: J-K inputs
DC 00 BA 00 01 11 10 DC 00 01 BA 00 01 11 10
0010 0001 0011 0100
1 X X X X X X 0 X X X X X X 0 X X X X X X 0
X X X X X X X X KA
0000
JA
01 11 10 00
0101
11 10 00 01 11 10 00 01 11 10 00 01 11 10
0110
JB
01 11 10 00
X X X X X X X X X X X X X X
KB
Present State Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
1-408
JC
01 11 10 00
KC
J-K operation: 0 0 0 X
1 0 1 X
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
1 0
X 1
JD
01
X X X X 10 X X CpE358/CS381
11
Switching Theory and Logical Design Summer-1 2004
X X X X X X Copyright 2004
Stevens Institute of Technology All rights reserved
KD
X 1 1 0
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Synchronous Counters
BCD Counter: J-K inputs
DC 00 BA 00 01 11 10 DC 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 BA 00 01 11 10
0010 0001 0011 0100
JA
01 11 10 00
1 1 X 1 0 0 X 0 0 X X 0
X X X X 1 1 X 0 0 X X 0
X X X X X X X X 1 X X X 0 1 X X
1 1 X X X X X X 0 X X X 0 0 X X
X X X X X X X X X 0 X X X X X 0
1 1 X 1 X X X X X 0 X X X X X 1
1 1 X X 1 1 X X X 1 X X X X X X
X X X X 0 0 X X X 0 X X
KA
0000
0101
0110
JB
01 11 10 00
KB
Present State Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
1-409
JC
01 11 10 00
KC
J-K operation: 0 0 0 X
1 0 1 X
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
0 0 01 0 0 JD 11 X X 10 X X CpE358/CS381
X X KD X X Copyright 2004
1 0
X 1 X 1 1 0
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Synchronous Counters
BCD Counter: J-K inputs
DC 00 BA 00 01 11 10 DC 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 BA 00 01 11 10
0010 0001 0011 0100
JA
01 11 10 00
1 1 X 1 0 0 X 0 0 X X 0
X X X X 1 1 X 0 0 X X 0
X X X X X X X X 1 X X X 0 1 X X
1 1 X X X X X X 0 X X X 0 0 X X
X X X X X X X X X 0 X X X X X 0
1 1 X 1 X X X X X 0 X X X X X 1
1 1 X X 1 1 X X X 1 X X X X X X
X X X X 0 0 X X X 0 X X
KA
0000
0101
0110
JB
01 11 10 00
KB
Present State Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
1-410
JC
01 11 10 00
KC
J-K operation: 0 0 0 X
1 0 1 X
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
0 0 01 0 0 JD 11 X X 10 X X CpE358/CS381
X X KD X X Copyright 2004
1 0
X 1 X 1 1 0
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Synchronous Counters
BCD Counter: J-K inputs
DC 00 BA 00 01 11 10 DC 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 BA 00 01 11 10
0010 0001 0011 0100
JA
01 11 10 00
1 1 X 1 0 0 X 0 0 X X 0
X X X X 1 1 X 0 0 X X 0
X X X X X X X X 1 X X X 0 1 X X
1 1 X X X X X X 0 X X X 0 0 X X
X X X X X X X X X 0 X X X X X 0
1 1 X 1 X X X X X 0 X X X X X 1
1 1 X X 1 1 X X X 1 X X X X X X
X X X X 0 0 X X X 0 X X
KA
0000
0101
0110
JB
01 11 10 00
KB
JA = 1 KA = 1 JB = AD KB = A JC = AB KC = AB JD = ABC KD = A
Present State 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Next State 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000
1-411
JC
01 11 10 00
KC
0 0 01 0 0 JD 11 X X 10 X X CpE358/CS381
X X KD X X Copyright 2004
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Synchronous Counters
BCD Counter
1 Clock
JA = 1 KA = 1
JDKD 00 01 00 01 00 01 00 11 JCKC 00 00 00 11 00 00 00 11 JBKB 00 11 00 11 00 11 00 11 JAKA 11 11 11 11 11 11 11 11
JB = AD KB = A
Next State 0001 0010 0011 0100 0101 0110 0111 1000
JC = AB KC = AB
Present State 1000 1001 1010 1011 1100 1101 1110 1111 JDKD 00 01 00 01 00 01 00 11 JCKC 00 00 00 11 00 00 00 11 JBKB 00 01 00 01 00 01 00 01 JAKA 11 11 11 11 11 11 11 11
JD = ABC KD = A
Next State 1001 0000 1011 0100 1101 0100 1111 0001
Present State 0000 0001 0010 0011 0100 0101 0110 0111
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1-412
Synchronous Counters
BCD Counter
Present State 0000 0001 0010 0011 0100 0101 0110 0111 JDKD 00 01 00 01 00 01 00 11 JCKC 00 00 00 11 00 00 00 11 JBKB 00 11 00 11 00 11 00 11 JAKA 11 11 11 11 11 11 11 11 Next State 0001 0010 0011 0100 0101 0110 0111 1000 Present State 1000 1001 1010 1011 1100 1101 1110 1111 JDKD 00 01 00 01 00 01 00 11 JCKC 00 00 00 11 00 00 00 11 JBKB 00 01 00 01 00 01 00 01 JAKA 11 11 11 11 11 11 11 11 Next State 1001 0000 1011 0100 1101 0100 1111 0001
0000
0101
1001 1000
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004
0110 0111
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1-413
Varieties of Counters
Counters with Parallel Load Normal counter operation D0 D1 D2 D3 1 CI CO LD Q0 Q1 Q2 Q3 0
State 0000 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 XXXX WXYZ
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0
D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX
Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ
CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-414
Varieties of Counters
Counters with Parallel Load Normal counter operation D0 D1 D2 D3 1 CI CO LD Q0 Q1 Q2 Q3 0
State 0000 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 XXXX WXYZ
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0
D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX
Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ
CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-415
Varieties of Counters
Counters with Parallel Load Loading next state in parallel D0 D1 D2 D3 = ABCD CI CO LD 1
State 0000 0001 0010 0011 0100 1000 1001 Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-416
Q0 Q1 Q2 Q3 --> ABCD
Varieties of Counters
Counters with Parallel Load
State 0000 Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-417
D0 D1 D2 D3 0 CI CO LD Q0 Q1 Q2 Q3
0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 XXXX WXYZ
Varieties of Counters
Counters with Parallel Load
State 0000 Load 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CI 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 D3D2D1D0 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX ABCD XXXX Next State 0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 0000 ABCD WXYZ CO 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 www.UandiStar
1-418
D0 D1 D2 D3 CI CO LD Q0 Q1 Q2 Q3
0001 0010 0011 0100 1000 1001 1010 1011 1100 1101 1110 1111 XXXX WXYZ
D0 D1 D2 D3 CI B 0 LD Q0 Q1 Q2 Q3 0 CO
D0 D1 D2 D3 CI C LD Q0 Q1 Q2 Q3 0 CO
CO
COA 0 1 1 1
COB 0 0 1 1
COC 0 0 0 1 www.UandiStar
1-420
CI
CO LD
CI
CI LD
CO
CI LD
CO
CI LD
Clock/N
Clock
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1-421
Reference Oscillator f R
Divide By K
Lowpass Filter
fS
Synthesized Frequency
fS/N
Divide By N
Channel Selection, N
fS =
N fR K
PLL frequency synthesizers used in TV, radio, cellular phones, PCs, modems, etc.
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
1-422
Master Clock
fm
Divide by A
fm/A
Divide by B
fm/B
Divide by C
fm/C
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1-423
Master Clock
fm
Clock Phase A
Clock Phase B
Clock Phase C
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1-424
Ring Counters
Only 1 FF is set at any given time
States 10000 01000
D Q D Q D Q D Q D Q
Clock Clock QA QB QC QD QE
10000
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1-425
E
Q
Clock Clock QA QB QC QD QE
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1-426
Summary
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
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1-427
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1-428