IFET COLLEGE OF ENGINEERING

VILLUPURAM DEPARTMENT OF
ELECTRICAL & ELECTRONICS ENGINEERING

LABORATORY MANUAL
EE2258 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY IV - SEMESTER EEE

PREPARED BY

G. LAVANYA M.E
Assistant Professor Department of Electrical and Electronics Engineering

INDEX
S.N o 1 2 DATE EXPERIMENTS Study of basic digital ICS Implementation of Boolean functions, adder/ subtractor circuits Code converters, parity generator and parity checking, excess-3,2s complement, binary to gray code using ICs Encoders and decorders Counters: design and implementation of 4-bit modulo counters as synchronous and asynchronous types. Shift registers: design and implementation of 4-bit shift registers in SISO,SIPO,PISO,PIPO Study of 4:1 multiplexer, 1:4 demultiplexer Timer IC application: Study of SE/NE 555 timer in Astable, Monostable Operation Application of Op-Amp: Slew rate verifications, inverting and non-inverting amplifier, adder, comparator, integrator, differentiator Study of analog to digital converter and digital to analog converter: verification of A/D conversion. Study of VCO and PLL ICs: i)voltage to frequency characteristics of NE/SE 566IC ii)frequency multiplication using NE/SE 565 PLL IC PAGE NO MARKS SIGNATURE

3(a)

3(b)

5 6 7

10

EE 2258 INTEGRATED CIRCUITS LABORATORY AIM To study various digital & linear integrated circuits used in simple system configuration. 1. Study of Basic Digital ICs. (Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF, D FF) 2. Implementation of Boolean Functions, Adder/ Subtractor circuits. 3. (a)Code converters, Parity generator and parity checking, Excess 3, 2s Complement, Binary to grey code using suitable ICs. (b)Encoders and Decoders: Decimal and Implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable ICs. 4. Counters: Design and implementation of 4-bit modulo counters as synchronous and asynchronous types using FF ICs and specific counter IC. 5. Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable ICs. 6. Multiplex/ De-multiplex : Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer 7. Timer IC application. Study of NE/SE 555 timer in Astable, Monostable operation. 8. Application of Op-Amp-I. Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrater and Differentiator. 9. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated ICs. 10. Study of VCO and PLL ICs. Voltage to frequency characteristics of NE/ SE 566 IC. Frequency multiplication using NE/SE 565 PLL IC. DETAILED SYLLABUS 1. Study of Basic Digital ICs. (Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF, D FF) Aim To test of ICs by using verification of truth table of basic ICs. Exercise 1. Breadboard connection of ICs with truth table verification using LEDs. 2. Implementation of Boolean Functions, Adder/ Subtractor circuits. (Minimization using K-map and implementing the same in POS, SOP from using basic gates)

Aim Minimization of functions using K-map implementation and combination circuit. Exercise 1. Realization of functions using SOP, POS, form. 2. Addition, Subtraction of atleast 3 bit binary number using basic gate IC s. 3a) Code converters, Parity generator and parity checking, Excess 3, 2s Complement, Binary to grey code using suitable ICs . Aim Realizing code conversion of numbers of different bar. Exercise 1. Conversion Binary to Grey, Grey to Binary; i. 1s. 2s complement of numbers addition, subtraction, 2. Parity checking of numbers using Gates and with dedicated ICs Encoders and Decoders: Decimal and Implementation of 4-bit shift registers in SISO, SIPO,PISO,PIPO modes using suitable ICs. Exercise 1. Decimal to binary Conversion using dedicated ICs. 2. BCD 7 Segment display decoder using dedicated decoder IC& display. Counters: Design and implementation of 4-bit modulo counters as synchronous and asynchronous types using FF ICs and specific counter IC Aim Design and implementation of 4 bit modulo counters. Exercise 1. Using flipflop for up-down count synchronous count. 2. Realization of counter function using dedicated ICs. Shift Registers. Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO modes using suitable ICs. Aim Design and implementation of shift register. Exercise 1. Shift Register function realization of the above using dedicated ICs a. For SISO, SIPO, PISO, PIPO, modes of atleast 3 bit binary word. 2. Realization of the above using dedicated ICs. Multiplex/ De-multiplex Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer Aim To demonstrate the addressing way of data channel selection for multiplex Demultiplex operation. Exercise 1. Realization of mux-demux functions using direct ICs 2. Realization of mux-demux using dedicated ICs for 4:1, 8:1, and vice versa. Timer IC application. Study of NE/SE 555 timer in Astable, Monostable operation.

3b)

4.

5.

6.

7.

Aim To design a multi vibrator circuit for square wave and pulse generation. Exercise 1. Realization of Astable multi vibrator & mono stable multi vibrator circuit using Timer IC. 2. Variation of R, C, to vary the frequency, duty cycle for signal generator. 8. Application of Op-Amp-I Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrater and Differentiator. Aim Design and Realization of Op-Amp application. Exercise 1. Verification of Op-Amp IC characteristics. 2. Op-Amp IC application for simple arithmetic circuit. 3. Op-Amp IC application for voltage comparator wave generator and wave shifting circuits. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated ICs. Aim Realization of circuit for digital conversions. Exercise 1. Design of circuit for analog to digital signal conversion using dedicated ICs. 2. Realization of circuit using dedicated IC for digital analog conversion. 10. Study of VCO and PLL Ics i) Voltage to frequency characteristics of NE/ SE 566 IC. ii) Frequency multiplication using NE/SE 565 PLL IC. Aim Demonstration of circuit for communication application Exercise 1. To realize V/F conversion using dedicated ICs vary the frequency of the generated signal. To realize PLL IC based circuit for frequency multiplier, divider.

9.

Ex. No. 1 Date : AIM:

STUDY OF BASIC DIGITAL ICS

To verify the truth table for AND, OR, EXOR, NOT, NOR, NAND and JK, RS, D, T Flip Flops. APPARATUS REQUIRED: Digital Trainer Kit. Connecting wires. COMPONENTS REQUIRED: IC 7408, IC 7404, IC 7432, IC 7486, IC 7400, IC 7402 and IC 7410. PROCEDURE: 1. Connections are made as per the pin/logic diagrams. 2. Truth tables are verified. PIN DIAGRAMS AND TRUTH TABLES: AND C= A.B 14 13 12 Vcc A 0 IC 7408 0 1 1 GND 1 2 3 4 5 6 7 B 0 1 0 1 C 0 0 0 1 11 10 9 8

OR 14 Vcc

C= A+B

A 0 0 IC 7432 1 1

B 0 1 0 1

C 0 1 1 1

9 1 2 3

8 4 5 6

GND

7 NOT Vcc 14 13 12 11 10 9 8 A 0 1 IC 7404 B 1 0 B=A

6 7

GND

Ex- OR Vcc 14 13 12 11 10 9 8

C=AB

A 0 0 IC 7486 1 1

B 0 1 0 1

C 0 1 1 0

3 4

6 7 GND

NAND 14 13 12 Vcc 11 10 9 8 A 0 0 IC 7400 1 1

C = A . B

B 0 1 0 1

C 1 1 1 0

GND 1 2 3 4 5 6 7

NOR 14 13 Vcc 12 11 10 9 8

C=A +B

A 0 0

B 0 1 0 1

C 1 0 0 0

IC

7402

1 1

2 3

6 7

GND

LOGIC DIAGRAMS AND TRUTH TABLES: JK FLIP FLOP:

J Q CLK K Q

Clk

R 0 1 0 1

S 0 0 1 1

Q NC 1 0 Toggl e

RS FLIP FLOP: S Q CLK R Q

Clk

R 0 0 1 1

S 0 1 0 1

Q NC 1 0 Race

D FLIP FLOP: D Q CLK

Clk

D 0 1

Q 0 1

T FLIP FLOP T Q CLK

Clk

T 0 1

Q NC Complement

RESULT: Thus the truth table for AND, OR, EXOR, NOT, NOR, NAND gates and JK, RS, D, T Flip Flops are verified.

Ex. No. 2 Date : AIM:

IMPLEMENTATION OF BOOLEAN FUNCTIONS

(a) To minimize Boolean functions using K-map and to implement the same in POS and SOP forms using basic gates. (b)To implement Half Adder, Full Adder, Half Subtractor and Full Subtractor Circuits. APPARATUS REQUIRED: Digital Trainer Kit. Connecting wires. COMPONENTS REQUIRED: IC 7408, IC 7432, IC 7404 and IC 7486. PROCEDURE: 1. The logic circuit is designed using K map. 2. Gates are decided for the logic circuit. 3. Connections are made as per the logic diagrams. 4. Truth tables are verified. (a) MINIMIZATION IMPLEMENT AND POS FORMS m(2,3,5,7,9,11,12,13,14) SOP: CD 00 AB 00 01 11 10 1 1 1 1 1 01 11 1 1 1 10 1 F= AB C + A B D + A BD + A BC + A B D OF BOOLEAN IN F= FUNCTION AND TO SOP

TRUTH TABLE: Inputs A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output F 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 0

LOGIC DIAGRAM: A B C D

POS: CD 00 AB 00 01 11 10 0 0 0 0 0 01 0 0 11 10

F= AB C + A B D + A BD + A B C D F=(A+B+C).(A+B + D).(A + B+D). (A+B+C+D)

TRUTH TABLE: Inputs B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Output F 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 0

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

LOGIC DIAGRAM: A B C D

A+B+C +D (A+B+C+D) (A+B+D)

F A+B+D A+B+D

(A+B+D) (A+B+C) A+B+C

(b)

IMPLEMENTATION OF HALF ADDER, FULL ADDER, HALF SUBTRACTOR AND FULL SUBTRACTOR CIRCUITS Half Adder: Block

Diagram: Inputs A 0 0 1 1 B 0 1 0 1 Outputs Sum 0 1 1 0 Carry 0 0 0 1 A B HA Sum Carry

Sum: A 0 1 1 0 B 0 0 1 1 A

Carry: B 0 1 0 0 0 1 0 1

Sum = (AB +A B) = A B A B

Carry = A. B Sum = A B

Carry = A.B

Full Adder: Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Outputs Sum 0 1 1 0 1 0 0 1 Carry 0 0 0 1 0 1 1 1 A B

Block Diagram:

C Sum FA Carry Expression = A + B + C

Sum: BC A 0 1 00 01 1 1 1 11 1 10

Carry: BC A 0 1 00 01 11 10 1 Expression = AB + C(A + B) 1 1 1

Sum = A B A B C

C AB

Carry = AB + C(A + B)

Sum= A B C

C(A+B) A+B AB Carry = AB + C(A+ B)

Half Subtractor:

Block Diagram:

Inputs A 0 0 1 1 B 0 1 0 1

Outputs Diff 0 1 1 0 Borr 0 1 0 0 A B HS Diff Borr

Difference:

Borrow:

A 0 1

0 0 1

1 1 0

A 0 1

0 0 0

1 1 0

Diff = (AB +A B) = A B A B

Borr= A. B

Difference = A

Borrow = A.B

Full Subtractor: Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Outputs Diff 0 1 1 0 1 0 0 1 Borr 0 1 1 1 0 0 0 1 A B

Block Diagram:

C Diff FS Borr

Difference: BC A 0 1 00 01 1 1 1 11 1 10

Borrow: BC A 0 1 00 01 1 11 1 1 Carry = AB + C(A + B) 10 1

Sum = A B

Difference

Borrow

RESULT: (a) gates Thus minimization of Boolean functions using K-map is

performed and same is implemented in POS and SOP forms using basic

(b) Thus Half Adder, Full Adder, Half Subtractor and Full Subtractor Circuits are implemented.

Ex. No. 3.a Date : AIM:

CODE CONVERTERS, PARITY GENERATOR, PARITY CHECKER

To construct logic diagram and to verify the truth table for (a) Binary to Gray code Converter (b) Gray to Binary code converter (c) Odd Parity Generator (d) Odd Parity Checker (e) Even Parity Generator (f) Even Parity Checker APPARATUS REQUIRED: Digital Trainer Kit Connecting wires COMPONENTS REQUIRED: IC7404, IC 7432, IC 7408, IC 7486 and IC 7411 PROCEDURE: The logic circuit is designed using K map. Gates are decided for the logic circuit. Connections are made as per the logic diagrams. Truth tables are verified.

(a) BINARY TO GRAY CODE CONVERTER TRUTH TABLE: Binary code B1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 K Map G1: B3B4 00 B1B2 00 01 11 10 1 1 1 1 1 1 1 1 G1 = B1 01 11 10 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Gray code G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G3 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G4 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

G2: B3B4 00 B1B2 00 01 11 G2 = B1 B2 10 1 1 1 1 1 1 1 1 01 11 10

G3: B3B4 00 B1B2 00 01 11 10 1 1 1 1 1 1 G3 = B2 B3 1 1 01 11 10

G4: B3B4 00 B1B2 00 01 11 10 1 1 1 1 1 1 1 1 G4 = B3 B4 01 11 10

LOGIC DIAGRAM: B1 B2 B3 B4 G1 G2

G3

G4

(b) GRAY TO BINARY CODE CONVERTER: TRUTH TABLE: Gray code G1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 G3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 G4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Binary code B2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B3 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 B4 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

K MAP: B1 : G3G4 00 G1G2 00 01 11 10 1 1 1 1 1 1 1 1 B1 = G1 01 11 10

B2: G3G4 00 G1G2 00 01 11 10 1 1 1 1 B2 = G1 G2 1 1 1 1 01 11 10

B3: G3G4 00 G1G2 00 01 11 10 1 1 1 1 1 1 B3= G1 G2 G3 1 1 01 11 10

B4:

G3G4 00 G1G2 00 01 11 10 1 1 1 1 1 1 1 B4= G1 G2 G3 G4 1 01 11 10

LOGIC DIAGRAM: G1 G2 G3 G4 B1 B2

B3

B4

(c) ODD PARITY GENERATOR: TRUTH TABLE: Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Output P 1 0 0 1 0 1 1 0

K - Map BC A 1 0 00 1 1 01 11 1 1 10

P = A BC + A B C + AB C + A BC P = A( BC + BC ) + A( B C ) LOGIC DIAGRAM: A B C

(d) ODD PARITY CHECKER TRUTH TABLE: Inputs A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 K Map CD 00 AB 00 01 11 10 1 1 1 1 1 1 1 1 01 11 10 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D(P) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output P 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1

P = (A+B+ C+D)

LOGIC DIAGRAM: A B C D P

(e) EVEN PARITY GENERATOR: TRUTH TABLE: Input A 0 0 0 0 1 1 1 1 K MAP: BC 00 A 0 1 1 1 1 1 01 11 10 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Output P 0 1 1 0 1 0 0 1

P = A B C

LOGIC DIAGRAM: A B C P

(f) EVEN PARITY CHECKER: TRUTH TABLE: Inputs A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D(P) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output P 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

K MAP: CD 00 AB 00 01 11 10 1 1 1 1 1 1 1 1 01 11 10

P=ABCD LOGIC DIAGRAM: A B C D P

RESULT: Thus the logic diagrams are constructed and truth tables are verified for a) Binary to Gray code Converter b) Gray to Binary code converter c) Odd Parity Generator d) Odd Parity Checker e) Even Parity Generator f) Even Parity Checker

Ex. No. 3.b Date : AIM:

ENCODERS AND DECODERS

To construct logic diagram and to verify the truth table for Encoder and decoders APPARATUS REQUIRED: Digital Trainer Kit Connecting wires COMPONENTS REQUIRED: IC7404, IC 7432, IC 7408, IC 7486 and IC 7411 PROCEDURE: The logic circuit is designed using K map. Gates are decided for the logic circuit. Connections are made as per the logic diagrams. Truth tables are verified.

8 TO 3 LINE ENCODER: TRUTH TABLE: D0 1 0 0 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0 D3 0 0 0 1 0 0 0 0 D4 0 0 0 0 1 0 0 0 D5 0 0 0 0 0 1 0 0 D6 0 0 0 0 0 0 1 0 D7 0 0 0 0 0 0 0 1 X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1

D0 D1 D2 D3 D4 D5 D6 LOGIC DIAGRAM:

D7

(h) 3 TO 8 LINE DECODER: TRUTH TABLE: X 0 0 0 0 1 1 1 Y 0 0 1 1 0 0 1 Z 0 1 0 1 0 1 0 D0 1 0 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0 D3 0 0 0 1 0 0 0 0 D4 0 0 0 0 1 0 0 0 D5 0 0 0 0 0 1 0 0 D6 D D7 = xyz 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

1 1 1 0 LOGIC DIAGRAM:

D1 = xyz

D2= xyz Y

D3= xyz

D4= xyz

D5 xyz

D6= xyz

D7= xyz

RESULT: Thus the logic diagrams are constructed and truth tables are verified for a) 8 to 3 line Encoder b) 3 to 8 line Decoder

Ex. No. 4 Date :

COUNTERS

AIM: To design and implement 4 bit Synchronous mod-10 Counter Asynchronous Up Counter using JK flip flops. APPARATUS REQUIRED: Digital Trainer Kit Connecting wires. COMPONENTS REQUIRED: IC 7408 and IC 7476. PROCEDURE: The logic circuit is designed using K map. Gates are decided for the logic circuit. Connections are made as per the logic diagrams. Truth tables are verified.

PIN DIAGRAM: JK FLIP FLOP:

Vcc = 5V 2 Pr 2.2K 2.2K 4 CLK SOURCE 1 16 K Cr 3 J Q 15 LED 330 _ Q 14 LED 330

7476

Vcc = 5V

a) SYNCHRONOUS MOD-10 COUNTER STATE TABLE: Present State A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 Next State A B C D + 0 0 0 0 0 0 0 1 1 0 + 0 0 0 1 1 1 1 0 0 0 + 0 1 1 0 0 1 1 0 0 0 + 1 0 1 0 1 0 1 0 1 0 Flip Flop Inputs K K JA JB A B 0 X 0 X 0 X 0 X 0 X 0 X 0 X 1 X 0 X X 0 0 X X 0 0 X X 0 1 X X 1 X 0 0 X X 1 0 X

JC 0 1 X X 0 1 X X 0 0

K C X X 0 1 X X 0 1 X X

JD 1 X 1 X 1 X 1 X 1 X

KD X 1 X 1 X 1 X 1 X 1

K MAP: JA : CD 00 AB 00 01 11 10 KA : CD 00 AB 00 01 11 X X X X X X X X 1 X X X KA = D 01 11 10 X X X X 1 X X X X JA = BCD 01 11 10

10 JB : CD 00 AB 00 01 11 10 X X

01

11 1

10

X X

X X X

X X X JB = CD

KB : CD 00 AB 00 01 11 10 JC : CD 00 AB 00 01 11 10 X X 1 1 X X X X X X X X X X JC = D 01 11 10 X X X X X X X 1 X X X X KB = CD X 01 11 10

KC :

CD 00 AB 00 01 11 10 X X X X X X X X 1 1 X X X X KC = D 01 11 10

JD : CD 00 AB 00 01 11 10 1 1 X X X X X X X X X X 1 1 X X JD = 1 01 11 10

KD : CD 00 AB 00 01 11 10 X X X X 1 1 X 1 1 1 X X X 1 X X KD = 1 01 11 10

LOGIC DIAGRAM:

HIGH JD

JC

JB

JA

KD

KC

KB

KA

KA QA

KA QA

KA QA

KA QA

CLK A

b) ASYNCHRONOUS UP COUNTER: STATE TABLE: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Present B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 State C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Next State A+ B+ C+ D+ 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0

LOGIC DIAGRAM: A B C D

J CLK CLK A CLK 0 K B 0 0 1

J CLK

J CLK

J CLK

0 Q 1

0 K 1 0

1 0

0 Q 1

0 K 1 0 0

1 0 0

0 Q 1 0

0 K 1 0

1 0

0 Q 1

TIMING DIAGRAM: 0 0 0 C 0 +5V D 0 0 0 0

0 1 1 1 1

1 0 0

1 0

1 0

RESULT: Thus the Synchronous and Asynchronous Counters are designed and implemented.

Ex. No. 5 Date :

SHIFT REGISTERS

AIM: To design and implement 4-bit shift registers in SIPO, PISO modes using suitable ICs. APPARATUS REQUIRED: Digital Trainer Kit. Connecting wires. COMPONENTS REQUIRED: IC 7474, IC 7408, IC 7432 and IC 7404. PROCEDURE: 1. Connections are given as per the logic diagram. 2. Input is given to the gates and flips flops. 3. Output is obtained and the truth table is verified. PIN DIAGRAM: D FLIP FLOP:

2 D Pr 4 J CLK SOURCE 1/6 7404 1 16 K Cr 3 Vcc = 5V Q 15 330 LED _ Q 330 14 LED

7476

(a) SERIAL IN PARALLEL OUT (SIPO):

Data Input 0 1 1 0 CLK 1 1 1 1 QA 0 1 1 0 QB 1 0 1 1 QC 1 1 0 1 QD 1 1 1 0

LOGIC DIAGRAM: SERIA L INPUT 2 3 D QA 7474 clk 5 12 D QA 7474 clk 9 2 D QA 5 7474 clk 12 D 11 1 QA 7474 clk 9

11

CLK SOURCE QA

QB

QC

QD

(b)PARALLEL IN SERIAL OUT (PISO): SHIFT 0 1 1 1 1 CLK 1 1 1 1 1 A 1 1 1 1 1 B 0 0 0 0 0 C 1 1 1 1 1 D 0 0 0 0 0 QD 0 1 0 1 0

LOGIC DIAGRAM:

SHIFT INPUT

PARALLEL INPUTS 7414

1 2 4 5 3 1 3 2 D 7474 clk 5 QA 11 12 D QA 7474 clk

10 9 13 12 8 11

1 2 4 5 3 10 3

4 6

5 QA

12 D QA 7474 clk

5 QA

12 D QA 7474 clk

9 QD

11

CLK SOURCE

RESULT: Thus 4-bit shift registers in SIPO, PISO modes using suitable ICs are designed and implemented.

Ex. No. 6 Date : AIM:

MULTIPLEXER AND DEMULTIPLEXER

To construct the logic diagram and verify the truth table for (a) 2:1 Multiplexer (b)1: 2 De multiplexer (c) 4:1 Multiplexer. (d)1: 4 De multiplexer. APPARATUS REQUIRED: Digital trainer kit Connecting Wires. COMPONENTS REQUIRED: IC 7408, IC 7404, IC 7486 and IC 7432. PROCEDURE: 1. Connections are made as per the logic diagram. 2. The truth tables are verified.

a) 2: 1 MULTIPLEXER:

S0 S0 O/P I0 0 O/P I1 1 0 1 I0 I1

LOGIC DIAGRAM: S0 I0 1 2 IC 7432 O/P IC 7408 3

I1

4 5

6 IC 7408

b) 1: 2 DE MULTIPLEXER: S0 S0 0 I/P 1 O1 O0 0 1 I/P at O0 O1

LOGIC DIAGRAM:

S0 IC 7408 3 O0

7404

1 2

I/P

4 5

6 IC 7408

O1

c) 4: 1 MULTIPLEXER: S0 S1 I0 I1 I2 I3 S0 0 00 01 10 11 O/P 0 1 1 S1 0 1 0 1 O/P I0 I1 I2 I3

LOGIC DIAGRAM:

So

S1

IC7408 IC7486 I0

I1 O/P

IC7432 I2

I3

d) 1:4 DE MULTIPLEXER: S0 S1 O0 O1 O2 O3 I/P 1 00 I/P 01 10 11 LOGIC DIAGRAM: So S1 I/P 0 0 0 0 S0 X 0 0 1 1 S1 0 0 1 0 1 O0 0 0 0 0 0 O1 0 0 1 0 0 O2 0 0 0 1 0 O3 0 0 0 0 1

IC7408

O0

O1

O2

O3

RESULT: Thus logic diagrams are constructed and truth tables are verified for (a) 2:1 Multiplexer (b)1: 2 De multiplexer (c) 4:1 Multiplexer. (d)1: 4 De multiplexer.

Ex. No. 7 Date : AIM:

STUDY OF 555 TIMER

(a) To design and obtain the Mono stable multivibrator using IC555 timer for the given time period, T= 5 sec. (b) To design and obtain the Astable multivibrator using IC555 timer for the given time period. APPARATUS REQUIRED: S.N o. 1 2 3 4 5 6 7 PROCEDURE: 1. Connections are made as per the Circuit diagram. 2. The trigger input is given to pin2 and the output voltage Vo is observed at pin6. 3. Voltage across the capacitor Vc is measured, with the help of CRO. PIN DIAGRAM: Ground Trigger Output Reset 1 2 3 4 IC 555 8 7 6 5 VCC Discharge Threshold Control Voltage

Items IC555 Resistor Capacitor RPS CRO Bread Board Connecting Wires

Range 10K,330 470F,0.01F (0- 30)V

Quantity 1 1 1 1 1 1

a) MONOSTABLE MULTIVIBRATOR: DESIGN: Given T = 5 sec. Assume C = 470 F 5 = 1.1 R ( 470 x 10

-6

T = 1.1 RC )

R = 9.6 K = 10 K .

CIRCUIT DIAGRAM:

+Vcc=5V

8 2 4 6 IC555 3 330 5 7

R =10k

470F

CR O

5 1 0.01F
TRIGGER INPUT

TABULAR COLUMN: S.NO. VOLTAGE (VOLTS) CHARGING TIME TC (SEC) DISCHARGING TIME TD (SEC)

MODEL GRAPH:

VCC

0V 2/3VC
C

VO

0V b) ASTABLE MULTIVIBRATOR: Vcc= 5V

VC

RA = 10K

RB = 4.5K

7 4

8 IC555

3 330 CRO LED

C = 470F

0.01F

TABULAR COLUMNS:

S.No.

VOLTAGE (VOLTS)

TON (mS)

TOFF (mS)

S.No.

V1 (VOLTS)

V2 (VOLTS)

TC (mS)

TD (mS)

MODEL GRAPH:

VO (Volts)

T (ms)

2/3VCC 1/3VCC T (ms)

RESULT: Thus the Mono stable multivibrator and Astable multivibrator using 555 timer for the given time period was designed and waveforms are obtained.

Ex. No. 8 Date :

APPLICATIONS OF OP-AMP

AIM: (a) To measure the following characteristics of Op-Amp IC 741: (i) Input rate. (b) To design and test the operation of Inverting amplifier. (c) To design and test the operation of Non-inverting amplifier. (d) To design and test the operation of summing amplifier. (e) To design and test the operation of Integrator. (f) To design and test the operation of Differentiator. (g)To design and test the operation of Comparator. bias current (ii) Input offset current (iii) Input offset Voltage (iv) Slew

APPARATUS REQUIRED:

S.No. 1 2 3 4 5 6 7 8 9

Name of the Item IC 741 Resistors Capacitors Dual Power Supply RPS Function Generator CRO Bread Board Connecting Wires

Range

Qty 1

1M,1k,10K,100,2.5K,5.2K .01F,.005F

2 2 1 1 1 1 1 Few

PROCEDURE: 1. The connections are made as per the circuit diagram. 2. The inputs are given and the outputs are observed from CRO. 3. In case of slew rate the input sine wave signal is adjusted so that the output is in peak time wave of 1 KHz, the frequency of the input is then increased until the output is diminished. 4. In case of comparator, the reference voltage Vref is varied and the corresponding change in the waveforms are observed. PIN DIAGRAM:

Offset Input Gnd -Ve

1 2 3 4 -

8 7 6 5

NC +Vcc Output Offset

(a) CHARACTERISTICS OF OP-AMP: Input Offset Current: 0.01f Rf = 1M 2 V+ 7 6 Vo Vo Ios = Rf = Observation: Input Offset Current:

IC 741
3 R1 = 1M Cf = 0.01f 4 V-

Input Offset Voltage: V+ 3 2 7 Vo 0.01f Rf= 10 K

IC 741
4 V-

Rcomp =100

Measure the Output Voltage using CRO. Vo = .. Volts Vo Vos = Rf Slew Rate: V+ 7 = .. Volts

R1= 100

Vo

A 741
3 4 V-

RL = 10 K

Measure the Magnitude and Frequency of the Output Voltage using CRO. F = .. Hz Vm = . V SR = ( 2 f Vm ) / 106 Volts / sec.

Inverting Input Bias Current: Cf = 0.01f Rf = 1M V+ 7 6 Vo

IC 741
4 V-

Measure the Output Voltage using CRO. Vo = .. Volts Vo IB - = Rf Non Inverting Input Bias Current = ..nA

V+ 7 6 Vo

IC 741
3 Rf = 1M Cf = 0.01f 4 V-

Measure the Output Voltage using CRO. Vo = .. Volts Vo IB + = Rf = ..nA

b) INVERTING AMPLIFIER:

CIRCUIT DIAGRAM:

Rf =10k

+15V

Rin =1k V
i

Signal Generator +

IC 741 CR O

V0= [-Rf/Rin] Vi

Rcomp=1k -15V

TABULAR COLUMN: DC INPUT: Vin (VOLTS) THEORETICAL OUTPUT (VOLTS) PRACTICAL OUTPUT (VOLTS)

AC INPUT:

Vin (VOLTS)

Tin (ms)

V0 (VOLTS)

T0 (ms)

MODEL GRAPH: Vin (Volts)

t (ms)

Vo (Volts)

t (ms)

c) NON INVERTING AMPLIFIER: CIRCUIT DIAGRAM: Rf =5.6k

+15V

Rin =1k + IC 741 Signal Generator CR O ~ -15V V0= [1+Rf/Rin]

TABULAR COLUMN: DC INPUT: Vin (VOLTS) THEORETICAL OUTPUT (VOLTS) PRACTICAL OUTPUT (VOLTS)

AC INPUT:

Vin (VOLTS)

Tin (mS)

V0 (VOLTS)

T0 (mS)

MODEL GRAPH:

Vin (Volts)

t (ms)

Vo (Volts)

t (ms)

d) SUMMING AMPLIFIER DESIGN: Vo/Rf =-[ V1/R1 +V2/R2 +V3/R3 ] If R1 = R2= R3 =Rf Then Vo= - [V1 +V2 + V3] and Rcomp =R1 || R2 || R3|| Rf If R1 = R2= R3 =Rf = 10 K ,then R comp =2.5 K CIRCUIT DIAGRAM: Rf =10k

V1 V2 V3

R1=10 k R2=10 k R3=10k 3 Rcomp=2.5k 2 V+ 7 6 Vo

IC 741
4 V-

TABULAR COLUMN : Wave form Sine O/P I/P Amplitude (v) Time (mS)

MODEL GRAPH:

Vm

V1

Vm t

V2

Vm

V3

3Vm

V0

e) INTEGRATOR: DESIGN: In an integrator circuit, Fa = Fb/10 where Fa is the frequency of the periodic signal and Fb is the break frequency, assuming the values Fa= 1khz, Rf=10K, Fb= 10Khz, R1 = 1 K From which Fa=1/ (2 Rf Cf) = Cf = 1/(2 R1 Fa) => Cf = 0.015f Fb = 1(2 R1 Cf )= R1 = 1(2 Fb Cf) => R1 = 1.06K CIRCUIT DIAGRAM:

Rf = 10K Cf = 0.015f

R1 = 1K 2 3

V+ 7 6 Vo

IC 741
4 V-

TABULAR COLUMN: Wave form Sine I/P O/P Square I/P O/P Amplitude (v) Time (mS)

MODEL GRAPH:

Vi (volt s)

t(ms) t(ms)

Vi (volts) V0 (volt s)

t(ms) Vo (volts) t(ms)

f) DIFFERENTIATOR: DESIGN: Fb=20 Fa, selecting C1 =0.1 F (C<1F) and Fa = 1KHZ then Fb= 20KHZ From which Fa = 1/(2 Rf C1) = Rf = 1/(2 Fa C1) = Rf= 1.5 K Fb = 1(2 Rf Cf) = Cf = 1/(2 Fb Rf) = Cf= 0.005F CIRCUIT DIAGRAM: Cf = 0.005f Rf = 1.5K R1 = 1K 2 V+ 7

Cf = 0.01f 3

Vo

IC 74 1
4 V-

TABULAR COLUMN: Wave form Sine O/P Square I/P O/P MODEL GRAPH: Vi (volts) I/P

Amplitude(v)

Time (mS)

t(ms)

t(ms) Vi (volts) V0 (volts)

t(ms) t(ms)

Vo (volts)

g) COMPARATOR: CIRCUIT DIAGRAM: Vi R =1K + Vo

R =1K

RL=10K

Vref

TABULAR COLUMN: Wave form Sine I/P Amplitude(v) Time (mS)

O/P

MODEL GRAPH:

Vm Vref 0V t

0V t

RESULT: Thus the characteristics and applications of Op-Amp IC 741 are verified.

Ex. No. 9 Date :

STUDY OF ANALOG TO DIGITAL & DIGITAL TO ANALOG CONVERTER

AIM: (a) To construct a circuit using successive approximation ADC(ADC0804) to convert the analog voltage into its digital equivalent. (b)To design a 3 bit R-2R resistor DAC using Op-Amp. (a) ANALOG TO DIGITAL CONVERTER: APPARATUS REQUIRED:

S.No. 1 2 3 4 5 6 7

Items Resistor Capacitor Pot LEDS ADC Bread Board Connecting wires

Range 10K 150pf 10K

Type

Quanti ty 1 1 1 8 1 1

IC 0804

PROCEDURE: 1. Connections are given as per the circuit diagram 2. In this circuit ADC is connected in free running mode. 3. Initially the conversions are started by connecting signal w R signal momentarily to ground.

4. The digital outputs are observed by means of LEDS for various pot positions and are noted down. COMPUTATION: For an n bit ADC Step size = Vref / pot (2,n) For a 8 bit ADC with Vref = +5v

CIRCUIT DIAGRAM:

+5V

R2 = 10K

Vin+(6) Vin-(7) AGND(8 ) Vreg (9) CLR (19)

D0(18) D1(17) D2(16) D3(15)

IC 080 4

D4(14) D5(13) D6(12) D7(11) wR(3)

TO LEDs

R1 = 1K C1 = 150pF

CLK IN (4) CS(1) RD(2) DGND (10)

INTR(5)

INTR

TABULAR COLUMN: S.No. ANALOG INPUT BINARY OUTPUT OUTPUT COUNT THEORETICAL OUTPUT

(b) DIGITAL TO ANALOG CONVERTER APPARATUS REQUIRED:

S.No.

Name of the Item

Range

Type

Qty

PIN DIAGRAM:

Offset Input Gnd -Ve

1 2 3 4 -

8 7 6 5

NC +Vcc Output Offset

DESIGN:

Vo=VR(Rf/R)[ D1 2-1 +D2 2-2 +D3 2-3 ] PROCEDURE: 1. The connections are given as per the circuit diagram. 2. The input voltages are given according to the circuit. 3. The outputs are observed and plotted.

CIRCUIT DIAGRAM: 1 K 1 K 1 K Rf = 1 K

2 2 K 2 K 2 K 2 K 3 D3 D2 D1

V+ 7 6 Vo

-Vref = -7V

IC 741
4 V-

R2 = 10 K

TABULAR COLUMN: INPUT A B C THEORITICAL OUTPUT PRACTICAL OUTPUT

MODEL GRAPH:

Vo (volts) Bits 000 001 010 011 100 101

RESULT: Thus the successive approximation ADC are R-2R DAC are designed and constructed

Ex. No. 10 Date :

STUDY OF VCO AND PLL ICS.

AIM: (a) (b) To study about voltage controlled oscillator To study about Phase locked loop.

(a)VOLTAGE CONTROLLED OSCILLATOR THEORY: A common type of VCO available in IC form is sign tics NE/SE 566. It consists of a timing capacitor CT linearly charged or discharged by a constant current source/sink. The amount of current can be controlled by changing the voltage Vc applied at the modulating input (Pin 5) or by changing the timing resistor Rr external to the IC chip. The voltage at Pin 6 is held at the same voltage as Pin 5. Thus, if the modulating voltage at Pin5 is measured, the voltage at Pin6 also increases, resulting in less voltage across R and there by decreasing the changing current. The voltage across the capacitor CT is applied at the inverting input terminal of Schmitt trigger A2 via buffer amplifier. The output voltage swing of the Schmitt trigger is designed to Vcc and 0.5Vcc. If Ra = Rb in the positive feedback loop, the voltage at the non inverting terminal of A2 swings from 0.5Vcc to 0.25 Vcc. When the voltage on the capacitor CT exceeds 0.5Vcc during charging the output of the Schmitt trigger goes low (0-5) Vcc. The capacitor now discharges and when it is at 0.25Vcc the output of Schmitt trigger goes high (Vcc). Since the source and sink currents are equal, capacitor charges and discharges for, the same amount of the time. Thus v = 0.25Vcc V = i t CT

0.25Vcc t

= i CT

t = 0.25VccCT i The frequency of oscillator f0 is f0 = 1/t = 1/2t = i 0.5Vcc CT i = Vcc - Vc Rt

PIN DIAGRAM:

Ground 1 NC NE/SE566 VCO

+Vc c CT RT

Square wave output Triangular wave output

Modulated input

CIRCUIT DIAGRAM: +Vcc

R1 Rf 6 Modulating input 5 Vc R2 7 CT 1 566 3 8 4

OUTPUT WAVEFORMS: 0.5 Vcc O/P at Pin4

0.25 Vcc Vcc Schmitt trigger O/P

0.5Vcc Vcc

O/P at Pin3

0.5Vcc

b) PHASE LOCKED LOOP THEORY: MONOLITHIC PHASE LOCKED LOOP: All the different building blocks of the PLL are available as independent IC packages and can be externally interconnected to make a PLL. Moreover a number of manufacturer have introduced monolithic PLLs too. Some of the important monolithic PLLs are SE/NE 560 series introduced by signetics and LM560 series by rational semiconductor. The SE/NE 560,561, 562,564,565 and 567 mainly differ in operating frequency range, power supply requirement, frequency and bandwidth adjustment ranges. Since 565 is the most commonly used PLL. 565 iss available as 14-Pin DIP Packages and as 10 Pin Metal can package. The output frequency of the VCO (both inputs 2,3 grounded) f0 = 0.25/RtCt hz where Rt and Ct are the external resistor and capacitor connected to Pin8 and Pin 9. A value between 2K and 20K is recommended for Rt. The VCO free running frequency is adjusted with R t and Ct to be at the centre of the input frequency range. It may be seen that phase locked loop is internally broken between the VCO output and the phase comparator input. A short circuit between pins 4 and 5 connects the VCO output to the phase comparator, so as to compare f0 with input signal fs. A capacitor C is connected between Pin 7 and Pin 10 to make a low pass filter with internal resistance of 3.6K.

PIN DIAGRAM: -Vcc 1 14 13 12 NE/SE565 11 NC +Vcc NC NC NC

input 2 input 3

VCO output 4 VCO input 5 Reference o/p 6 Demodulate d o/p 7

10

External capacitor for VCO

External resistor for VCO

CIRCUIT DIAGRAM:

+Vcc

10 i/p 2 i/p 3 i/p 5 Vco o/p 4 VCO 8 R

T

Phase detector

3.6 k Amplifier

Demodulated o/p Ref o/p

C
T

Vcc

-Vcc

RESULT: Thus the voltage controlled oscillator and the phase locked loop are studied.