EE 280: Design of Logic Circuits

Section 002 Course Syllabus, Spring 2013

Instructor: Email: Office: Office Hours: Course URL: Required Textbook: Dr. Jeffrey Ashley ashley@engr.uky.edu FPAT 565 M W 11 am 1 pm, R 3-4 pm, F 11 am -12 pm and by appointment. I also typically maintain an open-door policy. https://elearning.uky.edu/ Fundamentals of Digial Logic with Verilog Design Second Edition, Stephen Brown and Zvonko Vranesic, McGraw-Hill, 2008, ISBN 978-0-07-338033-4 MWF 1:00 - 1:50 pm in FPAT 259

Lecture:

Teaching Assistant: TA email: Office: Office Hours:

Hojjat Sarvari
TBA

TBA TBA

Overview
EE 280 students will learn the fundamentals of combinational and sequential logic circuit design. These principles apply to all digital systems. In addition to creating paper designs, students will create and simulate designs using the Verilog hardware description language.

Outcomes
Upon successful completion of EE 280 students will be able to: 1. Perform arithmetic in various number systems. 2. Apply Boolean algebra to design and minimize logic circuits. 3. Design combinational logic circuits and use computer simulation to verify correct design and operation of the circuits. 4. Design sequential logic circuits and use computer simulation to verify correct design and operation of the circuits. 5. Apply timing analysis and other techniques in the design of reliable logic circuits.

Course Work
Grading
Raw final grades will be based on a weighted average of the percent points earned in each category shown below. The weighting will be as follows: Homework Quizzes Exam 1 Exam 2 Exam 3 05% 10% 20% 20% 20% A 90-100 pts. B 80-90 pts. C 70-80 pts. D 60-70 pts. E <60 pts.

Final Exam 25%

Homework
Homework will be assigned to reinforce topics read in the book and discussed in class and assess course outcomes 1 through 5 above. Homework assignments will be collected and graded weekly. Partial credit will be based on work shown. Correct answers to problems that require substantial work may not get full credit if not enough work is present to demonstrate how the student solved the problem. Homework assignments may be written in pen or pencil, but should be neat enough to be legible. Illegible answers will be considered incorrect. Some homework problems may be collected and graded through a web form. Homework is due at the start of class. NO LATE HOMEWORK ASSIGNMENTS WILL BE ACCEPTED. If you might have a problem getting to class on time in the morning (due to traffic, oversleeping, etc) or have a valid reason to miss class you can turn in the homework early.

Quizzes
Quizzes will be given approximately once every two weeks to reinforce material covered in the homework. The lowest quiz score will be dropped at the end of the semester. Quizzes will assess all five course outcomes. A quiz missed due to an unexcused absence will receive a zero and cannot be made up.

Exams
Three exams and a comprehensive final exam will be given to assess student's progress in the class. You will take the first exam upon completion of Chapter 4. You will take the second exam after the completion of Chapter 6 and test 3 upon completing Chapter. I will give you at least one week advanced notice on the exact date of these tests. The final exam will be scheduled per University Guidelines and will be taken during finals week. The final will be comprehensive. The exams will assess all five course outcomes, but the simulation portion of outcomes 3 and 4 will not be emphasized. For those students who have verified conflicts, makeup exams will be arranged on an individual basis. In order to obtain approval for a conflict known ahead of time you must inform the instructor at least one week before the scheduled exam date. Verified conflicts are defined in the Students Rights and Responsibilities. Makeup exams may contain different questions and may be in a different format from the missed exam.

Re-grades
Re-grades incur a considerable amount of administrative overhead. In addition, they are unfair to the majority of students who accept the grade they receive. All assignments will be graded fairly, uniformly, and with great care. The students are expected to respect the judgment of the teaching assistants in evaluating graded assignments. However, students should not be unfairly penalized by "human error," such as errors in totaling up scores on an exam questions. Therefore, the re-grade policy for this class is as follows. To submit graded material for re-grade, describe the mistake on a separate sheet of paper and attach the sheet to the exam, quiz, or homework. The re-grade request must be submitted to the instructor (not the TA) by noon the day after the exam or homework is returned. Furthermore, the request for re-grade will make the entire assignment open for re-grade, that is, ALL of the grading on a particular exam or homework in question can be checked for fairness and accuracy.

Attendance
Students are responsible for all material covered in class regardless of whether or not it is covered in the book or supplemental reading material. Attendance is strongly recommended as lectures are designed to cover material important to the class.

Cheating
Cheating and Academic dishonesty of any kind will not be tolerated. The minimum penalty for cheating required by University policy is failing grade assigned for the course. We will follow this policy in this course. Cheating includes, but is not limited to: copying all or part of a homework assignment or project from another student copying verbatim from a book, the Internet, or any other source without reference communicating during an exam or quiz copying from another student's exam paper attempting to compromise security of any computer system used by course staff When answering a homework question that asks for a definition you should read and understand the definition and write an answer in your own words that means the same thing rather than simply copying from a book. Students may discuss general principles and approaches to homework problems or compare answers once a homework assignment is finished, however everything submitted for grading should be the student's own work. If you want to help another student learn to solve a problem, choose a similar problem as an example and let the other student solve the homework problem on their own. The similar problem could be one from the book or one you make up. This method will not only reduce the chance of the second student turning in an identical answer to yours, thus subjecting to suspicion of cheating, it will also help the student learn better.

Please contact me if there is ever a question about whether a certain action will be considered cheating before the fact. No harm is done if you ask first and avoid cheating, but once an assignment is submitted for grading, you run the risk of failing. It is much better to ask and be safe that to be penalized for cheating due to a misunderstanding.

Computer Accounts
Internet access is required to access the course web page, which contains class announcements, homework assignments, and other information that will be updated throughout the semester. Internet access can be through *nix, Mac or Windows machines as long as they are on the net and have web browsing software. In addition, some assignments will require using the Verilog simulation software, Xilinx ISE version 9. The specific software to use will is installed on machines in CE 228 (and the RGAN lab). We will discuss this software in class. The machines in CE 228, as well as many others around campus, can be accessed with a MyUK account, available through the computing center at McVey 111. You should have a MyUK account automatically set up when you enrolled. Additionally, we will be using Blackboard to disseminate information related to the course including grades.

Course Outline
Below is a list of topics that will be covered in class.
EE280 Spring 2006 Topics Introduction Logic functions and Boolean algebra Synthesis with NAND and NOR gates Expressing logic circuits in Verilog Implementation technology Karnaugh Maps Multi-level circuits Tabular minimization EXAM I Unsigned numbers and arithmetic Signed numbers Signed arithmetic Arithmetic circuits in Verilog Other number representations Multiplexers and decoders 5.1, 5.2 5.3 5.4 5.5, 5.6 5.7, 5.8 6.1, 6.2 2.1- 2.5 2.7, 2.8 2.9- 2.11 3.1- 3.7 4.1- 4.5 4.6, 4.7 4.8, 4.9 Synthesis of combinational circuits with AND, OR, NOT gates 2.6 Reading

Encoders, converters, and comparators Building blocks in Verilog EXAM II Introduction to sequential circuits; latches D, JK, and T Flip-flops Registers, shift registers, and counters Reset synchronization and more counter Sequential behavior in Verilog Design Examples Synchronous design with finite state machines (FSMs) State encoding FSM examples FSMs in Verilog State minimization and unused states Analysis of sequential circuits FSM design examples EXAM III Final Examination - PER UKY FINAL EXAM SCHEDULE

6.3 6.5 6.6 7.1- 7.3 7.4- 7.7 7.8, 7.9 7.10, 7.11 7.12- 7.14 7.15 8.1, 8.3 8.2 8.4, 8.5 8.6 8.9 8.7, 8.8

Note: This table is just a suggested outline; there may be assignments and/or topics added, removed, or rescheduled throughout the semester. You are responsible for all changes announced in lecture.