Sie sind auf Seite 1von 21

CPS 104 Computer Organization and Programming Lecture- 17: Circuits, Memory Elements

Feb 18, 2004

Gershon Kedem

http://kedem.duke.edu/cps104/Lectures

CPS104 Lec17.1

©GK Spring 2004

Admin.

Æ Homework-3 Due Feb. 23rd 11:59 pm.

Æ C++ version is posted.

Æ Start NOW!

CPS104 Lec17.2

©GK Spring 2004

Review:Circuit Example: 2x1 MUX

a

b

1 0 s
1
0
s

y

a Y b
a
Y
b

S

CPS104 Lec17.3

Y = (A * S) + (B * ~S)

©GK Spring 2004

Review: Example 4x1 MUX

A 1 B 0 1 0 C 1 D 0 S 0 S 1
A
1
B
0
1
0
C
1
D
0
S 0
S 1

CPS104 Lec17.4

a

b

c

d

3 2 1 0 2
3
2
1
0
2

S

y

©GK Spring 2004

Review: Circuit Example: Selector

Q 3 Q 2 Q 1 Q 0 I 1 I 0 CPS104 Lec17.5
Q
3
Q
2
Q
1
Q
0
I 1
I 0
CPS104 Lec17.5

I 1

I 0

Q 0 Q 1 Q 2 Q 3

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

0

1

0

1

1

0

0

0

1

©GK Spring 2004

Review: Full Adder

Cin

01101100

Review: Full Adder Cin 01101100 01101101 +00101100 Sum 10011001 a b Sum C in C out
Review: Full Adder Cin 01101100 01101101 +00101100 Sum 10011001 a b Sum C in C out
Review: Full Adder Cin 01101100 01101101 +00101100 Sum 10011001 a b Sum C in C out

01101101

+00101100 Sum 10011001 a b Sum C in C out 0 0 0 0 0
+00101100
Sum
10011001
a
b
Sum
C in
C out
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1

a

1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0

b

Cout
Cout

CPS104 Lec17.6

©GK Spring 2004

Example: 4-bit adder

S3 S2 S1 S0 C out Full Adder Full Adder Full Adder Full Adder b3
S3
S2
S1
S0
C
out
Full Adder
Full Adder
Full Adder
Full Adder
b3
a3
b2
a2
b1
a1
b0
a0

CPS104 Lec17.7

©GK Spring 2004

Example: Adder/Subtractor

S3 S2 S1 S0 C Full Adder Full Adder Full Adder Full Adder out Add/Sub
S3
S2
S1
S0
C
Full Adder
Full Adder
Full Adder
Full Adder
out
Add/Sub
b3
a3
b2
a2
b1
a1
b0
a0

CPS104 Lec17.8

©GK Spring 2004

Overflow

Example1:

0100000

Overflow Example1: 0100000 0110101 2 (= 53 1 0 ) +0101010 2 (= 42 1 0
Overflow Example1: 0100000 0110101 2 (= 53 1 0 ) +0101010 2 (= 42 1 0
Overflow Example1: 0100000 0110101 2 (= 53 1 0 ) +0101010 2 (= 42 1 0
Overflow Example1: 0100000 0110101 2 (= 53 1 0 ) +0101010 2 (= 42 1 0
Overflow Example1: 0100000 0110101 2 (= 53 1 0 ) +0101010 2 (= 42 1 0
Overflow Example1: 0100000 0110101 2 (= 53 1 0 ) +0101010 2 (= 42 1 0
Overflow Example1: 0100000 0110101 2 (= 53 1 0 ) +0101010 2 (= 42 1 0

0110101 2 (= 53 10 ) +0101010 2 (= 42 10 ) 1011111 2 (=-33 10 )

Example2:

1000000

1 0 ) 1011111 2 (= -33 1 0 ) Example2: 1000000 1010101 2 (=-43 1
1 0 ) 1011111 2 (= -33 1 0 ) Example2: 1000000 1010101 2 (=-43 1
1 0 ) 1011111 2 (= -33 1 0 ) Example2: 1000000 1010101 2 (=-43 1
1 0 ) 1011111 2 (= -33 1 0 ) Example2: 1000000 1010101 2 (=-43 1
1 0 ) 1011111 2 (= -33 1 0 ) Example2: 1000000 1010101 2 (=-43 1
1 0 ) 1011111 2 (= -33 1 0 ) Example2: 1000000 1010101 2 (=-43 1
1 0 ) 1011111 2 (= -33 1 0 ) Example2: 1000000 1010101 2 (=-43 1

1010101 2 (=-43 10 ) +1001010 2 (=-54 10 ) 0011111 2 (= 31 10 )

Example3:

1100000

1 0 ) 0011111 2 (= 31 1 0 ) Example3: 1100000 0110101 2 (= 53
1 0 ) 0011111 2 (= 31 1 0 ) Example3: 1100000 0110101 2 (= 53
1 0 ) 0011111 2 (= 31 1 0 ) Example3: 1100000 0110101 2 (= 53
1 0 ) 0011111 2 (= 31 1 0 ) Example3: 1100000 0110101 2 (= 53
1 0 ) 0011111 2 (= 31 1 0 ) Example3: 1100000 0110101 2 (= 53
1 0 ) 0011111 2 (= 31 1 0 ) Example3: 1100000 0110101 2 (= 53
1 0 ) 0011111 2 (= 31 1 0 ) Example3: 1100000 0110101 2 (= 53

0110101 2 (= 53 10 ) +1101010 2 (=-22 10 ) 0011111 2 (= 31 10 )

CPS104 Lec17.9

Example4:

0000000

2 (= 31 1 0 ) CPS104 Lec17. 9 Example4: 0000000 0010101 2 (= 21 1
2 (= 31 1 0 ) CPS104 Lec17. 9 Example4: 0000000 0010101 2 (= 21 1
2 (= 31 1 0 ) CPS104 Lec17. 9 Example4: 0000000 0010101 2 (= 21 1
2 (= 31 1 0 ) CPS104 Lec17. 9 Example4: 0000000 0010101 2 (= 21 1
2 (= 31 1 0 ) CPS104 Lec17. 9 Example4: 0000000 0010101 2 (= 21 1
2 (= 31 1 0 ) CPS104 Lec17. 9 Example4: 0000000 0010101 2 (= 21 1
2 (= 31 1 0 ) CPS104 Lec17. 9 Example4: 0000000 0010101 2 (= 21 1

0010101 2 (= 21 10 ) +0101010 2 (= 42 10 ) 0111111 2 (= 63 10 )

©GK Spring 2004

Add/Subtract With Overflow detection

Overflow

S S S 1 0 S n- 1 n- 2 Full Adder Full Adder Full
S
S
S
1
0
S n- 1
n- 2
Full Adder
Full Adder
Full Adder
Full Adder
Add/Sub
b 1
a 1
b 0
a 0
b n- 1
a n- 1
b n- 2
a n- 2

CPS104 Lec17.10

©GK Spring 2004

a

b

ALU Slice

C in 3 2 1 0 Add/sub 2 C out
C
in
3
2
1
0
Add/sub
2
C
out

Add/sub

F

CPS104 Lec17.11

 

A

F

Q

0

0

a + b

1

0

a - b

Q

-

1

NOT b

-

2

a OR b

-

3

a AND b

©GK Spring 2004

The ALU

Overflow = Zero Q Q Q Q n-1 n-2 1 0 ALU control ALU Slice
Overflow
= Zero
Q
Q
Q
Q
n-1
n-2
1
0
ALU control
ALU Slice
ALU Slice
ALU Slice
ALU Slice
b n-1
a n-1
b n-2
a n-2
b 1
a 1
b 0
a 0

CPS104 Lec17.12

©GK Spring 2004

Shifter

a7 a6 a5 a4 a3 a2 a1 a0 Shift-1 1 Shift-2 0 Shift-4 1 Q7
a7
a6
a5
a4
a3
a2
a1
a0
Shift-1
1
Shift-2
0
Shift-4
1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0

CPS104 Lec17.13

©GK Spring 2004

Memory Elements

Æ All the circuit we looked at so far are combinational circuits: the output is a Boolean function of the inputs.

Æ We need circuits that can remember values. (registers)

Æ The output of the circuit is a function of the input AND a function of a stored values (state) .

Æ Circuits with memory are called sequential circuits.

CPS104 Lec17.14

©GK Spring 2004

Rest-Set Latch

S Q Q R
S
Q
Q
R

R

S

Q

0

0

Q

0

1

1

1

0

0

1

1

-

CPS104 Lec17.15

©GK Spring 2004

Rest-Set Latch (cont.)

S 0 1 Q 0 1 Q 0 R 0
S
0
1
Q
0
1
Q
0
R
0
S 0 0 Q 1 0 Q 1 R 0
S
0
0
Q
1
0
Q
1
R
0

CPS104 Lec17.16

©GK Spring 2004

Rest-Set Latch (cont.)

S 1 0 Q 1 0 Q 1 R 0
S
1
0
Q
1
0
Q
1
R
0

CPS104 Lec17.17

S 0 1 Q 0 1 Q 0 R 1
S
0
1
Q
0
1
Q
0
R
1

©GK Spring 2004

Positive Edge Data-Latch

Data Q Enable Q
Data
Q
Enable
Q

D

E

Q

0

1

0

1

1

1

-

0

Q

D E Q Time
D
E
Q
Time

CPS104 Lec17.18

©GK Spring 2004

Negative Edge D-Latch

Data
Data

D

E

Q

0

1

0

1

1

1

-

0

Q

Q Q
Q
Q

Enable

D E Q Time
D
E
Q
Time

CPS104 Lec17.19

©GK Spring 2004

Data Master-Slave Data-Flip-Flop Master Slave Q Q Clock
Data
Master-Slave Data-Flip-Flop
Master
Slave
Q
Q
Clock

t

On C

D is transferred to the master stage and the slave is stable.t On C

t

On C

the Master stage is transferred into the slave stage (output),t On C

and the master stage is stable.

CPS104 Lec17.20

©GK Spring 2004

DFF Timing

Data M Clock
Data
M
Clock
Q Q
Q
Q
Clock 1 0 0 1 0 1 1 0 D M 1 0 0 1
Clock
1
0 0
1
0
1
1
0
D
M
1 0
0
1
0
1
1
0
Q
Time
CPS104 Lec17.21
©GK Spring 2004