CPS 104 Computer Organization and Programming Lecture- 23: Control, Memory

March 15, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

CPS104 Lec23.1

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Admin.

Homework-5: Posted, Due, Homework-6: Will be posted today.

CPS104 Lec23.2

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A Summary of the Control Signals

See Appendix A func 10 0000 10 0010 We Dont Care :-) op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add sub ori lw sw beq jump RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x MemtoReg 0 0 0 1 x x x RegWrite 1 1 1 1 0 0 0 MemWrite 0 0 0 0 1 0 0 Branch 0 0 0 0 0 1 x Jump 0 0 0 0 0 0 1 ExtOp x x 0 1 1 x x ALUctr<2:0> Add Subtract Or Add Add Subtract xxx 31 R-type I-type J-type op op op 26 rs rs 21 rt rt target address 16 rd 11 shamt immediate 6 funct 0 add, sub ori, lw, sw, beq jump
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CPS104 Lec23.3

The Concept of Local Decoding

op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop<N:0> 00 0000 R-type 1 0 0 1 0 0 0 x R-type 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1 0 0 0 0 0 1 0 0 0 0 0 1 x 0 0 0 0 1 0 1 1 x x Or Add Add Subtract xxx

op 6

Main Control

func 6 ALUop N

ALU Control (Local)

ALUctr 3 ALU

CPS104 Lec23.4

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The Encoding of ALUop

op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3

In this exercise, ALUop has to be 2 bits wide to represent: u (1) R-type instructions u I-type instructions that require the ALU to perform:

(2) Or, (3) Add, and (4) Subtract

To implement the full MIPS ISA, ALUop hat to be 3 bits to represent: u (1) R-type instructions u I-type instructions that require the ALU to perform:

(2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) R-type R-type 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 jump Subtract xxx xxx 0 01
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beq

ALUop (Symbolic) ALUop<2:0>

CPS104 Lec23.5

The Decoding of the func Field

op 6 Main Control func 6 ALUop N ori Or 0 10 16 rt rd ALUctr ALU Control (Local) lw Add 0 00 11 shamt ALUctr<2:0> 000 001 010 110 111 ALUctr 3

ALUop (Symbolic) ALUop<2:0> 31 R-type funct<5:0> 10 0000 10 0010 10 0100 10 0101 10 1010 op 26

R-type R-type 1 00 21 rs

sw Add 0 00 6

jump Subtract xxx xxx 0 01 0 funct ALU Operation Add Subtract And Or Set-on-less-than
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beq

Instruction Operation add subtract and or set-on-less-than

ALU

CPS104 Lec23.6

The Truth Table for ALUctr

R-type ALUop (Symbolic) R-type ALUop<2:0> 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 beq Subtract 0 01

funct<3:0> 0000 0010 0100 0101 1010

Instruction Op. add subtract and or set-on-less-than

ALUop bit<2> bit<1> bit<0> 0 0 0 0 x 1 0 1 x 1 x x 1 x x 1 x x 1 x x 1 x x

func bit<3> bit<2> bit<1> bit<0> x x x x x x x x x x x x 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0

ALU Operation Add Subtract Or Add Subtract And Or Set on <

ALUctr bit<2> bit<1> bit<0> 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1

CPS104 Lec23.7

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The Logic Equation for ALUctr<2>

ALUop bit<2> bit<1> bit<0> 0 x 1 1 x x 1 x x func bit<3> bit<2> bit<1> bit<0> x x x x 0 0 1 0 1 0 1 0 ALUctr<2> 1 1 1

This makes func<3> a dont care

ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

CPS104 Lec23.8

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The Logic Equation for ALUctr<1>

ALUop bit<2> bit<1> bit<0> 0 0 0 0 x 1 1 x x 1 x x 1 x x func bit<3> bit<2> bit<1> bit<0> ALUctr<1> x x x x 1 x x x x 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1

ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & !func<2> & !func<0>

CPS104 Lec23.9

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The Logic Equation for ALUctr<0>

ALUop bit<2> bit<1> bit<0> 0 1 x 1 x x 1 x x func bit<3> bit<2> bit<1> bit<0> ALUctr<0> x x x x 1 0 1 0 1 1 1 0 1 0 1

ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

CPS104 Lec23.10

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The ALU Control Block

func 6 ALUop 3 ALU Control (Local) ALUctr 3

ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & !func<2> & !func<0>

ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

CPS104 Lec23.11

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The Truth Table for the Main Control

op 6 RegDst ALUSrc Main Control

:
ALUop 3 00 0000 R-type 1 0 0 1 0 0 0 x R-type 1 0 0

func 6

ALU Control (Local)

ALUctr 3

op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) ALUop <2> ALUop <1> ALUop <0>

CPS104 Lec23.12

00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1 0 0 0 0 0 1 0 0 0 0 0 1 x 0 0 0 0 1 0 1 1 x x Or Add Add Subtract xxx 0 0 0 x 0 1 0 0 x 0 0 0 0 x 1 GK Spring 2004

The Truth Table for RegWrite

op RegWrite

00 0000 R-type 1

00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 1 1 0 0 0

RegWrite = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0>(R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0>(ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0>(lw)

op<5>

..

op<5>

..

op<5>

..

op<5>

..

op<5>

..
<0>

op<5>

..
op<0>

<0>

<0>

<0>

<0>

R-type

ori

lw

sw

beq

jump RegWrite

CPS104 Lec23.13

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PLA Implementation of the Main Control

op<5>

..

op<5>

..

op<5>

..

op<5>

..

op<5>

..
<0>

op<5>

..
op<0>

<0>

<0>

<0>

<0>

R-type

ori

lw

sw

beq

jump

RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0> GK Spring 2004

CPS104 Lec23.14

Putting it All Together: A Single Cycle Processor

ALUop op Main Control 6 Instr<31:26> Rd RegDst RegDst ALUSrc 3 func Instr<5:0> 6 ALU Control ALUctr 3

:
Rt Rs Rt 5 5

Branch Jump Clk Instruction Fetch Unit

Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

1 Mux 0 RegWr 5 ALUctr busA 32 0 Mux ALU

Rt Zero

Rs

Rd

Imm16 MemtoReg 0 Mux

busW 32 Clk

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr

32 32 WrEn Adr

1 32

imm16 Instr<15:0> 16

Data In 32 Clk

Data Memory

ALUSrc
CPS104 Lec23.15

ExtOp

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Worst Case Timing: lw $1, $2(offset)

Clk PC Old Value Rs, Rt, Rd, Op, Func Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Old Value Old Value Delay through Extender & Mux Old Value Old Value Data Memory Access Time Old Value New
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ALUctr ExtOp ALUSrc MemtoReg RegWr busA busB Addres s busW CPS104 Lec23.16

Instruction Memoey Access Time New Value Delay through Control Logic New Value New Value New Value New Value

New Value Register File Access Time New Value New Value ALU Delay

Register Write Occurs

New Value

Drawback of this Single Cycle Processor

Long cycle time: u Cycle time must be long enough for the load instruction:
PCs Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew

Cycle time is much longer than needed for all other instructions

CPS104 Lec23.17

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Memory
Outline Big Picture of Memory Memory Technology u SRAM u DRAM Reading Chapter 7

CPS104 Lec23.18

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Big Picture

The Five Classic Components of a Computer

Processor Input Control Memory Datapath

Output

Todays Topic: Memory System

CPS104 Lec23.19

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Where Are We?

Application Operating System Compiler CPU Firmware

Software Interface Between HW and SW

Instruction Set Architecture, Memory, I/O

Memory I/O system Digital Design

Circuit Design

Hardware

You are here.

CPS104 Lec23.20

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Review: Computer Memory

Memory is a large linear array of bytes. u Each byte has a unique address (location). u Byte of data at address 0x100, and 0x101 Most computers support byte (8-bit) addressing. Data may have to be aligned on word (4 byte) or double word (8 byte) boundary. u int is 4 bytes u double precision floating point is 8 bytes 32-bit v.s. 64-bit addresses u we will assume 32-bit for rest of course, unless otherwise stated

Byte Word Address Address Data 0 0 00110110 1 00001100 2 3 1 4

2n-1

2n-1-4 2n-1

CPS104 Lec23.21

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Clk

Our Nave View of Memory

PC Instruction Address

Ideal
Instruction Memory

Instruction Rd Rs 5 5 Rt 5 Imm 16 A Data Address Data In Clk

32 Clk

Rw Ra Rb 32 32-bit Registers

32 32 B ALU 32

Ideal
Data Memory

DataOut

CPS104 Lec23.22

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Question

What issues do we need to worry about in implementing the memory system?

CPS104 Lec23.23

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System Organization
Processor interrupts

Cache

Memory Bus

I/O Bridge

Core Chip Set

I/O Bus Memory Memory
Disk Controller Graphics Controller Network Interface

The memory hierarchy

CPS104 Lec23.24

Disk Disk

Graphics

Network

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Processor and Caches

Processor Module Processor Registers Internal Cache Datapath

Control

External Cache

To main memory
CPS104 Lec23.25
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Memory
SIMM Slot 0 SIMM Slot 1 SIMM Slot 2 SIMM Slot 3 SIMM Slot 4 SIMM Slot 5 SIMM Slot 6

Memory Controller

SIMM Slot 7

Memory Bus

DRAM SIMM
DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

Why is it called DRAM?

CPS104 Lec23.26

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Memory Technology

Random Access: u Random is good: access time is the same for all locations u DRAM: Dynamic Random Access Memory

u

High density, low power, cheap, slow Dynamic: need to be refreshed regularly Main memory Low density, high power, expensive, fast Static: content will last forever(until lose power) Caches

SRAM: Static Random Access Memory

Not-so-random Access Technology: u Access time varies from location to location and from time to time u Examples: Disk, CDROM Sequential Access Technology: access time linear in location (e.g.,Tape)
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CPS104 Lec23.27

Random Access Memory (RAM) Technology

Why do computer professionals need to know about RAM technology? u Processor performance is usually limited by memory latency and bandwidth. u Latency: The time it takes to access a word in memory. u Bandwidth: The average speed of access to memory (Words/Sec). u As IC densities increase, lots of memory will fit on processor chip

Tailor on-chip memory to specific needs.

- Instruction cache - Data cache - Write buffer What makes RAM different from a bunch of flip-flops? u Density: RAM is much more dense u Speed: RAM access is slower than flip-flop (register) access.
CPS104 Lec23.28
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Technology Trends
Logic: DRAM: Disk: Capacity 2x in 3 years 4x in 3 years 4x in 3 years Speed 2x in 3 years 1.4x in 10 years 1.4x in 10 years

Year 1980 1983 1986 1989 1992 1995

CPS104 Lec23.29

DRAM Size 1000:1! 64 Kb 2:1! 256 Kb 1 Mb 4 Mb 16 Mb 64 Mb

Cycle Time 250 ns 220 ns 190 ns 165 ns 145 ns 120 ns

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Static RAM Cell

6-Transistor SRAM Cell
0 1

word word (row select)

bit

bit

Write: 1. Drive bit lines (bit=1, bit=0) bit bit 2. Select row Read: 1. Precharge bit and bit to Vdd (set to 1) 2. Select row 3. Cell pulls one line low (pulls to 0) 4. Sense amp on column detects difference between bit and bit
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CPS104 Lec23.30

Typical SRAM Organization: 16-word x 4-bit

Din 3 Din 2 Din 1 Din 0
Precharge

WrEn

Wr Driver & - Precharger+ SRAM Cell SRAM Cell

Wr Driver & - Precharger+ SRAM Cell SRAM Cell

Wr Driver & - Precharger+ SRAM Cell SRAM Cell

Wr Driver & - Precharger+

Word 0

A0 A1 A2 A3

Address Decoder

SRAM Cell
Word 1

SRAM Cell

:
SRAM Cell - Sense Amp +

:
SRAM Cell - Sense Amp +

:
SRAM Cell - Sense Amp +

:
Word 15

SRAM Cell - Sense Amp +

Dout 3
CPS104 Lec23.31

Dout 2

Dout 1

Dout 0
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Logic Diagram of a Typical SRAM

A
N

WE_L OE_L

2 N words x M bit SRAM

M

Write Enable is usually active low (WE_L) Din and Dout are combined to save pins: u A new control signal, output enable (OE_L) is needed u WE_L is asserted (Low), OE_L is disasserted (High)

D serves as the data input pin D is the data output pin Result is unknown. Dont do that!!!

WE_L is disasserted (High), OE_L is asserted (Low)

Both WE_L and OE_L are asserted:

CPS104 Lec23.32

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Typical SRAM Timing

A
N

WE_L OE_L

2 N words x M bit SRAM

M

Write Timing:
D A OE_L WE_L Write Hold Time Write Setup Time
CPS104 Lec23.33

Read Timing:
High Z Junk Junk Data Out Read Address Junk Data Out

Data In Write Address

Read Address

Read Access Time

Read Access Time

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