CPS 104 Computer Organization and Programming Lecture- 32: I/O Systems.

April 5, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

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Admin.

Homework -7: is posted, Deadline extended, Due: next Friday, April 9th.

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Input / Output

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Review: I/O System Design Issues

u u u

Performance Expandability Resilience in the face of failure

interrupts

Processor

Cache

Memory - I/O Bus Main Memory I/O Controller Disk Disk I/O Controller Graphics I/O Controller Network Spring 2004 GK

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Review: I/O Device Examples

Device Behavior Keyboard Input Mouse Input Line Printer Output Laser Printer Output Graphics Display Output Network-LAN Input/Output Floppy disk Storage Optical Disk Storage Magnetic Disk Storage Partner Human Human Human Human Human Machine Machine Machine Machine Data Rate (KB/sec) 0.01 0.02 1.00 100 > 30,000 10,000 50 500 5,000

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Review: Technology Trends

Disk Capacity doubles every 1.5 years

Today: Processing Power Doubles Every 18 months Today: Memory Size Doubles Every 18 months(?) Today: Disk Capacity Doubles Every 12-18 months The I/O The I/O GAP GAP

Disk Positioning Rate (Seek + Rotate) Doubles Every Ten Years!

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Types of Storage Devices

Magnetic Disks Magnetic Tapes CD ROM Juke Box (automated tape library, robots)

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Magnetic Disks

Long term nonvolatile storage Another slower, less expensive level of memory hierarchy
Track Arm Cylinder Head Platter Sector

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Organization of a Hard Magnetic Disk

Platters Track

Typical numbers (depending on the disk size): u 500 to 2,000 tracks per surface u 32 to 128 sectors per track

Sector

A sector is the smallest unit that can be read or written

Traditionally all tracks have the same number of sectors: u Constant bit density: record more sectors on the outer tracks u Recently relaxed: constant bit size, speed varies with track location
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Magnetic Disk Characteristic

Track Sector

Cylinder: all the tacks under the head Cylinder at a given point on all surface Platter Read/write data is a three-stage process: Head u Seek time: position the arm over the proper track u Rotational latency: wait for the desired sector to rotate under the read/write head u Transfer time: transfer a block of bits (sector) under the read-write head Average seek time as reported by the industry: u Typically in the range of 8 ms to 12 ms u (Sum of the time for all possible seek) / (total # of possible seeks) Due to locality of disk reference, actual average seek time may: u Only be 25% to 33% of the advertised number

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Typical Numbers of a Magnetic Disk

Track Sector

Rotational Latency: u Most disks rotate at 3,600 to 10000 RPM u Approximately 16 ms to 3.5 ms per revolution, respectively Head u An average latency to the desired information is halfway around the disk: 8 ms at 3600 RPM, 4 ms at 7200 RPM Transfer Time is a function of : u Transfer size (usually a sector): 1 KB / sector u Rotation speed: 3600 RPM to 7200 RPM u Recording density: bits per inch on a track u Diameter typical diameter ranges from 2.5 to 5.25 in u Typical values: 2 to 12 MB per second

Cylinder Platter

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Disk Access

Access time =

queue + seek + rotational + transfer + overhead

Seek time u move arm over track u average is confusing (startup, slowdown, locality of accesses) Rotational latency u wait for sector to rotate under head u average = 0.5/(3600 RPM) = 8.3ms Transfer Time u f(size, BW bytes/sec)

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Disk Access Time Example

Disk Parameters: u Transfer size is 8K bytes u Advertised average seek is 12 ms u Disk spins at 7200 RPM u Transfer rate is 4 MB/sec Controller overhead is 2 ms Assume that disk is idle so no queuing delay What is Average Disk Access Time for a Sector? u Ave seek + ave rot delay + transfer time + controller overhead u 12 ms + 0.5/(7200 RPM/60) + 8 KB/4 MB/s + 2 ms u 12 + 4.15 + 2 + 2 = 20 ms Advertised seek time assumes no locality: typically 1/4 to 1/3 advertised seek time: 20 ms => 12 ms
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DRAM as Disk

Solid state disk, Expanded Storage, NVRAM Disk is slow, DRAM is fast => replace Disk with battery backed DRAM BUT, Disk is cheap, much cheaper than DRAM Network Memory u fast networks (e.g., Myrinet) u use DRAM of other workstations as backing store u Trapeze/GMS project here

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R-DAT Technology
2000 RPM

Helical Recording Scheme Four Head Recording Tracks Recorded 20 w/o guard band Read After Write Verify
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Tape vs. Disk

Longitudinal tape uses same technology as
hard disk; tracks its density improvements Inherent cost-performance based on geometry: fixed rotating platters with gaps (random access, limited area, fixed media) Vs. removable long strips wound on spool (sequential access, "unlimited" length) New technology trend: Helical Scan (VCR, Camcoder, DAT) Spins head at angle to tape to improve density

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Storage costs
Media Disk Tape CDR Flash EPROM Paper Capacity
80-300GB 2-300GB

750MB
256-1000MB

10KB

Cost $50-$300 $4-$100 $0.10 $40-$200 $0.01

$/byte 1 x 10-9 3 x 10-11 1.2x 10-10 2 x 10-7 1 x 10-6

Digital storage cost has a profound effect on the way we store and access Information!

Digital storage (and the Web) opens-up new exciting possibilities for access to information culture & knowledge. Digital storage introduces whole new set of problems to long term information storage.

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CDR vs. Tape

CDR Type Capacity 5.25" 0.75 GB Helical Scan Tape 8mm 5-90 GB $8 $600

Media Cost $0.10 Drive Cost $100 Access

Write Once Read/Write 10 - 20 s

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Robot Time 10 - 20 s
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Media cost ratio CDR vs. helical tape ~ 4 : 1

Current Drawbacks to Tape

Tape wear out: Helical 100s of passes to 1000s for longitudinal Head wear out: 2000 hours for helical Both must be accounted for in economic / reliability model Long rewind, eject, load, spin-up times;

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Buses: Connecting I/O to Processor and Memory

Processor Input Control Memory Datapath

Output

A bus is a shared communication link It uses one set of wires to connect multiple subsystems

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Advantages of Buses

Processor

I/O Device

I/O Device

I/O Device

Memory

Versatility: u New devices can be added easily u Peripherals can be moved between computer systems that use the same bus standard Low Cost: u A single set of wires is shared in multiple ways
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Disadvantages of Buses

Processor

I/O Device

I/O Device

I/O Device

Memory

The bus creates a communication bottleneck u Bus bandwidth can limit the maximum I/O throughput The maximum bus speed is largely limited by: u The length of the bus u The number of devices on the bus u The need to support a range of devices with:
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The General Organization of a Bus

Control Lines Data Lines

Control lines: u Signal requests and acknowledgments u Indicate what type of information is on the data lines Data lines carry information between the source and the destination: u Data and Addresses u Complex commands

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Master versus Slave

Master send address Bus Master Data can go either way Bus Slave

A bus transaction includes two parts: u Sending the address u Receiving or sending the data Master is the one who starts the bus transaction by: u Sending the address Slave is the one who responds to the address by: u Sending data to the master if the master ask for data u Receiving data from the master if the master wants to send data
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Output Operation
Output is defined as the Processor sending data to the I/O device: Step 1: Request Memory

Control (Memory Read Request)

Processor I/O Device (Disk) Step 2: Read Memory Processor I/O Device (Disk)

Data (Memory Address)

Memory

Control Data Memory

Step 3: Send Data to I/O Device Processor I/O Device (Disk)

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Control (Device Write Request) Data (I/O Device Address and then Data) Memory

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Input Operation
Input is defined as the Processor receiving data from the I/O device:

Step 1: Request Memory Processor

Control (Memory Write Request) Data (Memory Address) Memory

I/O Device (Disk)

Step 2: Receive Data Processor I/O Device (Disk)

Control (I/O Read Request) Data (I/O Device Address and then Data) Memory

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Types of Buses

Processor-Memory Bus (design specific) u Short and high speed u Only need to match the memory system

Maximize memory-to-processor bandwidth

Connects directly to the processor External I/O Bus (industry standard) u Usually is lengthy and slower u Need to match a wide range of I/O devices u Connects to the processor-memory bus or backplane bus Backplane Bus (industry standard) u Backplane: an interconnection structure within the chassis u Allow processors, memory, and I/O devices to coexist u Cost advantage: one single bus for all components Bit-Serial Buses (New trend: SBI, Firewire .. ) u Use High speed unidirectional point-to-point communication u Use differential signaling u Use Distributed control
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A Computer System with One Bus: Backplane Bus

Backplane Bus Processor Memory

I/O Devices

A single bus (the backplane bus) is used for: u Processor to memory communication u Communication between I/O devices and memory Advantages: Simple and low cost Disadvantages: slow and the bus can become a major bottleneck Example: IBM PC

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A Two-Bus System
Processor Memory Bus Processor Bus Adaptor I/O Bus Bus Adaptor I/O Bus Bus Adaptor I/O Bus Memory

I/O buses tap into the processor-memory bus via bus adaptors: u Processor-memory bus: mainly for processor-memory traffic u I/O buses: provide expansion slots for I/O devices Example: Apple Macintosh-II u NuBus: Processor, memory, and a few selected I/O devices GK Spring 2004 CPS104 Lec32.29 u SCCI Bus: the rest of the I/O devices

A Three-Bus System
Processor Memory Bus Processor Bus Adaptor Bus Adaptor Backplane Bus Bus Adaptor I/O Bus I/O Bus Memory

A small number of backplane buses tap into the processormemory bus u Processor-memory bus is used for processor memory traffic u I/O buses are connected to the backplane bus Advantage: loading on the processor bus is greatly reduced
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Synchronous and Asynchronous Bus

Synchronous Bus: u Includes a clock in the control lines u A fixed protocol for communication that is relative to the clock u Advantage: involves very little logic and can run very fast u Disadvantages:

Every device on the bus must run at the same clock rate To avoid clock skew, bus must be short if it is fast.

Asynchronous Bus: u It is not clocked u It can accommodate a wide range of devices u It can be lengthened without worrying about clock skew u It requires a handshaking protocol
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A Handshaking Protocol
ReadReq Data Ack
4 1 2 2 3

Address
4

Data
6 5 6 7

DataRdy

Three control lines u ReadReq: indicate a read request for memory

Address is put on the data lines at the same line
u

DataRdy: indicate the data word is now ready on the data lines
Data is put on the data lines at the same time

Ack: acknowledge the ReadReq or the DataRdy of the other party

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Increasing the Bus Bandwidth

Separate versus multiplexed address and data lines: u Address and data can be transmitted in one bus cycle if separate address and data lines are available u Cost: (a) more bus lines, (b) increased complexity Data bus width: u By increasing the width of the data bus, transfers of multiple words require fewer bus cycles u Example: SPARCstation 20s memory bus is 128 bit wide u Cost: more bus lines Block transfers: u Allow the bus to transfer multiple words in back-to-back bus cycles u Only one address needs to be sent at the beginning u The bus is not released until the last word is transferred u Cost: (a) increased complexity (b) decreased response time for request
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Obtaining Access to the Bus

Control: Master initiates requests Bus Master Data can go either way Bus Slave

One of the most important issues in bus design: u How is the bus reserved by a devices that wishes to use it? Chaos is avoided by a master-slave arrangement: u Only the bus master can control access to the bus:
It initiates and controls all bus requests

A slave responds to read and write requests The simplest system: u Processor is the only bus master u All bus requests must be controlled by the processor u Major drawback: the processor is involved in every transaction
u
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Multiple Potential Bus Masters: the Need for Arbitration

Bus arbitration scheme:

u u u

A bus master wanting to use the bus asserts the bus request A bus master cannot use the bus until its request is granted A bus master must signal to the arbiter after finish using the bus Bus priority: the highest priority device should be serviced first Fairness: Even the lowest priority device should never be completely locked out from the bus Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. Distributed arbitration by collision detection: Ethernet uses this. Daisy chain arbitration: single device with all request lines. Centralized, parallel arbitration: see next-next slide
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Bus arbitration schemes usually try to balance two factors:

u u

Bus arbitration schemes can be divided into four broad classes:

u

u u u

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Centralized Bus Arbitration

Request-C Grant-C

Arbitration Circuit

Request-B Grant-B Request-A Grant-A

Release

Master A

Master B

Master C

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The Daisy Chain Bus Arbitration Scheme

Device 1 Highest Priority Grant Bus Arbiter Grant

Device 2

Device N Lowest Priority Grant Release Request

Advantage: simple Disadvantages: u Cannot assure fairness: A low-priority device may be locked out indefinitely u The use of the daisy chain grant signal also limits the bus speed
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