CPS 104 Computer Organization and Programming Lecture- 33: I/O Systems: Busses

April 7, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

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Admin.

Homework -7: is posted, Deadline extended, Due: next Friday, April 9th.

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Buses: Connecting I/O to Processor and Memory

Processor Input Control Memory Datapath

Output

A bus is a shared communication link It uses one set of wires to connect multiple subsystems

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Advantages of Buses

Processor

I/O Device

I/O Device

I/O Device

Memory

Versatility: u New devices can be added easily u Peripherals can be moved between computer systems that use the same bus standard Low Cost: u A single set of wires is shared in multiple ways
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Disadvantages of Buses

Processor

I/O Device

I/O Device

I/O Device

Memory

The bus creates a communication bottleneck u Bus bandwidth can limit the maximum I/O throughput The maximum bus speed is largely limited by: u The length of the bus u The number of devices on the bus u The need to support a range of devices with:
Widely varying latencies Widely varying data transfer rates Lec33.5

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The General Organization of a Bus

Control Lines Data Lines

Control lines: u Signal requests and acknowledgments u Indicate what type of information is on the data lines Data lines carry information between the source and the destination: u Data and Addresses u Complex commands

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Master versus Slave

Master send address Bus Master Data can go either way Bus Slave

A bus transaction includes two parts: u Sending the address u Receiving or sending the data Master is the one who starts the bus transaction by: u Sending the address Slave is the one who responds to the address by: u Sending data to the master if the master ask for data u Receiving data from the master if the master wants to send data
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Output Operation
Output is defined as the Processor sending data to the I/O device: Step 1: Request Memory

Control (Memory Read Request)

Processor I/O Device (Disk) Step 2: Read Memory Processor I/O Device (Disk)

Data (Memory Address)

Memory

Control Data Memory

Step 3: Send Data to I/O Device Processor I/O Device (Disk)

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Control (Device Write Request) Data (I/O Device Address and then Data) Memory

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Input Operation
Input is defined as the Processor receiving data from the I/O device:

Step 1: Request Memory Processor

Control (Memory Write Request) Data (Memory Address) Memory

I/O Device (Disk)

Step 2: Receive Data Processor I/O Device (Disk)

Control (I/O Read Request) Data (I/O Device Address and then Data) Memory

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Types of Buses

Processor-Memory Bus (design specific) u Short and high speed u Only need to match the memory system

Maximize memory-to-processor bandwidth

Connects directly to the processor External I/O Bus (industry standard) u Usually is lengthy and slower u Need to match a wide range of I/O devices u Connects to the processor-memory bus or backplane bus Backplane Bus (industry standard) u Backplane: an interconnection structure within the chassis u Allow processors, memory, and I/O devices to coexist u Cost advantage: one single bus for all components Bit-Serial Buses (New trend: SBI, Firewire .. ) u Use High speed unidirectional point-to-point communication u Use differential signaling u Use Distributed control
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A Computer System with One Bus: Backplane Bus

Backplane Bus Processor Memory

I/O Devices

A single bus (the backplane bus) is used for: u Processor to memory communication u Communication between I/O devices and memory Advantages: Simple and low cost Disadvantages: slow and the bus can become a major bottleneck Example: IBM PC

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A Two-Bus System
Processor Memory Bus Processor Bus Adaptor I/O Bus Bus Adaptor I/O Bus Bus Adaptor I/O Bus Memory

I/O buses tap into the processor-memory bus via bus adaptors: u Processor-memory bus: mainly for processor-memory traffic u I/O buses: provide expansion slots for I/O devices Example: Apple Macintosh-II u NuBus: Processor, memory, and a few selected I/O devices GK Spring 2004 CPS104 Lec33.12 u SCCI Bus: the rest of the I/O devices

A Three-Bus System
Processor Memory Bus Processor Bus Adaptor Bus Adaptor Backplane Bus Bus Adaptor I/O Bus I/O Bus Memory

A small number of backplane buses tap into the processormemory bus u Processor-memory bus is used for processor memory traffic u I/O buses are connected to the backplane bus Advantage: loading on the processor bus is greatly reduced
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Synchronous and Asynchronous Bus

Synchronous Bus: u Includes a clock in the control lines u A fixed protocol for communication that is relative to the clock u Advantage: involves very little logic and can run very fast u Disadvantages:

Every device on the bus must run at the same clock rate To avoid clock skew, bus must be short if it is fast.

Asynchronous Bus: u It is not clocked u It can accommodate a wide range of devices u It can be lengthened without worrying about clock skew u It requires a handshaking protocol
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A Handshaking Protocol
ReadReq Data Ack
4 1 2 2 3

Address
4

Data
6 5 6 7

DataRdy

Three control lines u ReadReq: indicate a read request for memory

Address is put on the data lines at the same line
u

DataRdy: indicate the data word is now ready on the data lines
Data is put on the data lines at the same time

Ack: acknowledge the ReadReq or the DataRdy of the other party

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Increasing the Bus Bandwidth

Separate versus multiplexed address and data lines: u Address and data can be transmitted in one bus cycle if separate address and data lines are available u Cost: (a) more bus lines, (b) increased complexity Data bus width: u By increasing the width of the data bus, transfers of multiple words require fewer bus cycles u Example: SPARCstation 20s memory bus is 128 bit wide u Cost: more bus lines Block transfers: u Allow the bus to transfer multiple words in back-to-back bus cycles u Only one address needs to be sent at the beginning u The bus is not released until the last word is transferred u Cost: (a) increased complexity (b) decreased response time for request
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Obtaining Access to the Bus

Control: Master initiates requests Bus Master Data can go either way Bus Slave

One of the most important issues in bus design: u How is the bus reserved by a devices that wishes to use it? Chaos is avoided by a master-slave arrangement: u Only the bus master can control access to the bus:
It initiates and controls all bus requests

A slave responds to read and write requests The simplest system: u Processor is the only bus master u All bus requests must be controlled by the processor u Major drawback: the processor is involved in every transaction
u
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Multiple Potential Bus Masters: the Need for Arbitration

Bus arbitration scheme:

u u u

A bus master wanting to use the bus asserts the bus request A bus master cannot use the bus until its request is granted A bus master must signal to the arbiter after finish using the bus Bus priority: the highest priority device should be serviced first Fairness: Even the lowest priority device should never be completely locked out from the bus Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. Distributed arbitration by collision detection: Ethernet uses this. Daisy chain arbitration: single device with all request lines. Centralized, parallel arbitration: see next-next slide
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Bus arbitration schemes usually try to balance two factors:

u u

Bus arbitration schemes can be divided into four broad classes:

u

u u u

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Centralized Bus Arbitration

Request-C Grant-C

Arbitration Circuit

Request-B Grant-B Request-A Grant-A

Release

Master A

Master B

Master C

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The Daisy Chain Bus Arbitration Scheme

Device 1 Highest Priority Grant Bus Arbiter Grant

Device 2

Device N Lowest Priority Grant Release Request

Advantage: simple Disadvantages: u Cannot assure fairness: A low-priority device may be locked out indefinitely u The use of the daisy chain grant signal also limits the bus speed
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Summary of Bus Options

Option Bus width Data width Transfer size Bus masters Clocking

High performance Separate address & data lines Wider is faster (e.g., 64 bits) Multiple words has less bus overhead Multiple (requires arbitration) Synchronous

Low cost Multiplex address & data lines Narrower is cheaper (e.g., 8 bits) Single-word transfer is simpler Single master (no arbitration) Asynchronous

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1993 Backplane/IO Bus Survey

Bus Originator SBus Sun TurboChannel MicroChannel PCI DEC 16-25 Physical 8,16,24,32 Single Central 33 84 26 IBM 12.5-25 Physical 8,16,24,32,64 Multi Central 25 75 13 Intel async Physical 8,16,24,32,64 Multi Central 20 111 (222) 25 33 33-

Clock Rate (MHz) 66 Addressing Master Arbitration Peak (MB/s) Max Power (W) Virtual Multi Central 89 16 Data Sizes (bits) 8,16,32

32 bit read (MB/s)

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New Generation of I/O Busses: Bit Serial Busses

A

new Generation of busses u Uses bit-serial (differential drive) technology to simplify interconnections. u Uses hot-wire connect and disconnect. u Uses on-line device drivers (Hot-Plug technology). u Automatically detects plugged in devices and configures the controlling software. u Provides power for peripheral devices.
+

Signal Power

+ Signal

Two main bit-serial bus technologies: USB and IEEE 1394 (FireWire)

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Mac-G5 I/O architecture

1. Fast O/I bus 8GB/S. 2. Point to point switch. 3. 400MHz 128b Memory bus. 4. 533MHz Graphics bus. 5. 133Mhz PCI-X bus. 6. 150MB/s ATA bus. 7. High performance I/O controller.

l Differences from conventional

3 bus system.
u

Use a switch to connect fast system components. Use high performance bit serial buses for external devices.

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The USB bus

USB 1.1: Current generation serial bus u 12 Mb/s serial bus. u Hot-plug technology (plug & play). u supports up to 127 external devices. u Provides power. u Daisy-Chain arbitration. u Up to 5 M long cable USB 2.0: Next generation serial bus. u 480 Mb/s serial bus (40x faster than USB 1.1) u Intel and Microsoft effort to sabotage FireWire.

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IEEE1394 FireWire serial bus.

IEEE 1394 bit serial bus. IEEE standard. u 400 Mb/S transfer rate. u Use hot plug technology (plug & play). u Supports up to 63 devices. u Provides power. u Use fairness arbitration scheme (?).
u u

Used for digital video camcorders. 1.2 Gb/s is in development.

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OS and I/O Systems Communication Requirements

The Operating System must be able to prevent: u The user program from communicating with the I/O device directly If user programs could perform I/O directly: u Protection to the shared I/O resources could not be provided Three types of communication are required: u The OS must be able to give commands to the I/O devices u The I/O device must be able to notify the OS when the I/O device has completed an operation or has encountered an error u Data must be transferred between memory and an I/O device

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Polling: Programmed I/O

CPU Is the data ready? Memory IOC no yes read data busy wait loop not an efficient way to use the CPU unless the device is very fast! but checks for I/O completion can be dispersed among computation intensive code

device store data done?

no

Advantage: u Simple: the processor is totally in control and does all the work Disadvantage: GK Spring 2004 CPS104 Lec33.28 u Polling overhead can consume a lot of CPU time

yes

Interrupt Driven Data Transfer

CPU (1) I/O interrupt (2) save PC Memory IOC (3) interrupt service addr read store ... : rti memory interrupt service routine add sub and or nop user program

device (4)

Advantage: u User program progress is only halted during actual transfer Disadvantage, special hardware is needed to: u Cause an interrupt (I/O device) u Detect an interrupt (processor) u Save the CPS104 Lec33.29 proper states to resume after the interrupt GK Spring 2004 (processor)

I/O Interrupt

An I/O interrupt is just like the exceptions except: u An I/O interrupt is asynchronous u Further information needs to be conveyed An I/O interrupt is asynchronous with respect to instruction execution: u I/O interrupt is not associated with any instruction u I/O interrupt does not prevent any instruction from completion

You can pick your own convenient point to take an interrupt

I/O interrupt is more complicated than exception: u Needs to convey the identity of the device generating the interrupt u Interrupt requests can have different urgencies:

Interrupt request needs to be prioritized

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Delegating I/O Responsibility from the CPU: DMA

CPU sends a starting address, direction, and length count to DMAC. Then issues "start".

Direct Memory Access (DMA): u External to the CPU u Act as a maser on the bus u Transfer blocks of data to or from memory without CPU intervention

CPU

Memory

DMAC

IOC

device DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory.
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