CPS 104 Computer Organization and Programming Lecture- 35: Interrupts and exceptions

April 12, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

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Admin.

Homework -8: is posted. Due: Monday April 19

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Interrupts and Exceptions

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Interrupts Exceptions and Traps

Interrupts, Exceptions and Traps are asynchronous changes in the control flow. Interrupts and Exceptions can be viewed as asynchronous (unscheduled) procedure calls. Interrupts and exceptions are designed to provide:
u

u u

protection mechanisms: Error handling, TLB management. efficiency: Overlap I/O and execution, . . . Illusion of parallelism: Timesharing, multithreading Ability to handle Asynchronous external events: Network connections, keyboard input, DMA I/O, . . .

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Interrupts and Exceptions

Exception: a change in execution caused by a condition that occurs within the processor.
u

u u u u

segmentation fault (access outside program boundaries, illegal access, . . .) bus error divide by 0 overflow page fault (virtual memory) devices: disk, network, keyboard, etc. clock for timesharing (multitasking) These are useful events, must do something when they occur.

Interrupt: a change in execution caused by an external event

u u u

Trap: a user-requested exception u Operating system call (syscall) u Breakpoints (debugging mode)
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An Execution Context

The state of the CPU associated with a thread of control (process) u general purpose registers (integer and floating point) u status registers (e.g., condition codes) u program counter, stack pointer Need to be able to switch between contexts u timesharing: sharing the machine among many processes u better utilization of machine (overlap I/O of one process with computation of another) u different modes (Kernel v.s. user) Maintained by operating system

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Context Switches

Save current execution context u Save registers and program counter u information about the context (e.g., ready, blocked) Restore other context Need data structures in kernel to support this u process control block Why do we context switch? u Timesharing: HW clock tick u I/O begin and/or end How do we know these events occur? u Interrupts...

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Handling an Exception
User Program ld add st mul beq ld sub bne Interrupt Handler

RETT

The same mechanism is used to handle interrupts, exceptions, traps.

Invoke specific kernel routine based on type of interrupt u interrupt/exception handler Must determine what caused interrupt u Cause register holds information on what caused the interrupt u PC <= interrupt_handler Vectored Interrupts u PC = interrupt_table[i] Clear the interrupt Return from interrupt (RETT) to different process (e.g, context switch)

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Execution Mode

What if interrupt occurs while in interrupt handler? u Problem: Could lose information for one interrupt
clear of interrupt #1, clears both #1 and #2

Solution: disable interrupts Disabling interrupts is a protected operation u Only the kernel can execute it u user v.s. kernel mode u mode bit in CPU status register Other protected operations u installing interrupt handlers u manipulating CPU state (saving/restoring status registers) u Updating TLB, Changing page table, changing page protection. Changing modes u interrupts u system calls (syscall instruction)
u

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Interrupts and exceptions in the MIPS 2000

The MIPS has a special coprocessor CP0, that is dedicated to Exception handling.
Status Register Index Register Random Register Context Register BdAddr. Register Cause Register EPC Register PRId Register

EntryHi

EntryLo

TLB

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MIPS-2000 CP0

EPC (Exception Program Counter): a 32-bit register used to hold the address of the affected instruction u register 14 of coprocessor 0 Cause: a register used to record the cause of the exception. u In the MIPS architecture this register is 32 bits, though some bits are currently unused. BadVAddr: register contains memory address at which memory reference occurred u when memory access exception occurs u register 8 of coprocessor 0 Status: interrupt mask and enable bits u register 12 of coprocessor 0 PRId: Processor Revision Identifier register

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Additions to MIPS ISA

Special coprocessor instruction: u mfc0 rt, rd # register rd in CP0 is loaded into register rt u mtc0 rt, rd # register rt is loaded into CP0 register rd u rfe # Return from exception, restore Interrupt mask and status register, (allow change in execution mode). TLB special instructions: u tlbp # The index register is loaded with the address of the TLB entry whose contents match the contents of EntryHi and EntryLo registers. u tlbr # Read Indexed TLB entry: The EntryHi and EntryLo registers are loaded with the content of the TLB pointed at by the TLB Index register u tlbwi # Write Indexed TLB entry: The EntryHi and EntryLo registers are stored in the TLB entry pointed at by the TLB Index register u tlbwr # Write random TLB entry: The EntryHi and EntryLo registers are stored in the TLB entry pointed at by the TLB random register
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Details of Status register Status 15 Mask 8 5 4 3 2 1 0 k e k e k e

old prev current

Mask = 1 bit for each of 5 hardware and 3 software interrupt levels u 1 enables interrupts, 0 disables interrupts k = kernel/user u 0 => was in the kernel when interrupt occurred u 1 => was running user mode e = interrupt enable u 0 means disabled, 1 means enabled Interrupt handler runs in kernel mode with interrupts disabled u When interrupt occurs, 6 LSB shifted left 2 bits, setting 2 LSB to 0
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Details of Cause register 15 10 5 Status Pending Code

Pending interrupt 5 hardware levels: bit set if interrupt occurs but not yet serviced u handles cases when more than one interrupt occurs at same time, or records interrupt requests when interrupts disabled Exception Code encodes reasons for interrupt u 0 (INT) => external interrupt u 4 (ADDRL) => address error exception (load or instr fetch) u 5 (ADDRS) => address error exception (store) u 6 (IBUS) => bus error on instruction fetch u 7 (DBUS) => bus error on data fetch u 8 (Syscall) => Syscall exception u 9 (BKPT) => Breakpoint exception u 10 (RI) => Reserved Instruction exception u 12 (OVF) => Arithmetic overflow exception
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How are Exceptions Handled?

Machine must save the address of the offending instruction in the EPC (Exception Program Counter) Then transfer control to the Operating System (OS) at some specified address OS performs some action in response OS terminates program or returns (eventually) using EPC u could return to different program (context switch) Exceptions are an unscheduled procedure call to a fixed location!

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How are Exceptions Handled?

2 types of exceptions in our current implementation u undefined instruction u arithmetic overflow Which Event caused Exception? u Option 1 (used by MIPS): Cause register contains reason u Option 2 Vectored interrupts: cause is part of the address.

u

addresses separated by 32 instructions E.g.,

Exception Type Undefined instruction Arithmetic overflow

Exception Vector Address C0 00 00 00 C0 00 00 20

Jump to appropriate address

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What happens to Instruction with Exception?

Some problems could occur in the way the exceptions are handled. Example: u in the case of arithmetic overflow, the instruction causing the overflow completes writing its result, because the overflow branch is in the state when the write completes. u However, the architecture may define the instruction as having no effect if the instruction causes an exception; MIPS specifies this. Virtual memory exceptions must prevent handler from changing the machine state. This aspect of handling exceptions becomes complex and potentially limits performance => why it is hard

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Pipelining

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Pipelining: Its Natural!

Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 40 minutes Folder takes 20 minutes

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Sequential Laundry 6 PM 7 8 9
Time

10

11

Midnight

30 40 20 30 40 20 30 40 20 30 40 20
T a s k O r d e r

A B C D

Sequential laundry takes 6 hours for 4 loads

If they learned pipelining, how long would laundry take?

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Pipelined Laundry: Start work ASAP 6 PM 7 8 9

Time

10

11

Midnight

30 40
T a s k O r d e r

40

40

40 20

A B C D

Pipelined laundry takes 3.5 hours for 4 loads

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Pipelining Lessons 6 PM

9
Time

30 40
T a s k O r d e r

40

40

40 20

A B C D

Pipelining doesnt help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to fill pipeline and time to drain it reduces speedup

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