Total No.

of Questions : 10]

[Total No. of Pages :2

P 1564

[4065] - 642 M.E. (E&TC-VLSI and Embedded Systems)

SOFTWARE DEFINED RADIO (504192) (2008 Course) (Elective - IV)

Time : 3 Hours] [Max Marks : 100 Instructions to the candidates : 1) Answer any three questions from each Section. 2) Answers to the two sections should be written in separate books. 3) Figures to the right indicate full marks. 4) Assume suitable data, if necessary.

SECTION-I Q1 ) a) Explain the concept and need of Software defined radio? List the advantages of software defined radio over existing wireless technologies. [8] How is software radio different than other radios? Explain the relation between cognitive radio and software defined radio. [8] Explain the relation of software communications architecture (SCA) in relation with Software defined radio. [8] Explain different overview in relation to SDR namely: Architecture Overview. Functional Overview and Networking Overview. [8] In relation to SRD. explain the steps involved in transmitter and receiver of RF front end. [8] Explain how smart selection of ADC/DAC enables better design of software defined radio? [8] Draw and explain the functional architecture (typical architecture) of Software defined radio. [8] Enlist the various factors to be considered while designing the dynamic range of SDR receiver? [8]

b) Q2) a) b)

Q3) a) b)

Q4 ) a) b)

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Q5 ) Write short notes on (Any Three): a) b) c) d) e) Q6) a) b) Q7) a) b) Q8 ) a) b) SDR Forum. Joint Tactical Radio System (JTRS). COBRA in relation to SDR/JTRS. SPEAKeasy. SDR and hardware issues (FPGA/CPLD/ASIC). SECTION-II

[18]

What are the different adaptive techniques involved in the processing of Software defined radios? Explain any one of them. [8] How to apply Software defined radios principles to antenna systems? [8] What are the factors to be considered while selecting the antenna for SDR? [8] Explain the implementation of low cost SDR platform? [8] Explain the role of Digital Signal processing algorithms in software defined radios. [8] Explain the parameters to be considered for selecting a processor for SDR application? [8]

Q9 ) Explain any two applications of SDR/JTRS amongst the following: [16] a) Military b) Commercial systems c) RFID d) Aerospace Q10 ) Write short notes (Any Three): a) Smart Antennas b) Future of Software defined radio c) GNU radio d) RTOS e) Core Framework in relation to JTRS [18]

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Total No. of Questions :8]

[Total No. of Pages :2

P1301

[4065] - 628 M.E. (E&TC) (VLSI & Embedded System) ASIC DESIGN AND MODELLING (2008 Course) (504184(a)) (Elective - I)
[Max. Marks :100

Time : 3 Hours] Instructions to the candidates: 1) Answer any three questions from each section. 2) Neat diagrams must be drawn wherever necessary. 3) Assume suitable data, if necessary.

SECTION - I Q1) a) b) Q2) a) b) Q3) a) b) Classify and explain in detail Gate Array based ASICs. [8] With neat flow chart explain the sequence of steps to design an Application specific Integrated circuits. [10] Explain in brief different modeling techniques used in VHDL. [8] Classify and explain in detail different simulation modes in simulators.[8] With neat timing diagram, explain step by step process of SCAN Path technique for testing of sequential circuit. [8] Define path sensitization. Explain step by step process to derive the test set for the figure 1 using the same method. [8]

Q4) Write short note on : a) b) c) Automatic Test Vector Generation. Methods to minimise clock skew. Differentiate Testing and Verification.

[18]

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SECTION - II Q5) a) b) List out goals and objectives for each block in the physical design of ASIC. [8] Explain with step by step process, K-L algorithm for system partitioning. List out different issues to be considered before the implementation.[8] Classify placement algorithm. With example explain one from each in detail. [8] What are different approaches to global routing. Explain in detail one algorithm to find the shortest path. [8] Explain in detail the different factors contribute to best floor planning. Also define wire load model. [6] Classify and explain different issues in verification. [6] Write a note on DRC. [6] [18]

Q6) a) b)

Q7) a) b) c)

Q8) Write short note on : a) Power dissipation. b) Measurement of interconnect delay. c) Features of EDA tool.

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Total No. of Questions :10]

[Total No. of Pages :2

P1302

[4065] - 632 M.E. (E & TC) (VLSI and Embedded Systems) MEMORY TECHNOLOGIES (2008 Course) (Elective - II) (504185)

Time : 3 Hours] Instructions to the candidates: 1) 2) 3) 4) 5) Answer any three questions from each section.

[Max. Marks :100

Answers to the two sections should be written in separate books. Neat diagrams must be drawn wherever necessary. Figures to the right indicate full marks. Assume suitable data, if necessary.

SECTION - I Q1) a) Draw and explain various CMOS SRAM cell configurations. b) Draw and explain various circuit elements of BiCMOS circuit. [6] [6]

c) Compare SRAM and DRAM based various performance parameters of memory technology. [6] Q2) a) Draw and explain the functional diagram of a typical Application Specific SRAM? [8] b) Explain trench cell and stacked capacitor cell structure of DRAM. [8] Q3) a) Explain with block diagram CMOS ROM. b) Explain with block diagram flash memory architecture. [8] [8]

Q4) a) Explain Silicon-on-insulator (SOI) technology? What are advantages and disadvantages of the same? [8] b) Explain with sketches soft failure error in DRAM. [8]

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Q5) a) What is Non volatile memory and explain with different classifications highlighting the silent features. [6] b) Explain OTP with silent features. c) What is antifuse, explain in brief. SECTION - II Q6) a) List the different faults that can occur in a memory chip and explain in brief? [8] b) Explain Pattern sensitive fault in detail? Q7) a) Explain any one algorithm used for functional testing of RAM? [8] [8] [8] [16] [6] [4]

b) Explain bathtub curve in the context of memory failures. Q8) Write short notes on any four. a) Operational life test (OLT) b) Radiation hardening techniques. c) Analog memory. d) Ferroelectric memories. e) Radiation effects on semiconductor memory.

Q9) a) Explain in detail various high density memory packages in both insertion mount and surface mount technologies. [8] b) Explain in detail 3D memory stacks in multichip modules (MCM). Q10) Write short notes on any three: a) Digital Tablet PC. b) LCD c) DVD Player. d) Memory cards e) High-density memory packaging future directions. [8] [18]

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Total No. of Questions : 6]

[Total No. of Pages : 2

P1426

[4065]-134 M.E. (E&TC) (VLSI & Embedded System) FAULT TOLERANT SYSTEM DESIGN
(2002 Course)

Time : 3 Hours]

[Max. Marks : 100

Instructions to the candidates: 1) All questions are compulsory. 2) Answers to the two sections should be written in separate answer books. 3) Neat diagrams must be drawn wherever necessary. 4) Assume suitable data, if necessary.

SECTION - I
Q1) a) b) What is Binary Decision Diagram. Construct a binary decision diagram for the exclusive- OR function of two variables. [8] Define unknown logic value. Construct a Truth table of NAND and not gate using 6-value logic. [8] Define fault detection and fault Redundancy. Prove the theorem. Define fault dominance of a combinational circuits. Prove the theorem. Define fault equivalence of a combinational circuit. Prove the theorem. Explain step by step process for testing of a sequential CKT using state table. [18] [16]

Q2) a) b) c) d)

Q3) Write a short note on (any two) a) Parallel fault simulation. b) Logical fault models. c) Zoom table.

P.T.O.

SECTION - II
Q4) a) Explain the following terms: i) ii) iii) iv) b) Controllability Observability Predictability Reliability [8]

Explain in detail Generic Scan-Based DFT technique for external Testing. [8]

Q5) a) b)

Explain Transition-Count Compression Technique in detail.

[8]

Classify pseudo exhaustive Test pattern generator. Explain cyclic LFSR in detail. [8] [18]

Q6) Write short note on: a) b) c) Self checking system PLA Testing Fault Dictionary

abab

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Total No. of Questions :8]

[Total No. of Pages :2

P1521

[4065] - 636 M.E. (E & TC) (VLSI & Embedded System) RF IC DESIGN (2008 Course) (Sem. - II) (504190)
[Max. Marks :100

Time : 3 Hours] Instructions to the candidates: 1) 2) 3) 4) 5) 6) Answer any three questions from each section.

Answers to the two sections should be written in separate books. Neat diagrams must be drawn wherever necessary. Figures to the right indicate full marks. Use of logarithmic tables, slide rule, Mollier charts, electronic pocket calculator and steam tables is allowed. Assume suitable data, if necessary.

SECTION - I Q1) a) What is Open CKT Time constant method? Explore with example & mathematical analysis in detail. What are its limitations? [8] b) What is subthreshold operating region? Explain the effects of short channel. [8] Q2) a) List the sources of RFI/EMI & cross talk. [8]

b) Explain the causes of cross talk. What are the mitigation techniques? How to achieve them? [8] Q3) a) Design CMOS amplifier for voltage gain of 60dB & bandwidth of 200 MHz. Assume suitable data. [8] b) With the help of incremental model of MOSFET based tuned amplifier, explain unilateralization & neutrilization techniques in detail. [8]

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Q4) Write short notes on: (any three) a) Power match versus noise match. b) Back gate bias effect c) RF sensitive MOSFET parasitics. d) MOSFET capacitors in various operating regions. SECTION - II

[18]

Q5) a) Explain ASIC design flow. At what stage will you care for cross talk. [8] b) Why S parameters are needed to analyse RF amplifiers? Give S matrix of two port RF amplifer & its meaning. [8] Q6) a) Differentiate single ended & differential LNA. Draw the schematics. [8] b) Design LNA to operate at 650 MHz. Design suitable bias. Compute device width degenerating inductance, noise figure & Lg. Assume suitable data. [8] Q7) a) Explain different types of mixers with the concepts & mathematical expressions. [8] b) What is noise model? Explain any one noise optimization technique in detail. [8] Q8) Write short notes on: (any three) a) Series and shunt peaking amplifier. b) Requirements of LNA. c) AM - PM Conversion. d) Linearity & isolation. [18]

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[4065]-636

Total No. of Questions : 8]

[Total No. of Pages : 2

P1477

[4065] - 625 M.E. (E & T/C) (VLSI & Embedded Systems) ANALOG AND DIGITAL CMOS IC DESIGN (2008 Course) (504181) (Sem. - I)

Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates: 1) Answer any three questions from each section. 2) Answer to the two sections should be written in separate answer books. 3) Neat diagrams must be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary.

SECTION - I Q1) a) b) c) Q2) a) b) Q3) a) b) What is body effect in case of MOSFET? What is latch-up problem in CMOS? How to overcome it? [4] What is MOS model? What are its objectives? How it is used by designers? [4] Where and How MOSFET is used as diode/Active Resistor? [8] Use self-biased high-swing cascode current sink configuration to design a current sink of 250 A and a VMIN of 0.5V. Assume suitable data. [8] Explain in detail the concept of BGR with its necessity. [8] Current mirrors are based on which principle? Explain in short nonideal effects of current mirrors. What is the use of current mirrors? [8] Explain various architectures of High gain amplifier. [8] [18]

Q4) Write short notes on any three : a) Active Load Inverter & its parameters. b) Techniques used in Micro power opamp. c) Current Amplifiers. d) Buffered Op Amps using MOSFETs.

P.T.O.

SECTION - II Q5) a) b) c) In CMOS technology why do we design the size of pMOS to be higher than the nMOS? Why PMOS and NMOS are sized equally in a transmission gate? [4] Why is NAND gate preferred over NOR gate for implementing a design using CMOS logic? Design NAND gate using pass transistor logic and transmission gate. [4] Consider a complex CMOS logic gate that implements the function F = (A.B + C.D.E) [8] i) Design the circuit. ii) An inverter with bn = bp is used as a sizing reference. Find the device sizes in the gate if we chose to equalize the nMOS and pMOS resistances. What is metastability? How long does it stay in this state? What are the cases in which metastability occurs? How do designer tolerate metastability? [8] Compare Domino and NORA high performance CMOS logic circuits. Explain NORA CMOS logic in detail. [8]

Q6) a) b)

Q7) Design FSM controller for a coin - operated vending machine. Machine dispenses candy under the following conditions: [16] The machine accepts 1 rupee and 2 rupee coins. Only one coin at particular instant. It takes 3 rupees for a piece of candy to be released from the machine. If 4 rupees are deposited, the machine will not return the change, but it will credit the buyer with 1 rupee and wait for the buyer to make a second purchase. Draw the minimized state diagram. Write VHDL code and test bench for the same. Q8) Write short notes on any three : a) Significance and Types of Hazards. b) Technology Scaling: Types and effects. c) CMOS Parasitic. d) Power dissipations and PDP in CMOS logic. [18]

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