A Novel Offset Based

ABSTRACT

PWM Method For 3f AC-AC Matrix Converter

Therefore, it may not be convenient to apply further for more complicated or combined structures. Similar PWM performance was obtained by Venturinis proposal, which was based on the analysis of conventional three-phase modulation switching time diagram, its gain was however limited to 0.5 [1]. A later version had improved and extended this value up to 0.866 with use of a particular offset function [10]. Unfortunately, the injected offset required the knowledge of the input/output phase arguments. Another disadvantage of Venturini offset was its validity for three phase sinusoidal and balance system. The carrier PWM method using two nearest voltage sources for producing the output voltages was produced with low output current ripples, but it couldnt justify the ability to control the input power factor [11]. A two-stage power conversion had shown be an efficient approach to control the ac-ac matrix converter for unity power factor. The input phase displacement can be adjusted in the rectifier stage and independently from output voltages in the inverter stage [5-8]. This two-stage space vector PWM method was later properly implemented in carrier based PWM techniques [12-14]. In these methods, the phase displacement of input current was defined by selecting the two active input sources and calculating the corresponding two half time periods of an asymetrical carrier waveform. The flexibility of PWM control was decided by the offset controller. The first work [12] used different nonzero offsets and carriers in every half-triangle. The later one [13] prefered with using the zero offset for a transfer ratio lower than 0.5 and the Venturinis offset for higher voltage range. The existence of the various offset functions had emphasized its flexible capability and key role for attaining PWM performance. It has still remained an unjustified problem, what is the offset based PWM model and its characteristics. A universal offset model of ac-ac matrix converter should cover all characteristics of the mentioned PWM methods and it may offer a general guide for further development. In this paper, an analysis of a novel universal offset based PWM model of the ac-ac matrix converter will be presented. Its main characteristics as the offset operating ranges, matrix voltage ranges, output voltage ranges and

Abstract: The paper presents a novel universal offset based PWM method for 3f ac-ac matrix converter, whose characteristics can be controlled by the offset regulation. Typical characteristics of the offset based PWM control for the matrix converter will be described. The proposed PWM algorithm may help to simplify further study of PWM techniques for ac-ac matrix converter. Different variants of the offset functions for unity input power factor will be presented. The theoretical analysis will be verified by simulation and also experimental results.

Keywords: ac-ac matrix converter, offset based PWM, common mode, input power factor, Discontinuous PWM.

I. Introduction
AC-AC matrix converter is commonly used as a power circuit for a direct changing a three-phase sinusoidal voltage sources at the input to variable ac voltage outputs. Comparing to a conventional voltage source inverter, the ac-ac matrix converter is advantageous for higher efficency because it doesnt need a dc linkFig.1. Avoiding the use of dc capacitor, the system will become more reliable. The features of the matrix converter enable a bidirectional power tranfer between the input source and the load without any extra circuit. The drawback of the matrix converter is a reduction of the voltage output gain, which can attain a maximum value of 0.866 related to the input voltages [1]. Another problem of matrix converter is caused by the sophisticated commutation process. In recent year, in order to overcome the voltage limits, several solutions have been introduced, either with the help of hardware modifications [2] or with an extension in overmodulation range [3-4]. For controlling the matrix converter, several PWM methods have been developed during the decades. Similar to voltage source inverters, the space vector PWM has been a very common approach, which can attain output voltages up to transfer ratio of 0.866 and unity input power factor [5-9]. The disadvantage of the method is the sophisticated mathematical derivation and the use of a look-up table.

PWM modes will be described. As a general approach, selection of a PWM pattern, which is defined for gaining PWM quality and deduced from circuit analysis, would be a starting point. The parameters and their operating ranges are deduced from defined PWM patterns. The offset based model of matrix converter will determine operating ranges and offer possible solutions to meet the practical demands. II. Proposed General offset based PWM of the matrix converter and its characteristics. This section will study general characteristics of the offset based PWM controller without any special requirements on the PWM performances. The maximum available ranges of the related parameters will be deduced for further consideration. An example as PWM method using the two nearest voltage levels was introduced in [11] can be implemented for simple applications. Its principle would justify the reduction of the current ripple but without considering any impact on the input power factor. 1. Circuit diagrams and definitions From the circuit point of view, a 3f ac-ac matrix converter can be seen as a modified topology of a three-level voltage source inverter that three- voltage levels are given by instantaneous three phase voltages, which are time-variable. Lets neglect the influence of the input filter, the circuit diagram can be simplified and drawn as shown in Fig.2a. Lets define a neutral point of ac souces 0 and

Figure 1: Circuit diagram of

3f ac-ac matrix converter

Lets define MAX, MID and MIN as the maximum, medium and minimum values of three voltage sources-Fig.3:

MAX = Max(vSA , vSB , vSC ) MIN = Min(vSA , vSB , vSC ) MID = Mid (vSA , vSB , vSC )

(3) (4) (5)

2. Offset Based PWM Method of the ac-ac matrix converter Principle of the offset based PWM method: The offset control block defines basic parameters for PWM implementation. Firstly, for given fundamental voltages and the ac source conditions, the offset controller will optimize and produce an offset, which adds to the fundamental one. The resulting matrix voltages will be then put at the input of the PWM pulse generator, which generate the trigger pulse signals Fig.4. Lets define

vSA , vSB , vSC the three phase voltages ; va , vb , vc three

phase load voltages; voltages.

v A1 , vB1 , vC1 the three-phase fundamental v0 the matrix offset. Any offset

v A0 , vB 0 , vC 0 the three phase matrix

(1a) (1b) (1c) (2a)

matrix voltages and

vSA = VS cos(S t ) vSB = VS cos(S t 2 / 3) vSC = VS cos(S t 4 / 3) va = Vm cos(Ot + O )

injected into the matrix voltage doesnt have any influence on the load voltage. The matrix voltage can be expressed as a sum of the fundamental and the offset ones as- Fig.2c:

v X 0 = v X 1 + v0 ; X = A, B, C

(6)

vb = Vm cos(Ot + O 2 / 3) (2b) vc = Vm cos(O t + O 4 / 3) (2c)

For balance three-phase load voltages, it can be deduced that the fundamental components are equal to the load voltages, i.e. :

v x = v X 1 ; x = a, b, c; X = A, B, C

(7)

Limits of the matrix voltages and its components The matrix output voltage measured from the output to the neutral point of three phase voltage sources may attain some from MAX, MID and MIN values. The equivalent circuit diagram is shown in Fig.2b.

maximum amplitude, defined by (9). From the limits of the line-line voltages shown in Fig.3, for symmetrical and sinusoidal three-phase voltages of the amplitude of

VS ,

the fundamental phase voltages, applying to the load can attain the limit given by :

V1M = 3VS / 2 = 0.866VS

(10)

The limits of the matrix offset The offset can be set equal to any value in the range defined as follows:

v0 min v0 v0 max

(11)

where two extreme values of the offset can be defined as follows:

v0 min = MIN min v0 max = MAX max

(12) (13)

and the maximum and minimum values of the load voltages are defined as:
Figure 2: Derivation of proposed offset model of matrix converter. 3f ac-ac

max = Max(v A1 , vB1 , vC1 ) min = Min(v A1 , vB1 , vC1 )

(14-15)

The offset limit defined by (13)-(14) introduces a maximum availabe offset boundaries for given maximum output voltages without special requirement on PWM controller. As simple examples shown in Fig.5, there are shown two PWM patterns with modulation between a) MIN and MAX levels or b) between two nearest levels.

Figure 3: Diagrams of voltage limits for medium common mode PWM ( qV

= 0.866

0 = 2 / 3 , f 0 = 60 Hz ).

Figure 4: The principle of the Offset based PWM Controller.

The limits of the

matrix voltages are given by:

MIN v X 0 MAX ;

X = A, B, C

(8)

Figure 5: PWM patterns with maximum voltage gain.

The line-line voltages are confined by the conditions as :

v XY 1 MAX MIN ; X=A,B,C; Y=A,B,C (9)

The line-line voltages supplied to the load attain a

The equation system (8),(9),(12) and (13) establishes a basis for the carier based PWM of the matrix converter. In order to satisfy further demand such as unity input power

factor, the PWM algorithm should be studied in detail. The related setting in the offset controller may be modified. The novel parameter limits would be derived from the conditions involved in the related PWM algorithm. The validity of the offset model and previously general deduced equations should be remained the same for applications. This rule will be shown in the next section of the offset controller for unity input power factor. 2. Typical offsets without Power factor control In order to demonstrate the flexibility of the offset control for the matrix converter, lets consider several particular cases of the offsets, defined as following. Continuous PWM Methods a) The minimum common mode PWM: the offset helps to reduce average common mode voltage and defined as:

min value is connected to the voltage source of the minimum instantaneous value MIN for the
load voltage of whole sampling period. The offset is defined by (12) and shown in Fig.8. If the PWM pattern 5a) is used,

Figure 6: The Minimum common mode PWM. ( qV

= 0.866

0 = 2 / 3 , f 0 = 60 Hz ).

v0 max v0 = v0 min 0

if if if

v0 min v0 max 0 0 v0 min v0 max else

(16)

The offset is zero and the reference matrix voltage for producing output voltage up to the tranfer ratio of 0.5 has a sinusoidal waveform. A nonzero offset occurs in several discontinuous durations for m>0.5 as shown in Fig.6. b) The medium common mode PWM: is defined as average value from both extremes (12) and (13) as- Fig.7:

v +v v0 = 0max 0min 2
zero vectors

Figure 7: The medium common mode PWM. ( qV

= 0.866

(17).

0 = 2 / 3 , f 0 = 60 Hz ).
.

In the previous two PWM methods, several from three as

[ MIN , MIN , MIN ]T

[ MID, MID, MID]T and [ MAX , MAX , MAX ]T may

appear in a switching state sequence. Discontinuous PWM methods c) The maximum offset discontinuous PWM is defined by (13) and drawn in Fig.8. The phase load voltage of max value is connected to the voltage source of the maximum instantaneous value

MAX for the whole sampling period. The maximum offset v0 max presents

the switching states with the highest common mode. For example, if the PWM pattern in Fig.5a) is used, the only zero vector of maximum offset

[ MAX , MAX , MAX ]T will appear in the switching

state sequence. d) The minimum offset discontinuous PWM : The phase
Figure 8: The three-phase matrix voltages for the extreme offsets. The PWM method with a) maximum offset (upper) and b)

minimum

offset

(below)

qV = 0.866

as follows:
' v0 max = MAX ' max

0 = 2 / 3 , f 0 = 60 Hz ).
, the only zero vector

(18a) (19a)

[ MIN , MIN , MIN ]T will appear

' v0 min = MIN' min

in the switching state sequence. III. The offset based PWM method For Unity Input Power Factor 1.The characteristics of Unity power factor offset For studying particular requirements upon the input/output quality of the matrix converter, the designing PWM patterns and determination of parameters for the offset controller presents a significant stage. A proper PWM algorithm can guarantee some demanding performance and may be different for each application. The principle described in Fig.4 and the algorithms (1)-(15) are also valid to offset based PWM for unity power factor. The difference is that the offset and matrix voltage limits will be needed to redefine depending on the selected PWM patterns/ algorithms. As mentioned in the introduction, the idea of the carrier PWM for unity input power factor was similar to the two-stage power conversion [5],[6],[8] where the phase angle of reference input current vector is properly controlled for corresponding time duties of two related pivot input current vectors. In order to utilize the maximum output voltages for inverter stage, it was selected the virtual dc-link voltage of maximum amplitude. A sequence of switching state voltages can be distributed while the vector of input current is held at each pivot vector position. With a proper setting of the offset, the load voltages can be extented to a maximum value of m=0.866. The principle of two-stage power conversion was advantageously described in carrier PWM methods using two PWM patterns [12],[13] as shown in Fig.10, which can attain maximum operating voltage range. For further consideration and in order to demonstrate the applications of the proposed universal offset based PWM method for unity input power factor, the two previously described PWM patterns will be used. The main problem of offset based PWM method will be to define offset function. Finally the reference for PWM generator can be easily obtained. The requirement of a unity-power factor of the mentioned PWM generator contributes further conditions for the offset controller. Comparing with the offset limits defined in (12),(13), novel quantities have similar forms. Their values are more restricted and defined

Figure

9:

Two

PWM and b)

patterns

are
2 m

defined .

for

a)

MAX > MIN

Where
'

MAX < MIN

MAX ' = Min( MAX ,

3V + MIN ) (18b) 2MIN

2 3Vm + MAX , MIN ) (19b). MIN = Max( 2MAX

The corresponding operating range of the matrix voltages will be reduced and expressed as follows:
' v 'X 0 min v 'X 0 v X 0 max

(20a)

v 'X 0 max = Min(

v 'X 0 min = Max(

2 3Vm + MIN , MAX ) (21) 2MIN

2 3Vm + MAX, MIN) (22) 2MAX

Maximum available line-line voltages are restricted by:

' v XY = 2 3Vm 2M M = Max( MAX , MIN )

(23a) (23b).

With the selected PWM patterns, the equation system (20)-(23) provides a basis for studying the carrier based PWM method for unity input power factor. The amplitude of the fundamental output voltages for unity power factor may gain the highest value of

0.866VS defined by (9) for

the linear modulation range. The lost of the volt-second area from (23) compared to (9) doesnt cause any reduction of the fundamental output voltage, but the new

limits of the matrix voltage would reduce capability for extending the fundamental voltage over the transfer ratio of 0.866. 2. Typical offsets For unity Power factor It is clear that the PWM patterns and the offset based PWM method described by (18)-(23) can ensure a unity input power factor. Continuous PWM methods: a) Medium common mode PWM Lets define medium offset by substituting the offset limits
' ' v0 max , v0 min into (17), we obtain: ' v0 = m 2 3Vm mid + 4m 2 MAX for MAX MIN m= MIN for MAX < MIN

b) Minimum common mode PWM method: Its offset function is obtained by substituting
' ' v0 max , v0 min from

(18) into (16). For a transfer ratio higher than 0.5, the PWM becomes partly a discontinuous PWM mode.

(24b)
Figure 11: Small difference between Venturinis

(24c)
medium common mode offset for

v0VENT and
;

qV = 0.866

The medium offset (24) is simply expressed without the need of any information about the input/output frequency or their corresponding phase arguments, and depending only on the instantaneous values of the input sources and reference output voltages. Therefore, its implementation in a control system is practically comfortable. In order to get a complete view about the method, the offset diagram is compared with the Venturinis one [10],[13] as shown in Fig.10-11. The difference between them is negligible in most part of the waveform. The Venturinis offset shows be a particular solution of the offset problem for unity input power factor, defined by (18) and (19). It is approximate to the medium offset function. Small differences between them may appear obviously in higher transfer ratio as shown in Fig.11. Therefore, both methods are expected to have similar dynamic characteristics.

0 = 2 / 3 , f 0 = 60 Hz
Discontinuous PWM methods: The advantage of the offset regulation can be simply utilized for improving the switching loss by reducing the number of switchings in a so-called Discontinuous PWM (DPWM). A proper offset setting can help to attain Discontinuous PWM mode and effectively improve commutation and switching loss problem. Because the offset range is small at high voltage tranfer ratio, the contribution of the offset regulation for the input power factor would be negligible. For considered PWM approach for unity power factor, three-phase modulation may be needed to produce an output voltage. Number of switchings may be reduced , i.e. single-phase and two-phase modulation, depending on the concrete conditions and the required output performance Fig.12. Therefore, the analysis of the discontinuous PWM in matrix converter is more complicated than that of the conventional voltage source inverter. From (18)-(19), there are practically four available offsets for setting DPWM modes. During period of each input current vector, two different extreme offsets may be selected. This following section introduces several typical offset settings. c) Single-phase DPWM: The first type as so called fully DPWM. For example, the diagrams of the offset, the fundamental voltage and matrix voltage of single-phase DPWM are shown in Fig.13. One phase is without commutations. Its offset can be described as:

Figure

10:

The

difference

between

Venturini
' 0

offset

v0VENT and medium common mode offsets v f 0 = 60 Hz , qV = 0.2

;

is negligible for

0 = 2 / 3 .

MAX max for MAX MIN v0DPWM1 = (25) MIN min for MAX < MIN For MAX MIN , the output phase load voltage of maximum value max will be connected to the highest input voltage source of MAX (duty ratio d A = 0 ) and remain unchanged during sampling periodMAX < MIN , the output voltage of minimum value min will be connected the lowest input voltage of MIN ( d A = 1 ) and remain
Fig.12a. Otherwise for unchanged during sampling period-Fig.12b. d) Two-phase DPWM: Compared with three-phase modulation, number of switchings for one phase may be reduced. This partly DPWM type uses the offset defined by :
2 3V m + MAX min = 2 MAX 2 3V m + MIN max 2 MIN

MAX MIN , the output phase voltage of value min will have the only one switching between two input sources of MIN and MID -Fig.12a ( d A = 1 ). Otherwise for MAX < MIN , the output phase voltage of value max will have the only switching between two input sources of MAX and MID -Fig.12b ( d A = 0 ). For example, the diagrams of
As results, for the offset, the fundamental voltage and matrix voltage of the mentioned two-phase DPWM are shown in Fig.14. Single-phase and two-phase DPWM methods establish a basis for implementing different DPWM techniques. Different DPWM proposals can be deduced by applying them into practical applications. Further modified DPWM methods in respect to common mode can be introduced as following.

for for

MAX MIN MAX < MIN

v 0 DPWM 2

(26).

Figure

13:

Single-phase

DPWM-

qV = 0.866

0 = 2 / 3 , f 0 = 60 Hz .

Figure

14:

Two-phase

DPWM-

qV = 0.866

0 = 2 / 3 , f 0 = 60 Hz .
Figure 12: DPWM methods. Single-phase and two-phase modulations for a)

MAX > MIN

and

b)

MAX < MIN .

e) Discontinuous PWM methods for extreme common modes: The offsets for both maximum and minimum common mode DPWM methods can be established as

follows:

RESULTS
' 0 max

v0 DPWMMAX = v

(27) (28)

' v0 DPWMMIN = v0 min

These DPWM methods alternate both single-phase and two-phase modulations each one sixth period of input voltage sources. An example of DPWM with maximum offset was presented in Fig.15.

For demonstration, the proposed offset based PWM method for input unity power factor has been verified by simulation and experimental results. The MATLAB/SIMULINK simulation were realized for two cases as a)

qV = 0.5; f 0 = 30 Hz

and

b)

qV = 0.866; f 0 = 60 Hz . The offset was selected as

medium common mode. For experimental verification, a 3f ac-ac matrix converter was set using fast IGBT FGH40N120. The whole system was connected to the power supply throught 3f transformer 3f 380/ 50

3 [V], 50Hz. The main hardware

Figure 15: DPWM with maximum offset.

qV = 0.866

0 = 2 / 3 , f 0 = 60 Hz
f) DPWM method for minimum common mode: its related diagrams are drawn as shown in Fig.16, the offset can be defined as:
' v 0 max v0 DPWM CM = ' v0 min

for for

' ' v0 max < v0 min ' ' v0 min < v0 max

(29)

Optimizing the DPWM methods may be considered with a proper use of both two DPWM methods described above. However, a detail study of this content could exceed the paper limit.

parameters were described in Table 1. The PWM algorithm was implemented with the use of the card ezdsp TMS320F2812. The frequency of the triangle waves was set equal to 5kHz. The four step commutations were realized with the help of FPGA Kit SPARTAN 3E. The input voltage sources were synchronized using the voltage transducer LEM LV 25NP. The load currents were measured with LEM LA55-P. All the diagrams were captured with Tektronix 200MHz TDS 2014. Finally, the diagrams of simulations were drawn as shown in Fig.17-22 for the 1st case and in Fig.23-29 for the 2nd case. For simplifying the simulation, the ac-ac matrix converter was modelled without the input filter LC and the deduced input current as shown in Fig.21 and 27 was obtained by using the MATLAB tool of the digital LF filter. The experimental results were shown for both cases in Fig. 29-33 and 34-40, respectively. The identical and high performances of the ouput voltages and currents and nearly unity input power factor obtained from both simulation and experiments have confirmed the rightness of the proposed modeling and the correctness of the theoretical analysis. Table 1: Hardware setting Phase input voltages (RMS) 50V Input frequency 50 Hz Resistance 10 Inductance LC filter 80mH

Figure

16:

DPWM ;

with

minimum

common

mode.

L f = 1mH C f = 20 F

qV = 0.866
III.

0 = 2 / 3 , f 0 = 60 Hz
AND EXPERIMENTAL

SIMULATION

Figure 17: Simulation results-Diagrams of 3 phase load currents.

Figure 20: Simulation results-Diagram of a line-line load voltage.

qV = 0.5; f 0 = 30 Hz

qV = 0.5; f 0 = 30 Hz

Figure 18: Simulation results-Diagrams of FFT analysis of a phase load current.

Figure 21: Simulation results-Diagrams of input voltage and current.

qV = 0.5; f 0 = 30 Hz

qV = 0.5; f 0 = 30 Hz

Figure 19: Simulation results-Diagrams of and voltage.

phase load current

qV = 0.5; f 0 = 30 Hz

Figure 22: Simulation results-Diagram of FFT analysis of input current.

qV = 0.5; f 0 = 30 Hz

Figure 23: Simulation results-Diagrams of 3 phase load currents.

Figure 26: Simulation results-Diagram of line-line load voltage.

qV = 0.866; f 0 = 60 Hz

qV = 0.866; f 0 = 60 Hz

Figure 24: Simulation results-Diagram of FFT analysis of phase load current.

qV = 0.866; f 0 = 60 Hz

Figure 27: Simulation results-Diagrams of input voltage and current.

qV = 0.866; f 0 = 60 Hz

Figure 25: Simulation results-Diagram of phase load voltage and current.

qV = 0.866; f 0 = 60 Hz

Figure 28: Simulation results-Diagram of FFT analysis of input phase current.

qV = 0.866; f 0 = 60 Hz

Figure 29: Experimental results -Diagram of 3f load current.

Figure 32: Experimental results -Diagram of a line-line voltage.

qV = 0.5; f 0 = 30 Hz .

qV = 0.5; f 0 = 30 Hz

Figure 30: Experimental results -Diagram of FFT analysis of load current.

Figure 33: Experimental results -Diagram of input phase voltage and current.

qV = 0.5; f 0 = 30 Hz

qV = 0.5; f 0 = 30 Hz

Figure 31: Experimental results -Diagram of phase load voltage and current.

Figure 34: Experimental results -Diagram of FFT analysis of input current.

qV = 0.5; f 0 = 30 Hz

qV = 0.5; f 0 = 30 Hz

11

Figure 35: Experimental results -Diagram of 3f load current.

Figure 38: Experimental results -Diagram of a line-line load voltage.

qV = 0.866; f 0 = 60 Hz

qV = 0.866; f 0 = 60 Hz

Figure 36: Experimental results -Diagram of FFT analysis of load current.

Figure 39: Experimental results -Diagram of input voltage and current.

qV = 0.866; f 0 = 60 Hz

qV = 0.866; f 0 = 60 Hz

Figure 37: Experimental results -Diagram of phase load voltage and current.

qV = 0.866; f 0 = 60 Hz

Figure 40: Experimental results -Diagram of FFT analysis of input.

qV = 0.866; f 0 = 60 Hz

IV. CONCLUSIONS

The paper presents a novel offset based PWM model for 3f ac-ac matrix converter. Basic characteristics and parameter limits of the proposed circuit model as the fundamental voltages, the offset extremes have been analyzed and evaluated. A capability of ac-ac matrix converter can be fully explored with various offset based PWM techniques. The paper has also shown the impact of a PWM solution on the offset and the output voltages. The algorithm of the proposed offset based PWM method is simple. The universal characteristics of the proposed algorithm can be easily modified for further study on PWM control of matrix converter. In the final section, the offset based PWM method for medium common mode was verified and demonstrated by experimental results. REFERENCES
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