Beruflich Dokumente
Kultur Dokumente
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - PMC/XMC Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 1 GHz A/D and D/A, Virtex-6 FPGA - XMC 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - XMC 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Wideband DDC, Virtex-6 FPGA - XMC Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - XMC 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - XMC 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - XMC 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMC 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-7 FPGA - XMC 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - XMC Customer Information
RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR
Model 7150
Virtex-5 FPGAs
The Model 7150 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factoryshipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters,
Features
Complete software radio interface solution VITA 42.0 XMC compatible with switched fabric interfaces Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Clock/Sync Bus
TTL In
LVPECL Bus
XTL OSC To All Sections Control/ PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T, LX155T or FX100T
LVDS GTP GTP GTP
Timing Bus
Status
4X
GTP
4X
4X
32
32
64
4X
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7150
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs P4 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 7150 complies with the VITA 42.0 XMC specification for carrier boards. This emerging standard provides serial data links with up to 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7150 achieves up to 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.
PCI-X Interface
The Model 7150 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66, 100 MHz are supported.
Ordering Information
Model 7150 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs PMC/XMC
Options: -104 FPGA I/O through the P4 connector -5xx XMC interface
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7151
256 channels of DDC Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization
The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.
CH 1 RF In
RF XFORMR
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D
CH 2
M U X DIGITAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024
CH 3 CH 4
I+Q
M U X
FIFO 2
PCI-X BUS Sample Clock In PPS In TTL In LVPECL Bus Timing Bus Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 4: CH 193-256 DEC: 128 - 1024
CH 3 I+Q
M U X
FIFO 3
CH 4 I+Q
M U X
FIFO 4
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7151
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 133 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: Standard: 0 to 50 C L2 Extended Temp (Option -702): 20 to 65 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
PCI-X Interface
The Model 7151 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 133 MHz are supported.
Ordering Information
Model 7151 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7152
Features
32 channels of DDC in four banks of 8 channels Four 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all 32 channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Common decimation factor within each DDC bank Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multimodule synchronization
CH 1 RF In
RF XFORMR
CH 1 I+Q
M U X F I F 0 1 F I F 0 2
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHOLD DETECTORS
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D
CH 2
M U X
CH 3 CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 3: CH 17-24 DEC: 16 - 8192
I+Q
POWER METER & THRESHOLD DETECTORS
TTL In
CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 4: CH 25-32 DEC: 16 - 8192
CH 4
M U X
LVPECL Bus
I+Q
POWER METER & THRESHOLD DETECTORS
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7152
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
PCI-X Interface
The Model 7152 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Ordering Information
Model 7152 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7153
Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization
The front end accepts four full scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling to four Texas Instruments ADS5485 200 MHz, 16-bit A/Ds. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.
Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.
SUM IN SUM OUT 4X 4X P15 XMC
F I F 0 1 F I F 0 2
CH 1 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER
CH 2 RF In
RF XFORMR
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
I+Q
POWER METER & THRESHOLD DETECTORS
CH 4 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
PCI-X NTERFACE
XILINX XC5VLX30T
CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7153
XMC Interface
The Model 7153 complies with the VITA 42.0 XMC specification. This standard provides serial data links between the XMC module and the carrier board. The 7153 beamformer architecture uses this link to create a board-to-board summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.
PCI-X Interface
The Model 7153 includes an industrystandard PCI-X interface. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*
GAIN
I Q
I Q
I
Q
I
Q
AURORA PORT
F om P evious Board
P15
GAIN
I
Q
I
Q
I
Q
I
Q
I Q
I Q
I Q
GAIN
(DECIMATION: 2-256)*
I Q
I Q
I
Q
I
Q
AURORA PORT
To Next Boa d
GAIN
P15 I Q
(DECIMATION: 2-256)*
I Q
I Q
I Q
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7153
Ordering Information
Model 7153 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - PMC/XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7156
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
General Information
Model 7156 is a dual-channel, highspeed data converter suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters, two Virtex-5 FPGAs and two banks of DDR2 SDRAM. The Model 7156 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces.
Virtex-5 FPGAs
The Model 7156 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
Features
Complete software radio interface solution Two 400 MHz, 14-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O on P14
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Tr g TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
Timing Bus
VCXO
Control/ Status
32 DDR2 SDRAM 512 MB
8 64 FLASH 32 MB 4X
GTP
4X
4X
32
32
64
4X
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7156
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds the P14 PMC connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the P14 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 7156 complies with the VITA 42.0 XMC specification for carrier boards. This standard provides, among others, for a 4X link with a 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7156 achieves 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
The Model 7156 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Options: -104 FPGA I/O through the P14 connector -5xx XMC interface
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7158
Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
General Information
Model 7158 is a dual-channel, highspeed data converter suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters, two Virtex-5 FPGAs and two banks of DDR2 SDRAM. The Model 7158 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces.
Virtex-5 FPGAs
The Model 7158 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
Features
Complete software radio interface solution Two 500 MHz, 12-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O on P14
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample C k Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
Timing Bus
VCXO
Control/ Status
32 DDR2 SDRAM 256 MB
8 64 FLASH 32 MB 4X
GTP
4X
4X
32
32
64
4X
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7158
Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds the P14 PMC connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the P14 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 7158 complies with the VITA 42.0 XMC specification for carrier boards. This standard provides, among others, for a 4X link with a 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7158 achieves 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.
Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Ordering Information
Model 7158 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
PCI-X Interface
The Model 7158 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Options: -104 FPGA I/O through the P14 connector -140 1 GB DDR2 SDRAM -5xx XMC interface
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - XMC
General Information
Model 71620 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71620 includes general purpose and gigabit serial connectors for application-specific I/O . nization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
8X
4X
4X
40
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71620
A/D Acquisition IP Modules
The 71620 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - XMC
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
Memory Resources
The 71620 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
to D/A D/A loopback
TEST SIGNAL GENERATOR
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - XMC
modules DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 71620 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71620 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.
Ordering Information
Model 71620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
General Information
Model 71621 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71621 includes a general purpose connector for application-specific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
8X
4X
4X
40
Sum to next board x8 PCIe Aurora Gigabit Serial P16 XMC FPGA GPIO (option 104) P14 PMC
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71621
A/D Acquisition IP Modules
The 71621 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 71621 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
Memory Resources
The 71621 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71621 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71621 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beamforming accross multiple modules.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Ordering Information
Model 71621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA XMC
Options: -062 -064 -104 -150 XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71630
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF Out
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Gate In Sync In
VCXO
GTX
LVDS
16
16
16
16
16 Config FLASH 64 MB
8X
4X
4X
40
Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71630
The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.
Memory Resources
The 71630 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROLLER MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71630
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be locked to an external 4 to 200 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock
Ordering Information
Model 71630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
General Information
Model 71640 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71640 includes optional general purpose and gigabit serial connectors for application-specific I/O. and a PCIe interface complete the factoryinstalled functions and enable the 71640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multimodule synchronization PCI Express Gen. 2 interface x8 wide Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Sync Bus
GTX
LVDS
16 Config FLASH 64 MB
8X
4X
4X
40
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 71640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 71640s can be synchronized using the Cobalt high speed sync module to drive the sync bus.
Memory Resources
The 71640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71640 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 5 GHz bit clock. With dual XMC connectors, the 71640 supports x8 PCIe on the first XMC connector leaving the optional second connector free to support user-installed transfer protocols specific to the target application.
from A/D
from A/D
TEST SIGNAL GENERATOR
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE
MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 8X PCIe Gigabit Serial I/O 4X 4X 40 to Mem Bank 3 to Mem Bank 4
FPGA GPIO
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
PCI Express Interface
The Model 71640 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock
Ordering Information
Model 71640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - XMC
General Information
Model 71641 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, Model 71641 includes an optional connection to the Virtex-6 FPGA for custom I/O . controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 71641 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
Features
Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds Programmable one- or twochannel DDC (Digital Downconverter) 2 GB of DDR3 SDRAM Sync bus for multimodule synchronization PCI Express Gen. 2 interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Sync Bus
16 Config FLASH 64 MB
8X
40
x8 PCIe
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71641
A/D Acquisition IP Module
The 71641 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - XMC
DDC IP Cores
Within the FPGA is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the A/D at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the A/Ds 1.8 GHz two-channel operation . In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 16-bit I + 16-bit Q samples at a rate of s/N.
Memory Resources
The 71641 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.
from A/D
from A/D
DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE MEMORY CONTROLLER A/D ACQUISITION IP MODULE PCIe INTERFACE to MEM CONTROL
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
8X PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - XMC
PCI Express Interface
The Model 71641 complies with the VITA 42.3 XMC specification and includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. Sample Clock Sources: Front panel SSMC connector Sync Bus: Multipin front panel connector, includes gate, reset, and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include trigger and gate Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
Ordering Information
Model 71641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D with Wideband DDC, Virtex-6 FPGA - XMC
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T LVDS FPGA I/O through P14 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC
General Information
Model 71650 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes two A/Ds, one DUC (Digital Upconverter), two D/As, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71650 includes optional general-purpose and gigabit serial card connectors for application-specific I/O. memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 71650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
VCXO
Timing Bus
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
8X
4X
4X
40
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC
A/D Converter Stage
Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
The front end accepts two full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.
Memory Resources
The 71650 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
from A/D Ch 1
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC
modules DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 71650 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71650 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.
Ordering Information
Model 71650 Description Two 500 MHz A/Ds, one DUC, Two 800 MHz D/As with Virtex-6 FPGA - XMC
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240 FPGA XC6VSX315 FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
General Information
Model 71651 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes two A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71651 includes a general purpose connector for application-specific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
VCXO
Timing Bus
GTX
LVDS
16 Config FLASH 64 MB
4X
40
Sum to next board Aurora Gigabit Serial P16 XMC FPGA GPIO (option 104) P14 PMC
Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71651
A/D Acquisition IP Modules
The 71651 features two A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 71651 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average
from A/D Ch 1
to D/A
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
Memory Resources
The 71651 architecture supports up to three independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71651 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71651 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beamforming accross multiple modules.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Ordering Information
Model 71651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA XMC
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71660
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
8X
4X
4X
40
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71660
Memory Resources
The 71660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71660 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71660
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71660
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock
Ordering Information
Model 71660 Options: -062 -064 -104 -105 -150 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - XMC
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC
General Information
Model 71661 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs (digital downconverters), it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71661 includes a general purpose connector for application-specific I/O. for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71661 to operate as a complete turnkey solution without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
LVDS
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
8X x8 PCIe
4X
4X
40
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71661
A/D Acquisition IP Modules
The 71661 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 71661 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536
INPUT MULTIPLEXER
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC
controlled crystal oscillator. In this mode,
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 71661 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71661 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beamforming accross multiple boards.
Memory Resources
The 71661 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Ordering Information
Model 71661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC
General Information
Model 71662 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. interface complete the factory-installed functions and enable the 71662 to operate as a complete turnkey solution without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable serial gigabit interfaces Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
LVDS
16 Config FLASH 64 MB
8X
4X
4X
40
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71662
A/D Acquisition IP Modules
The 71662 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC
available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.
Memory Resources
The 71662 architecture supports up to four independent memory banks which can be configured with DDR3 SDRAM.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the
INPUT MULTIPLEXER
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC
Each DDR3 SDRAM bank can be up to
512 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 71662 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71662 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation
Ordering Information
Model 71662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71670
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF Out
RF Out
RF Out
RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO
GTX
LVDS
16 Config FLASH 64 MB
8X
4X
4X
40
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71670
Memory Resources
The 71670 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71670 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 3.125 GHz bit clock. With dual XMC connectors, the 71670 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.
16 to D/A Ch 3 & 4
to D/A Ch 1 & 2
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71670
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference
Ordering Information
Model 71670 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
General Information
Model 71671 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O . SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 71671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF Out
RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO
GTX
LVDS
16 Config FLASH 64 MB
8X
4X
4X
40
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
Digital Upconverter and D/A Stage
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 71671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. SSMC connector. This clock can be used directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A pair of front panel Sync connectors allows multiple modules to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave 71671 module. For larger systems, the Pentek Model 7191 Cobalt Synchronizer can drive multiple 71671s enabling large, multichannel synchronous configurations.
Memory Resources
The 71671 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
16 to D/A Ch 3 & 4
to D/A Ch 1 & 2
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
XMC Interface
The Model 71671 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 3.125 GHz bit clock. With dual XMC connectors, the 71671 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as two 4X or one 8X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15
Ordering Information
Model 71671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71690
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds digitize the I + Q signals synchronously Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Ref Out GC
12-BIT D/A
Sample Clk / Reference Clk In Trigger 1 Trigger 2 TIMING GENERATOR Clock / Sync / Gate / PPS
Control
I 200 MHz 16-BIT A/D Q 200 MHz 16-BIT A/D
TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B
16
16
IC
2
Timing Bus
VCXO
GTX
LVDS
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
8X
4X
4X
40
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71690
Memory Resources
The 71690 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71690
XMC Interface
The Model 71690 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71690 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.
Ordering Information
Model 71690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71720
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - XMC
General Information
Model 71720 is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71720 includes general-purpose and gigabit-serial connectors for application-specific I/O . IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71720 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 VITA 42.0 XMC compatible with switched-fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
LVDS
CONFIG FLASH 1 GB
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71720
A/D Acquisition IP Modules
The 71720 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - XMC
GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA-PCIe configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a PCIe target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCIe discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCIe interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCIe interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded through PCIe as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCIe configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
48
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71720
Memory Resources
The 71720 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factoryinstalled functions, custom userinstalled IP within the FPGA can take advantage of the memories for many other purposes.
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - XMC
When operating as a DUC, it interpolates
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs the PMC P14 connector with 24 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.
XMC Interface
The Model 71720 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 GB/sec per lane. With dual XMC connectors, the 71720 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.
Ordering Information
Model 71720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA XMC XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 71760
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Advanced reconfigurability features VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
LVDS
CONFIG FLASH 1 GB
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71760
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
48
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 71760
Memory Resources
The 71760 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
XMC Interface
The Model 71760 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 Gb/sec per lane. With dual XMC connectors, the 71760 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.
Ordering Information
Model 71760 Options: -073 -076 -104 -105 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - XMC
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
DESCRIPTION
Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 6U/3U cPCI 256- or 512-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - 6U/3U cPCI 32- or 64-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - 6U/3U cPCI 4/8-Channel DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - 6U/3U cPCI Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U/3U cPCI Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U/3U cPCI 3/6-Ch 200 MHz A/D, 2/4-Ch 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 3/6-Ch 200 MHz A/D, DDCs, DUC, 2/4-Ch. 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 1 GHz A/D and 1/2-Ch 1 GHz D/A, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 3.6 GHz or 2/4-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 3.6 GHz or 2/4-Ch 1.8 GHz 12-bit A/D, DDC, Virtex-6 FPGA - 6U/3U cPCI 2/4 500 MHz A/Ds, 1/2 DUCs, 2/4 800 MHz D/As, Virtex-6 FPGA - 6U/3U cPCI 2/4-Ch 500 MHz A/D w. DDC, DUC w. 2/4-Ch 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 4/8-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 200 MHz A/D with DDCs, Beamformer and Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 200 MHz A/D with 32/64-Ch DDC and Virtex-6 FPGA - 6U/3U cPCI 4/8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 1.25 GHz D/A with DUC, Extend. Interpol. and Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch L-Band RF Tuner, 2/4-Ch 200 MHz A/D, Virtex-6 FPGA - 6U/3U cPCI 3/6-Ch 200 MHz A/D, 2/4-Ch 800 MHz D/A, Virtex-67FPGA - 6U/3U cPCI 4/8-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 6U/3U cPCI Customer Information
RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR
Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - cPCI
General Information
Models 7250 and 7350 are cPCI Quad 200 MHz A/Ds. They consist of one Model 7150 Quad A/D mounted on a cPCI carrier. The Model 7250 is a 6U cPCI board, while the Model 7350 is a 3U cPCI board. Model 7250D is the same as the Model 7250, except it contains two 7150s rather than one. different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Models 7250 and 7350 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs the J3 connector (Model 7250) or the J2 connector (Model 7350) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O. With Model 7250D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory-shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of
Model 7350
Model 7250D
Features
Complete software radio interface solutions Four or eight 200 MHz, 16-bit A/Ds Up to 1 or 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D
TTL In
Clock/Sync Bus
LVPECL Bus
XTL OSC
To All Sections
Timing Bus
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T or LX155T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X LVDS
PCI X INTERFACE
64
Model 7250 and 7350 Block Diagram Model 7250D doubles all resources except the PCI Bridge
32
PCI-X BUS
Model 7250 uses J3 Model 7350 uses J2 Model 7250D uses J3 and J5
PCI BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - cPCI
Clocking and Synchronization
The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to two slave 7250Ds and three slave 7350s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.
Specifications
Model 7250 or Model 7350: 4 A/Ds Model 7250D: 8 A/Ds Model 7250D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XCV5FX100T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Memory DDR2 SDRAM: Up to 2 GB in four banks PCI Interface PCI Bus: 32- or 64-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.
PCI Interface
Both Models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, and 66 MHz are supported.
Ordering Information
Model 7250 Description Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs 6U cPCI Octal 200 MHz, 16-bit A/D with four Virtex-5 FPGAs 6U cPCI Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs 3U cPCI FPGA I/O through cPCI J3 for 7250 or J2 for 7350; cPCI J3 and J5 for 7250D
7250D
7350
Options: -104
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7351
Model 7251D
Features
256 or 512 channels of DDC Four or eight 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization
Model 7251 and 7351 Block Diagram Model 7251D doubles all resources except the PCI Bridge
CH 1 RF In
RF XFORMR 200 MHz 16-bit A D
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A D
CH 2
M U X D G TAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024
CH 3 CH 4
I+Q
M U X
FIFO 2
PCI-X BUS CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 4: CH 193-256 DEC: 128 - 1024
CH 3
M U X D G TAL DOWNCONVERTER BANK 3: CH 129-192 DEC: 128 - 1024
CH 2 CH 3 CH 4
I+Q
M U X
FIFO 3
TTL In
CH 4 I+Q
M U X
FIFO 4
LVPECL Bus
XTAL OSC
XILINX XC5VSX95T
Timing Bus
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Specifications
Model 7251 or 7351: 4 A/Ds, 256-channel DDC Model 7251D: 8 A/Ds, 512-channel DDC Model 7251D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI Bus: 32 or 64 bits at 66 MHz and 32 or 64 bits at 33 MHz DMA: 8 channel demand-mode and chaining controller Local Bus: 64 bits at 33, 66 and 100 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: standard 6U cPCI board
PCI Interface
Both models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.
Ordering Information
Model 7251 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - 6U cPCI 512-Channel DDC with eight 200 MHz, 16-bit A/Ds - 6U cPCI 256-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U cPCI
7251D
7351
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7352
Model 7252D
Features
32 or 64-channel DDC with four or eight banks of 8 channels Four or eight 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths: 20 kHz to 10 MHz Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multiboard synchronization
Model 7252 and 7352 Block Diagram Model 7252D doubles all resources except the PCI Bridge
CH 1 RF In
RF XFORMR
CH 1 I+Q
M U X F I F 0 1 F I F 0 2
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHO D DETECTORS
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A D
CH 2
M U X
CH 3 CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
TTL In
PCI-TO-PCI BRIDGE
CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
LVPECL Bus
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Specifications
Model 7252 or 7352: 4 A/Ds, 32-channel DDC Model 7252D: 8 A/Ds, 64-channel DDC Model 7252D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI Bus: 32 or 64 bits at 66 MHz and 32 or 64 bits at 33 MHz DMA: 8 channel demand-mode and chaining controller Local Bus: 64 bits at 33, 66 and 100 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
PCI Interface
Both models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.
Ordering Information
Model 7252 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - 6U cPCI 64-Channel DDC with eight 200 MHz, 16-bit A/Ds - 6U cPCI 32-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U cPCI
7252D
7352
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7353
Model 7253D
Features
Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel 6U and 3U cPCI boards 2 or 4 (Models 7253 and 7353) and 4 or 8 (Model 7753D) channels of DDC Four or eight 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 LVPECL clock/sync bus for multiboard synchronization
Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the
Model 7253 and 7353 Block Diagram Model 7253D doubles all resources except the PCI Bridge
CH 1 RF In
RF XFORMR 200 MHz 16-bit A D
CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER
4X 4X P15 XMC
CH 2 RF In
RF XFORMR
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
I+Q
POWER METER & THRESHO D DETECTORS
CH 4 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
POWER METER & THRESHO D DETECTORS
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
PCI BUS
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
PCI-X INTERFACE
XIL NX XC5VLX30T
PCI-TO-PCI BRIDGE
CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
XIL NX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Beamformer
In addition to the A/Ds and DDCs, these Models include essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI bus. For larger systems, multiple Models can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.
XMC Interface
For large systems, multiple 7253s, 7353s or 7253Ds can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.
PCI Interface
These models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.
PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*
GA N
I Q
I Q
I
Q
I
Q
DIGITAL DOWNCONVERTER A
AURORA PORT
P15
GA N
I
Q
I
Q
I
Q
I
Q
DIGITAL DOWNCONVERTER B
I Q
I Q
I Q
GA N
I
Q
I
Q
I
Q
(DECIMATION: 2-256)*
DIGITAL DOWNCONVERTER C
AURORA PORT
To Next Board
GA N
P15 I
Q
(DECIMATION: 2-256)*
I Q
I Q
I
Q
DIGITAL DOWNCONVERTER D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Ordering Information
Model 7253 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - 6U cPCI 8-Channel DDC with eight 200 MHz, 16-bit A/Ds and Beamformers - 6U cPCI 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - 3U cPCI
7253D
7353
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
General Information
Models 7256 and 7356 are cPCI boards that include two 400 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. They consist of one Model 7156 PMC module mounted on a cPCI carrier. The Model 7652 is a 6U cPCI board, while the Model 7356 is a 3U cPCI board. Model 7256D is the same as the Model 7652, except it contains two 7156s rather than one.
Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
Features
Complete software radio interface solution Two or four 400 MHz, 14-bit A/Ds One or two digital upconverters Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
Timing Bus
VCXO
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32
4X
Model 7256 and 7356 Block Diagram Model 7256D doubles all resources except the PCI Bridge
PCI X INTERFACE
64
32
PCI-X BUS
Model 7256 uses J3 Model 7356 uses J2 Model 7256D uses J3 and J5
PCI-TO PC BRIDGE
PCI BUS
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs the J3 connector (Model 7256) or the J2 connector (Model 7356) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O. With Model 7256D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs to the interface FPGA.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4) Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters (4) Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs (4) Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Environmental Specifications Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
PCI Interface
All Models include an industrystandard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.
7256D
Up to four independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
7356
Specifications
Models 7256 or 7356: Dual version Model 7256D: Quad version Model 7256D shown in the Specifications Front Panel Analog Signal Inputs (4) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB
Options: -104 FPGA I/O through cPCI J3 for 7256 or J2 for 7356; cPCI J3 and J5 for 7256D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
General Information
Models 7258 and 7358 are cPCI boards that include two or four 500 MHz A/Ds and 800 MHz D/As and Virtex-5 FPGAs. They consist of one Model 7158 PMC module mounted on a cPCI carrier. The Model 7258 is a 6U cPCI board, while the Model 7358 is a 3U cPCI board. Model 7258D is the same as the Model 7258, except it contains two 7158s rather than one.
Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
Features
Complete software radio interface solution Two or four 500 MHz, 12-bit A/Ds One or two digital upconverters Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
Timing Bus
VCXO
Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 256 MB
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32
4X
Model 7258 and 7358 Block Diagram Model 7258D doubles all resources except the PCI Bridge
PCI X INTERFACE
64
32
PCI-X BUS
Model 7258 uses J3 Model 7358 uses J2 Model 7258D uses J3 and J5
PCI-TO PC BRIDGE
PCI BUS
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs the J3 connector (Model 7258) or the J2 connector (Model 7358) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O. With Model 7258D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs to the interface FPGA.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4) Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters (4) Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs (4) Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Environmental Specifications Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board
PCI Interface
All Models include an industrystandard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.
Ordering Information
Model 7258 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U cPCI
Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
7258D
7358
Options: -104 FPGA I/O through cPCI J3 for 7258 or J2 for 7358; cPCI J3 and J5 for 7258D -140 1 GB DDR2 SDRAM, Models 7258 and 7358; 2 GB DDR2 SDRAM, Model 7258D
Specifications
Models 7258 or 7358: Dual version Model 7258D: Quad version Model 7258D shown in the Specifications Front Panel Analog Signal Inputs (4) Input Type: Transformer-coupled, front panel female SMC connectors
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
General Information
Models 72620, 73620 and 74620 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71620 XMC modules mounted on a cPCI carrier board. Model 72620 is a 6U cPCI board while the Model 73620 is a 3U cPCI board; both are equipped with one Model 71620 XMC. Model 74620 is a 6U cPCI board with two XMC modules rather than one. These models include three or sixA/Ds, one or two DUCs, two or four D/As and four or eight banks of memory. clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three or six 200 MHz 16-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72620 Model 74620 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
x4 PCIe
4X
GTX
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts three or six fullscale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three or six Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory.
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
Each QDRII+ SRAM bank can be up
to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73620; J3 connector, Model 72620; J3 and J5 connectors, Model 74620 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73620: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73620: 32 bits only.
Specifications
Model 72620 or Model 73620: 3 A/Ds, 1 DUC, 2 D/As Model 74620: 6 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Ordering Information
Model 72620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 6U cPCI 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 3U cPCI 6-Channel 200 MHz A/D and 4-Channel 800 MHz D/A and two Virtex-6 FPGAs - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73620; J3 connector, Model 72620; J3 and J5 connectors, Model 74620 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73620
74620
-150
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
General Information
Models 72621, 73621 and 74621 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71621 XMC modules mounted on a cPCI carrier board. Model 72621 is a 6U cPCI board while the Model 73621 is a 3U cPCI board; both are equipped with one Model 71621 XMC. Model 74621 is a 6U cPCI board with two XMC modules rather than one. These models include three or six A/Ds, three or six multiband DDCs, one ot two DUCs, two or four D/As and four or eight banks of memory. ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three or six 200 MHz 16-bit A/Ds Three or six multiband DDCs (digital downconverters) One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
4X
4X
x4 PCIe
4X
GTX
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
4X
J3
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple boards can be chained together via the built-in Xilinx Aurora gigabit serial interfaces through the J3 and J5 connectors. This allows summation across channels on multiple boards.
Modules
These models feature three or six A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
Beamformer IP Cores
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers.
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC.
MEMORY CONTROL
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
4X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts three or six analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three or six Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73621: 32 bits only.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
Specifications
Model 72621 or Model 73621: 3 A/Ds, 3 DDCs, 1 DUC, 2 D/As Model 74621: 6 A/Ds, 6 DDCs, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (3 or 6) Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolators (1 or 2) Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformers (1 or 2) Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via J3 connector using Aurora protocol; via J3 and J5 for Model 74621 Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs (2 or 4) Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73621: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Ordering Information
Model 72621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 6U cPCI 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 3U cPCI 6-Channel 200 MHz A/D with DDCs, DUCs with 4-Channel 800 MHz D/A, and two Virtex-6 FPGAs 6U cPCI XC6VLX240T XC6VSX315T Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73621
74621
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/A with Virtex-6 FPGA - cPCI
General Information
Models 72630, 73630 and 74630 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71630 XMC modules mounted on a cPCI carrier board. Model 72630 is a 6U cPCI board while the Model 73630 is a 3U cPCI board; both are equipped with one Model 71630 XMC. Model 74630 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 1 GHz A/D and D/A converters and four or eight banks of memory clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these modles to operate as complete turnkey solutions, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Model 74630
Model 73630
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One or two 1 GHz 12-bit A/D One or two 1 GHz 16-bit D/A Up to 2 or 4 GB of DDR3 SDRAM; or: 16 MB or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL sync bus for multimodule synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72630 Model 74630 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF Out
RF XFORMR
RF XFORMR
Gate In Sync In
GTX
16
16
16
16
16 Config FLASH 64 MB
40
x4 PCIe
4X
GTX
40
Memory Banks 1 & 2 DDR3 option 155 PCIe QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB
J2
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/A with Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts one or two analog HF or IF input on front panel SSMC connectors with transformer coupling into one or two Texas Instruments ADS5400 1 GHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. Two or four front panel 7-pin LVPECL Sync connectors allow multiple boards to be synchronized. One connector for the A/D and one for the D/A provide sync and gate signals.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROLLER MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/A with Virtex-6 FPGA - cPCI
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73630: 32 bits only. External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus (1 or 2): 7-pin connectors, LVPECL bus for sync and gate, one A/D connector and one D/A connector External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73630; J3 connector, Model 72630; J3 and J5 connectors, Model 74630 Memory Banks (1 or 2) Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73630: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Specifications
Model 72630 or Model 73630: 1 A/D, 1 D/A Model 74630: 2 A/Ds, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be locked to an external 4 to 200 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock
Ordering Information
Model 72630 73630 74630 Options: -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73630; J3 connector, Model 72630; J3 and J5 connectors, Model 74630 -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required -002* -062 -064 -104 Description 1 GHz A/D and D/A, Virtex-6 FPGA - 6U cPCI 1 GHz A/D and D/A, Virtex-6 FPGA - 3U cPCI Two 1 GHz A/D and D/A, Virtex-6 FPGA - 6U cPCI
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - cPCI
General Information
Models 72640, 73640 and 74640 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71640 XMC modules mounted on a cPCI carrier board. Model 72640 is a 6U cPCI board while the Model 73640 is a 3U cPCI board; both are equipped with one Model 71640 XMC. Model 74640 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit A/D converters and four or eight banks of memory. generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Model 74640
Model 73640
Features
Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One or two 1-channel mode with 3.6 GHz, 12-bit A/Ds Two or four 2-channel mode with 1.8 GHz, 12-bit A/Ds 2 or 4 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72640 Model 74640 doubles all resources except the PCI-to-PCI Bridge
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF In
RF XFORMR
RF XFORMR
Sync Bus
VIRTEX-6 FPGA LX130T, LX240T or SX315T MODEL 73640 INTERFACES ONLY VIRTEX-6 FPGA
LVDS LVDS
GTX
16 Config FLASH 64 MB
40
GTX
x4 PCIe
4X
40
PCIe
J2
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing these models to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple boards can be synchronized using the Cobalt high speed sync board to drive the sync bus.
Memory Resources
The Cobalt architecture supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73640: 32 bits only.
from A/D
from A/D
TEST SIGNAL GENERATOR
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE
MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 4X PCIe 40 FPGA I/O to Mem Bank 3 to Mem Bank 4
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - cPCI
Specifications
Model 72640 or Model 73640: One A/D Model 74640: Two A/Ds Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources (1 or 2) Front panel SSMC connector Sync Bus (1 or 2) Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 Memory Banks (1 or 2) Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73640: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Ordering Information
Model 72640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U cPCI 2-Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI
73640
74640
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS I/O between the FPGA and J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - cPCI
General Information
Models 72641, 73641 and 74641 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71641 XMC modules mounted on a cPCI carrier board. Model 72641 is a 6U cPCI board while the Model 73641 is a 3U cPCI board; both are equipped with one Model 71641 XMC. Model 74641 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit A/D converters and four or eight banks of memory. and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73641; J3 connector, Model 72641; J3 and J5 connectors, Model 74641.
Model 74641
Model 73641
Features
Ideal radar and software radio interface solution One or two 1-channel mode with 3.6 GHz, 12-bit A/Ds Two or four 2-channel mode with 1.8 GHz, 12-bit A/Ds Programmable one- or twochannel DDC (Digital Downconverter) 2 or 4 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72641 Model 74641 doubles all resources except the PCI-to-PCI Bridge
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF In
RF XFORMR
RF XFORMR
Sync Bus
GTX
16 Config FLASH 64 MB
40
GTX
x4 PCIe
4X
40
PCIe
J2
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - cPCI
DDC IP Cores
Within the FPGA is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the A/D at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the A/Ds 1.8 GHz two-channel operation . In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 16-bit I + 16-bit Q samples at a rate of s/N.
Memory Resources
The Cobalt architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.
from A/D
from A/D
DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE MEMORY CONTROLLER A/D ACQUISITION IP MODULE PCIe INTERFACE to MEM CONTROL
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
4X 4x PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - cPCI
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73641: 32 bits only. Sample Clock Sources (1 or 2) Front panel SSMC connector Sync Bus (1 or 2) Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 Memory Banks (1 or 2) Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73641: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Specifications
Model 72641 or Model 73641: One A/D Model 74641: Two A/Ds Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converters (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters (2 or 4) Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
Ordering Information
Model 72641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 6U cPCI 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 3U cPCI 2-Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 6U cPCI
73641
74641
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T LVDS I/O between the FPGA and J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
2- or 4-Channel 500 MHz A/D, DUC with 2-or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
General Information
Models 72650, 73650 and 74650 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71650 XMC modules mounted on a cPCI carrier board. Model 72650 is a 6U cPCI board while the Model 73650 is a 3U cPCI board; both are equipped with one Model 71650 XMC. Model 74650 is a 6U cPCI board with two XMC modules rather than one. These models include two or four A/Ds, one or two DUCs, two or four D/As and four banks of memory. clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two or four 500 MHz 12-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72650 Model 74650 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
VCXO
Timing Bus
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
x4 PCIe
4X
GTX
QDRII+ option 150 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
J2
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
2- or 4-Channel 500 MHz A/D, DUC with 2-or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts two or four full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two or four Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
2- or 4-Channel 500 MHz A/D, DUC with 2-or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin front panel connector LVPECL bus includes, clock/sync/ gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73650; J3 connector, Model 72650; J3 and J5 connectors, Model 74650 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73650: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73650: 32 bits only.
73650
74650
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73650; J3 connector, Model 72650; J3 and J5 connectors, Model 74650 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Models 72650 and 73650: 2 A/Ds, 1 DUC, 2 D/As Model 74650: 4 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) (2 or 4) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) (2 or 4) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
2 or 4-Channel 500 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
General Information
Models 72651, 73651 and 74651 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71651 XMC modules mounted on a cPCI carrier board. Model 72651 is a 6U cPCI board while the Model 73651 is a 3U cPCI board; both are equipped with one Model 71651 XMC. Model 74651 is a 6U cPCI board with two XMC modules rather than one. These models include two or four A/Ds, two or four multiband DDCs, one ot two DUCs, two or four D/As and three or six banks of memory. ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two or four 500 MHz 12-bit A/Ds Two or four multiband DDCs (digital downconverters) Two or four 800 MHz 16-bit D/As One or two DUCs (digital upconverters) One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or 16 or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization
RF In
RF In
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
VCXO
Timing Bus
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
4X
4X
4X
PCIe to PCI BRIDGE
GTX
4X
next board
J3
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
2 or 4-Channel 500 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
frequency. Each DDC can have its own unique decimation setting, supporting as many as two or four different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple models can be chained together via a built-in Xilinx Aurora gigabit serial interface through the dual 4X serial connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average
from A/D Ch 1
to D/A
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MEMORY CONTROL
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
4X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
2 or 4-Channel 500 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts two or four analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two or four Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The Cobalt architecture supports up to three or six independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boardss DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73651: 32 bits only.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
2 or 4-Channel 500 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
Specifications
Model 72651 or Model 73651: 2 A/Ds, 2 DDCs, 1 DUC, 2 D/As Model 74651: 4 A/Ds, 4 DDCs, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) (2 or 4) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (Option -014) (2 or 4) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters (2 or 4) Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolators (1 or 2) Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformers (1 or 2) Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via a dual 4X connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs (2 or 4) Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/ A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Memory (1 or 2) Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73651: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Ordering Information
Model 72651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 6U cPCI 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 3U cPCI 4-Channel 500 MHz A/D with DDCs, DUCs with 4-Channel 800 MHz D/A, and two Virtex-6 FPGAs 6U cPCI
73651
74651
Options: 002* -014 -062 -064 -150 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Model 74660
Model 73660
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds Up to 2 or 4 GB of DDR3 SDRAM; or: 32 or 64 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72660 Model 74660 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
4X
PCIe to PCI BRIDGE
GTX
QDRII+ option 150 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
J2
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73660: 32 bits only.
from A/D Ch 3 from A/D Ch 4
from A/D Ch 1
from A/D Ch 2
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Ordering Information
Model 72660 Description 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA 6U cPCI 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA 3U cPCI 8-Channel 200 MHz 16-bit A/D with two Virtex-6 FPGAs - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73660; J3 connector, Model 72660; J3 and J5 connectors, Model 74660 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73660
74660
-150
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
4- or 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - cPCI
General Information
Models 72661, 73661 and 74661 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71662 XMC modules mounted on a cPCI carrier board. Model 72661 is a 6U cPCI board while the Model 73661 is a 3U cPCI board; both are equipped with one Model 71661 XMC. Model 74661 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds, four or eight multiband DDCs and four or eight banks of memory. QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory- installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Model 74661
Model 73661
Block Diagram, Model 72661 Model 74661 doubles all resources except the PCI-to-PCI Bridge
RF In
RF In
RF In
RF In
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds Four or eight multiband DDCs (digital downconverters) One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
4X
4X
x4 PCIe
4X
GTX
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
4X
J3
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4- or 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - cPCI
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Cores
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation
from A/D Ch 1
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536
INPUT MULTIPLEXER
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
4X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4- or 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - cPCI
controlled crystal oscillator. In this mode,
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation Beamformers (1 or 2) Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73661: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73661: 32 bits only.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Ordering Information
Model 72661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 6U cPCI 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U cPCI 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGAs - 6U cPCI XC6VLX240T XC6VSX315T Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Model 72661 or Model 73661: 4 A/Ds Model 74660: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (4 or 8) Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients
73661
74661
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
4- or 8-Channel 200 MHz A/D with 32- or 64-Channel DDC and Virtex-6 FPGA - cPCI
General Information
Models 72662, 73662 and 74662 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71662 XMC modules mounted on a cPCI carrier board. Model 72662 is a 6U cPCI board while the Model 73662 is a 3U cPCI board; both are equipped with one Model 71662 XMC. Model 74662 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds, 32 or 64 multiband DDCs and four or eight banks of memory. trigger functions, a test signal generator, voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Model 74662
Model 73662
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds 32 or 64 channels of multiband DDCs (digital downconverters) Up to 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72662 Model 74662 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
VIRTEX-6 FPGA
LVDS
40
GTX
x4 PCIe
4X
40
PCIe
J2
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4- or 8-Channel 200 MHz A/D with 32- or 64-Channel DDC and Virtex-6 FPGA - cPCI
of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with DDR3 SDRAM.
from A/D Ch 2 from A/D Ch 3 from A/D Ch 4
INPUT MULTIPLEXER
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps
DIGITAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 TO 8192
.
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4- or 8-Channel 200 MHz A/D with 32- or 64-Channel DDC and Virtex-6 FPGA - cPCI
Each DDR3 SDRAM bank can be up to
512 MB deep and is an integral part of the Boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73662; J3 connector, Model 72662; J3 and J5 connectors, Model 74662 MemoryBanks (1 or 2) Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73662: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73662: 32 bits only.
Specifications
Model 72662 or Model 73662: 4 A/Ds, 32 DDCs Model 74660: 8 A/Ds, 64 DDCs Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (32 or 64) Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation
Ordering Information
Model 72662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 6U cPCI 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U cPCI 8-Ch 200 MHz A/D with 64-Ch DDC and Virtex-6 FPGA - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73662; J3 connector, Model 72662; J3 and J5 connectors, Model 74662 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
73662
74662
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 1.25 GHz 16-bit D/As Four or eight digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-or Quad Sync clock/ sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72670 Model 74670 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Trigger In
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO
GTX
16 Config FLASH 64 MB
40
x4 PCIe
4X
GTX
Memory Banks 1 & 2 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe
J2
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Memory Resources
The architecture of these models supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths
16 to D/A Ch 3 & 4
to D/A Ch 1 & 2
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Specifications
Models 72670 and 73670: 4-Channel DUC, 4-channel D/A Model 74670: 8-Channel DUC, 4-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference
Ordering Information
Model 72670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 6U cPCI 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 3U cPCI 8-Channel 1.25 GHz D/A with Virtex-6 FPGA - 6U cPCI
73670
74670
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73670; J3 connector, Model 72670; J3 and J5 connectors, Model 74670 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
4- or 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - cPCI
General Information
Models 72671, 73671 and 74671 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71671 XMC modules mounted on a cPCI carrier board. Model 72671 is a 6U cPCI board while the Model 73671 is a 3U cPCI board; both are equipped with one Model 71671 XMC. Model 74671 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight D/As with a wide range of programmable interpolation factors, four or eight DUCs, and four or eight banks of memory. modules for DDR3 SDRAM memories, controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 1.25 GHz 16-bit D/As Four or eight digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-or Quad Sync clock/ sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72671 Model 74671 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Trigger In
RF Out
RF Out
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO
GTX
16 Config FLASH 64 MB
40
x4 PCIe
4X
GTX
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4- or 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - cPCI
Digital Upconverter and D/A Stage
Two or four Texas Instruments DAC3484s provide four or eight DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, these models feature an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog outputs are through front panel SSMC connectors. SSMC connector. This clock can be used directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A pair of front panel Sync connectors allows multiple boards to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave board. For larger systems, the Pentek Model 7291, 7391 and 7291D Cobalt Synchronizers can drive multiple 72671s 73671s and 74671s respectively, thereby enabling large, multichannel synchronous configurations.
Memory Resources
The architecture of these models supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
16 to D/A Ch 3 & 4
to D/A Ch 1 & 2
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
4X PCIe
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4- or 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - cPCI
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73671: 32 bits only. External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus (1 or 2): 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Arrays (1 or 2) Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73671; J3 connector, Model 72671; J3 and J5 connectors, Model 74671 Memory Banks (1 or 2) Four or eight 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73671: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Specifications
Models 72671 and 73671: 4-Channel DUC, 4-channel D/A Model 74671: 8-Channel DUC, 8-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference
Ordering Information
Model 72671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 6U cPCI 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U cPCI 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 6U cPCI
73671
74671
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73671; J3 connector, Model 72671; J3 and J5 connectors, Model 74671 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D, Virtex-6 FPGA - cPCI
General Information
Models 72690, 73690 and 74690 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71690 XMC modules mounted on a cPCI carrier board. Model 72690 is a 6U cPCI board while the Model 73690 is a 3U cPCI board; both are equipped with one Model 71690 XMC. Model 74690 is a 6U cPCI board with two XMC modules rather than one. These models include one ot two L-Band RF tuners, two or four A/Ds and four or eight banks of memory. test signal generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Model 74690
Model 73690
Features
One or two L-Band tuners accept RF signals from 925 MHz to 2175 MHz One or two programmable LNAs boost LNB (low-noise block) antenna signal levels with up to 60 dB gain One or two programmable analog downconverters provide I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two or four 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72690 Model 74690 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Trigger 1 Trigger 2 TIMING GENERATOR Clock / Sync / Gate / PPS
Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Control
I 200 MHz 16-BIT A/D Q 200 MHz 16-BIT A/D
TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B
16
16
IC
2
Timing Bus
VCXO
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
40
x4 PCIe
4X
GTX
QDRII+ option 150 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
J2
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D, Virtex-6 FPGA - cPCI
RF Tuner Stage
One or two front panel SSMC connectors accept L-Band signals between 925 MHz and 2175 MHz from the antenna LNBs (low noise blocks). The Maxim MAX2112 tuners directly convert these L-Band signals to baseband using broadband I/Q downconverters. The devices include RF variable-gain LNAs (low noise amplifiers), PLL (phaselocked loops) synthesized local oscillators, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cutoff frequency, and variable-gain baseband amplifiers. The fractional-N PLL synthesizers lock their VCOs to the timing generator output, or to an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the RF LNA offer a programmable linear gain range of 60 dB. The integrated lowpass filters with variable bandwidths provide bandwidths ranging from 4 to 40 MHz, programmable with 8 bits of resolution.
Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D, Virtex-6 FPGA - cPCI
Each QDRII+ SRAM bank can be up to 8
MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . Sample Clock Sources (1 or 2) On-board timing generator/synthesizer A/D Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Inputs (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus (1 or 2): 26-pin front panel connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Inputs (2 or 4) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74950 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73690: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
PCI-X Interface
The models include an industry-standard interface compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73690: 32 bits only.
Specifications
Model 72690 or Model 73690: 1 RF tuner, 2 A/Ds Model 74690: 2 RF tuners, four A/Ds Front Panel Analog Signal Inputs (1 or 2) Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuners (1 or 2) Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters (2 or 4) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
Ordering Information
Model 71690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74690 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-150
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-7 FPGA - cPCI
General Information
Models 72720, 73720 and 74720 are members of the Onyx family of high-performance CompactPCI boards based on the Xilinx Virtex-7 FPGA. They consist of one or two Model 71720 XMC modules mounted on a cPCI carrier board. Model 72720 is a 6U cPCI board while the Model 73720 is a 3U cPCI board; both are equipped with one Model 71720 XMC. Model 74720 is a 6U cPCI board with two XMC modules rather than one. These models include three or sixA/Ds, one or two DUCs, two or four D/As and four or eight banks of memory. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCI-X interface complete the factoryinstalled functions and enable these models to operate as a complete turnkey solutions, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus Three or six 200 MHz 16-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Block Diagram, Model 72720 Model 74720 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF In
RF Out
RF Out
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40
40 CONFIG FLASH 1 GB
x4 PCIe
x4 PCIe
x4 PCIe
PCIe to PCI BRIDGE
x4 PCIe
PCIe to PCI BRIDGE PCI to PCI BRIDGE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-7 FPGA - cPCI
GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCI-X discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCI-X interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCI-X interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCI-X configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-7 FPGA - cPCI
When operating as a DUC, it interpolates
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes, the DAC5688 provides interpolation factors of 2x, 4x and 8x. D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73720; J3 connector, Model 72720; J3 and J5 connectors, Model 74720 Memory Banks (1 or 2) Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73620: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board
Memory Resources
The architecture supports four or eight independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factoryinstalled functions, custom userinstalled IP within the FPGA can take advantage of the memories for many other purposes.
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73620: 32 bits only.
Ordering Information
Model 72720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex7 FPGA 6U cPCI 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA 3U cPCI 6-Channel 200 MHz A/D and 4-Channel 800 MHz D/A and two Virtex-7 FPGAs - 6U cPCI XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73720; J3 connector, Model 72720; J3 and J5 connectors, Model 74720
Specifications
Model 72620 or Model 73620: 3 A/Ds, 1 DUC, 2 D/As Model 74620: 6 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
73720
74720
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Model 74760
Model 73760
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus Four or eight 200 MHz 16-bit A/Ds Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-7 FPGA for custom I/O
Block Diagram, Model 72760 Model 74760 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF In
RF In
RF In
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16 VCXO
16
16
16
Timing Bus
GTX
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40
40 CONFIG FLASH 1 GB
x4 PCIe
x4 PCIe
x4 PCIe
PCIe to PCI BRIDGE
x4 PCIe
PCIe to PCI BRIDGE PCI to PCI BRIDGE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Memory Resources
The Onyx architecture supports four or eight independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Ordering Information
Model 72760 Description 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA 6U cPCI 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA 3U cPCI 8-Channel 200 MHz 16-bit A/D with two Virtex-7 FPGAs - 6U cPCI XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73760; J3 connector, Model 72760; J3 and J5 connectors, Model 74760
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73760: 32 bits only.
73760
74760
Specifications
Model 72760 or Model 73760: 4 A/Ds Model 74760: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PCI 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - PCI Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI Customer Information
RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR
Model 7650
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory-shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA,
Features
Complete software radio interface solution Four or 200 MHz, 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS 200 or 135 MHz 16 BIT A/D
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
TTL In
Clock/Sync Bus
LVPECL Bus
XTL OSC
To A l Sections
Timing Bus
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T or LX155T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X LVDS
PCI X INTERFACE
64
LVDS 32 32
32
PCI-X BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7650
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O Memory DDR2 SDRAM: Up to 1 GB in two banks PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI card
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.
PCI-X Interface
The Model 7650 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Ordering Information
Model 7650 Description Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs PCI FPGA I/O through a 64-pin DIN connector
Options: -104
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7651
Features
256 channels of DDC Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization
CH 1 RF In
RF XFORMR
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A D
CH 2
M U X D G TAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024
CH 3 CH 4
I+Q
M U X
FIFO 2
PCI-X BUS CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
M U X D GITAL DOWNCONVERTER BANK 4: CH 193-256 DEC: 128 - 1024
PCI-X BUS
CH 3
M U X D GITAL DOWNCONVERTER BANK 3: CH 129-192 DEC: 128 - 1024
CH 2 CH 3 CH 4
I+Q
M U X
FIFO 3
TTL In
CH 4 I+Q
M U X
FIFO 4
LVPECL Bus
XTAL OSC
XILINX XC5VSX95T
Timing Bus
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7651
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Local Bus: 64-bit, 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI card
PCI-X Interface
The Model 7651 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Ordering Information
Model 7651 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7652
Features
32 channels of DDC in four banks of 8 channels Four 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all 32 channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Common decimation factor within each DDC bank Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multiboard synchronization
CH 1 RF In
RF XFORMR
CH 1 I+Q
M U X F I F 0 1 F I F 0 2
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHO D DETECTORS
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D
CH 2
M U X
CH 3 CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
PCI-X BUS
CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 4: CH 25-32 DEC: 16 - 8192
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
TTL In
CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
LVPECL Bus
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7652
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Local Bus: 64-bit, 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board
PCI-X Interface
The Model 7652 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Ordering Information
Model 7652 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7653
Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization
The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.
Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.
CH 1 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER
4X 4X P15 XMC
CH 2 RF In
RF XFORMR
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
I+Q
POWER METER & THRESHOLD DETECTORS
CH 4 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4
PCI-X BUS
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
PCI-X NTERFACE
XILINX XC5VLX30T
PCI-TO-PCI BRIDGE
CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7653
XMC Interface
For large systems, multiple 7653s can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.
PCI-X Interface
The Model 7653 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*
GAIN
I Q
I Q
I
Q
I
Q
AURORA PORT
F om P evious Board
P15
GAIN
I
Q
I
Q
I
Q
I
Q
I Q
I Q
I Q
GAIN
(DECIMATION: 2-256)*
I Q
I Q
I
Q
I
Q
AURORA PORT
To Next Boa d
GAIN
P15 I Q
(DECIMATION: 2-256)*
I Q
I Q
I Q
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7653
Ordering Information
Model 7653 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - PCI
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7656
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
General Information
Model 7656 is a half-length PCI board that includes two 400 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. It consists of one Model 7156 PMC module mounted on a PCI carrier board. The Model 7656 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.
Virtex-5 FPGAs
The Model 7656 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
Features
Complete software radio interface solution Two 400 MHz, 14-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
Tim ng Bus
VCXO
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X
LVDS
PCI X INTERFACE
64
LVDS 32 32
32
PCI-X BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7656
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds a 64-pin DIN connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
PCI-X Interface
The Model 7656 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Ordering Information
Model 7656 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7658
Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
General Information
Model 7658 is a half-length PCI board that includes two 500 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. It consists of one Model 7158 PMC module mounted on a PCI carrier board. The Model 7658 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.
Virtex-5 FPGAs
The Model 7658 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
Features
Complete software radio interface solution Two 500 MHz, 12-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER
Tim ng Bus
VCXO
Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 265 MB
PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X
LVDS
PCI X INTERFACE
64
LVDS 32 32
32
PCI-X BUS
PCI-TO-PCI BRIDGE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7658
Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds a 64-pin DIN connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board
Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Options: -104 FPGA I/O through a 64-pin DIN connector -140 1 GB DDR2 SDRAM
The Model 7658 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
DESCRIPTION
Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x16 PCIe 256- or 512-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - x16 PCIe 32- or 64-Channel DDC with 4or 8 200 MHz, 16-bit A/Ds - x16 PCIe 4/8-Channel DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - x16 PCIe Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x16 PCIe Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x16 PCIe Customer Information
RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR
Quad/Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x16 PCIe
General Information
Model 7750 is a high-speed data converter suitable for connection as the HF or IF input of a communications system. It features either four 200 MHz, 16-bit A/Ds (Model 7750) or eight A/Ds (Model 7750D). These are supported by an array of data processing and transport resources ideally matched to requirements of high-performance systems. The 7750 attaches to motherboards with full length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. There are two FPGA types on the 7750: processing and interface. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, these Models can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. The interface FPGA provides board connections including PCI-X or PCI Express. Implementing the PCI interfaces in this FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to each processing FPGA, and 16 pairs of LVDS connections to each interface FPGA for custom I/O.
Model 7750D
Features
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x16 wide Four or eight 200 MHz 16-bit A/Ds Up to 2 GB of DDR2 SDRAM Two or Four Xilinx Virtex-5 FPGAs Up to 5.12 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization Up to 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
Virtex-5 FPGAs
The Model 7750 architecture includes two (Model 7750) or four (Model 7750D) Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering, and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user- created IP with the factory-shipped functions.
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR Sample Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS To All Sections
Sample Clk In PPS In TTL In TIMING BUS GENERATOR Clock / Sync / Gate / PPS To All Sections
Clock/Sync Bus
Clock/Sync Bus
PPS In
TTL In
Control/ Status
32 DDR2 SDRAM 512 MB
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
LVPECL Bus
XTL OSC
Timing Bus
8
4X 4X
8 4X
GTP
64
64
4X
GTP
4X
4X
Timing Bus
FLASH 32 MB
FLASH 32 MB
4X
64
32
32
32
32
64
4X
GPIO 1 (68-Pin)
4X Gbit Serial 4X Gbit Serial 4X 4X
PCI TO PCIe BRIDGE
GPIO 2 (68-Pin)
PCI TO PCIe BRIDGE
4X Gbit Serial 4X
4X Gbit Serial
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
x4 PCIe
4X
Model 7750D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Quad/Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x16 PCIe
Clocking and Synchronization
The Model 7750 architecture includes a flexible timing and synchronization circuit for each bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. One or two front panel 26-pin LVPECL Clock/Sync connectors allow multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7750s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More bords can be synchronized with an external clock and sync generator.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T (one for 7750, two for 7750D); optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: Xilinx Virtex-5 XC5VLX30T (one for 7750, two for 7750D); optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks per processing FPGA (2 GB max.) PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: two x4 ports per FPGA one x4 port per PCI bus one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe , 4.38 in. x 12.3 in.
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.
7750D
Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit Serial I/O - two full duplex 4X paths (Model 7750) or four full duplex 4X paths (Model 7750D)
The 7750 includes a multiple port, 48-lane Gen 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x16 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with two x4 PCIe connections provided to each FPGA, as well as one x4 connection to each 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
256/512-Channel DDC with 4/8 200 MHz, 16-bit A/Ds - x16 PCIe
General Information
Model 7751 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features either four 200 MHz 16-bit A/Ds (Model 7751) or eight A/Ds (Model 7751D). Each bank of four A/Ds is supported by a high-performance 256-channel installed DDC IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 7751 attaches to motherboards with full length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. Each of the DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.
Model 7751D
256 or 512 DDC channels Four or eight 200 MHz 16-bit A/Ds PCI Express 2.0 (Gen. 2) Interface up to x16 wide Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization
The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.
CH 1 RF In
RF XFORMR
RF XFORMR
CH 5 RF In
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 1 CH 1 64 DEC 128 1024
CH 1 I+Q
M U X
CH 5 FIFO 1 FIFO 5
M U X
CH 5 I+Q
DIGITAL DOWNCONVERTER BANK 5 CH 257 320 DEC 128 1024 M U X
CH 6 CH 7 CH 8
RF XFORMR
CH 6 RF In
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16 bit A/D
CH 2
M U X DIGITAL DOWNCONVERTER BANK 2 CH 65 128 DEC 128 1024
CH 6
M U X
RF XFORMR
CH 7 RF In
CH 3 CH 4
I+Q
FIFO 2
FIFO 6
M U X
CH 5 I+Q
DIGITAL DOWNCONVERTER BANK 6 CH 321 384 DEC 128 1024 M U X
CH 6 CH 7 CH 8
200 MHz 16 b t A/D RF XFORMR
CH 8 RF In
CH 3
M U X DIGITAL DOWNCONVERTER BANK 3 CH 129 192 DEC 128 1024
CH 7
M U X
CH 2 CH 3 CH 4
I+Q
FIFO 3
FIFO 7
M U X
CH 5 I+Q
DIGITAL DOWNCONVERTER BANK 7 CH 385 448 DEC 128 1024 M U X
CH 6 CH 7 CH 8
CH 4 I+Q
M U X
CH 8 FIFO 4 FIFO 8
M U X
CH 5 I+Q
DIGITAL DOWNCONVERTER BANK 8 CH 449 512 DEC 128 1024 M U X
CH 6 CH 7 CH 8 XTAL OSC
XIL NX XC5VSX95T
X linx XC5VLX30T PCI X INTERFACE Xilinx XC5VLX30T PCI X INTERFACE
X L NX XC5VSX95T
PCI X BUS 1
PCI X BUS 2
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
x4 PCIe
Model 7751D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
256/512-Channel DDC with 4/8 200 MHz, 16-bit A/Ds - x16 PCIe
Each of the output FIFOs operates at its
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T (one for 7751, two for 7751D) dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface (one for 7751, two for 7751D) PCI to PCIe Interface PCI-X Bus: 64-bits, 133 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: one x4 port per PCI-X bus one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe, 4.38 in. x 12.3 in.
own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.
Ordering Information
Model 7751 Description 256-Channel DDC with four 200 MHz, 16-bit A/D - Full-Length x16 PCIe 512-Channel DDC with eight 200 MHz, 16-bit A/D - Full-Length x16 PCIe
7751D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
32/64-Channel DDC with 4/6 200 MHz, 16-bit A/Ds - x16 PCIe
General Information
Model 7752 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds (Model 7752) or eight A/Ds (Model 7752D). Each group of four A/Ds is supported by a high-performance 32-channel installed DDC IP Core, and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 7752 attaches to motherboards with full length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. Each of the DDCs has an independent 32-bit tuning frequency setting ranging from DC to s (s is the A/D sample rate).
Model 7752D
Features
PCI Express 2.0 (Gen. 2) Interface up to x16 wide 32 or 64 channels of DDC in banks of 8 channels Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multimodule synchronization
CH 1 RF In
RF XFORMR
CH 1 I+Q
M U X F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4 F I F 0 5 F I F 0 6 F I F 0 7 F I F 0 8 M U X
CH 1 I+Q
RF XFORMR
CH 5 RF In
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHOLD DETECTORS
CH 5 I+Q
POWER METER & THRESHOLD DETECTORS DDC BANK 5 CH 33 40 DEC 16 8192 M U X
CH 6 CH 7 CH 8
RF XFORMR
CH 6 RF In
CH 3 RF In
RF XFORMR
CH 2
M U X
CH 2
M U X
RF XFORMR
CH 7 RF In
CH 4 RF In
RF XFORMR
CH 3 CH 4
I+Q
POWER METER & THRESHOLD DETECTORS
I+Q
POWER METER & THRESHOLD DETECTORS
CH 3
M U X
CH 3
M U X
CH 5 I+Q
DDC BANK 7 CH 49 56 DEC 16 8192 M U X
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
CH 6 CH 7 CH 8
CH 4
M U X
CH 4
M U X
CH 5 I+Q
DDC BANK 8 CH 57 64 DEC 16 8192 M U X
LVPECL Bus
I+Q
POWER METER & THRESHOLD DETECTORS
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Xilinx XC5VLX30T PCI X INTERFACE Xi inx XC5VLX30T PCI X INTERFACE
XILINX XC5VSX95T
Timing Bus
PCI X BUS 1
PCI X BUS 2
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
x4 PCIe
Model 7752D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
32/64-Channel DDC with 4/6 200 MHz, 16-bit A/Ds - x16 PCIe
Output Multiplexers and FIFOs
Four output MUXs in each SX95T FPGA can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T (one for 7752, two for 7752D) dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface (one for 7752, two for 7752D) PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: one x4 port per PCI-X bus one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe , 4.38 in. x 12.3 in.
Ordering Information
Model 7752 Description 32-Channel DDC with four 200 MHz, 16-bit A/D s - Full-Length x16 PCIe 64-Channel DDC with eight 200 MHz, 16-bit A/D s - Full-Length x16 PCIe
7752D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - x16 PCIe
General Information
Model 7753 is a high-speed software radio board designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds (Model 7753) or eight A/Ds (Model 7753D). Each group of four A/Ds is supported by a high-performance 4-channel installed DDC and a complete set of beamforming functions. With built-in multiboard synchronization, it is ideally matched to the requirements of realtime software radio and radar systems. The 7753 attaches to motherboards with full length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sampling frequency.
Model 7753D
Features
Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel PCI Express 2.0 (Gen. 2) Interface up to x16 wide 2 or 4 (Model 7753) and 4 or 8 (Model 7753D) channels of DDC Four or eight 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization
Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.
Block Diagram, Model 7753. Model 7753D doubles all resources except the PCIe switch.
CH 1 RF In
RF XFORMR 200 MHz 16-bit A/D
CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER
4X 4X P15 XMC
CH 2 RF In
RF XFORMR
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
I+Q
POWER METER & THRESHOLD DETECTORS
CH 4 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
CH 3
M U X
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
CH 4
M U X
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
I+Q
POWER METER & THRESHOLD DETECTORS
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - x16 PCIe
Beamformer
In addition to the A/Ds and DDCs, these Models include essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI-X bus. For larger systems, multiple Models can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.
XMC Interface
For large systems, multiple 7753s or 7753Ds can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.
PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*
GAIN
I Q
I Q
I
Q
I
Q
AURORA PORT
F om P evious Boa d
P15
GAIN
I Q
I Q
I Q
I Q
SUMMATION CHA N B T GROWTH COMPENSAT ON
I Q
I Q
I Q
GAIN
(DECIMATION: 2-256)*
I Q
I Q
I
Q
I
Q
AURORA PORT
To Next Board
GAIN
P15 I
Q
I
Q
I
Q
(DECIMATION: 2-256)*
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - x16 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 and 4 or 8 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, user-programmable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four or eight channels onboard; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four or eight FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI to PCIe Interface PCI-X Bus: 64 bits, 100 MHz and 64 or 32 bits at 33 or 66 MHz DMA: 4-channel demand-mode and chaining controller per PCI-X bus PCIe Interface: Gen. 2, x16 width PCIe Ports: one x4 port per PCI-X bus one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe , 4.38 in. x 12.3 in.
Ordering Information
Model 7753 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - Full-Length x16 PCIe 8-Channel DDC with eight 200 MHz, 16-bit A/Ds and Beamformers - Full-Length x16 PCIe
7753D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Dual/Quad 400 MHz A/D, 800 MHz D/A,Virtex-5 FPGAs - x16 PCIe
General Information
Model 7756 is a high-speed data converter suitable for connection to HF or IF ports of a communication system. It is available with either two A/Ds, D/As and FPGAs (Model 7756), or four A/Ds, D/As and FPGAs (Model 7756D). It attaches to motherboards with full-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.
Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family
RF In
RF XFORMR
Model 7756D
Features
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x16 wide Two or four 400 MHz, 14-bit A/Ds One or two DUCs (Digital Upconverters) Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS
DIGITAL UPCONVERTER 32
Timing Bus
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
8 FLASH 32 MB
4X
4X
4X
GTP
64
GTP
4X
64
32
32
Block Diagram, Model 7756. Model 7756D doubles all resources except the PCIe switch.
4X Gbit Serial
4X Gbit Serial 4X 4X
GP O 1 (68-Pin)
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
SER I/O A
SER I/O B
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Dual/Quad 400 MHz A/D, 800 MHz D/A,Virtex-5 FPGAs - x16 PCIe
part, providing not only interface
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to each processing FPGA, and 16 pairs of LVDS connections to each interface FPGA for custom I/O. Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks per processing FPGA (2 GB max.) PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: two x4 ports per FPGA; one x4 port per PCI bus; one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe, 4.38 in. x 12.3 in.
Memory Resources
Up to four independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Ordering Information
Model 7756 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length x16 PCIe Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length x16 PCIe
7756D
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688
Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit serial I/O: two fullduplex 4X paths (Model 7756) or four full duplex4X paths (Model 7756D)
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Dual/Quad 500 MHz A/D, 800 MHz D/A,Virtex-5 FPGAs - x16 PCIe
General Information
Model 7758 is a high-speed data converter suitable for connection to HF or IF ports of a communication system. It is available with either two A/Ds, D/As and FPGAs (Model 7758), or four A/Ds, D/As and FPGAs (Model 7758D). It attaches to motherboards with full-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.
Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family
RF In
RF XFORMR
Model 7758D
Features
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x16 wide Two or four 500 MHz, 12-bit A/Ds One or two DUCs (Digital Upconverters) Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS
DIGITAL UPCONVERTER 32
Timing Bus
Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 256 MB
8 FLASH 32 MB
4X
4X
4X
GTP
64
GTP
4X
64
32
32
Block Diagram, Model 7758. Model 7758D doubles all resources except the PCIe switch.
4X Gbit Serial
4X Gbit Serial 4X 4X
GP O 1 (68-Pin)
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
SER I/O A
SER I/O B
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Dual/Quad 500 MHz A/D, 800 MHz D/A,Virtex-5 FPGAs - x16 PCIe
part, providing not only interface
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to each processing FPGA, and 16 pairs of LVDS connections to each interface FPGA for custom I/O. Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks per processing FPGA (2 GB max.) PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: two x4 ports per FPGA; one x4 port per PCI bus; one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe, 4.38 in. x 12.3 in.
Ordering Information
Model 7758 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length x16 PCIe Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length x16 PCIe
Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
7758D
Options: -104 FPGA I/O through the GPIO connector(s) -140 1 GB DDR2 SDRAM, Model 7758; 2 GB DDR2 SDRAM, Model 7758D -5xx Gigabit serial I/O: two fullduplex 4X paths (Model 7758) or four full duplex4X paths (Model 7758D)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x8 PCIe 256-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe 32-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - x8 PCIe Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIe 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - x8 PCIe 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Wideband DDC, Virtex-6 FPGA - x8 PCIe Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - x8 PCIe 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - x8 PCIe 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIe 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - x8 PCIe 4-Channel SFP Transceiver PCIe Module for Cobalt Boards 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-7 FPGA - x8 PCIe 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - x8 PCIe Customer Information
RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR
Model 7850
Virtex-5 FPGAs
The Model 7850 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory- shipped functions. There are two FPGA types on the 7850: processing and interface. The pro-
Features
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization Up to 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Clock/Sync Bus
TTL In
LVPECL Bus
XTL OSC
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
Timing Bus
8
4X 4X
4X
GTP
64
FLASH 32 MB
4X
64
32
32
4X Gbit Serial
4X Gbit Ser al 4X 4X
GPIO 1 (68-Pin)
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
x8 PCI Express
SER I/O A SER I/O B
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7850
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to processing FPGA; one can be alternately routed to interface FPGA one x4 port to PCI bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe , 4.38 in. x 6.6 in.
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.
Ordering Information
Model 7850 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs Half-length x8 PCIe
Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit Serial I/O - two full duplex 4X paths
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7851
Features
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling 256 DDC channels Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization
CH 1 RF In
RF XFORMR
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X D GITAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D
CH 2
M U X D GITAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024
CH 3 CH 4
I+Q
M U X
FIFO 2
CH 3
M U X DIGITAL DOWNCONVERTER BANK 3: CH 129-192 DEC: 128 - 1024
CH 2 CH 3 CH 4
I+Q
M U X
FIFO 3
CH 4 I+Q
M U X
FIFO 4
XILINX XC5VSX95T
Xilinx XC5VLX30T PCI-X NTERFACE
PCI-X BUS 1
x4 PCIe
PCI EXPRESS SW TCH PEX 8648
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7851
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 133 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI-X bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.
Ordering Information
Model 7851 Description 256-Channel DDC with four 200 MHz, 16-bit A/D - Half-length x8 PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7852
Features
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling 32 channels of DDC in banks of 8 channels Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multimodule synchronization
CH 1 RF In
RF XFORMR
CH 1 I+Q
M U X F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHOLD DETECTORS
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16 bit A/D
CH 2
M U X
CH 3 CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
Sample C k In PPS In
CH 3
M U X
CH 2 CH 3 CH 4
M U X
TTL In
I+Q
POWER METER & THRESHOLD DETECTORS
CH 4
M U X
LVPECL Bus
I+Q
POWER METER & THRESHOLD DETECTORS
XTAL OSC
Timing Bus
XILINX XC5VSX95T
Xilinx XC5VLX30T PCI X INTERFACE
PCI X BUS 1
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7852
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI-X bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe , 4.38 in. x 6.6 in.
Ordering Information
Model 7852 Description 32-Channel DDC with four 200 MHz, 16-bit A/D s Half-length x8 PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7853
Features
Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC PCI Express 2.0 (Gen. 2) interface up to x8 wide Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization
Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.
CH 1 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER
4X 4X P15 XMC
CH 2 RF In
RF XFORMR
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
I+Q
POWER METER & THRESHO D DETECTORS
CH 4 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
POWER METER & THRESHO D DETECTORS
CH 3
M U X
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
CH 4
M U X
I+Q
POWER METER & THRESHO D DETECTORS
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7853
XMC Interface
For large systems, multiple 7853s can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.
PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*
GAIN
I Q
I Q
I
Q
I
Q
AURORA PORT
F om P evious Boa d
P15
GAIN
I Q
I Q
I Q
I Q
SUMMATION CHA N B T GROWTH COMPENSAT ON
I Q
I Q
I Q
GAIN
(DECIMATION: 2-256)*
I Q
I Q
I
Q
I
Q
AURORA PORT
To Next Board
GAIN
P15 I
Q
I
Q
I
Q
(DECIMATION: 2-256)*
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7853
Ordering Information
Model 7853 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - Half-length x8 PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7856
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
General Information
Model 7856 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 400 MHz A/Ds, 800 MHz D/ As and Virtex-5 FPGAs. The 7856 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family
Features
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Two 400 MHz, 14-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR Sample Clk / Reference Clk In PPS In TIM NG BUS GENERATOR Clock / Sync / Gate / PPS
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS
DIGITAL UPCONVERTER 32
T ming Bus
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
8 FLASH 32 MB
4X
4X
4X
GTP
64
GTP
4X
64
32
32
4X Gbit Serial
4X Gbit Serial 4X 4X
GPIO 1 (68-Pin)
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
SER /O A
SER /O B
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7856
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
part, providing not only interface
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O. Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to FPGA; one x4 port to PCI bus; one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Ordering Information
Model 7856 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688
Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit serial I/O: two fullduplex 4X paths
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7858
Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
General Information
Model 7858 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 500 MHz A/Ds, 800 MHz D/ As and Virtex-5 FPGAs. The 7858 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR
Features
Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Two 500 MHz, 12-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS
DIGITAL UPCONVERTER 32
T ming Bus
Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 256 MB
8 FLASH 32 MB
4X
4X
4X
GTP
64
GTP
4X
64
32
32
4X Gbit Serial
4X Gbit Serial 4X 4X
GPIO 1 (68-Pin)
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
SER /O A
SER /O B
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 7858
Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to FPGA; one x4 port to PCI bus; one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.
Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Ordering Information
Model 7858 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688
Options: -104 FPGA I/O through the GPIO connector -140 1 GB DDR2 SDRAM -5xx Gigabit serial I/O: two fullduplex 4X paths
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - x8 PCIe
General Information
Model 78620 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78620 includes optional general-purpose and gigabit serial card edge connectors for application-specific I/O . and a PCIe interface complete the factoryinstalled functions and enable the 78620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
8X
4X
4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78620
A/D Acquisition IP Modules
The 78620 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - x8 PCIe
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The 78620 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
to D/A D/A loopback
TEST SIGNAL GENERATOR
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - x8 PCIe
boards DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Ordering Information
Model 78620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-105
-150
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
General Information
Model 78621 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78621 includes an optional general-purpose connector for applicationspecific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 78621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
8X
4X
4X
x8 PCIe Optional FPGA GPIO 68-pin Header x8 PCI Express Sum from previous board
Aurora Gigabit Serial I/O Sum to next board Dual 4X Serial Conn
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78621
A/D Acquisition IP Modules
The 78621 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or 16-bit I + 16-bit Q samples at a rate of s/N. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 78621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 78621 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold.
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The 78621 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Ordering Information
Model 78621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-150
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78630
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Gate In Sync In
VCXO
GTX
GTX
GTX
16
16
16
16
16 Config FLASH 64 MB 40
8X
4X
4X
Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78630
A/D Acquisition IP Module
The 78630 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, a test signal generator, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
Memory Resources
The 78630 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROLLER MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78630
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be locked to an external 4 to 200 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock
Ordering Information
Model 78630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - x8 PCIe
General Information
Model 78640 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The 78640 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78640 includes optional general-purpose and gigabit serial connectors for application-specific I/O protocols. and a PCIe interface complete the factoryinstalled functions and enable the 78640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Sync Bus
GTX
GTX
GTX
16 Config FLASH 64 MB
40
8X
4X
4X
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - x8 PCIe
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 78640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 78640s can be synchronized using the Cobalt high speed sync board to drive the sync bus.
Memory Resources
The 78640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
from A/D
from A/D
TEST SIGNAL GENERATOR
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE
MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 8X PCIe Gigabit Serial I/O 4X 4X 40 to Mem Bank 3 to Mem Bank 4
FPGA GPIO
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Ordering Information
Model 78640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - x8 PCIe
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - x8 PCIe
General Information
Model 78641 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter, with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78641 includes an optional connection to the Virtex-6 FPGA for custom I/O. nization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 78640 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 pairs of LVDS connections from the FPGA on PMC P14 to a 68-pin DIL ribboncable header on the PCIe board for custom I/O.
Features
Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Programable one- or twochannel DDC (Digital Downconverter) 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Sync Bus
16 Config FLASH 64 MB
8X
40
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78641
A/D Acquisition IP Module
The 78641 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - x8 PCIe
DDC IP Cores
Within the FPGA is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the A/D at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the A/Ds 1.8 GHz two-channel operation . In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 16-bit I + 16-bit Q samples at a rate of s/N.
Memory Resources
The 78640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.
from A/D
from A/D
DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE MEMORY CONTROLLER A/D ACQUISITION IP MODULE PCIe INTERFACE to MEM CONTROL
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
8X PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - x8 PCIe
PCI Express Interface
The Model 78641 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
Ordering Information
Model 78641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - x8 PCIe
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78650
Two 500 MHz A/Ds, DUC, 800 MHz D/As,Virtex-6 FPGA - x8 PCIe
General Information
Model 78650 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes two A/Ds, one DUC (Digital Upconverter), two D/As, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78650 includes optional generalpurpose and gigabit serial card connectors for application specific I/O protocols. the factory-installed functions and enable the 78650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
VCXO
Timing Bus
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB 40
8X
4X
4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78650
Two 500 MHz A/Ds, DUC, 800 MHz D/As,Virtex-6 FPGA - x8 PCIe
A/D Converter Stage
Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
The front end accepts two full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.
Memory Resources
The 78650 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
from A/D Ch 1
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78650
Two 500 MHz A/Ds, DUC, 800 MHz D/As,Virtex-6 FPGA - x8 PCIe
boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8 Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock
Ordering Information
Model 78650 Description Two 500 MHz A/Ds, one DUC, two 800 MHz D/As with Virtex-6 FPGA x8 PCIe
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
General Information
Model 78651 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 78651 includes two A/Ds, two D/As and four banks of memory. It features native support for PCI Express Gen 2. memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 78651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM PCI Express (Gen. 2) interface up to x8 Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
VCXO
Timing Bus
GTX
GTX
GTX
16 Config FLASH 64 MB 40
8X
4X
4X
Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB
Aurora Gigabit Serial I/O Sum to next board Dual 4X Serial Conn
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78651
A/D Acquisition IP Modules
The 78651 features two A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 78651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the dual 4X serial connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 78651 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average
from A/D Ch 1
to D/A
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MEMORY CONTROL
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The 78651 architecture supports up to three independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boardss DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via via a dual 4X connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Ordering Information
Model 78651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds
XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through a 68-pin DIL connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78660
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB 40
8X
4X
4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78660
Memory Resources
The 78660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78660
Ordering Information
Model 78660 Options: -062 -064 -104 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - PCIe
-105
-150
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe
General Information
Model 78661 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs (digital downconverters), it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution. It includes four A/Ds, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78661 includes an optional general-purpose connector for application-specific I/O. nization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory- installed functions and enable the 78661 to operate as a complete turnkey solution without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
8X
4X
4X
x8 PCIe Optional FPGA GPIO 68-pin Header Sum from previous board
Aurora Gigabit Serial I/O Sum to next board Dual 4X Serial Conn
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78661
A/D Acquisition IP Modules
The 78661 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 78661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 78661 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536
INPUT MULTIPLEXER
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe
controlled crystal oscillator. In this mode,
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Memory Resources
The 78661 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
-150
-160
-155
-165
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe
General Information
Model 78662 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78662 includes optional generalpurpose and gigabit serial connectors for application-specific I/O protocols. voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable the 78662 to operate as a complete turnkey solution without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable serial gigabit interfaces Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
GTX
GTX
16 Config FLASH 64 MB 40
8X
4X
4X
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78662
A/D Acquisition IP Modules
The 78662 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe
available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.
Memory Resources
The 78662 architecture supports up to four independent memory banks which can be configured with DDR3 SDRAM.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the
INPUT MULTIPLEXER
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe
Each DDR3 SDRAM bank can be up to
512 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation Sample Clock Sources: On-board clock synthesizer
Ordering Information
Model 78662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-105
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78670
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO
GTX
GTX
GTX
16 Config FLASH 64 MB
40
8X
4X
4X
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78670
Memory Resources
The 78670 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
16
TEST SIGNAL GENERATOR
to D/A Ch 1 & 2
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78670
Ordering Information
Model 78670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - x8 PCIe
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe
General Information
Model 78671 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O. a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 78671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO
GTX
GTX
GTX
16 Config FLASH 64 MB
40
8X
4X
4X
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe
Digital Upconverter and D/A Stage
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user-selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 78671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. SSMC connector. This clock can be used directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A pair of front panel Sync connectors allows multiple boards to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave 78671 module. For larger systems, the Pentek Model 7891 Cobalt Synchronizer can drive multiple 78671s enabling large, multichannel synchronous configurations.
Memory Resources
The 78671 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
16 to D/A Ch 3 & 4
to D/A Ch 1 & 2
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe
PCI Express Interface
The Model 78671 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the board. External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array: Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference
Ordering Information
Model 78671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78690
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O
Ref Out GC
12-BIT D/A
Sample Clk / Reference Clk In Trigger 1 Trigger 2 TIMING GENERATOR Clock / Sync / Gate / PPS
Control
Option 100
TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B
16
16
IC
2
Timing Bus
VCXO
GTX
GTX
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB 40
8X
4X
4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
x8 PCI Express
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78690
Memory Resources
The 78690 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78690
Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
Ordering Information
Model 78690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-105
-150
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e
Model 7809
SFP Modules
SFP transceiver modules support a variety of different transmitter and receiver types. These modules simply plug into the SFP sockets so they can be easily installed or replaced by users. Users can choose the appropriate transceiver for each link to support the required distance and data rates. Both single-mode and multi-mode optical fibre devices are available for cable interconnection distances up to 550 m and 10 km, respectively. Pentek offers the 7809 with options for either two or four 850 nm multi-mode fibre optical SFP modules installed. Each 7809 is supplied with the gigabit serial flex circuit cable assembly for connection to a suitably equipped 786xx series PCIe Cobalt module.
Features
Compatible with Pentek 786xx PCI Express Cobalt boards Extends range of gigabit serial I/O links Four SFP modules drive cable lengths up to 10 km Support for both optical and copper cables Single-mode and multi-mode fibre optical Data rates to 5 Gbits/sec Payload data rates to 500 MB/sec for each cable
Ordering Information
Model Description 7809 Options: -002 Two 850 nm multi-mode fiber optical channel SFPs (500 m distance) Four 850 nm multi-mode fiber optical channel SFPs (500 m distance) 4-Channel SFP Transceiver PCIe Module
Optical or Copper Cable Optical or Copper Cable Optical or Copper Cable Optical or Copper Cable
-004
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78720
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - x8 PCIe
General Information
Model 78720 is a member of the Onyx family of high-performance PCIe boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 78720 includes optional general-purpose and gigabit-serial card edge connectors for application-specific I/O . nization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 78720 to operate as a complete turnkey solution without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF Out
RF Out
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
LVDS
CONFIG FLASH 1 GB
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78720
A/D Acquisition IP Modules
The 78720 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - x8 PCIe
GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA-PCIe configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a PCIe target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCIe discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCIe interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCIe interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded through PCIe as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCIe configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
48
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78720
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - x8 PCIe
When operating as a DUC, it interpolates
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Connects 24 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.
Memory Resources
The 78720 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factoryinstalled functions, custom userinstalled IP within the FPGA can take advantage of the memories for many other purposes.
-105
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 78760
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Advanced reconfigurability features Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
LVDS
CONFIG FLASH 1 GB
PCIe Gen. 3 x8
4X
4X
48
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78760
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
48
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 78760
Memory Resources
The 78760 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits
-105
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 3U VPX 256-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U VPX 32-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U VPX 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - 3U VPX Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX Front Panel x8 PCI Express Adapter - 3U VPX 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - 3U VPX 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, 3U VPX 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 3U VPX 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, DDC, Virtex-6 FPGA - 3U VPX Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - 3U VPX 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 3U VPX 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - 3U VPX 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-7 FPGA - 3U VPX 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 3U VPX Customer Information
RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR
ew
Model 5350
Complete software radio interface solution for 3U VPX systems Supports Gigabit Serial Fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization Up to 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
The Model 5350 architecture includes two Virtex-5 FPGAs. All data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP.
RF In
RF XFORMR
RF In
RF XFORMR
RF In
RF XFORMR
Clock/Sync Bus
TTL In
LVPECL Bus
XTL OSC
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
8
4X 4X
Timing Bus
4X
GTP
64
FLASH 32 MB
4X
64
32
XMC - P15
4X 4X
PMC - P14
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
24
64
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P1 VPX-P2
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 5350
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T standard; XC5VLX50T, XC5VSX95T, XC5VLX155T or XC5VFX100T, optional Interface FPGA: Xilinx Virtex-5 XC5VLX30T std.; XC5VSX50T optional Custom I/O Option -104: Provides GPIO to VPX-P2 with 16 LVDS pairs to processing FPGA (SX95T, LX155T or FX100T only) and 16 pairs to interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O: Processing FPGA: Two 4X ports to Fabric-Transparent Switch; one can be alternately routed to interface FPGA VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of all three banks to support various applications.
Ordering Information
Model 5350 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs 3U VPX
Options: -104 FPGA I/O to VPX-P2 -5xx Gigabit Serial I/O to VPXP1- four full duplex 4X paths -703 Level L3 ConductionCooled Version
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 5351
Features
256 DDC channels Four 200 MHz 16-bit A/Ds Independent tuning for each channel and decimation for each bank DDC decimation from 128 to 1024 in steps of 64 User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Each bank independently selects one of four A/Ds LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor with ruggedized and conductioncooled versions available
CH 1 RF In
RF XFORMR
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024
CH 1 I+Q
M U X
FIFO 1
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D A
CH 2
M U X DIGITAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024
CH 3 CH 4
I+Q
M U X
FIFO 2
PCI-X INTERFACE
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
XILINX XC5VLX30T
CH 3
M U X DIGITAL DOWNCONVERTER BANK 3: CH 129-192 DEC: 128 - 1024
24
CH 2 CH 3 CH 4
I+Q
M U X
FIFO 3
CROSSBAR SWITCH
CH 4 I+Q
M U X
FIFO 4
VPX BACKPLANE
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 5351
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70C (Level L3) Storage Temperature: Forced-Air Cooled: -20 to 90 C std; -40 to 100 C (Level L1, L2) Conduction-Cooled: -50 to 100C (L3) Relative Humidity: 0 to 95%, non-cond.; 0 to 100% with conformal coating Size: 3.937 in. x 6.717 in. (100 mm x 170.6mm)
Model 5351 includes a PCIe Gen. 2 switch. The switch provides a total of 24 PCIe lanes to the Fabric-Transparent Crossbar Switch on 6 ports. Dynamic lane width negotiation within the PCIe switch allows for x1, x4, x8 or x16 widths. These can be selected in any combination.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! ew N
Model 5352
Features
32 channels of DDC in banks of 8 channels Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor with ruggedized and conductioncooled versions available
CH 1 RF In
RF XFORMR
CH 1 I+Q
M U X F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4
CH 2 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHOLD DETECTORS
CH 3 RF In
RF XFORMR
CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D
CH 2
M U X
CH 3 CH 4
M U X
PCI-X INTERFACE
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
I+Q
POWER METER & THRESHOLD DETECTORS
XILINX XC5VLX30T
CH 3
M U X
24
CH 2 CH 3 CH 4
M U X
TTL In
I+Q
POWER METER & THRESHOLD DETECTORS
CROSSBAR SWITCH
CH 4
M U X
LVPECL Bus
I+Q
POWER METER & THRESHOLD DETECTORS
XTAL OSC
VPX BACKPLANE
Timing Bus
XILINX XC5VSX95T
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 5352
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Storage Temperature: Forced-Air Cooled: -20 to 90 C std; -40 to 100 C (Level L1, L2) Conduction-Cooled: -50 to 100 C (L3) Relative Humidity: 0 to 95%, non-cond.; 0 to 100% with conformal coating Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Ordering Information
Model 5352 Description 32-Channel DDC with four 200 MHz, 16-bit A/D s - 3U VPX
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! ew N
Model 5353
Features
Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor with ruggedized and conductioncooled versions available
Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.
CH 1 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER
4X 4X XMC - P15
CH 2 RF In
RF XFORMR
I+Q CH 1
M U X
CH 3 RF In
RF XFORMR
I+Q
POWER METER & THRESHOLD DETECTORS
CH 4 RF In
RF XFORMR
CH 1 CH 2 CH 3 CH 4
M U X
CH 2
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
4X Gbit Serial
PCI-X INTERFACE
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
CH 3
M U X
CH 2 CH 3 CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
XILINX XC5VLX30T
24
CH 4
M U X
I+Q
POWER METER & THRESHOLD DETECTORS
XILINX XC5VSX95T
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 5353
VPX Interface
For large systems, multiple 5353s can be chained together via a built-in Xilinx Aurora interface through the VPX-P1 connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.
GAIN
I Q
I Q
I
Q
I
Q
DIGITAL DOWNCONVERTER A
AURORA PORT
P15
GAIN
I Q
I Q
I Q
I Q
SUMMATION CHAIN BIT GROWTH COMPENSATION
DIGITAL DOWNCONVERTER B
I Q
I Q
I Q
GAIN
(DECIMATION: 2-256)*
I Q
I Q
I Q
I Q
DIGITAL DOWNCONVERTER C
AURORA PORT
To Next Board
GAIN
P15 I
Q
(DECIMATION: 2-256)*
I Q
I Q
I
Q
DIGITAL DOWNCONVERTER D
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 5353
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256
Ordering Information
Model 5353 Description 4/2-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - 3U VPX
Options: -5xx Gigabit Serial I/O to VPXP1- four full-duplex 4X paths -703 Level L3 ConductionCooled Version -730 Two-Slot Heat Sink
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 5356
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
General Information
Model 5356 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 400 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. The 5356 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC provides interpolation factors of 2x, 4x and 8x.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between
RF In
RF XFORMR
Features
Complete software radio interface solution for 3U VPX systems Supports Gigabit Serial Fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Two 400 MHz 14-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER 32
Timing Bus
Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB
8
4X 4X
4X
GTP
64
FLASH 32 MB
4X
64
32
XMC - P15
4X 4X
PMC - P14
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
24
64
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P1 VPX-P2
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 5356
Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 provides general purpose I/O to VPX-P2 with 16 pairs of LVDS connections to the processing FPGA, and 16 more to the interface FPGA for custom I/O. Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Option -104: Provides GPIO to VPX-P2 with 16 LVDS pairs to processing FPGA (SX95T, LX155T or FX100T only) and 16 pairs to interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O: Processing FPGA: Two 4X ports to Fabric-Transparent Switch; one can be alternately routed to interface FPGA VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Ordering Information
Model 5356 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation
Options: -104 FPGA I/O to VPX-P2 -5xx Gigabit Serial I/O to VPXP1- four full-duplex 4X paths -703 Level L3 ConductionCooled Version
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
e N
! w
Model 5358
Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
General Information
Model 5358 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 500 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. The 5358 features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch configuration adds gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC provides interpolation factors of 2x, 4x and 8x.
Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between
RF In
RF XFORMR
Features
Complete software radio interface solution for 3U VPX systems Supports Gigabit Serial Fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Two 500 MHz 12-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF XFORMR
RF Out
RF XFORMR
RF Out
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS
DIGITAL UPCONVERTER 32
Timing Bus
Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 256 MB
8
4X 4X
4X
GTP
64
FLASH 32 MB
4X
64
32
XMC - P15
4X 4X
PMC - P14
x4 PCIe
PCI EXPRESS SWITCH PEX 8648
24
64
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX P1 VPX P2
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 5358
Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
reception and transmission. For applications
requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 provides general purpose I/O to VPX-P2 with 16 pairs of LVDS connections to the processing FPGA, and 16 more to the interface FPGA for custom I/O. Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Option -104: Provides GPIO to VPX-P2 with 16 LVDS pairs to processing FPGA (SX95T, LX155T or FX100T only) and 16 pairs to interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus Gigabit Serial I/O: Processing FPGA: Two 4X ports to Fabric-Transparent Switch; one can be alternately routed to interface FPGA VPX-P1: Four 4X ports to Fabric-Transparent Crossbar Switch PCI Express: Six ports to Fabric-Transparent Switch, each configurable as x1, x4, x8 or x16 lanes, 24 lanes total Environmental Operating Temperature: Forced-Air Cooled: 0 to 50 C std; -20 to 65 C (Level L2) Conduction-Cooled: -40 to 70 C (Level L3) Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.
Ordering Information
Model 5358 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U VPX
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation
Options: -104 FPGA I/O to VPX-P2 -140 1 GB DDR2 SDRAM -5xx Gigabit Serial I/O to VPXP1- four full-duplex 4X paths -703 Level L3 ConductionCooled Version
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
ew
Model 5308
Features
Front Panel x8 PCI Express connection to host PC 3U VPX form factor provides a compact, rugged platform Cascade mode provides connection to an addtional VPX system Compatible with several VITA standards including: VITA-46 (VPX Baseline Standard) VITA-48 (VPX REDI) VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
PC Connection
The most common use for Model 5308 is for connection to an external host computer. In order to make this connection, the PC requires a PCIe host adapter which is also compliant to PCI-SIG PCI Express External Cabling 1.0 Specification. Adapters supporting either PCIe x8 Gen. 1 or Gen. 2 are available from Pentek under Model 4235.
3U VPX Interface
The 5308 provides full-duplex links to the VPX P1 connector, each capable of peak rates up to 1 gigabyte per sec. Four sets of x4 links support PCI Express.
Ordering Information
Model 5308 Description Front Panel x8 PCI Express Adadpter - 3U VPX
Front Panel I/O
-703
Level L3 ConductionCooled Version Accessories: Model Description 4235 PCI Express x8 Host Card for PC 2180 PCI Express x8 Cable
USB Interface
CPLD
FLASH 4 MB
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
VPX V TA 46 BACKPLANE
Options: -001 Host Adapter Mode (for connection to external host computer) -002 Cascade Mode (for connection to additional VPX system)
XMC-P15
! w e N
Model 53620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - 3U VPX
General Information
Model 53620 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 53620 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. and a PCIe interface complete the factoryinstalled functions and enable the 53620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF Out
RF Out
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53620
A/D Acquisition IP Modules
The 53620 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - 3U VPX
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The 53620 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
to D/A D/A loopback
TEST SIGNAL GENERATOR
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53620
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - 3U VPX
boards DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Ordering Information
Model 53620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
General Information
Model 53621 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53621 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 53621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) One DUC (digital upconverter) Two 800 MHz 16-bit D/As Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Optional LVPECL clock/sync bus for multiboard synchronization 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
8X x8 PCIe
4X 4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be program-med from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 53621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 53621 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average
from A/D Ch 1
from A/D Ch 2
to D/A
INPUT MULTIPLEXER
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency
MEMORY CONTROL
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The 53621 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53621
3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Ordering Information
Model 53621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53630
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF Out
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Gate In Sync In
VCXO
GTX
16
16
16
16
16 Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53630
The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.
Memory Resources
The 53630 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROLLER MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
FPGA GPIO
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53630
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock
Ordering Information
Model 53630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - 3U VPX
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - 3U VPX
General Information
Model 53640 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The 53640 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. installed functions and enable the 53640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Sync Bus
GTX
16 Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - 3U VPX
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 53640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 53640s can be synchronized using the Cobalt high-speed sync board to drive the sync bus.
Memory Resources
The 53640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
from A/D
from A/D
TEST SIGNAL GENERATOR
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE
MEMORY CONTROLLER
(supports user installed IP) to Mem Bank 1 to Mem Bank 2 8X PCIe Gigabit Serial I/O 4X 4X 40 to Mem Bank 3 to Mem Bank 4
FPGA GPIO
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53640
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - 3U VPX
Fabric-Transparent Crossbar Switch
The 53640 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X). External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm).
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out reference clock
Ordering Information
Model 53640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U VPX
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D w/ Wideband DDC, Virtex-6 FPGA - 3U VPX
General Information
Model 53641 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. The 53641 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. nization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 53641 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O.
Features
Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Programmable one- or twochannel DDC (Digital Downconverter) PCI Express (Gen. 1 & 2) interface, up to x8 Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
Sync Bus
16 Config FLASH 64 MB
40
8X x8 PCIe
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53641
A/D Acquisition IP Module
The 53641 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D w/ Wideband DDC, Virtex-6 FPGA - 3U VPX
DDC IP Cores
Within the FPGA is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the A/D at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the A/Ds 1.8 GHz two-channel operation . In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 16-bit I + 16-bit Q samples at a rate of s/N.
Memory Resources
The 53641 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.
from A/D
from A/D
DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE MEMORY CONTROLLER A/D ACQUISITION IP MODULE PCIe INTERFACE to MEM CONTROL
DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER
to Mem Bank 1
to Mem Bank 2
8X PCIe
FPGA GPIO
40
to Mem Bank 3
to Mem Bank 4
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53641
1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D w/ Wideband DDC, Virtex-6 FPGA - 3U VPX
PCI Express Interface
The Model 53641 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. Sample Clock Sources: Front panel SSMC connector Sync Bus: Multipin connectors, bus includes gate, reset and in and out reference clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm).
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
Ordering Information
Model 53641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 3U VPX
Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX
General Information
Model 53650 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 53650 includes two A/Ds, one DUC (digital upconverter), two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. the factory-installed functions and enable the 53650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
VCXO
Timing Bus
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
8X
4X
4X
40
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
x8 PCIe
Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC
P15 XMC
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX
A/D Converter Stage
Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
The front end accepts two full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.
Memory Resources
The 53650 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
from A/D Ch 1
to D/A
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
MEMORY CONTROL
to Mem Bank 3
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53650
Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - 3U VPX
boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Ordering Information
Model 53650 Description Two 500 MHz A/Ds, one DUC, Two 800 MHz D/As with Virtex-6 FPGA - 3U VPX
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
General Information
Model 53651 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53651 includes two A/Ds, two D/As and four banks of memory. It features builtin support for PCI Express over the 3U VPX backplane. or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 53651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
VCXO
Timing Bus
GTX
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
8X x8 PCIe
4X 4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53651
A/D Acquisition IP Modules
The 53651 features two A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 53651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 53651 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average
from A/D Ch 1
to D/A
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.
Memory Resources
The 53651 architecture supports up to three independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boardss DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53651
2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link over the VPX P1connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-T2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Ordering Information
Model 53651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - 3U VPX
Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240 FPGA XC6VSX315 FPGA LVDS FPGA I/O through the VPX P2 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53660
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Supports gigabit serial fabrics including PCI Express, Serial RapidIO and Xilinx Aurora Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53660
Memory Resources
The 53660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53660
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock
Ordering Information
Model 53660 Description 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX
General Information
Model 53661 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53661 includes four A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. nization functions, a test signal generator, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 53661 to operate as a complete turnkey solution without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs (digital downconverters) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 QDRII+ SRAM 8 MB
16
16 Config FLASH 64 MB
40
8X x8 PCIe
4X 4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53661
A/D Acquisition IP Modules
The 53661 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 53661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the VPX P1 connector. This allows summation across channels on multiple boards.
Beamformer IP Core
In addition to the DDCs, the 53661 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536
INPUT MULTIPLEXER
MUX
DDC CORE
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
SUMMER
PCIe INTERFACE
BEAMFORMER CORE
8X PCIe
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53661
4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX
controlled crystal oscillator. In this mode,
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 53661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
The 53661 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Ordering Information
Model 53661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX
General Information
Model 53662 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution. The 53662 includes four A/Ds and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable the 53662 to operate as a complete turnkey solution without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
16
16
16
16
Timing Bus
VCXO
GTX
16 Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53662
A/D Acquisition IP Modules
The 53662 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX
available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.
Memory Resources
The 53662 architecture supports up to four independent memory banks which can be configured with DDR3 SDRAM.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
from A/D Ch 4
DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the
INPUT MULTIPLEXER
DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
32 Memory Bank 1
32 Memory Bank 2
32 Memory Bank 3
32 Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53662
4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX
Each DDR3 SDRAM bank can be up to
512 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm).
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user-programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation
Ordering Information
Model 53662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through VPX P2 Gigabit serial FPGA I/O through VPX P1 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53670
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization User-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO
GTX
16 Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53670
Memory Resources
The 53670 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
16
TEST SIGNAL GENERATOR
to D/A Ch 1 & 2
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53670
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference
Ordering Information
Model 53670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 3U VPX
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX
General Information
Model 53671 is a member of the Cobalt family of high performance 3U VPX boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 over the 3U VPX backplane, the Model 53671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O . data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 53671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels Extended interpolation range from 2x to 1,048,576x 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
Gate In Sync In
mSync Bus A
Gate In Sync In
mSync Bus B
VCXO
GTX
16 Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX
Digital Upconverter and D/A Stage
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 53671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A pair of front panel Sync connectors allows multiple boards to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave 53671 module. For larger systems, the Pentek Model 5391 Cobalt Synchronizer can drive multiple 53671s enabling large, multichannel synchronous configurations.
Memory Resources
The 53671 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
to D/A Ch 1 & 2
16
to D/A Ch 3 & 4
DATA INTERLEAVER
DATA INTERLEAVER
MEMORY CONTROL
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
8X PCIe
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53671
4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX
PCI Express Interface
The Model 53671 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the board. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array: Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15
Ordering Information
Model 53671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U VPX
Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 -105 Gigabit serial FPGA I/O to VPX P1 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53690
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
Ref In
RF In
MAX2112
Ref Out GC
12-BIT D/A
Sample Clk / Reference Clk In Trigger 1 Trigger 2 TIMING GENERATOR Clock / Sync / Gate / PPS
Control
I 200 MHz 16-BIT A/D Q 200 MHz 16-BIT A/D
TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B
16
16
IC
2
Timing Bus
VCXO
GTX
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
QDRII+ SRAM 8 MB
16
16
Config FLASH 64 MB
40
8X x8 PCIe
4X
4X
QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB
QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53690
Memory Resources
The 53690 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2
to Mem Bank 1
to Mem Bank 2
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53690
Ordering Information
Model 53690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - 3U VPX XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O to VPX P2 Gigabit serial FPGA I/O to VPX P1 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)
Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution
-160
-155
-165
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53720
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - 3U VPX
General Information
Model 53720 is a member of the Onyx family of high-performance 3U VPX boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. The 53720 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 53720 to operate as a complete turnkey solution without the need to develop any FPGA IP.
Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 and 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A
16
16
16
Timing Bus
VCXO
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40 CONFIG FLASH 1 GB
PCIe Gen. 2 x8
4X
4X
PCIe Gen. 2 x8
Option -104 FPGA I/O
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53720
A/D Acquisition IP Modules
The 53720 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - 3U VPX
GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA-PCIe configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a PCIe target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCIe discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCIe interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCIe interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded through PCIe as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCIe configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.
from A/D Ch 1
from A/D Ch 2
from A/D Ch 3
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
MEMORY CONTROL
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
4X PCIe
40 FPGA I/O
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53720
3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - 3U VPX
input signals to any IF center frequency
up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX485T-2 or XC7VX690T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O. Option -105: Provides one 8X or two 4X gigabit links between the FPGA and the VPX P1 connector to support serial protocols. Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: 3.937 in. x 6.717 in. (100 mm x 170.6 mm)
Memory Resources
The 53720 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode.
Crossbar Switch
The 53620 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output preemphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X).
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
! w e N
Model 53760
Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.
Features
Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Advanced reconfigurability features Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O 3U VPX form factor provides a compact, rugged platform Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPXTM System Specification) Ruggedized and conductioncooled versions available
RF In
RF In
RF In
RF In
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS
RF XFORMR
RF XFORMR
RF XFORMR
RF XFORMR
TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B
Timing Bus
GTX
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
32 DDR3 SDRAM 1 GB
40 CONFIG FLASH 1 GB
PCIe Gen. 2 x8
4X
4X
PCIe Gen. 2 x8
Option -104 FPGA I/O
CROSSBAR SWITCH
4X 4X 4X 4X Gbit Gbit Gbit Gbit Serial Serial Serial Serial VPX-P2 VPX-P1
VPX BACKPLANE
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53760
from A/D Ch 1
from A/D Ch 2
TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL
INPUT MULTIPLEXER
DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL
DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4
to Mem Bank 1
to Mem Bank 2
to Mem Bank 3
to Mem Bank 4
PCIe INTERFACE
Memory Bank 1
Memory Bank 2
Memory Bank 3
Memory Bank 4
PCIe
8X
4X
4X
FPGA GPIO
40
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Model 53760
Memory Resources
The 53760 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
The 53760 features a unique high-speed switching configuration. A fabric-transparent crossbar switch bridges numerous interfaces and components on the board using gigabit serial data paths with no latency. Programmable signal input equalization and output pre-emphasis settings enable optimization. Data paths can be selected as single (1X) lanes, or groups of four lanes (4X).
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz
Pentek, Inc.
One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com
www.pentek.com
Customer Information
Placing an Order
When placing purchase orders for Pentek products, please provide the model numbers and descriptions used in this catalog. You may place your orders by letter, telephone, email or fax; you should confirm a verbal order by mail, email or fax. All orders should specify a purchase order number, bill-to and ship-to address, method of shipment, and a contact name and telephone number. U.S. orders should be made out to Pentek, Inc. and may be placed directly at our office address, or c/o our authorized sales representative in your area. International orders may be placed with us, or with our authorized distributor in your country. They have pricing and availability information and they will be pleased to assist you. The obligation of Pentek arising from a warranty claim shall be limited to repairing or, optionally, replacing without charge any product which proves to be defective within the term and scope of the warranty. Pentek must be notified of the defect or nonconformity within the warranty period. The affected product must be returned with shipping charges and insurance prepaid. Pentek will pay shipping charges for the return of product to buyer, except for products returned from outside of the USA.
Limitations of Warranty
This warranty does not apply to products which have been repaired or altered by anyone other than Pentek or its authorized representatives. The warranty does not extend to products that have been damaged by misuse, neglect, improper installation, unauthorized modification, or extreme environmental conditions. Pentek specifically disclaims merchantability or fitness for a particular purpose. We will not be held liable for incidental or consequential damages arising from the sale, use, or installation of any of our products. Under any circumstances Penteks liability under this warranty will not exceed the purchase price of the product.
Extended Warranty
You may purchase an extended warranty on our hardware products for a fee of 1% of the list price per month of coverage, or 10% of the list price per year of coverage. All Pentek software products (excluding 3rd-party products) include free maintenance and free upgrades for one year. Extended software maintenance is available for one, two, and three years, starting after the first year.
Terms
Terms are Net 30 days for accounts with established credit; until credit is established, we require prepayment, or will ship C.O.D.
Shipping
For new orders, we normally ship UPS ground with shipping charges prepaid and added to our invoice. If you are in a hurry, we will ship UPS Red, UPS Blue, FedEx, or the carrier of your choice, as you request.
Warranty
Pentek warrants its products to conform to published specifications and to be free from defects in materials and workmanship for a period of one year from the date of delivery, when used under normal operating conditions and within the service conditions for which they were furnished.
Trademarks
Microsoft, MS-DOS, Windows, Windows 2000, Windows NT, Windows XP and PowerPoint are trademarks or registered trademarks of Microsoft Corp. Sun, Sun Microsystems, SunOS and Solaris are trademarks or registered trademarks of Sun Microsystems, Inc. PowerPC and PC-AT are trademarks or registered trademarks of IBM Corp. UNIX is a registered trademark of The Open Group. VxWorks and Tornado are trademarks of Wind River Systems. Ethernet is a trademark of Xerox Corp. MIX is a trademark of RadiSys Corp. VelociTI is a trademark of Texas Instruments, Inc. SHARC is a trademark of Analog Devices, Inc. Pentek, SwiftNet, SwiftTools, VIM, ReadyFlow, GateFlow, SystemFlow and RTS are registered trademarks of Pentek, Inc. Other trademarks are properties of their respective owners.
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