FACTS Controllers

FACTS
Controllers and Applications

Mr. Suresh Kumar K.S & Dr. S. Ashok
Department of Electrical Engineering, N.I.T Calicut

Original edition published by
NALANDA DIGITAL LIBRARY at NATIONAL INSTITUTE OF TECHNOLOGY CALICUT

Copyright 2003 by Nalanda Digital Library

All rights reserved. No part of this publication may be reproduced,
stored in a retrieval system, or transmitted, in any form or by any
means electronic, mechanical, photocopying, recording, or otherwise,
without the prior written permission from both the Author and the
Publisher.

Published, 2003

Published by Nalanda Digital Library
National Institute of Technology Calicut
Kerala, India - Pin - 673 601

Email: nalanda@nitc.ac.in

FACTS Controllers and Applications - Contents

1 FACTS Controllers - An Overview - Dr. T.L Jose
2 Introduction to Simulink - Dr. Abraham T Mathew
3 FACTS Simulation Using PSCAD EMTDC - Dr. R. Sreeram Kumar
4 Introduction to Microsim Design Lab 8.0 - Part I - Mr. Suresh Kumar K.S
5 Introduction to Microsim Design Lab 8.0 - Part II - Mr. Suresh Kumar K.S
6 Linear Transformations Presentation in PDF - Dr. S. Ashok
7 Pulse Width Modulation Techniques - Dr. Saly George
8 Augmentation of Transmission - A Review Presentation in PDF - Mr. S.G. Menon
9 HVDC and FACTS - Ms. Preetha P.
10 Single-Phase Shunt Active Power Filter - Mr. Suresh Kumar K.S
11 Harmonic Voltage Cancellation and Isolation by Series Active Power Filtering in Distribtion
Systems Slides in PDF - Mr. Suresh Kumar K.S
12 Three Phase Shunt Active Power Filters - Part I Introduction - Mr. Suresh Kumar K.S
13 Three Phase Shunt Active Power Filters - Part II - Control Strategies - Mr. Suresh Kumar K.S
14 Three Phase ShuntActive Power Filters - Part III - Simulation of Control Strategies - Mr. Suresh
Kumar K.S
15 Dynamic Voltage Restorers and Their Control - Mr. Suresh Kumar K.S
16 Simulation of a Single-Phase Active Power Line Conditioner Using Microsim Design Lab 8.0 -
Mr. Suresh Kumar K.S
17 Unified Power Quality Conditioner (UPQC - A Simulation Study) Slides in PDF - Mr. Suresh
Kumar K.S
18 Variable Impedance Type Static Series Compensators Presentation in PDF - Ms. Subha D
Puthankattil
19 Variable Impedance Type Static Shunt VAr Compensators Presentation in PDF - Ms. Elizabeth P
Cherian
20 Static Synchronous Compensators (STATCOM) at Distribution and Transmission Levels - Mr.
Suresh Kumar K.S
21 Static Synchronous Series Compensator (SSSC) and its Control - Mr. Suresh Kumar K.S
22 Improvement of Power System Stability Using Static Var Compensators - Dr. R. Sreeram Kumar
23 Optimal Allocation of Multifunctional FACTS Devices for Power Transit Control - Ms. Elizabeth P
Cherian
24 Application of STATCOM and TCSC for improvement of System Dynamic Performance - Dr. R.
Sreeram Kumar
25 Unified Power Flow Controller (UPFC) - An Introduction - Mr. Suresh Kumar K.S
26 Control of a Unified Power Flow Controller - Mr. Suresh Kumar K.S
27 Simulation of UPFC Using Matlab Simulink - Mr. Suresh Kumar K.S

TLJ1
FACTS Controllers An Over-view
Dr T.L. Jose
Professor, Electrical Engg.
N.I.T. Calicut
Most of the worlds electric power systems are widely
interconnected to reduce cost of electricity and to
improve the reliability of power supply. It is ideal to
locate the generators at load centers. Because of
economical and environmental reasons, the
generating stations are usually located at remote
locations. The interconnection of generating stations
and utilities improve the reliability with minimum
generation resources. If the transmission capability is
less, then more generation would be required to serve
the same load with same reliability. Hence the cost
of electricity would be higher.
The power system is a complex network of
synchronous generators, transmission lines, loads,
etc. As the power system grows it becomes more
complex to operate the system and can become less
secure for riding through the major outages. The
power that can be transmitted over a line depends on
series reactance of the line, bus voltages and
transmission angle . The voltage profile along the
line can be controlled by reactive shunt
compensation. The series line inductive reactance
can be controlled by series capacitive compensation.
The transmission angle can be varied by phase
shifting. Generally the reactive power compensation
and phase angle control are applied by fixed or
mechanically switched capacitors, reactors and tap
changing transformers to improve the power
transmission. The recovery from dynamic
disturbances was accomplished by generous stability
margins at the price of relatively poor system
compensation. Speed of operation of mechanically
controlled systems are lower compared to systems
using static devices. The mechanical devices wear
out quickly hence cannot be operated frequently.
The important limitations on loading capability of
transmission lines are thermal, dielectic and stability
limits. There are several stability issues that limit the
transmission capability some of them are steady state
stability, transient stability, dynamic stability,
frequency collapse, voltage collapse and
subsynchronous resonance.
Flexible AC Transmission Systems (FACTS) using
advanced solid state controllers offer flexibility of
system operation through fast and reliable control. It
helps to increase the usable transmission capacity of
lines and to control power flow over designated
transmission lines.
FACTS CONTROLLERS
There are two different approaches to the realization
of power electronic based FACTS Controllers. The
first group employs reactive impedances or a tap
changing transformer with thyristor switches as
controlled elements. The thyristor-controlled static
VAR compensator, thyristor-controlled series
capacitor and thyristor-controlled phase shifter comes
under this group.
The second group use self commutated static
converters as controlled voltage sources. The
FACTS Controllers in this group are static
synchronous compensator, the series compensator,
the unified power flow controller and the interline
power flow controller. The converter based FACTS
controllers generally provide superior performance
characteristics compared to thyristor controlled
FACTS controllers.
Static VAR Compensator (SVC)
It is a shunt-connected static VAR generator or
absorbed whose output is adjusted to exchange
capacitive or inductive current so as to maintain or
control specific parameters of the electrical system
(typically bus voltage). SVC is based on thyristors
without gate turn off capability. It includes separate
equipment for lagging and leading VARs; thyristor
controlled or thyristor switched reactor for absorbing
reactive power and thyristor switched capacitor for
supplying the reactive power. This compensator is
normally used to regulate the voltage of the
transmission system at a selected terminal. They are
also employed for transient and dynamic stability
improvement.
Thyristor Controlled Series Capacitor (TCSC)
It is a capacitive reactance compensator which
consists of a series capacitor bank shunted by a
thyristor-controlled reactor in order to provide a
smoothly variable capacitive reactance TCSC is
based on thyristors without gate turn off capability.
The variable series capacitive compensation is useful
TLJ2
in steady state control of power flow, transient
stability improvement, power oscillations damping
and balancing power flow in parallel lines.
Thyristor-Controlled Phase Shifting Transformer
(TCPST)
It is a phase-shifting transformer, adjusted by
thyristor switches to provide a rapidly variable phase
angle. In general, the phase shifting is obtained by
adding a perpendicular voltage vector in series with a
phase. This vector is derived from other two phases
using shunt connected transformers. The
perpendicular series voltage is made variable with a
variety of power electronics topologies. The TCPST
can be used to regulate the transmission angle to
maintain balanced power flow in multiple
transmission paths or to control so as to increase the
transient and dynamic stability of the power system.
Static Synchronous Compensator (STATCOM)
Static synchronous generator is static self
commutated switching power converter supplied
from an appropriate electric energy source and
operated to produce a set of adjustable multiphase
output. Voltages, which may be coupled to an AC
power system for the purpose of exchanging
independently controllable real and reactive power.
A STATCOM is a static synchronous generator
operated as a shunt-connected static VAR
compensator whose capacitive or inductive output
current can be controlled independent of system
voltage. It can be a voltage sourced or current
sourced converter. From an overall cost point of
view, the voltage sourced converters are preferred.
The STATCOM is able to control its output current
over the rated maximum capacitive or inductive
range independent of the system voltage. The ability
of the STATCOM to produce the current at low
system voltage make it more effective than SVC in
improving transient stability. The ability of the
STATCOM to generate and absorb reactive power
make it suitable for power oscillation damping.
Static Synchronous Series Compensator (SSSC)
It is a static synchronous generator operated without
an external electric energy source as a series
compensator whose output voltage is in quadrature
with, and controllable independently of, the line
current for the purpose of increasing or decreasing
the overall reactive voltage drop across the line and
thereby controlling the transmitted electric power.
The SSSC may include transiently rated energy
storage or energy absorbing devices to enhance the
dynamic behaviour of the power system by additional
temporary real power compensation, to increase or
decrease momentarily the overall real (resistive)
voltage drop across the line. It is like STATCOM
except that the output AC voltage is in series with the
line. Usually the injected voltage in series in very
small compared to the line voltage and the insulation
to ground would be quite high.
Unified Power Flow Controller (UPFC)
Using a unified power flow controller all the three
line parameters, the voltage, impedance and phase
angle, can be controlled to influence the real and
reactive power flow in AC line. The control of
voltage, impedance and phase angle can be carried
out concurrently or selectively. It may also provide
independently controllable shunt reactive
compensation. It is a complete controller for
controlling active and reactive power control through
the line as well as line voltage control.
Interline Power Flow Controller (IPFC)
It is a recently introduced controller. IPFC is a
combination of two or more static synchronous series
compensators which are coupled via a common DC
link to facilitate bi-directional flow of real power
between the AC terminals of the SSSCs and are
controlled to provide independent reactive
compensation for the adjustment of real power flow
in each line and maintain the desired distribution of
reactive flow among the line. The IPFC may include
a STATCOM, coupled to the IPFCs common DC
link, to provide shunt reactive compensation and
supply or absorb the overall real power deficit of the
combined SSSCS. It can be used to equivalize both
real and reactive power flow between the lines, to
transfer power demand from overloaded lines to
under loaded lines and to compensate line voltage
drops and the corresponding reactive line power and
to increase the effectiveness of the compensating
system for dynamic disturbances. The IPFC provides
a highly effective scheme for power transmission
management at multilane substation.
Benefits of Using FACTS Controllers
Some of the benefits that can be achieved by
implementation of FACTS Controllers are
1) Control of power flow
2) Increase in the loading capability of the lines
to their thermal limits.
3) Increase in system security
TLJ3
4) Provide secure tie line connections to
neighbouring utilities thereby decreasing the overall
generation reserve requirements on both sides.
5) Provide greater flexibility in siting new
generation
6) Reduce reactive power flow and allow the
lines to carry more active power.
7) Reduce loop flows
8) Increase utilization of lowest cost generation.
Conclusion
Using the advanced solid state technology FACTS
Controllers offer flexibility of system operation
through fast and reliable control. They enable better
utilization of existing power generation and
transmission facilities without compromising system
availability and security. The system planner has to
select a controller out of the set if FACTS
Controllers, for improving the system operation,
based on cost benefit analysis.
ATM1
Introduction to Simulink
Dr Abraham T Mathew
Department of Electrical Engineering
National Institute of Technology Calicut
Kozhikode 673 610, KERALA
atm@nitc.ac.in
INTRODUCTION
Simulink is an interactive tool for modelling, simulating and prototyping discrete, analog, and
mixed signal systems using the block sets rather than the line of code. It works as an integral part of the
MATLAB
environment. MATLAB/Simulink platform is being extensively used in industries also to

simulate algorithms and evaluate alternatives early in the design process.
For example with the DSP Blockset, the Simulink helps to build block diagrams, simulate dynamic
systems, evaluate system performance, and iterate the designs for complex DSP algorithms.
Power System Blockset is an application based on Simulink for studies in Power Engineering.
Simulink has a graphical interface for the user for constructing block diagram models using "drag-
and-drop" operations with the help of mouse and few keystrokes.
It is found that in many engineering applications Simulink is used to create high fidelity plant
models of real world systems and to design algorithms to control these systems.
COMPUTATIONAL ASPECTS OF Simulink
The Simulink simulation engine offers numerous computational features for simulating large,
challenging systems. Foremost among these is the set of integration algorithms, called solvers, which are
based on the MATLAB ordinary differential equation (ODE) suite. These solvers are well suited to
continuous-time (analog), discrete-time, hybrid, and mixed-signal simulations of any size. They provide fast,
reliable, and extremely accurate simulation results.
The solvers offer support for certain differential algebraic equations (DAEs) with multi-channel
algebraic loops. An algebraic constraint block facilitates the solution of a system in which an algebraic
constraint applies to the governing set of equations. The solvers also support stiff systems, and systems with
state events (such as discontinuities, including instantaneous changes in plant dynamics).
SIMULATION OF DYNAMIC SYSTEMS USING Simulink
Simulating a dynamic system is a two-step process with Simulink. First, we create a graphical
model of the system to be simulated, using the Simulink model editor. The model depicts the time-dependent
mathematical relationships among the system's inputs, states, and outputs Then, we use Simulink to simulate
the behaviour of the system over a specified time span. Simulink uses information that we have entered into
the model to perform the simulation.
BLOCK DIAGRAMS
The Simulink block diagram or the so-called graphical model is a pictorial model of the dynamic
system. It consists of a set of symbols, called blocks, interconnected by lines. Each block represents an
elementary dynamic system that produces an output either continuously (a continuous block) or at specific
points in time (a discrete block). The lines represent connections to the blocks inputs mostly from the output
of another block/s.
Every block in a block diagram is an instance of a specific type of block. The type of the block
determines the relationship between a block's outputs and its inputs, states, and time. A block diagram can
contain any number of instances of any type of block needed to model a given system. Behind each block
there is an underlying MATLAB-executable program, which is executed during the run of the simulation.
BLOCKS
Blocks represent elementary dynamic systems that Simulink knows how to simulate. A block
comprises one or more of the following: a set of inputs, a set of states, a set of parameters and a set of
outputs.
state(x)
parameters(P)
Input(
)
Output
( )
ATM2
A block's output is a function of time and the block's inputs and states (if any). The specific function
that relates a block's output to its inputs, states, and time depends on the type of block of which the block is
an instance.
TO START Simulink
To start Simulink, one has to start MATLAB. So, first start a MATLAB session by clicking on the
MATLAB 5.3 shortcut icon on the desktop. We will get the MATLAB screen with a command prompt .
The Menu toolbar would also be visible.
Now to open the Simulink session, either use the mouse and click on the Simulink icon as in
Fig.1 or type Simulink at the MATLAB command prompt and press the ENTER key(remember MATLAB
is case sensitive and hence use only lowercase letters). This will open a Simulink window as shown in Fig.2.
Now we can start building the models using Simulink.
STEPS TO BUILD A SIMPLE MODEL USING SIMULINK
We may follow the steps given below, in order to build a simple transfer function model of a linear
continuous time system.
1. To begin with
Start a Simulink session as given above.
2. Opening the Target window
Open a new model-window by clicking New icon the File menu as given in Fig.3
CLICK
HERE
Type simulink and
press ENTER key
Fig.1
Fig.2
One of
this will
start a
Simulink
session
CLICK
HERE
Fig.3
You get this
target model
window
ATM3
Fig.4
3. To construct the model
Drag the chosen block into the target model window using the mouse. For example, if we want to
simulate the Transfer function
4 2
1
) (
2
+ +
+
=
s s
s
s G , we may choose the block Transfer Fcn under
Continuous under Simulink. We may drag the mouse from Transfer Fcn to the target model window. We
will get a simple transfer function block. We may double click this icon of the block to get a Dialog box in
which we can the parameters as {Numerator [1 1] and Denominator [1 2 4]} and applying it by clicking on
the Apply button of the Dialog box. We will get a screen as shown in Fig. 4.
4. To add Source & Sink
Source is the block corresponding to the source of signal. A number of blocks are available under
this category. We have to choose the appropriate block for the given simulation case. For example we may
choose Step under Sources under Simulink for the above case.
Similarly, sink is block pertaining to the destination to which the simulation results have to be sent
during the course of simulation. Scope is a block analogous to the CRO, using which we can view the
progress of the simulation. Output can be sent to file or MATLAB WORKSPACE also.
We may choose the Scope as the sink and Step as the source. We will get a Simulink model as
shown in Fig.5. Blocks are interconnected using lines. The connecting line from an output poit to an input
point can be drawn by holding down the mouse button and dragging the mouse cursor from starting point ot
eh ending point. An arrow will appear to show the direction of the signal flow. Obviously, we have to drag
the mouse in the intended direction of signal flow.
In the example model being built, the output of the source is joined with the input of the Transfer
Fcn block and then the output of the Transfer Fcn is connected to the scope as shown in Fig.5.
This completes the construction of the block diagram in Simulink. The analysis/simulation can be
done by running the simulation using the simulation option from the menu bar as given below.
Fig.5
ATM4
TO RUN A SIMULATION
For running the simulation of a model, we have to choose the Start option under the Simulation
menu from the Menu bar of the model window. Before we could run a trial simulation, we have to set the
parameters of the various blocks. For the above case we may follow the steps as given below.
1. Double click on the Step block to get its Dialog box. Set the step time, Initial value, Final value and
step size as 0,0 10 and 0.1 respectively. Apply it by clicking on the Apply button of the Dialog box.
Close the Dialog box.
2. Go to the Menu bar of the target window and pull down the Simulation menu.
3. Click on the Start option using the mouse. This will cause the simulation to run once.
4. Double click on the Scope block to view the output. We will get a display as shown in Fig.6.
CONSTRUCTING SOPHISTICATED & ADVANCED MODELS
In order to use Simulink for the analysis and simulation of sophisticated systems, it is advisable to
follow a bottom-up approach. We may segregate the complete system into subsystems and build them
separately, preferably on separate simulation target windows. There upon build the complete system on a
single window. We can exercise a control on the overall size of the model built on the window by using the
mask option. One has to be very thorough about the expected outcome of the simulation, so as to be able to
troubleshoot the model if any error warnings pop up during the run of the simulation. Simulink facilitates
repetition of the runs of the simulation any number of times.
TO IMPROVE SIMULATION PERFORMANCE AND ACCURACY
Simulation performance and accuracy can be affected by many factors, including the model design
and choice of simulation parameters. The Solvers handle most model simulations accurately and efficiently
with their default parameter However, some models will yield better results if we adjust solver and
simulation parameters. I addition, if we have information on the expected behaviours of the given model the
simulation can be improved by providing this information through the solver.
Some tips are:
i) Use the built-in Fcn block or Elementary Math block whenever possible.
ii) Adjust the maximum step size or use the default value by choosing auto.
iii) Reduce the time interval.
iv) Adjust the relative tolerance limits wherever admissible
v) Configure the S functions properly either as a subsystem or as a C-MEX S Function.
FOR IMPROVING ACCURACY
For a model that has states whose values approach zero, and if the absolute tolerance parameter is
too large, the simulation will take too few steps around areas of non-zero state values. Reduce this parameter
value or adjust it for individual states in the Integrator dialog box.
Fig.6
ATM5
If reducing the absolute tolerances do not sufficiently improve the accuracy, reduce the size of the
relative tolerance parameter to reduce the acceptable error and force smaller step sizes and more number of
steps.
ANALYSING SIMULATION RESULTS
Output trajectories from Simulink can be plotted using one of the three methods
Feeding a signal into either a Scope or an X-Y Graph block
Writing output to return values to MATLAB workspace memory using To Workspace blocks and
then plotting
Sending values to a file and then plotting later.
USE OF MASK TO BUILD COMPLEX MODELS
As mentioned earlier, when we have to simulate very complex systems, a straight forward
construction of model on the Simulink window may render a model which is too unwieldy and full view of
model will not be possible. We may have to often scroll up down left or right. There may also be situations
where a particular type of subsystem be not available in the set of blocks.
When the model is not limited to the viewable area of the screen, we may use the masking options.
When there is no suitable block User may create one using S-functions.
Masking is a powerful Simulink feature that enables us to customise the dialog box and icon for the
subsystems.
With masking we can:
Simplify the use of the models by replacing many dialog boxes in a subsystem with a single one.
Instead of requiring the user of the model to open each block and enter parameter values, those
parameter values can be entered on the mask dialog box and get it passed to the underlying blocks
in the masked subsystem.
Provide a more descriptive and helpful user interface by defining a dialog box with user defined
block description, parameter field labels and help text.
Define commands that compute variables whose values depend on block parameters.
Prevent unintended modifications of subsystems by hiding their contents behind a customised
interface.
Create a block icon that is relevant to the context of the subsystem.
To mask a block or set of interconnected blocks first select the subsystem using mouse, and choose Create
Mask option from the Edit menu. A Mask Editor dialog box will appear. The Mask Editor has three
pages, each handling a particular aspect of the mask. I.e.
Initialisation-This page is to define and describe mask dialog box parameter prompts, name the
variables associated with the parameters, and specify initialisation commands.
Icon- This can be used to define an icon for the masked subsystem
Documentation- This can be used to define the mask type, specify the block description and the
block help
CONDITIONALLY EXECUTED SUBSYSTEMS
There are a few options like Triggered Subsystems, Enabled subsystems, Trigger and Enable
subsystems which will help us to simulate systems which will need conditional execution.
An enabled subsystem executes when the enable signal is positive. A Triggered subsystem
executes once each time a Trigger Event occurs. A trigger event can occur on the rising or falling edge of
a trigger signal, which can be continuous or discrete.
A Triggered and Enabled Subsystem executes once on the time step when a trigger event occurs if
the enable control signal has a positive value at that step. The behaviour of this tyoe subsystems is a
compbination of the enabeled subsystem and the triggred subsystem as shown below.
ATM6
MUX
AND
DEMUX
The Mux block combines several input lines into one vector line. Each input line can carry a scalar
or vector signal. The output of a Mux block is a vector.
The Demux block separates a vector input signal into output lines, each of which can carry a scalar
or vector signal. Simulink determines the number and widths of the output signals by the Number of
outputs parameter and that of input to Mux by Number of inputs
THE POWER SYSTEM BLOCKSET
The Power System Blockset allows scientists and engineers to build models that simulate power
systems. The blockset uses the Simulink environment, allowing a model to be built using click and drag
procedures. Not only can the circuit topology be drawn rapidly, but the analysis of the circuit can include its
interactions with mechanical, thermal, control, and other disciplines. This is possible because all the
electrical parts of the simulation interact with Simulink's extensive modeling library. Because Simulink uses
MATLAB as the computational engine, MATLAB's toolboxes can also be used by the designer.
THE NONLINEAR CONTROL DESIGN BLOCKSET
The Nonlinear Control Design (NCD) Blockset offers time domain-based, robust, nonlinear control
design. Controller designs are developed as block diagrams in Simulink. You select a set of tunable model
parameters and graphically place time response constraints on selected output signals. Successive simulation
and optimization methods are applied automatically, thereby tuning the selected model parameters.
Simulink is required with the NCD Blockset
THE SIMULINK REAL-TIME WORKSHOP
The Simulink Real-Time Workshop
automatically generates C code directly from Simulink block

diagrams. This allows the execution of continuous, discrete-time, and hybrid system models on a wide range
of computer platforms, including real-time hardware. Simulink is required.
The Real-Time Workshop can be used for:
Rapid Prototyping. As a rapid prototyping tool, the Real-Time Workshop enables you to implement
your designs quickly without lengthy hand coding and debugging. Control, signal processing, and
dynamic system algorithms can be implemented by developing graphical Simulink block diagrams
and automatically generating C code.
Embedded Real-Time Control. Once a system has been designed with Simulink, code for real-time
controllers or digital signal processors can be generated, cross-compiled, linked, and downloaded
onto your selected target processor. The Real-Time Workshop supports DSP boards, embedded
controllers, and a wide variety of custom and commercially available hardware.
ATM7
Real-Time Simulation. You can create and execute code for an entire system or specified
subsystems for hardware-in-the-loop simulations. Typical applications include training simulators
(pilot-in-the-loop), real-time model validation, and testing.
Stand-Alone Simulation. Stand-alone simulations can be run directly on your host machine or
transferred to other systems for remote execution. Because time histories are saved in MATLAB as
binary or ASCII files, they can be easily loaded into MATLAB for additional analysis or graphic
display.
CLOSURE
Simulink provides the right set of tools for fast, accurate modelling and simulation. Simulink
features an extensive block library for building complex models, convenient tools for monitoring simulation
results, and tight integration with MATLAB for access to the most comprehensive collection of design and
analysis tools.
It helps us in building block diagrams, simulating the system's behaviour for evaluating its performance, and
to refine the design. Simulink integrates seamlessly with MATLAB, providing you with immediate access
to an extensive range of analysis and design tools. These benefits make Simulink the tool of choice for
control system design, DSP design, communications system design, and other simulation applications.
Have a nice simulation with Simulink
FACTS SIMULATION USING PSCAD/EMTDC
Dr R. Sreeram Kumar
National Institute of Technology, Calicut
1. Introduction
PSCAD/EMTDC is the professionals
simulation tool for analyzing power systems. PSCAD
is the graphical user interface and EMTDC is the
simulation engine. PSCAD/EMTDC is suitable for
simulating the time domain instantaneous responses,
the electromagnetic transients, of electrical power
systems with FACTS equipment. The PSCAD
Graphical Interface greatly enhances the power of
EMTDC. It allows the user to schematically
construct a circuit, run a simulation, analyze the
results, and manage the data in a completely
integrated graphical environment. The following are
some of the common components found in systems
studied using PSCAD/EMTDC:
Resistors (R), inductors (L), capacitors (C)
Mutually coupled windings such as transformers
Frequency dependent transmission lines and
cables
Current and voltage sources
Switches and breakers
Diodes, thyristors and GTOs
Analogue and digital control functions
Ac machines, exciters, governors, and stabilizers
models
Meters and measuring functions
Generic DC and AC controls
HVDC, SVC, and other FACTS controllers
2.Typical Studies Conducted using
PSCAD/EMTDC
The following are samples of types of studies that can be
conducted using EMTDC.
Contingency studies of AC networks consisting
of rotating machines, exciters, governors, turbines,
transformers, transmission lines, cables and loads
Relay coordination
Transformer saturation effects
Insulation coordination of transformers, breakers
and arrestors
Impulse testing of transformers
Sub-synchronous resonance (SSR) studies of
networks with machines, transmission lines and
HVDC systems
Evaluation of filter design and harmonic analysis
Control system design and coordination of
FACTS and HVDC; including STATCOM, VSC and
cycloconverters
Optimal design of controller parameters
Investigation of new circuit and control concepts
Studies to determine the worst case over voltage
due to lightning strikes, faults or breaker operations.
3. Features of PSCAD
Multi-platform: PSCAD is available for use on
all Windows operating systems
Totally Integrated: You can put run-time plots
alongside the circuit or arrange them on a separate
page. Circuits, plots and descriptive comments can
all be printed together.
Modular: Electrical systems can be split into
different modules (or pages) without having to
connect them using transmission lines. Control
systems can be modeled in separate modules as in
earlier versions.
Hierarchical: Circuits assembled using basic
building blocks can be contained inside modules
(also called pages), which can in turn contain more
such modules. Simply double-click on one of these
modules to see the circuit inside.
Online information: Point to any circuit
component and you will get useful information about
such topics as the circuit connection, short
component help, simulation data such as node voltage
if the case is running, etc.
HTML Help: All the detailed online help is
written in HTML. It is fast, portable and easy to
maintain. Users can write these help pages for their
own components very easily.
Graphical Component Design Tool: You can
design your PSCAD components in a completely
graphical environment called Component Workshop.
This is the tool used to write/edit all the components
in the Master library.
Multiple Libraries and Cases in a Project: Now
you can easily build cases that depend on multiple
libraries and simultaneously load multiple cases.
Thus, you can copy circuit components from one case
and paste them into another easily.
Multilevel Zoom and Split Views: You can
zoom in on the entire circuit as well as selectively
SRK- B1
zoom in on selected plots. A single circuit can be
displayed in multiple views, each with a different
zoom level.
Sequencer Components: You can now monitor
and control asequence of events easily using the
library of Sequence Components. They can be used
to set up complex sequences to control the
application of faults, opening/closing of breakers, and
waiting for events (such as a zero crossing).
4. Features of EMTDC
Faster Solution and Memory Efficient
Storage: Computationally intensive parts of
EMTDC are rewritten to maximize the speed.
Network branch models and transmission line models
are internally reorganized to provide memory
efficient storage.
Dynamic Dimensioning: EMTDC is written in
a FORTRAN 77 and FORTRAN 90 compliant
model. When used in FORTRAN 90 mode, it
dynamically allocates network dimensions to exactly
fit the simulation requirements. This enables you to
model much larger cases compared to FORTRAN 77
mode before you run out of computer memory.
Ideal Branches: You can model infinite voltage
sources, infinite transmission lines and cables, ideal
ammeters and zero resistance switches. There is no
restriction on how many such elements you can have
in series and parallel.
Interpolation with Instantaneous Switch
Algorithm: EMTDC interpolates the solution
between two time steps to find the solution at the
exact instant of the event. The instantaneous Switch
algorithm virtually eliminates losses due to
interpolation, producing very accurate results.
MATLAB Interface: You can simulate all or
part of the controls in MATLAB and interface it to
the rest of the system simulation in PSCAD/EMTDC.
You can process or plot EMTDC results in MATLAB
interactively.
5. Component Library
Components are the basic building blocks of
PSCAD circuits. Fig. 1 shows the major components
of PSCAD. A component can have external
connection points, which can be input, output and
electrical types. In addition, it can have internal
parameters for inputting model data. Each
component is usually designed to perform one
specific function. Double clicking on a component
opens its parameters.
6. Circuit Simulation using PSCAD/EMTDC
Double click on PSCAD icon: Start PSCAD
Select file & click on load project
: Load an existing case (with psc extension)
Open tutorial directory and click on Vdiv-1.psc
* [ The project tree will now show this project Vdiv-
1.psc ]
Double click on the title to open and view the
circuit.
[ In the circuit, since V
source
= 1 and V
load
= V
source/2
.
This voltage is measured using a volt meter V
mid
connected to the node between the source and the
load. I
load
= E
source
/ (R
source
+ R
load
)]
Double click on the source component to view
its data. [Note that V
source
= 70.71 kV rms or
100 V peak]
Click anywhere in the empty space to de-select
the selected component.
Click the RUN Button to run the simulation
(Watch the graphs as the simulation progress. At the
end of the run, the message EMTDC run completed
will appear].
7. Creating a New Case
Select file and click on Create New
Project (By default, the new project is labeled no
name.psc. This will appear as the las project on the
project tree.
Click the right mouse button on
noname.psc and select properties.
Click inside the Description field and
type a name for the case, say, Voltage Divider.
(You can accept the rest of the default settings on this
form for the time being. The case is set up to run for
0.5 seconds with a 50 microsecond time stop)
Right click on the case name in the
project tree and select save project as
Type the name of the file as test.psc.
Double click on test.psc in the project
tree with the left mouse button to open the main page
of your case.
Double click on Master-Library to
open the same.
8. Typical Functions
Resizing Wires: The wire component is a special,
built-in component that is resizable in length. Press
the left mouse button close to either end of the wire
and drag the mouse. If the entire wire moves you
were not close enough to the end. Let go the button
and repeat the operation closer to the end. As the
wire is resizing, move the mouse along the length of
SRK- B2
the wire this will simply change its length. However,
if you move the mouse in a circle around the opposite
end of the wire, you can rotate it while resizing.
Editing Component Parameters: Nearly all
components have editable parameters. The
parameters are in the form of editable text fields, drop
down lists or radio buttons. To change a value in the
text field, click inside the white field and type the
value. The drop down list has a downward pointing
arrow on the right hand side. Click on that arrow to
see the list and click on the required item. To select a
radio button, click on the item.
Viewing and Editing Component Parameters: To
view/edit component parameters, double click on it.
Or select the Edit Parameters from its component
menu. This will open the component parameters
dialog. The component name is displayed on the top
bar of this dialog. Click in the data field and enter
the value. Most of the fields have a default value and
[unit] where applicable. Make sure that you enter the
value in the right unit as displayed.
Editing Multiple Components: Many of the basic
circuit design commands such as cut, copy, paste,
move and rotate can be applied on a selection of
multiple components.
Selecting Multiple Components: To select multiple
components, press and hold the left button on an
empty space and drag the mouse. You will see a
selection rectangle stretching with the cursor. Stretch
it so that all the components to be selected are
completely enclosed. Components that are partially
enclosed are not selected. The selected components
flash to confirm that they are selected.
Including or Excluding components from Selection:
To add a component to the selection or to remove it
from the selection, hold the SHIFT key down and
click the left button on the component. If the
component is already flashing (selected), it will stop
flashing, signifying that it is deselected, otherwise it
will be added to the selection and will start flashing.
This is particularly an essential operation when you
want to select components that are scattered around.
Editing a Selection: Click the right button on any of
the flashing components and select the desired menu
item from the pop up menu.
Electrical and Data Wire: A wire is a special
component that is used for connecting two points on
the page and assumes its property based on what it is
connected to. A wire connecting electrical nodes
becomes an electrical wire (bus) and a wire
connecting non-electrical nodes becomes a data wire.
Connecting an electrical node to a non-electrical node
using a wire is not permitted. An electrical wire can
be considered as a zero resistance conductor used in
building the electrical network. A node label may
be placed on an electrical wire to name the bus.
Electrical wires have a voltage, with respect to
ground and can be viewed on the flyby message
window. Data wires are used for building the controls
part of the power system and they carry control data
during a simulation. Only a single component can be
the source of data for a data wire, but several
components may be recipients or sinks. The data
wire assumes the type of the source signal which can
be REAL, INTEGER. A data label placed on a data
wire gives the data source a signal name. Once a data
source is labeled, you can use that data label name
anywhere in the circuit to receive and use that
signal.To pass data from one page to another, it must
be exported on the page with the component that
generates the data, and imported on the pages where
it is required.
9. Monitoring Quantities in PSCAD
For the PSCAD simulation software to be
useful, access to the information generated during the
simulation must exist. For a simple circuit, it is
theoretically possible to store all the simulation data
for every time-step of the simulation; for more
complex circuits, this would consume a lot of
computer resources and unnecessarily slow down the
simulation. For these reasons, PSCAD lets the circuit
designer select the quantities that are to be monitored.
These quantities are either collected by EMTDC
throughout the simulation and can be sent to PSCAD
(plot, meter, and flyby) on demand or they are
outputted into a file at the end of the run. There is no
limit on the number of quantities that can be
monitored; however monitoring does have an impact
on the simulation speed.
10. ASSEMBLING THE VOLTAGE
DIVIDER CASE
The voltage divider circuit in this example
uses eight different components. Locate these
components in the Master Library. When you double
click on the Master Library target on the Project
Tree, the main page of the library that contains all
these components opens.
Saving the Circuit: Whenever changes are made to a
case, its title in the Project Tree will turn red. To
save the changes, click the right mouse button on the
case title, Voltage Divider, in the Project Tree and
SRK- B3
left click on the item Save. The title will return to its
regular mode. This means that the case is saved to
disk.
Running Your Case: Finally, click on the menu
button with the picture of the green arrow (at the top
of the PSCAD window) to compile and run the case.
This is the last step, assuming there are no errors. If
there are any errors, they will be logged in the
Message Tree. By default, the message tree window
is situated at the bottom left corner of PSCAD
window. However, it can be moved, resized or
closed. If you cannot locate the message window,
select it from top menu bar using View => Messages
menu. Resizes and move the windows as desired.
11. Plotting in PSCAD
Creating a New Plot: To create a new plot with a
signal, right click on Output Channel component
marked with Mid Point Voltage, and select
Input/Output Reference => Create new plot with
signal.
The Plot Menu: The above menu action creates and
empty plot labeled Untitled next to your cursor. Plot
is a complex component with many features and has
its own special menu referred to as the Plot Menu.
Right click on the plot title bar (top bar on the plot)
and the plot menu will pop up.
Plot Properties: Select Plot Properties from the plot
menu to change the title. When the Plot Properties
dialog appears, click in the Title box and replace
Untitled with Currents and Voltages. Accept the
default settings for the rest of the parameters. Click
on OK button at the bottom of the dialog to save the
changes and close the dialog. We will learn more
about plots from the online help on plots at a later
time.
Resizing the Plot: To resize the plot, press the left
mouse button on any corner of the plot, say button
right, and drag the mouse diagonally away from the
plot. If the entire plot moves, it means you were not
close enough to the corner. Let go of the mouse
button and repeat the operation from closer to the
corner. Resize the plot to approximately 3x3 inches.
Graphs: A plot is MERELY A CONTAINER THAT
CAN HOLD MULTIPLE GRAPHS AND EACH
GRAPH CAN CONTAIN MULTIPLE CURVES.
Next, we have to add graphs inside this plot and
curves inside those graphs.
Adding a Graph to the Plot: To add graphs to a plot,
right click on the plot title the Add => Graph menu
item. This will insert a new plot. Repeat this to
insert the second graph. Voltage in the top graph and
Current in the bottom.
Graph Properties: To customize the graph title and
vertical axis label, right click on the top graph (white
space in the center of the graph) and select Graph
Properties Enter Voltage in the Title box where it
says no name and click the button Edit_Y_Axis and
enter kV in the Label field. Click OK and select the
second graph titled noname. Enter Current for the
title and kA for the vertical axis label.
Curves: Now we have to associate the current signal
measured on the circuit to the second graph. This is
done in two steps. First we have to create a curve
reference to the monitored signal on the circuit and
then paste it inside the graph.
Step 1: Creating a Curve Reference
To create a curve reference to the Load Current
signal, right click on the Plot Channel component that
is connected to the load signal, then click on the
menu item Input/Output Reference => Add as
Curve.
Step 2 : Pasting the Curve Reference into the
Graph
To paste this reference into the graph, right click on
top of the graph entitled Currents and select Paste
Curve from the pop up menu.
Now you should have a plot entitled Currents and
Voltages containing two graphs namely, Current and
Voltage. The Voltage graph contains Midpoint
Voltage curve and the Current graph contains Load
Current curve. When you run the simulation, you
will be able to see these curves.
Help on Plots, Graphs and Curves: We have
discussed only those features of plots, graphs and
curves that are essential to this example in this
chapter. There are a lot more features that you
should be aware of to make effective use of them.
For a detailed help, right click anywhere on the plot
and select Help from the pop up menu.
Reference
1. PSCAD/EMTDC (Version 3.0) Reference
Manual, Manitoba HVDC Research Centre Inc.,
Canada
SRK B4
SK15 1
INTRODUCTION TO MICROSIM DESIGN LAB 8.0 PART I
Suresh Kumar.K.S
Asst.Prof.,Dept.of Elect. Engg.,
N.I.T Calicut
1. Introduction
MicroSim Design Lab 8.0 is an EDA (Electronic Design & Analysis) Suite based on PSpice
brought out by M/s MicroSim Corporation originally. MicroSim merged with ORCAD recently and this product
with few modifications is available now from M/s ORCAD.
A full installation of Design Lab 8.0 will install MicroSim Schematics, MicroSim PSpice A/D,
MicroSim PSpice Optimizer, MicroSim Plogic, MicroSim PLSyn, MicroSim Parts, MicroSim Probe, MicroSim
Stimulus Editor, MicroSim PCBoards, SPECCTRA Autorouter and the model libraries. This introduction will
deal only with Schematics, PSpice A/D and Probe mainly with cursory coverage on Stimulus Editor and Parts
routine.The remaining components of Design Lab are beyond the scope of this introductory lecture.
The interaction between various programs in the Design Lab is shown in the Fig.1 below.
Fig.1 Flow Diagram showing Program Interactions in Design Lab
2. Who Does What in Design Lab?
PSpice A/D does the most important job of solving the equations describing the circuit to be
simulated and preparing the output data i.e it does all the analysis. But it asks for many files related to the circuit
before it can start simulating. These files are described below.
The primary circuit file contains analysis commands and references to netlist, alias, model and
other files required by the circuit to be simulated. I t has .cir as its extension. The second file needed is the netlist
file that contains the components and connections of the circuit and goes with the extension .net. The third file is
the alias file with the extension .als. The PSpice program also calls for model files-both primitive device models
and subcircuit definitions. Though PSpice provides standard stimulus functions for use in the circuit, custom
made voltage and current waveforms may need to be used in some simulation studies. Design Lab permits
synthesis of such user defined stimulus functions in an Interactive Graphic program called Stimulus Editor. The
stimulus function drawn and saved in this editor will have the extension .stl and the PSpice A/D will ask for these
files too.
The Schematics program is the one that prepares all these files for PSpice A/D .It is a visual
interface to the whole of Design Lab. The circuit to be simulated is first drawn in this interface by drawing
element symbols from the part library, editing their attribute values, making interconnections between elements
SK15 2
etc. A symbol may be edited for changing its graphics if necessary by invoking the Symbol Editor from
Schematics .In fact Schematics is the general entry point into the whole of Design Lab and all other programs
can be started from Schematics .The commands to start all other programs are available as various menu entries
in Schematics. After preparing the diagram, the circuit thereby constructed ,will have to be checked for electrical
rule consistency. Running Electrical Rule Check or Net List from analysis menu in Schematics does this.
If the net listing is error free the .net,. cir and .als get written at this stage. Invoking Simulate command from
the analysis menu will start PSpice A/D and simulation will proceed to completion if there are no run time errors.
The Schematics program supports all Windows features like copy, cut, paste, print etc from the
application environment. Cross application copy/cut/paste is allowed in a limited sense in that the circuit
diagram or its parts can be copied into windows clipboard by specifically invoking Copy to Clipboard
command under Edit menu; but clipboard contents from other applications can not pasted into Schematics
window.
The analysis options (which analysis is to be carried out, what kind of outputs are to be
generated, what error tolerances are to be used, what kind of control is needed on the simulation time step etc.)
are to be selected before netlisting is done. Similarly the settings needed by the Probe program also are to be
done from Schematics. All the menu commands needed for this come under the Analysis/Setup submenu. It is
possible to put voltage markers and current markers in the circuit diagram so that when the output visualisation
program Probe starts up later it will know which waveforms to show by default. Also it is possible to make
Probe show a particular waveform by double clicking on the marker placed on the corresponding variable in the
Schematics window.
The figure shows a very useful single phase rectifier with passive power
factor correction. This circuit is used in many Electronic Fluorescent Lamp Ballasts available in the market. The
diagram was prepared in Schematics and Copy to Clipboard from Edit menu in Schematics and Paste from Edit
menu of Microsoft Word brought this figure into this lecture note. The circuit file-set for this circuit was
prepared by running Net List from Analysis menu of Schematics. Design Lab includes its own text editor
called MicroSim Text Editor. The three circuit files, namely lamppfc.cir, lamppfc.als and lamppfc.net were
viewed in this text editor and copied from there and pasted below.
Lamppfc.cir
* D:\Msim Projects\lampPFC.sch
* Schematics Version 8.0 - July 1997
* Sun Feb 20 03:02:39 2000
** Analysis setup **
.tran 20us 100ms 0 20us
.OP
* From [SCHEMATICS NETLIST] section of msim.ini:
.lib "D:\MSim_8\UserLib\MyBlocks.lib"
.lib "D:\MSim_8\lib\nom.lib"
.INC "lampPFC.net"
.INC "lampPFC.als"
.probe
.END
SK15 3
Lamppfc.als
* Schematics Aliases *
.ALIASES
D_Diode1 Diode1(1=$N_0001 2=Output )
D_Diode3 Diode3(1=0 2=$N_0002 )
D_Diode4 Diode4(1=0 2=$N_0001 )
C_Cbulk1 Cbulk1(1=Output 2=$N_0003 )
C_Cbulk2 Cbulk2(1=$N_0004 2=0 )
R_Rload Rload(1=Output 2=0 )
D_Dout1 Dout1(1=0 2=$N_0003 )
D_Dout2 Dout2(1=$N_0004 2=Output )
D_Dcharging Dcharging(1=$N_0005 2=$N_0004 )
R_Rlimit Rlimit(1=$N_0003 2=$N_0005 )
V_Vsource Vsource(+=Input -=$N_0002 )
L_Linput Linput(1=Input 2=$N_0001 )
_ _(Output=Output)
_ _(Input=Input)
.ENDALIASES
Lamppfc.net
* Schematics Netlist *
D_Diode1 $N_0001 Output D1N4007
D_Diode3 0 $N_0002 D1N4007
D_Diode4 0 $N_0001 D1N4007
C_Cbulk1 Output $N_0003 47uF IC=150
C_Cbulk2 $N_0004 0 47uF IC=150
R_Rload Output 0 1k
D_Dout1 0 $N_0003 D1N4007
D_Dout2 $N_0004 Output D1N4007
D_Dcharging $N_0005 $N_0004 D1N4007
R_Rlimit $N_0003 $N_0005 22
V_Vsource Input $N_0002
+SIN 0 320 50 0 0 0
L_Linput Input $N_0001 10mH
These files reveal what in general circuit files will contain. Of course one is free to write these
files in some text editor program without drawing the circuit in Schematics. Only that one has to be very familiar
with the syntax of files and one has to have genuine hatred for the Mouse! Otherwise there is no reason for
subjecting oneself to quite unneeded inconveniences. The PSpice A/D program does not mind us preparing the
circuit files outside Schematics.
The simulation in PSpice A/D results in two output files-one with .out extension and the other
with .dat extension. The first one can be opened with MicroSim Text Editor or by any other text editor for that
matter and it will contain all the information contained in the three circuit files and in addition results of d.c and
small signal bias solutions, initial transient solution etc. It will also report the total time taken for the number
crunching. It will contain details of the error conditions that PSpice faced before quitting on error. The .out file
for the circuit above is given below.
**** 02/20/100 03:48:50 **** Win95 PSpice 8.0 (July 1997) ***** ID# 97696 ****
**** CIRCUIT DESCRIPTION
****************************************************************************
* Schematics Version 8.0 - July 1997
* Sun Feb 20 03:02:39 2000
** Analysis setup **
.tran 20us 100ms 0 20us
.OP
* From [SCHEMATICS NETLIST] section of msim.ini:
.lib "D:\MSim_8\UserLib\MyBlocks.lib"
SK15 4
.lib "D:\MSim_8\lib\nom.lib"
.INC "lampPFC.net"
**** INCLUDING lampPFC.net ****
* Schematics Netlist *
D_Diode3 0 $N_0002 D1N4007
D_Diode4 0 $N_0001 D1N4007
C_Cbulk1 Output $N_0003 47uF IC=150
C_Cbulk2 $N_0004 0 47uF IC=150
R_Rload Output 0 1k
D_Dout1 0 $N_0003 D1N4007
D_Dout2 $N_0004 Output D1N4007
D_Dcharging $N_0005 $N_0004 D1N4007
R_Rlimit $N_0003 $N_0005 22
V_Vsource Input $N_0002
+SIN 0 320 50 0 0 0
L_Linput Input $N_0001 10mH
**** RESUMING lampPFC.cir ****
.INC "lampPFC.als"
**** INCLUDING lampPFC.als ****
* Schematics Aliases *
.ALIASES
D_Diode3 Diode3(1=0 2=$N_0002 )
D_Diode4 Diode4(1=0 2=$N_0001 )
C_Cbulk1 Cbulk1(1=Output 2=$N_0003 )
C_Cbulk2 Cbulk2(1=$N_0004 2=0 )
R_Rload Rload(1=Output 2=0 )
D_Dout1 Dout1(1=0 2=$N_0003 )
D_Dout2 Dout2(1=$N_0004 2=Output )
D_Dcharging Dcharging(1=$N_0005 2=$N_0004 )
R_Rlimit Rlimit(1=$N_0003 2=$N_0005 )
V_Vsource Vsource(+=Input -=$N_0002 )
L_Linput Linput(1=Input 2=$N_0001 )
_ _(Output=Output)
_ _(Input=Input)
.ENDALIASES
**** RESUMING lampPFC.cir ****
.probe
.END
_
**** Diode MODEL PARAMETERS
****************************************************************************
D1N4007 D1N4001
IS 14.110000E-09 14.110000E-09
N 1.984 1.984
IKF 94.81 94.81
BV 1.500000E+03 75
IBV 10.000000E-06 10.000000E-06
RS .03389 .03389
TT 5.700000E-06 5.700000E-06
CJO 25.890000E-12 25.890000E-12
VJ .3245 .3245
M .44 .44
SK15 5
**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C
****************************************************************************
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(Input) 74.7280 (Output) 149.2000 ($N_0001) 74.7280
($N_0002) 74.7280 ($N_0003) -.7969
($N_0004) 150.0000 ($N_0005) -.7969
VOLTAGE SOURCE CURRENTS
NAME CURRENT
V_Vsource 0.000E+00
TOTAL POWER DISSIPATION 0.00E+00 WATTS
**** OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C
****************************************************************************
**** DIODES
NAME D_Diode1 D_Diode2 D_Diode3 D_Diode4 D_Dout1
MODEL D1N4007 D1N4007 D1N4007 D1N4007 D1N4007
ID -1.42E-08 -1.42E-08 -1.42E-08 -1.42E-08 7.46E-02
VD -7.45E+01 -7.45E+01 -7.47E+01 -7.47E+01 7.97E-01
REQ 1.00E+12 1.00E+12 1.00E+12 1.00E+12 6.88E-01
CAP 2.36E-12 2.36E-12 2.36E-12 2.36E-12 8.28E-06
NAME D_Dout2 D_Dcharging
MODEL D1N4007 D1N4007
ID 7.46E-02 -1.43E-08
VD 7.97E-01 -1.51E+02
REQ 6.88E-01 1.00E+12
CAP 8.28E-06 1.73E-12 _
**** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C
****************************************************************************
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
(Input) 74.7280 (Output) 149.2000 ($N_0001) 74.7280
($N_0002) 74.7280 ($N_0003) -.7969
($N_0004) 150.0000 ($N_0005) -.7969
VOLTAGE SOURCE CURRENTS
NAME CURRENT
V_Vsource 0.000E+00
TOTAL POWER DISSIPATION 0.00E+00 WATTS
JOB CONCLUDED
TOTAL JOB TIME 29.36
The other output file with .dat extension contains all the simulation output of variables of the
circuit. The simulation algorithm is a variable step integration algorithm. But the data file will contain values
written at equal intervals of time. The print step i.e. the time increment used in writing the values into the .dat
file is set in analysis/setup menu in Schematics program. Also the Probe Set Up submenu under Analysis
menu in Schematics will ask for our decision on whether we want all the circuit variables written into the .dat
file or only those variables that we have marked using markers in the circuit diagram. Also, there is a provision
to skip the data till a specified time point in the Analysis/set up menu in Schematics. All these points are vital
in controlling the .dat file size. It takes only a few simulation runs (and may be an hour) of a somewhat complex
circuit to fill up the hard disk and make the PC crawl if all the variables are written into .dat file at too small a
print step with a too long a simulation final time! Even if the hard disk has ample space, it takes unbearably long
time to load large .dat files into the Probe program and display update in that program can be excruciatingly
slow if the .dat file is much bigger than the RAM size of the PC.
Only the Probe data visualisation program can open these files. Waveforms can be observed,
analyzed, modified and printed from this program. It can be set up to run automatically at the start of simulation
or after the simulation from Schematics. It can also run independent of other Design Lab programs and output
data analysis can be done provided the required data file has been created already as a result of a simulation run.
SK15 6
Note that the .dat file created in one simulation run gets overwritten as soon as another simulation run on the
same circuit. If the .dat file from a run has to be saved for future use it has to be saved under a different name
before running another simulation of the same circuit.
Fig.3 Sample Output from Probe Program for the Circuit in Fig.2
The above figure reveals the basic capability of Probe in displaying the waveforms and doing
a Fourier analysis on them. The same data file was opened in two windows in the program (the program supports
multiple windows) and Fourier analysis option was activated in one window. By the way, notice that the a.c line
current has very good power factor and much reduced harmonic content compared to a traditional single-phase
rectifier.
3. More About Schematics Program
3.1 Symbol & Model Library
A part available from part browser in Schematics program for placement in a circuit diagram
has three two major dimensions as far as circuit simulation is concerned. The first is the graphic appearance it
has along with its changeable and fixed attributes. The second is its model i.e. its behavioral description in
PSpice syntax. Both informations are placed in suitable files in the Msim_8/lib directory of the program. The
first dimension is available in a file with extension .slb and the model information is available in .lib extension.
For example the file opamp.slb contains the symbols of many opamps and the corresponding models are
available from opamp.lib.
It is not enough to have the libraries in the disk; it is necessary to configure the libraries for use
by the Schematics program. Opening the editor configuration dialog box from options/editor configuration
submenu in Schematics program after it starts up for the first time does this. The library path is to be entered in
the box provided for that purpose. After setting the library path go to library setting dialog box. The dialog
boxes are shown in the next page. The available libraries are listed in the list box (or can be brought up by
browsing) and they are to be added to the list of configured libraries by clicking on the needed library and then
clicking on add local or add*. If library is added locally, this library will be configured and loaded by the
Schematics program only when the particular .sch file i.e. the particular circuit diagram which was being
prepared at the time of adding this library i.e., the library is purely local to that circuit alone. On the otherhand, if
added globally (add*) that library will be configured and loaded every time Schematics program is started and
will be available to any circuit project. The package extension .plb need not be added unless the installation
includes PCB Software and Autorouter also. Browsing in the Library Setting dialog box may bring up libraries
which are not identified in the library path setting in the parent dialog box i.e. in the Editor Configuration Box.
It is also possible to add library files from such a library directory either locally or globally. But since the
directory is not listed in the path setting , the program will return unable to find library path error every time it
SK15 7
starts up. So the first thing to do is to enter the directory path from which we want to configure libraries to the
library path list.
3.2 The Symbol Editor
When a part is placed in the schematics it becomes an instance of the part. It is possible and it
is needed to change one or more attributes of the part instance before the schematic is ready for simulation. For
example the figure below shows the dialog box for a resistor instance (obtained by double clicking on it after
placing it in the schematic).
The box shows all the
attributes including the
ones that can not be
changed from the
Schematics program (the
ones with asterisk). The
only ones to be changed
are the value of the
resistor and the packages
reference (the last entry
which is not visible in the
figure). Obviously the
changes made from
schematic can be saved
only in the instance part
and not to the part in the
library. And it should be
so. But what if we want to edit the attributes of some symbol and save it to the library so that the changes
(changes in graphics or attributes, addition or deletion to the attribute list, changes in pin configurations etc.)
made will be effective for all instances of the concerned part? What if we want to create a new symbol and add it
to the library? And what if we want to create a new library of new symbols? That is when we need the Symbol
Editor program. This program can be started by choosing to edit an already placed symbol in the Schematics
program or by choosing File/Edit Library submenu in the same program.
3.3 Hierarchical and Multi Page Designs
Not all designs can be drawn in a single page. Not all designs can be visualised in a single
layer since there will be too many details cluttering vision in every sense. It is only natural on the part of an
intelligent designer to think of a hierarchical approach to the problem of a complex design. And Schematics
permits this. We can draw the system using functional blocks and define it as the top layer. Then each block may
be pushed into ('push' is a submenu available under navigate menu of the program) and the detailed circuit in
each block may be put together. Of course, the detailed circuit inside a block in the top layer may in its turn
SK15 8
contain blocks that may have to be pushed into to see the details. And, so on to as many levels of hierarchy as
needed. The technique described just now involves drawing blocks first and then getting down to filling them up
with circuits and/or further blocks. This is the so-called Top-Down approach.
The opposite approach is also possible in Schematics. In the Bottom-Up method the detailed
circuits, based on functions performed by them, will be assembled separately. Then they will be converted into
hierarchical symbols by using File/Symbolize submenu in Schematics. Later these hierarchical symbols will be
assembled together to form the top layer of the system. The menu Navigate and its submenu items deal with
the navigation in the layers of a hierarchical design.
Different schematics at different levels of the same hierarchical design or of another design
may make use of hierarchical blocks that contain same sub-schematic inside. But if any of them is pushed into
and edited then the changes made will be effective for all the blocks using this underlying schematic. Similarly
hierarchical symbols may also be used many times in the same design or in different designs. But all of them
map to same entity and any editing done on the internal circuit of a hierarchical symbol from any schematic will
enforce those changes every where that symbol is used. In this sense the hierarchical symbols created by users is
very much different from the symbols available from a library.
Even with hierarchical approach, it may not be possible to draw the entire design in one page.
Schematics allow multi page design and off-page connector symbols allow signal passing between pages. Global
off-page connectors with a common label connect the points in different pages together even if these points
belong to different layers of the hierarchical design. Local off-page connectors of same label connect points in
different pages only if the pages belong to the same level in a hierarchical design.
3.4 Model Files and Model Editing
Usually; but not always, a symbol is associated with a model. Models define the electrical
behaviour of parts or subcircuits for simulation. Two kinds of models are in use. The first is the so-called
primitive spice device models and goes with a declaring statement of .MODEL .The second kind of model
definition is a subcircuit definition and it describes the behaviour of the candidate part in terms of a circuit
description employing PSpice devices i.e. the ones which have primitive device models. This kind of model will
go with a .SUBCKT/.ENDS construct.
An example of a .MODEL definition is given below.This is included in the model library file
diode.lib. Library files can be opened with any text editor.
.MODEL D1N4148/TEMP D (
+ IS = 1.27106E-8
+ RS = 0.7546332
+ N = 1.9215823
+ TT = 3.679E-9
+ CJO = 1.72434E-12
+ VJ = 0.3026211
+ M = 0.2
+ EG = 1.11
+ XTI = 3
+ KF = 0
+ AF = 1
+ FC = 0.998001
+ BV = 1E5
+ IBV = 1.0E-10
+ )
*$
An example for a SUBCKT definition type MODEL file of an opamp is given below. This was
taken from the file opamp.lib opened in Wordpad.
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt mc1741 1 2 3 4 5
*
c1 11 12 8.660E-12
c2 6 7 30.00E-12
dc 5 53 dy
SK15 9
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2),(3,0),(4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 42.44E6 -1E3 1E3 42E6 -42E6
ga 6 0 11 12 188.5E-6
gcm 0 6 10 99 5.961E-9
iee 10 4 dc 15.16E-6
hlim 90 0 vlim 1K
q1 11 2 13 qx
q2 12 1 14 qx
r2 6 9 100.0E3
rc1 3 11 5.305E3
rc2 3 12 5.305E3
re1 13 10 1.837E3
re2 14 10 1.837E3
ree 10 99 13.19E6
ro1 8 5 25
ro2 7 99 25
rp 3 4 18.16E3
vb 9 0 dc 0
vc 3 53 dc 1
ve 54 4 dc 1
vlim 7 8 dc 0
vlp 91 0 dc 20
vln 0 92 dc 20
.model dx D(Is=800.0E-18)
.model dy D(Is=800.00E-18 Rs=1m Cjo=10p)
.model qx NPN(Is=800.0E-18 Bf=93.75)
.ends
*$
It is
possible to edit the
model associated with
a symbol placed in a
schematic by selecting
it and invoking
Edit/Model submenu.
It is even possible to
associate an entirely
different model. But
whether editing or
complete change, it
will be valid only for
the instance part and
not for the library part.
This editing can be
done by the Model
Editor in the text
editing mode or by the
Parts program if that
particular part is
supported by that
program. The Model
Editor window is shown in the last page. Model Editor can be opened from the Symbol Editor window too. But
the model editing done within the Symbol Editor window is global i.e. it changes the library itself.
================
SK16 1
INTRODUCTION TO MICROSIM DESIGN LAB 8.0 PART II
Suresh Kumar.K.S
Asst.Prof.,Dept.of Elect. Engg.,
N.I.T Calicut
1. The MicroSim PSpice A/D Program
MicroSim PSpice A/D is a simulation program that models the behavior of a circuit containing
any mix of analog and digital devices. Used with MicroSim Schematics for design entry, we can think of PSpice
A/D as a software-based breadboard of our circuit that we can use to test and refine our design before ever
touching a piece of hardware by running basic and advanced analyses PSpice A/D can perform. Such analyses
that this program can perform are:
DC, AC, and transient analyses, so we can test the response of our circuit to different inputs.
Parametric, Monte Carlo, and sensitivity/worst-case analyses, so we can see how our circuits behavior
varies with changing component values.
Digital worst-case timing analysis to help we find timing problems that occur with only certain
combinations of slow and fast signal transmissions.
1.1 Analyses We Can Run with PSpice A/D
1.1.2 Basic Analyses
DC sweep & other DC calculations
These DC analyses evaluate circuit performance in response to a direct current source.
DC Analysis Types
DC Sweep - Steady-state voltages, currents, and digital states when sweeping a source, a model parameter, or
temperature over a range of values.
Bias point detail - Bias point data in addition to what is automatically computed in any simulation.
DC Sensitivity - Sensitivity of a net or part voltage as a function of bias point.
Small-signal DC transfer - Small-signal DC gain, input resistance, and output resistance as a function of bias
point.
AC sweep and noise
These AC analyses evaluate circuit performance in response to a small-signal alternating current source. To run
a noise analysis, we must also run an AC sweep analysis.
AC Analysis Types
AC sweep - Small-signal response of the circuit (linearized around the bias point) when sweeping one or more
sources over a range of frequencies. Outputs include voltages and currents with magnitude and phase; we can
use this information to obtain Bode plots.
Noise - For each frequency specified in the AC analysis:
Propagated noise contributions at an output net from every noise generator in the circuit.
RMS sum of the noise contributions at the output.
Equivalent input noise.
Transient and Fourier
These time-based analyses evaluate circuit performance in response to time-varying sources. To run a Fourier
analysis, we must also run a transient analysis.
Time-Based Analysis Types
Transient - Voltages, currents, and digital states tracked over time. For digital devices, we can set the
propagation delays to minimum, typical, and maximum. If we have enabled digital worst-case timing analysis,
then PSpice A/D considers all possible combinations of propagation delays within the minimum and maximum
range.
Fourier - DC and Fourier components of the transient analysis results.
1.1.2 Advanced Multi-Run Analyses
The multi-run analysesparametric, temperature, Monte Carlo, and sensitivity/worst-caseresult in a series of
DC sweep, AC sweep, or transient analyses depending on which basic analyses we enabled.
SK16 2
Parametric and temperature-For parametric and temperature analyses, PSpice A/D steps a circuit value in a
sequence that we specify and runs a simulation for each value.
Parametric
Global parameter
Model parameter
Component value
DC source
Operational temperature
Temperature
Operational temperature
Monte Carlo and sensitivity/worst-case
Monte Carlo and sensitivity/worst-case analyses are statistical. PSpice A/D changes device model parameter
values with respect to device and lot tolerances that we specify, and runs a simulation for each value.
Monte Carlo - For each simulation, randomly varies all device model parameters for which we have defined a
tolerance.
Sensitivity/worst-case- Computes the probable worst-case response of the circuit in two steps:
1. Computes component sensitivity to changes in the device model parameters. This means PSpice A/D
nonrandomly varies device model parameters for which we have defined a tolerance, one at a time for each
device and runs a simulation with each change.
2. Sets all model parameters for all devices to their worst-case values (assumed to be at one of the tolerance
limits) and runs a final simulation.
1.2 The Analysis Output Files
After first reading the circuit file, netlist file, model libraries, and any other required inputs,
PSpice A/D starts the simulation. As simulation progresses, PSpice A/D saves results to two filesthe Probe
data file with .dat extension and the PSpice output file with .out extension.
1.2.1 Probe
Probe is a graphical results analyzer. When PSpice A/D completes the simulation, Probe plots
the waveform results so we can visualize the circuits behavior and determine the validity of our design. Perform
post-simulation analysis of the result. This means that we can plot additional information derived from the
waveforms. What we can plot depends on the type of analyses we run. Bode plots, phase margin, derivatives for
small-signal characteristics, and waveform families are only a few of the possibilities. We can also plot other
waveform characteristics such as rise time versus temperature, or percent overshoot versus component value.
Probe also pinpoints design errors in digital circuits When PSpice A/D detects setup and hold violations, race
conditions, or timing hazards, Probe displays detailed message text along with corresponding waveforms. Probe
also helps to locate the problem in our schematic.
The Probe data file contains simulation results in a format that Probe can read. Probe reads
this file automatically and displays waveforms reflecting circuit response at nets, pins, and parts that we marked
in our schematic (cross-probing). We can set up our simulation so that Probe displays the results as the
simulation progresses or after the simulation completes. Once Probe has read the Probe data file and displays the
initial set of results, we are free to add more waveforms and to perform post-simulation analysis of the data.
The PSpice output file is an ASCII text file with .out extension that contains:
8 The netlist representation of the circuit.
8 The PSpice command syntax for simulation commands and options (like the enabled analyses).
8 Simulation results, and warning and error messages for problems encountered during read-in or simulation.
Its content is determined by:
8 the types of analyses we run,
8 the options we select for running PSpice A/D
8 the simulation control symbols (like VPRINT1 and VPLOT1) that we place and connect to nets in our
schematic.
SK16 3
1.3 The DC Sweep Analysis
The DC sweep analysis causes a DC sweep to be performed on the circuit. DC sweep allows
you to sweep a source (voltage or current), a global parameter, a model parameter, or the temperature through a
range of values. The bias point of the circuit is calculated for each value of the sweep. This is useful for finding
the transfer function of an amplifier, the high and low thresholds of a logic gate, and so on. The setting up of all
analyses is done from Schematics program by choosing Analysis/Set up submenu. The relevant dialog box is
shown below with the no analysis option enabled.
A Common Emitter Amplifier
drawn in Schematics program is shown in
Fig.1.Simulating the circuit with no analysis
option selected in the analysis/set up menu results
in simulation calculating only the d.c operating
point. Opening the output file in MicroSim Text
Editor by choosing Analysis/Examine Output
submenu can see the resulting information. Or the
result can be displayed in Schematics itself by
choosing analysis/display results in
Schematics/Enable Voltage Display submenu in
Schematics program. The resulting display is
shown in Fig.2.If DC Sweep analysis is selected
and the tab is pressed the following set up screen
is displayed. Notice that Voltage Source type
sweep is selected and name is entered as V1 that is
the reference designator of the bias supply. Sweep
type is selected as Linear and start value, End
value and Increment are also set. Pressing OK
followed by closing the set up dialog completes
SK16 4
the setting up of DC Sweep. Running the simulation and configuring the Probe properly results in the V
CE
waveform shown in Fig.3.
Selecting Transfer Function
Analysis in the set up menu and pressing tab
brings up the following dialog box.
Notice the entries made. Running
simulation results in calculation of d.c small signal
gain between the bias supply and collector output
and some resistance levels. These results will be
available in the .out file. The relevant portion of
the file is pasted below.
SMALL-SIGNAL CHARACTERISTICS
V(Out1)/V_V1 = 5.066E-01
INPUT RESISTANCE AT V_V1 = 7.565E+03
OUTPUT RESISTANCE AT V(Out1) =
4.995E+03
Selecting Sensitivity Analysis results in a
dialog box shown below.Notice that V(Out1) is entered there. This means that we want to calculate the change in
this voltage when the component values and transistor model parameter values change one at a time.The relevant
portion of simulation output file is pasted below.
DC SENSITIVITIES OF OUTPUT V(Out1)
ELEMENT ELEMENT ELEMENT NORMALIZED
NAME VALUE SENSITIVITY SENSITIVITY
(VOLTS/UNIT) (VOLTS/PERCENT)
R_R2 1.000E+04 -3.899E-04 -3.899E-02
R_R1 2.000E+04 1.980E-04 3.959E-02
R_Ro 1.000E+04 0.000E+00 0.000E+00
R_Re 3.300E+03 1.477E-03 4.873E-02
R_Rc 5.000E+03 -9.918E-04 -4.959E-02
V_V2 0.000E+00 0.000E+00 0.000E+00
V_V1 1.200E+01 5.066E-01 6.079E-02
Q_Q1
RB 0.000E+00 0.000E+00 0.000E+00
RC 1.464E+00 9.671E-07 1.416E-08
RE 0.000E+00 0.000E+00 0.000E+00
BF 3.755E+02 -1.010E-04 -3.794E-04
ISE 7.049E-15 7.286E+12 5.136E-04
BR 2.611E+00 1.535E-11 4.007E-13
ISC 1.217E-10 -1.484E+04 -1.806E-08
SK16 5
IS 7.049E-15 -1.111E+13 -7.832E-04
NE 1.281E+00 -8.026E-01 -1.028E-02
NC 1.865E+00 9.686E-07 1.806E-08
IKF 4.589E+00 -5.339E-06 -2.450E-07
IKR 5.313E+00 2.902E-17 1.542E-18
VAF 1.163E+02 2.576E-05 2.995E-05
VAR 0.000E+00 0.000E+00 0.000E+00
The nested DC Sweep tab in the DC Sweep Set up dialog box can be used to set up a nested
DC Sweep i.e a second sweep on another variable.For every value of first sweep variable the second variable
will be swept and repeated simulations will be performed.An example circuit for this is shown below.This ckt
was DC Swept with main sweep on V1 from 0 to 5V in increments of 0.01V and second sweep was on I1 from 0
to 200A with increment set at 20A.The marker shown will result in a display of common base characteristic
of the transistor shown in Fig.5.
1.4 AC Sweep Analysis
AC sweep is a frequency response analysis. PSpice A/D calculates the small-signal
response of the circuit, linearized around the bias point, to a combination of inputs. Here are a few
SK16 6
things to note:
Nonlinear devices, such as voltage- or current-controlled switches, are linearized about their bias point value
before PSpice A/D runs the linear (small-signal) analysis.
Digital devices hold the states that PSpice A/D calculated when solving for the bias point.
Because AC sweep analysis is a linear analysis, it only considers the gain and phase response of the circuit;
it does not limit voltages or currents.
The best way to use AC sweep analysis is to set the source magnitude to one. This way, the
measured output equals the gain, relative to the input source, at that output.
To run an AC sweep analysis, we need to place and connect one or more independent sources
and then set the AC magnitude and phase for each source. The source to be used for conducting this analysis is
either VAC or IAC source from the Schematics parts. The AC Sweep set up screen for the Circuit in Fig.1 is
shown above and resulting Probe output after simulation is shown in Fig.6.The input signal amplitude was
10mV.
1.5 Transient Analysis
The Transient response analysis causes the response of the circuit to be calculated from TIME
= 0 to a specified time. The transient analysis does its own calculation of a bias point to start with, using the
same technique as described for DC sweep. This is necessary because the initial values of the sources can be
different from their DC values. If we want to report the small-signal parameters for the transient bias point, we
should use the Transient command and enable Detailed Bias Point. Otherwise, if all we want is the result of the
transient run itself, we should only enable the Transient command.
During analog analysis, PSpice A/D maintains an internal time step that is continuously
adjusted to maintain accuracy while not performing unnecessary steps. During periods of inactivity, the internal
time step is increased. During active regions, it is decreased. The maximum internal step size can be controlled
by specifying so in the Step Ceiling text box in the Transient dialog. PSpice A/D will never exceed either the step
ceiling value or two percent of the total transient run time, whichever is less. The internal time steps used may
not correspond to the time steps at which information has been requested to be reported. The values at the print
time steps are obtained by 2
nd
order polynomial interpolation from values at the internal steps. When simulating
mixed analog/digital circuits, there are actually two time steps: one analog and one digital. This is necessary for
efficiency. Since the analog and digital circuitry usually have very different time constants, any attempt to lock
them together would greatly slow down the simulation. The time step shown on the PSpice A/D display during a
transient analysis is that of the analog section.
Running transient analysis on switching circuits can lead to long run times. PSpice A/D must
keep the internal time step short compared to the switching period, but the circuits response extends over many
switching cycles. One method of avoiding this problem is to transform the switching circuit into an equivalent
circuit without switching. The equivalent circuit represents
a sort of quasi steady state of the actual circuit and can
correctly model the actual circuits response as long as the
SK16 7
inputs do not change too fast. The Transient Analysis set up box with entries suitable for conducting transient
analysis of the Common Emitter Amplifier circuit in Fig.1 with a square wave source coupled to the base is
shown above. The fourier analysis options can be enabled but much better fourier analysis can be done in the
Probe program and hence the fourier option in this screen is generally never used. The simulation output is
shown in Fig.7 and shows a somewhat surprising result that there is d.c component in the output after the
coupling capacitor. Not surprising when we remember that the simulation was for 0-10uS and the capacitors had
initial voltages of zero value.
1.6 Parametric and Temperature Analysis
1.6.1 Parametric Analysis
If a parametric analysis is to be done, the circuit must be set up according to the swept variable
type as voltage source voltage source with a DC specification (VDC, for example), temperature, current source
current source with a DC specification (IDC, for example), model parameter PSpice A/D model or a global
parameter defined with a parameter block (PARAM). And a DC Sweep or AC Sweep or Transient Analysis must
be set up.
In the Analysis Setup dialog box, click the Parametric button. Complete the Parametric dialog box as needed.
If needed, in the Analysis Setup dialog box, select the Parametric check box to enable it.
Start the simulation
Note- Do not specify a DC sweep and a parametric analysis for the same variable.
Parametric analysis performs multiple iterations of a specified standard analysis while varying
a global parameter, model parameter, component value, or operational temperature. The effect is the same as
running the circuit several times, once for each value of the swept variable.
The CE amp with a parameter called R with a default value of 10k and with the value of the
element Ro set to this parameter value is shown in fig.8.The parametric analysis dialog box with entries made for
running a parametric analysis on the amplifier is also shown. Two analyses i.e transient analysis and parametric
analysis are selected. The simulation results in a data file with 11 sections.
When the Probe program starts it will seek the information on the number of sections to be
loaded. If all sections are loaded and the performance analysis menu selected and if MAX(V(Out2))/).01 is
entered in the trace add dialog box the following plot in Fig.9 appears in the Probe window. This is a plot of the
mid frequency gain of the amplifier Vs load resistance.
SK16 8
1.6.2 Temperature Analysis
In the Analysis Setup dialog
box, click the Temperature button.
Specify the temperature or list of
temperatures in the Temperature
Analysis dialog box. If needed, in the
Analysis Setup dialog box, select the
Temperature check box to enable it
and start the simulation.
When a temperature analysis
is run, PSpice A/D reruns standard
analyses enabled in the Analysis Setup
dialog box at different temperatures.
Temperature analysis allows zero or
more temperatures to be specified. If
no temperature is specified, the circuit
is run at 27C. If more than one
temperature is listed, the effect is the
same as running the simulation several
times, once for each temperature in
the list. Setting the temperature to a
value other than the default results in
recalculating the values of
temperature-dependent devices.
2. The MicroSim Probe Program
MicroSim Probe is the waveform analyzer for PSpice A/D simulations. In Probe, we can
visually analyze and interactively manipulate the waveform data produced by circuit simulation. Probe uses
high-resolution graphics so we can view the results of a simulation both on the screen and in hard copy. In effect,
Probe is a software oscilloscope. Running PSpice A/D corresponds to building or changing a breadboard, and
running Probe corresponds to looking at the breadboard with an oscilloscope.
With Probe we can:
view simulation results in multiple plot windows
compare simulation results from multiple circuit designs, including checkpoint schematics, in a single plot
window
display simple voltages, currents, and noise data
display complex arithmetic expressions that use the basic measurements
display Fourier transforms of voltages and currents, or of arithmetic expressions involving voltages and
currents
for mixed analog/digital simulations, display analog and digital waveforms simultaneously with a common
time base
add text labels and other annotation symbols for clarification
PSpice A/D generates two forms of output: the simulation output file and the Probe data file.
The calculations and results reported in the simulation output file act as an audit trail of the simulation. However,
the graphical analysis of information in the Probe data file is the most informative and flexible method for
evaluating simulation results.
A single Probe plot consists of the analog (lower) area and the digital (upper) area. A single
Probe plot consists of the analog (lower) area and the digital (upper) area. A plot window is a separately
managed waveform display area. A plot window can include multiple analog and digital plots. Because a plot
window is a window object, we can minimize and maximize the window or move and scale the window within
the Probe window area. A toolbar can be displayed in the Probe window and applies to the active plot window.
We can have one or more Probe data files open in one plot window. Do one of the following:
9 Using the Design Journal feature in Schematics set up Probe to automatically load open working
schematics and checkpoint files.
9 After the first file is loaded, load other files into the same plot window by manually appending them in
Probe.
SK16 9
Any number of plot windows can be opened. Each plot window is an independent window.
The same Probe data file can be displayed in more than one plot window. Only one plot window is active at any
given time, identified by a highlighted title bar. Menu, keyboard, and cursor operations affect only the active plot
window. Another plot window can be made active by clicking anywhere in the window.
We can print all or selected plot windows, with up to nine windows on a single page. When we
select Print from the File menu, a list of all open plot windows is displayed. Each plot window is identified by
the unique identifier in parentheses in its title bar. The arrangement of plot windows on the page can be
customized using the Page Setup dialog box. We can print in either portrait (vertical) or landscape (horizontal)
orientation. We can also use Print Preview to view all of the plot windows as they will appear when printed.
2.1 Starting Probe
If we are using Schematics, we can automatically start Probe after a simulation is run, or we
can start Probe separately from Windows 95 or NT. When we start Probe, we can use the default .prb file or we
can use a custom .prb file.
To automatically start Probe after simulation
1. In Schematics, from the Analysis menu, select Probe Setup.
2. In the Probe Setup Options dialog box, select the Probe Startup tab.
3. In the Auto-Run Option frame, select Automatically Run Probe after Simulation.
4. Select any other options that we want to use.
5. Click OK.
To start Probe and monitor results during a simulation -
2. In the Probe Setup Options dialog box, select the Probe Startup tab.
3. In the Auto-Run Option frame, select Monitor Waveforms (Auto-Update). If this option is unavailable, do the
following:
a. Select the Data Collection tab.
b. Clear the Text Data File Format (CSDF) check box. The Monitor Waveforms (Auto-Update) option should
now be available from the Probe Startup tab.
4. Click OK.
5. From the Analysis menu, select Simulate to start the simulation. Probe starts automatically and displays one
window in monitor mode.
6. Do one of the following to select the waveforms to be monitored:
In Probe, from the Trace menu, select Add, and enter one or more trace expressions.
In Schematics, from the Markers menu, select and place one or more markers (and marker color, as needed).
To start Probe from Schematics
1. From the Analysis menu, select Run Probe.
To start Probe in Windows 95
1. From the Windows Start menu, select the MicroSim program folder and then the Probe shortcut.
Other Ways to Run Probe
Starting Probe during a simulation
Once a simulation is in progress, we can monitor the results for the data section currently being written by
PSpice A/D. This function is only available when Monitor Waveforms (Auto-Update) is not enabled in
Schematics in the Probe Setup Options dialog box.
To start Probe during a simulation
1. Start the simulation
2. In Schematics, from the Analysis menu, select Run Probe. Probe automatically opens the data file and the
data section that PSpice is currently writing. When started during a simulation, the Probe window monitors
the waveforms for as long as the current data section is being written. After the data section is finished, the
window reverts to manual mode.
SK16 10
Pausing a simulation and then running Probe
We can pause a simulation to analyze waveforms before the simulation is finished. Once we pause the
simulation, we can either resume the simulation or terminate it.
To pause a simulation and then run Probe
1. In the PSpice A/D simulation status window, from the File menu, select Pause Simulation.
2. From the File menu, select Run Probe and verify that the analysis is proceeding correctly.
3. Do one of the following:
9 In the PSpice A/D simulation status window, from the File menu, select Pause Simulation to clear the
check mark.
9 In the PSpice A/D simulation status window, from the File menu, select Terminate Simulation.
Interacting with Probe while in monitor mode
All of the Probe functionality is available when in monitor mode. However, functions that change the x-axis
domain (set a new x-axis variable) pause monitoring and place the window in manual mode until the x-axis is
reverted to its original domain.
Using Schematic Markers to Add Traces
We can place markers on a schematic to identify the points where we want to see the waveform results displayed
in Probe. Markers can be placed before simulation to limit results written to the Probe data file and automatically
display those traces in Probe.
Fast Fourier transforms
1. From the Plot menu, select X Axis Settings.
2. In the Processing Options frame, choose the Fourier option.
Performance analysis
1. From the Plot menu, select X Axis Settings.
2. In the Processing Options frame, choose the Performance Analysis option.
New x-axis variable
1. From the Plot menu, select X Axis Settings, and click Axis Variable.
2. In the X Axis Variable dialog box, specify a new x-axis variable.
Goal function evaluation
1. From the Trace menu, select Eval Goal
Function.
2. In the Evaluate Goal Function(s) dialog box,
specify a goal function.
Load a completed data section
1. From the File menu, select Append.
2.Specify a .dat file to append.
Limiting Probe Data File Size
When PSpice A/D runs, it creates a Probe data file. The size of this file for transient analyses is roughly equal to:
(# transistors)(# simulation time points)24 bytes The size for other analyses is about 2.5 times smaller. For long
runs, especially transient runs, this can generate Probe data files that are several megabytes in size. Even if this
does not cause a problem with disk space, large Probe data files take longer to read in and longer to display
traces on the screen. We can limit Probe data file size by: placing markers on our schematic before simulation
and having PSpice A/D restrict the saved data to these markers only excluding data for internal subcircuits
suppressing simulation output
Limiting file size using markers
One reason that Probe data files are large is that, by default, PSpice A/D stores all net voltages and device
currents for each step (for example, time or frequency points). However, if we have placed markers on our
schematic prior to simulation, PSpice A/D saves only the results for the marked wires and pins.
To limit file size using markers
2. In the Probe Setup Options dialog box, select the Data Collection tab.
3. In the Data Collection frame, select At Markers Only and click OK.
4. In Schematics, from the Markers menu, select the marker type we want to place.
5. If desired, on the Simulation toolbar, from the marker color list, select a color for one or more of the markers
(and its Probe trace).
6 Click wires or pins to place markers.
7 Right-click to quit placing markers.
8 From the Analysis menu, select Simulate.
SK16 11
Limiting file size by excluding internal subcircuit data
By default, PSpice A/D writes data to the Probe file for all internal nodes and devices in subcircuit models on a
schematic. We can choose to exclude data for internal subcircuit nodes and devices.
To limit file size by excluding data for internal subcircuits
2. In the Probe Setup Options dialog box, select the Data Collection tab.
3. In the Data Collection frame, select All Except Internal Subcircuit Data and click OK.
4. From the Analysis menu, select Simulate.
Limiting file size by suppressing the first part of simulation output
Long transient simulations create large Probe data files because PSpice A/D stores many data
points. We can suppress a part of the data from a transient run by setting the simulation analysis to start the
output at a time later than 0. This does not affect the transient calculations themselvesthese always start at time
0. This delay only suppresses the output for the first part of the simulation.
To limit file size by suppressing the first part of transient simulation output
1. In Schematics, from the Analysis menu, select Setup.
2. In the Analysis Setup dialog box, click the Transient button.
3. In the No-Print Delay text box, type a delay time and click OK.
4. From the Analysis menu, select Simulate. No data will be stored until the delay has elapsed.
Using Simulation Data from Multiple Files
We can load simulation data from multiple files into the same Probe plot in two ways:
9 By setting up Probe for automatic loading of checkpoint and working schematic data files.
9 By appending data files.
When more than one data file is loaded, we can add traces using all loaded data, data from only
one file, or individual data sections from one or more files.
Setting up Probe for automatic loading of data files
In Schematics, we can set up Probe so data from open checkpoint and working schematics simulations is
automatically loaded.
To set up Probe for automatic loading of data files
2. In the Probe Setup Options dialog box, select the Checkpoint tab.
3. Select the following option: Automatically load data for open checkpoints.
4. In the Show Results In frame, choose proper option.
5. Click OK.
Appending data files
We can manually load data sets one at time into a plot window using the Append command.
To append a data file
1. In Probe, from the File menu, select Append.
2. Select a .dat file to append, and click OK.
3. If the file has multiple sections of data for the selected analysis type, the Available Sections dialog box
appears. Do one of the following:
9 Click the sections we want to use.
9 Click the All button to use all sections.
SK16 12
4 Click OK.
Adding traces from specific loaded data files
If two or more data files have identical simulation output variables, trace expressions that
include those variables will plot traces for each file. However, we can specify which data file to use in the trace
expression. We can also determine which data file was used to generate a specific trace.
To add a trace from a specific loaded data file
In Probe, from the Trace menu, select Add to display the Add Traces dialog box. In the Trace
Expression text box, type an expression using the following syntax: trace_expression@fn where n is the
numerical order (from left to right) of the data file as it appears in the Probe title bar, or trace_expression@s@fn
where s is a specific data section of a specific data file. Click OK.
To identify the source file for an individual trace
In the trace legend, double-click the symbol for the trace we want to identify . The Section
Information dialog box appears, containing the trace name and, if there is more than one data file loaded in the
plot, the full path for the file from which the trace was generated. Also listed is information about the simulation
that generated the data file and the number of data points used. If the trace is from a checkpoint data file, the
dialog box includes the checkpoint description.
Probe Trace Expressions
Traces are referred to by Probe output variable names. Probe output variables are similar to the
PSpice A/D output variables specified in the Schematics Analysis Setup dialog boxes for noise, Monte Carlo,
worst-case, transfer function, and Fourier analyses. However, there are additional alias forms that are valid
within Probe. Both forms are discussed here.
To add traces using Probe output variables
1 From the Trace menu, select Add to display the Add Traces dialog box.
2 Construct a trace expression using any combination of these controls:
In the Simulation Output Variables frame, click output variables.
In the Functions or Macros frame, select operators, functions, constants, or macros.
In the Trace Expression text box, type in or edit output variables, operators, functions, constants, or macros.
3 If we want to change the name of the trace expression as it displays in the plot window, use the following
syntax: trace expression;display name
3. Click OK.
SA 1
LINEAR TRANSFORMATIONS
Ashok S
Electrical Dept, NIT Calicut
Linear transformations simplifies the analysis and calculation. In 3-phase rotating machines
induced e.m.fs are depends upon mutual inductance between stator and rotor windings, so mutual
inductance depends upon angle between stator reference frame and rotor reference frame, i.e depends on
angular speed. So e.m.f equation becomes differential equations to solve that are difficult, to simplify the
calculation transform stator 3-phase to rotor 2-phase (, , 0).
A symmetrical 2- pole, 3-phase winding on the rotor is represented by three coils A, B, C each of
N effective turns and mutually displayed by 120
o
, see Fig given below Maximum values of m.m.fs. F
a,
F
b,
and

F
c
are shown along their respective phase-axes. The combined effect of these three m.m.fs, results in a
constant magnitude m.m.f., which rotates at a constant angular velocity depending on the poles and
frequency.
Fig.(a) Balanced 3-phase windings
Fig.(b) 2-phase windings on the rotor
If the three currents are
|
.
|
\
|
=
=
3
2
cos
cos
t l i
t l i
m b
m a
and
|
.
|
\
|
=
3
4
cos

t l i
m c
(1)
then, these will produce a m.m.f. of constant magnitude
2
3 N l
m
rotating with respect to the three phase
winding must comply with the time-phase angle between the currents.
In Fig.(b), a balanced two-phase winding is represented by two orthogonal coils , on the
rotor. For convenience in transformation the axis of phase A and C are taken to be coincident.
If two-phase currents
A
B
C
Fa
F
b
F
c
120
o
w
r
F
SA 2
And
t l t l i
t l i
m m
m

sin
2
cos
cos
= |
.
|
\
|
=
=
(2)
flow in the two-phase windings, the result will be a m.m.f. of constant magnitude N l
m
, revolving with
respect to the two-phase windings at the time frequency of the phase currents.
The m.m.f.s of three-phase and two-phase systems can be rendered equal in magnitude by
making any one of the following changes:
(i) by changing magnitude of the two-phase currents,
(ii) by changing number of turns of the two-phase windings,
(iii) by changing both the magnitude of currents and number of turns.
These will be now discussed one after other.
(i) If the effective number of turns per phase in case of two-phase winding is N (ie. The winding
factors are same for both three-and two-phase windings) then for equal m.m.fs the magnitude of the current
in the two phases, must be 3/2 times the magnitude of the three phase currents. This can be proved by
resolving the instantaneous 3-phase m.m.fs along the - axis. Ref. to Fig. above, gives
[ ]
0 0 0
240 cos 120 cos 0 cos
c b a a
i i i N N i + + =
or ( )
(
+ =
c b a a
i i i i
2
1
Similarly [ ]
0 0 0
240 sin 120 sin 0 sin
c b a
i i i N N i + + =
or
(
+ =
c b
i i i
2
3
2
3
0
(3)
For a balanced system
( )
(
+ =
= + +
c b a a
c b a
i i i i
i i i
2
1
0
or
a a a
i i or i i i
2
3
2
1
= + =

(4)
Thus the magnitude of the two-phase currents is 3/2 times the magnitude of the three phase
currents
.
With the conditions given above, equal m.m.fs will give rise to equal fluxes. Number of effective turns
per phase being the same in both the windings, the magnitude of phase e.m.fs of the two and three phase
windings would be equal. The power per phase of the two-phase system (V.3/2.1) is thus 3/2 times the
power per phase (V.!) of the three phase system. Note that the total power of the two-phase
system( ( ) 1 . . . 2
3
2
V = .and the three phase system (=3 VI) is the same. Thus the invariance of power has
been attained. The only disadvantage is that the transformation of current and voltage will differ because of
the presence of factor 3/2 in the current transformation. As factor 3/2 appears in the current transformation
and not in voltage transformation, the per phase parameters of the two-phase induction machines will not
be the same.
SA 3
(ii) If the effective number of per-phase turns winding is made 3/2 times that of the three phase
winding, then for equal m.m.fs the magnitude of the currents in the two-phase and three phase system must
be equal i.e. i
=I
a
. This can be proved as is done in the previous case.
With these conditions, the per phase voltage of two-phase machine will be 3/2 times (3/2 V) the
per phase voltage (v) of the three-phase system.
The power per phase in two-phase system = VI
2
3
Total power in the two-phase system = VI 3
Also total power in the three-phase system = VI 3
Here again the invariance of power has been obtained, but, s earlier, the transformation of current
and voltage will differ because of factor 3/2 in the voltage transformation. As such, per phase parameters of
the 2-phase induction machine will be different from that of the 3-phase induction machine
.
(iii) Here both the magnitude of currents and number of turns of the two-phase system are changed to
obtain identical transformation for voltage and current.
Let the number of per-phase turns in the two-phase winding be made
2
3
times the per- phase turns of
the three-phase winding.
Then for equal m.m.fs,
.
2
3
a a
i i = his can be proved by resolving the 3-phase m.m.fs along the - axis
as shown below:
(
=
c b a
i i i N N i
2
1
2
1
2
3
or ( )
(
+ =
c b a
i i i i
2
1
3
2
a
a a
i
i i
2
3
2
1
3
2
=
(
+ =
( 5)
The voltage per-phase of the two-phase winding is
2
3
times that of the three-phase winding. Thus the
phase voltage and current of the two-phase system are
2
3
times those of the three-phase system. This fact
results in identical transformations for both the voltage and current.
SA 4
(
(
(
+ =
=
c b
c b a a
i i i and
i i i i
2
3
2
3
0
3
2
2
1
2
1
3
2
(6)
.
Since the transformations for voltage and current are identical, impendence per-phase of the two-and three-
phase systems is the same. This is illustrated by an example given below:
Example: A three phase induction motor has the following per-phase parameters referred to stator:
Stator resistance 0.30
Rotor resistance 0.45
Stator and rotor leakage reactance 2.1
Magnetizing reactance 30.00
Find out the parameters of an equivalent 2-phase induction motor if its per-phase turns are:
(a) Same as that of the 3-phase induction motor.
(b) 3/2 times that of the 3-phase induction motor.
(c) 2 / 3 times that of the 3-phase induction motor.
Solution. (a) Let
( )
( )

=
=
0
120 cos
cos
t l i
t l i
m b
m a
And ( ) =
0
240 cos t l i
m c
Since per-phase turns in both 2-phase and 3-phase induction motors are the same, for equal m.m.f.s,
the magnitude of currents in the 2-phase motor must be
2
3
times the magnitude of currents in the 3-phase
motor. Thus from Eq. (4),
( ) = = t l i i
m a a
cos
2
3
2
3
From Eq. (3),
( )
( ) ( [ ]
( ) [ ( )
( ) ( ) ]
0 0
0 0
0 0
0 24 sin sin 240 cos cos
120 sin sin 120 cos cos
2
3
240 cos 120 cos
2
3
2
3

+ =
=
=
t t
t t l
t t l
i i i
m
m
c b
But
0
120 cos = ;
2
1
60 cos
0
=
SA 5
( ) ( ) ( ) ( )
( )

=
(
+ + + =
= = =
= =
t l
t t t t l i
m
m
sin
2
3
sin
2
3
cos
2
1
sin
2
3
cos
2
1
2
3
2
3
240 sin ;
2
1
60 cos 240 cos
2
3
60 sin 120 sin
0 0 0
0 0
Further, let
( )
( )
0
0
240 cos
120 cos
cos
=
=
=
t V U
t U
t V U
m c
b
m a
and
Since the per-phase turns in both the machines are equal and their rotating m.m.fs. have the same
magnitude, factor
2
3
will not appear in the voltage transformations, i.e
and
[ ]
( ) ( ) [ ]
[ ]
[ ] . sin sin sin 3
3
1
sin
2
3
cos
2
1
sin
2
3
cos
2
1
3
1
240 sin sin 240 cos cos 120 sin sin 120 cos cos
3
1
240 cos 120 cos
3
1
3
1
cos
0 0 0 0
0
t V V t V
t t t t V
t t t t V
t t V
U U U
t V U U
m m m
m
m
o
m
c b
m a

= =
(
+ + + =
+ =
=
=
= =
For obtaining the phase voltage ,
U the factor
3
1
is essential, because ( )
c b
U U gives the
line voltage for a 3-phase system.
From above, it is seen that
For a 3-phase motor,
=
=
I phase current
V phase voltage
/
/
And for a 2-phase motor,
=
=
I phase current
V phase voltage
2
3
/
/
SA 6
3
2
/
2
3
/
/
/
3
2
= =

=
i V
i V
current phase per voltage phase Per
current phase per voltage phase Per
parameters motor induction phase
parameters motor induction phase
Now
This shows that the parameters of the 2-phase induction moor are
3
2
times the corresponding
parameters of the 3-phase induction motor. In view of this, the parameters of the equivalent two-phase
induction motor are:
Stator resistance = = 20 . 0 30 . 0
3
2
x
Rotor resistance = = 30 . 0 45 . 0
3
2
x
Stator and rotor leakage reactance
= ( ) each = 4 . 1 1 . 2
3
2
Magnetizing reactance = ( ) . 00 . 20 30
3
2
=
(b)When per phase turns of the two-phase motor are
2
3
times that of the 3-phase motor, then it can
be shown that
=
=
l current phase per

V voltage phase per
motor phase a for 3
=
=
i current phase per

V voltage phase per
motor phase a for and 2
3
, 2
Thus the parameters of the equivalent 2-phase induction motor are
2
3
times the corresponding
parameters of the equivalent parameters of the 3-phase induction motor and their magnitudes are:
Stator resistance = = 45 . 0 30 . 0
2
3
x
Rotor resistance = = 675 . 0 45 . 0
2
3
x
Stator and rotor leakage reactance
= each x = 15 . 3 1 . 2
2
3
Magnetizing reactance = . 00 . 45 00 . 30
2
3
= x
(c)In this case it can be shown that per phase values of 3-phase induction motor, are V, I and the
corresponding per phase values of 2-phase induction motors are .
2
3
,
2
3
l V Since the ratio of per-phase
SA 7
voltage to per-phase current is the same in both the induction motors, the parameters of the equivalent 2-
phase induction motor are the same as that of the 3-phase induction motor.
The transformation equations giving the new currents

i i
,
in terms of
c b a
i i i , , i.e. Eq.(6), can be
expressed in matrix form as follows:
(6)
The transformation matrix,
containing the constant
coefficients, in a singular
one and thus
c b a
i i i , , cant
be obtained from

i i , ; since inverse of singular matrix does not exist. The matrix can be made square
matrix if there is a third equation of constraint between
c b a
i and i i , . Since the magnitude and direction of
the m.m.f. Produced by two and three-phase systems are identical, the third current in terms of
c b a
i i i , ,
should not produce any resultant air-gap m.m.f. The only obvious choice is the zero sequence current
0
i which, for convenience, is defined as:
( )
c b a
i i i i + + =
3
1
0
Note that zero sequence current does not produce any rotating m.m.f. and here the factor
|
|
.
|
\
|
3
1
is chosen
arbitrarily to suit the transformations.
The three phase currents
c b a
i i i , , are thus replaced by two-phase currents

i i , plus zero
sequence current
0
i according to the equations,
|
|
.
|
\
|
+ =
|
.
|
\
|
=
c b
c b a
i i i
i i i i
2
3
2
3
0
3
2
2
1
2
1
3
2
and |
.
|
\
|
+ + =
c b a
i i i i
2
1
2
1
2
1
3
2
0
In matrix form
(7)
The transformation
matrix now is non-
singular and its inverse
can be easily obtained.
i
1
2
1
2
1
a
i
i
3
2
=
2
3
-
2
3 b
i
c
i
i
1
-
2
1
-
2
1
a
i
i
0
2
3
-
2
3 b
i
0
i
3
2
=
2
1
2
1
2
1
c
i
SA 8
Let [ ]
3
2
= A a b c
1
2
1
2
1

3
2
-
6
1
6
1
0
2
3
-
2
3
=
2
1
-
2
1
2
1
2
1
2
1 0
3
1
3
1
3
1
Now = A
3
2
(
+ +
(
(
(
+
12
1
12
1
3
1
6
1
6
1
= . 1
3
1
3
1
3
2
3
2
=
(
+
(
Co- factor matrix =

3
2
-
6
1
-
6
1
2
1
-
2
1
3
1
3
1
3
1
Inverse of matrix A is given by
[ ] [ ] matrix factor fco transposeo
A
A =
1
1
3
2
-
6
1
-
6
1
3
2
=
2
1
-
2
1
3
1
3
1
3
1

0
SA 10
Or [ ] [ ]
1
= A A
t
Thus it is seen that if the transpose of the transformation matrix (here A
t
) equals the inverse of
the transformation matrix (A
-1
), the power is invariant or constant.
In the present case of transformation from three phases to two-phases, it is observed that
[ ] [ ]
1
= A A
t
and so the power invariance has been maintained.
Transformation from Rotating axes ( , , 0) to Stationary axes (d, q, 0):
In the above Fig., three-phase and two-phase windings are shown on the rotor and for convenience, the axis
of phase is taken to coincide with the axis of phase A Since the two rotors rotate at the same angular
velocity and in the same direction, axis of phase a continues coinciding the axis of phase A. In other words,
the rotating 2-phase axes , and the rotating 3-phase axes a, b, c ; moving in one direction at the same
angular speed, are at rest with respect to each other. Consequently, the transformation matrix relating the 3-
phase and 2-phase variables has constant coefficients, as in Eqs. (7) and (8).
In the above Fig. the transformation from 3-phase rotating axes to 2-phase rotating axes means the
transformation from rotating reference frame a, b, c to rotating reference frame ,,0. A reference frame is,
quite simply, any fixed point that enables one to judge motion or change. In this article, the transformation
from rotating axis to stationary axis means the transformation from rotating reference frame, ,,0 to
stationary reference frame d, q, 0.
When the transformation is carried out from rotating to stationary axes, the relative position of
rotating axes varies with respect to stationary or fixed axes. In view of this, the matrix giving the trans
formation from rotating to stationary axes or vice-versa must contain coefficients, which are functions of
the relative position of the moving (,) and fixed (d, q) axes. The transformation from rotating to
stationary axes results in replacing the moving coils by pseudo-stationary coils.
Zero sequence quantities are not transformed and thus the required transformation is only from -
to d-q axes. The two windings and on the rotor are shown inside the circle in Fig.(c) given below. As
the rotor moves, the - axes (i.e. , windings) also revolve along with it. By the revolving axes on the
rotor, it is meant that these axes are moving with respect to the stator. By stationary axes on the rotor, it is
understood that these axes are fixed with respect to the stator, (pseudo-stationary coil-axes). In the present
case, rotating and stationary axes refer to the rotor and are described with respect to the d-q-o axes.
F
=Ni
i
i
r
D
Q
i
d
i
q
F
d
d-axis
q-axis
F
=Ni
F
R
F
=Ni
F
d
=Ni
d
F
R
F
q
=Ni
q
R
Fig.(c) Fig.(d)
SA 11
In the above Fig. (c), angle is such that at atime t=0,=0. In other words, rotating axes and are
aligned along d and q axes respectively at t = 0. At any time t, =
r
t,
r
is the angular velocity in radians
per second.
Phases and of the rotating angle with the stationary d-q axes windings and F
d
, F
q
for d, q
windings shown in above Fig. Assuming that the effective number of turns in , and d-q windings is
same, m.m.fs F
can be resolved along the d- and q-axes, giving the relationship,

Fd = F

cos + F
sin
or N
id
= N
i
cos + N
i
sin
i
d
= i cos + i sin
Similarly,
I
q
= i
sin + i cos
In matrix form,

cos sin
sin cos
q
d
iq
id
i
i
(14)
let C=

cos sin
sin cos

cos sin
sin cos
= Ct
1 sin cos
2 2
= + = C
t C C =
=

cos sin
sin cos
1
As C
-1
=C
t
, the matrix is orthogonal and the voltage and current have identical transformations.
d q
q
d
i
i
i
i

cos sin
sin cos
= (15)
Let the current in d-q axes windings be functions of time and be given by
i
d
= I
m
sin (t+)
and i
q
= I
m
cos (t+)
Where is a constant arbitarary phase angle. The equivalent currents i
and i
can now be
obtained with the help of Eq. (15) where is taken equal to t.
i
=
I
m
sin
and i
=
I
m
cos
Thus time varying currents in stationary d-q coils results in m.m.f which is identical with the
m.m.f produced by constant (or d.c) currents in rotating
, coils.
If coils ,

are stationary , d.c currents in them would set up stationary m.m.f . now if these coils
are to rotate at a certain constant speed their m.m.f will also rotate at the same speed and in also be
produced by stationary d-q coils ,carrying time varying currents.
If coils and are stationary, d.c. currents in them would set up stationary m.m.f. Now if these
coils are made to rotate at a certain the rn.m.f. will also rotate at the same speed and in also be produced by
stationary d-q coils, carrying time varying currents.
SA 12
In the above transformation from - to d-q axes, zero sequence current is not transformed. But if
it exits, it can be taken into account in matrix C, by an additional row an additional column, containing a
unity as their common element. Thus,
o

a
i
D Cos Sin
i
b
i
=
Q
-sin Cos
i
c
i
O 1
0
i
..(16)
the transformation from three phases a,b,c t two phases ,,0 and from the two phases to stationary axes
d,q,0 have been obtained. With the help of Eqs (16) and (7), the transformation follows, where Eq. (7) is
substituted in Eq (16).
a b c

a
i
D Cos
Cos(- )
3
2
Cos(- )
3
4
i
a
b
i
= 3 / 2
Q
-sin
-sin(- )
3
2
-sin(- )
3
4
i
b
c
i
O
2 / 1 2 / 1 2 / 1
i
c
..(17)
Thus the new currents (or fictitious currents) i
d,
i
q
, and i
0
can be expressed in terms of actual
three phase currents i
a
,i
b,
i
c,
Eq.(17) or two phase currents i
,i
,i
0
.Eq.(16).
The equations of the inverse transformation giving the actual currents i
a
,i
b,
i
c
in terms of the
currents i
d,
i
q
,i
0
can be obtained by substituting Eq. (15) in Eq. (8). In order to include zero sequence current,
an additional row and an column containing unity, has been added to the transformation matrix of Eq(15),
as illustrated below.
d q 0

a
i
a Cos -sin
2 / 1
i
a
b
i
= 3 / 2
b
Cos(- )
3
2
-sin(- )
3
2
2 / 1
i
b
c
i
C
Cos (- )
3
4
-sin(- )
3
4
2 / 1
i
c
..(18)
From Eq.(17) and (18), it can be observed that inverse of transformation matrix=transpose of
transformation matrix.
So the axes voltages v
d
,v
q
,and v
0
are related to the armature phase voltages of two or three
phase systems by expressions of identical form. For example, for - to d-q transformation or vice versa,
oltages can be substituted for currents in Eqs. (14) and (15). Similarly, voltages can replace currents in Eqs.
(17) and (18).
In Eqs. (17) and (18), three phase variables i
a
,i
b,
i
c
or v
a
,v
b
,v
c
are related to d-q variables i
d
,i
q
or
v
d
,v
q
. these two sets of relations in between the 3-phase variables and d-q variables are called parks
transformations.
SA 13
The stator may carry single phase,2-phase or 3-phase windings. The stator axes, a,b,c or ,
will be stationary relative to the stator and its windings. The stator two phase axes , may coincide with
d,q axes and thus there is no disparity between , and d,q axes in case of a star\tor. So if the stator carries:
(i)1-phase windings, it is taken along d-axis;
(ii)2-phase windings, they are taken along d-q axes;
(iii)3-phase windings, transformation has to be made from 3-phase axes to , or d-q axes;
through the coefficients of the transformation matrix will be constant.
Simulink -
Power System block in Matlab-simulink computes the direct axis, quadratic axis, and zero sequence
quantities in a two- axis rotating reference frame for a three-phase sinusoidal signal.
Reference
J. Arrilaga, CP Arnold , Computer aided power systems analysis
Charles G. Cullen, Culten, Matrices and Linear Transformations
Stephen Campbell and Carl D. Meyer. , Generalized Inverses of Linear Transformations
SG 1
Pulse Width Modulation Techniques
Dr. Saly George
AP,EED,N.I.T Calicut
1. Introduction
An inverter is a circuit which converts a dc power
into an ac power at desired output voltage and
frequency. This can be achieved by controlled turn
on and turn off devices. The dc power input to the
inverter may be battery, fuel cell, solar cells or other
dc sources. But in most industrial applications, it is
fed by a rectifier. This configuration of ac to dc
converter and dc to ac converter is called a dc link
converter. The output voltage waveforms of an ideal
inverter should be sinusoidal. But for practical
inverter, the voltage waveforms are nonsinusoidal
and contains certain harmonics. Square wave and
quasi square wave voltages may be acceptable for
low and medium power applications. For high power
application, low distributed sinusoidal waveforms are
required.
Inverters find application in
Variable speed ac motor drives.
Induction heating
Aircraft power supplies
Uninterrupted power supplies
High voltage dc transmission lines
Static VAR generator (SVG) or
compensator (SVC)
Active harmonic filter (AHF)
2. Half Bridge Inverters
One of the simplest possible inverter configuration is
the single-phase, half-bridge inverter shown in Fig. 1.
The circuit consists of a pair of devices T
A
+
and T
A
-
connected in series across the dc supply, and
the load is connected between point A and the centre-
point 0 of a split-capacitor power supply. The
devices T
A
+
and T
A
-
are closed alternately for angle
to generate the square-wave output voltage, as
shown. In fact, a short gap, or lock out time (t
d
), is
maintained, to prevent in a short circuit or shoot-
through fault due to turn-off switching delay. The
load is usually inductive, and assuming perfect
filtering, the sinusoidal load current will lag the
fundamental voltage by angle , as shown. When the
supply voltage and load current are the same polarity,
the mode is active, meaning the power is absorbed by
the load. On the other hand, when the voltage and
current are opposite polarity (indicated by diode
conduction), the power is fed back to the source.
However, the average power will flow from the
source to the load. To maintain the center-point of
the supply voltage V
d
, the capacitors should be large.
3. Full, or H-Bridge, Inverter
Two half bridges or phase-legs can be connected to
construct a full, or H-bridge, inverter, as shown in
Fig. 2.
The split-capacitor power supply is not needed in this
case, and the load is connected between the center-
points, A and B. in the square-wave operation mode,
the device pairs T
A
+
, T
B
-
and T
B
+
, T
A
-
are switched
alternately to generate the square wave output
voltage of amplitude V
d
. Again, assuming inductive
and harmonic-free load current at face angle , the
load current in active mode will be carried by the T
A
+
, T
B
-
or T
B
+
, T
A
-
pair, whereas the feedback current
will flow through the D
A
+
, D
B
-
or D
B
+
, D
A
--
. Both
the diodes and IGBTs are designed to withstand the
supply voltage V
d
with the current waves, it can be
easily seen that the peak current in the IGBT is I
m
,
whereas that in the diode is I
m
sin .
Because an inverter contains electronic switches, it is
possible to control the output voltage magnitude,
frequency as well as to optimize the harmonics by
performing multiple switching with the inverter with
Fig.1. Half Bridge Inverter Configuration
Fig.2. Full Bridge Inverter Configuration
SG 2
a constant dc input voltage. In this context, PWM
techniques find application in inverters. PWM
techniques are classified as
Sinusoidal PWM (SPWM)
Selected Harmonic Elimination (SHE) PWM
Minimum ripple current PWM
Hysterisis band current control PWM
Sigma delta modulation
Space vector PWM (SVM)
4. Sinusoidal PWM Method
4.1 Sinusoidal PWM with Bipolar Voltage
Switching Scheme
In order to have a sinusoidal output voltage
waveform, a sinusoidal control signal V
control
at the
desired inverter output frequency f
1
is compared with
a triangular carrier waveform to generate the
switching signals as in Fig. 3.. The frequency of the
triangular waveform establishes the inverter
switching frequency f
s
and is kept constant.
The amplitude modulation ratio
tri
control
a
V
V
m
=
Where
control
V
is the peak amplitude of the control

signal and
tri
V
is the peak of the triangular carrier

wave.
Frequency modulation ratio
1
f
f
m
s
f
= .
When V
control
> V
tri
,
+
B A
T and T are kept on
and V
0
= V
d
.
When V
control
< V
tri
,
+
A B
T and T are kept on
and V
0
= V
d
..
The output voltage fluctuates between +V
d
and -V
d
..
The harmonic spectrum of V
0
is shown in Fig. 4.
The peak value of fundamental frequency component
of the output voltage.
d a
V m V =
01
.
Amplitude of the fundamental frequency component
of the output voltage varies linearty with m
a
provided
m
a
1.0. Range of m
a
in 0 to 1 is referred to as the
linear range. The harmonics in the inverter output
voltage waveform appear as sideboard contained
around the switching frequency and its multiples like
m
f
, 2
mf
, 3
mf
and so on. m
f
should be an odd integer so
that the output voltage waveform has only odd
harmonics. It is easier to filter out harmonics at high
frequencies. Hence, it is desirable to use high
switching frequency as possible which has the
drawback that the switching losses increase
proportionally. The border line between large and
small values of m
f
is selected as 21
For small values of m
f
(m
f
21), the
triangular waveform signal and the control signal
should be synchronized to each other. It is called
synchronous PWM. It requires m
f
be an integer. In
asynchronous PWM, where m
f
is not an integer,
subharmonics of the fundamental frequency are
produced which is not desirable. When m
f
is made
large, subharmonics due to asynchronous PWM are
small. Hence, at large values of m
f
, asynchronous
PWM can be used.
For SPWM, m
a
< 1.0 corresponds to linear
range and the amplitude of the fundamental
frequency voltage varies linearly with m
a
. But the
draw back is that the maximum available amplitude
of the fundamental frequency component is less.
When m
a
is increased beyond 1.0, amplitude also
increases which results in overmodulation. The
output voltage waveform contain many more
harmonics in the side bands as compared with the
linear range as in Fig. 5. Normalised peak amplitude
of the fundamental frequency component
d Ao
V V /
1
as
a function of modulation ratio m
a
is shown

in Fig. 6.
Fig.3. Bipolar SPWM scheme
Fig.4. Harmonic spectrum for Bipolar SPWM
SG 3
Harmonics that are dominant in the linear range may
not be dominant during overmodulation. Amplitude
of the fundamental frequency component does not
vary linearly with m
a
. In UPS application over
modulation region is avoided to minimise the
distortion in the output voltage . In induction motor
drives, over modulation is normally used. When m
a
is sufficiently large, the inverter voltage waveform
degenerates from a PWM into a square waveform.
4.2 PWM with Unipolar Voltage Switching
Each inverter of the full bridge configuration is
controlled separately by comparing the triangular
wave V
tri
with V
control
and V
control
.
When
V
control
> V
tri
T
A
+
on and V
AN
= Vd
V
control
< V
tri
T
A
-
on and V
AN
= 0.
For controlling leg B, -V
control
is compared with the
triangular waveform.
When
V
control
> V
tri
T
B
+
on and V
BN
= Vd
V
control
< V
tri
T
B
-
on and V
BN
= 0.
There are four combinations of switch on states and
the corresponding voltage levels.
This scheme is called Unipolar voltage switching
scheme because the output voltage changes from zero
and +vd or between zero and vd.
Devices in
the on state
V
AN
V
BN
V
0
+
A
T ,
B
T
A
T ,
+
B
T
+
A
T ,
+
B
T
A
T ,
B
T
Vd
0
Vd
0
0
Vd
Vd
0
Vd
-Vd
0
0
Harmonic spectrum is shown below. The switching
frequency is effectively doubled as far as the output
Fig.5. Harmonic spectrum for overmodulation in
Bipolar SPWM scheme
Fig.6. Variation of fundamental component of
output voltage with m
a.
Fig.7. Unipolar SPWM Scheme
SG 4
harmonics are concerned. Hence harmonics appear
at and side bands of m
f
, 2 m
f
, 3m
f
etc. Harmonics
disappear at 2 m
f
, 4 m
f

,
, 6 m
f
etc and they occur at
the side bands of the above frequencies.
4.3 Effect of blanking time on output voltage in
PWM inverters
When one switch of the inverter is in the on state, the
turn on of the other switch in the same leg is delayed
by a blanking time t
to avoid short circuiting. This

blanking time is chosen as few microseconds for fast
devices like MOSFETs and larger for slower devices.
The effect of blanking time on output voltage is
shown in Fig. 9. A constant dc voltage V
control
is
compared with the triangular waveform V
tri
which
determines the switching instants. During the
blanking time both the switches in one leg are off and
output voltage V
AN
depends on the direction of i
A
.
V
AN
(actual) is shown in for both types of i
A
.
The difference is
V
= V
AN
ideal V
AN
actual.
Average drop in output due to this is
Ts
t
V V
d AN

= if i
A
> 0.
=
Ts
t
V
d

if i
A
< 0.
Thus V
AN
does not depend on the magnitude of
current. But its polarity depends on the current
direction. It is proportional to the blanking time t
and the switching frequency f
s
(=1/T
s
). At higher
switching frequencies, faster switching devices that
allow t to be small should be used.
Applying the same analysis for leg B,
i
A
= -i
B
.
. 0 >
=

A d
s
BN
i V
T
t
V
. 0
A d
s
i V
T
t
V
0
= V
AN
- V
BN,
i
o
= i
A
.
The instantaneous average value of the voltage
difference is the average value during T
s
of the
idealized waveform minus the actual waveform is

. 0
2
0
2
0
0
0
<

=
>
=
=
i Vd
Ts
t
i Vd
Ts
t
V V V
BN AN
A plot of the instantaneous average value V
0
as a
function of V
control
is shown below with and without
blanking time. For sinusoidal V
control
, the
instantaneous average output V
0
(t) for a load current
i
0
(t) is shown below. i
0
(t) is assumed sinusoidal
and lagging behind V
0
(t). The distortion in V
0
(t) at
the current zero crossings results in low order
harmonics such as third fifth, seventh and so on of
the fundamental frequency in the inverter output.
Similar distortion occur in the line to line voltages at
the output of a three phase PWM inverter where the
low order harmonics are of the order 6m 1 (m = 1,
2, 3, ..) of the fundamental frequency.
Fig.8. Harmonic spectrum for unipolar SPWM
Scheme
Fig.10
Fig.9. Effect of blanking time
SG 5
.
.
4.4 PWM in 3 phase voltage source Inverters
To generate the switching signals, same triangular
voltage waveform is compared with three sinusoidal
control voltages that are 120
o
out of phase.
The phase difference between the m
f
harmonic in V
AN
and V
BN
is (120 x m
f
). this will be zero if m
f
is odd
and multiple of 3. Thus, the harmonic at m
f
is
suppressed in the line to line voltage V
AB
.
Modulation ratio m
a
1.0 is considered as the linear
range. The fundamental frequency component in the
output voltage varies linearly with the amplitude
modulation ratio m
a
.
The voltage V
AO
varies between
2 2
Vd
and
Vd +
.
The peak value of the fundamental component in V
ao
is
.
2
1
Vd
m V
a ao
=
RMS value of
2
2
01
Vd m
V
a
A
=
RMS value of the line to line fundamental voltage is
d a
d a
V m
V m
612 . 0
2
2
3
In overmodulation (m
a
>1.0), peak of the control
voltages are allowed to exceed the peak of the
triangular wave. Here, fundamental frequency
voltage does not increase proportionally with m
a
. In
the following figure, rms value of the fundamental
line to line voltage is plotted as a function of m
a
. For
sufficiently large values of m
a
, the PWM waveform
degenerates into square waveform. This results in
maximum value of V
LLI
equal to 0.78 V
d
. In the over
modulated region, more sideband harmonics appear
centred around the frequency of harmonics m
f
and its
multiples. However, dominant harmonics may not
have as large as an amplitude as with m
a
1.0.
Therefore, the power loss in the load due to harmonic
frequencies may not be as high in the over
modulation region as the presence of the sidebands
harmonics would suggest.
Fig.11. Effect of blanking time on output voltage
Fig.12. Three phase inverter
Fig.13. Three phase inverter output voltage
Fig.12. Harmonic spectrum in three phase
inverter output voltage
SG 6
5. Selected Harmonic Elimination PWM
(SHE PWM)
The undesirable lower order harmonics of a square
wave can be eliminated and the fundamental voltage
can be controlled as well by the SHE PWM method.
In this method, notches are created on the square
wave at predetermined angles as shown in the Fig.
15. Positive half cycle is shown with quarter wave
symmetry. Four notch angles
1
,
2
,
3
and
4
can be
controlled to eliminate three significant harmonic
components and control the fundamental voltage.
The general Fourier series of the wave is given as
t w n b t w n a t V
n
n
n
sin cos ) (
1
+ =

=
.
For the waveform with quarter cycle symmetry, only
the odd harmonics with sine components will be
present. Hence
=
=
1
sin ) (
n
n
t w n b t V
where
=
2 /
0
. sin ) (
4

dwt nwt t V b
n
Assuming that the wave has unit amplitude, that is,
V(t)=1, b
n
can be written as
(
(
(
(
(
+ + +
+ + +
=

3
2
2 /
2
1
1
0
sin ) 1 ( ....... sin ) 1 (
sin ) 1 ( sin ) 1 (
4
k
n
dwt nwt dwt nwt
dwt nwt dwt nwt
b
[ ] ) cos ..... cos cos ( 2 1
4
2 1 k
n n n
n

+ + + =
. cos ) 1 ( 2 1
4
1
(
+ =

K
K
k
K
n
The equation contains K number of variables like

1
,
2
,
3
.
k
. With K number of angles, the
fundamental voltage can be controlled and (K 1)
harmonics can be eliminated. The SHE method can
be conveniently implemented with a microcomputer
using lookup table of notch angles.
6. Minimum Ripple Current PWM.
One disadvantage of the SHE PWM method is that
the elimination of lower order harmonics
considerably boosts the next higher level of
harmonics. Since the harmonic loss in a machine is
dictated by the rms ripple current, it is this parameter
that should be minimized instead of emphasizing the
dimension of individual harmonics. RMS ripple
current is given by
I
ripple
= ......
2
11
2
7
2
5
+ + + I I I
= ......
2 2
2
7
2
5
+ +

I I
=
2
,... 11 , 7 , 5
2
1
= (
(
n
n
L n
V
Where,
I
5
, I
7
, .. rms harmonic currents.
L effective leakage inductance of the machine
per phase

7 5
, I I peak value of harmonic currents
n
V peak value of n
th
order harmonic
fundamental frequency.
n
V depends on notch angles . Thus, ripple current
can be obtained as a function of angles. The
angles can be iterated in a computer program so as to
minimize I
ripple
for a certain desired fundamental
magnitude.
7. Hysterisis bard Current Control
PWM
High performance drives invariably require current
control because, it influences the flux and developed
torque directly. Hysterisis band PWM is basically an
instantaneous feedback current control method of
PWM where the actual current continuously tracks
the command current within a hysterisis band. Fig.
Explains the principle of hysterisis band PWM for a
half bridge inverter. The control circuit generates the
sine reference current wave of desired magnitude and
frequency. It is compared with the actual phase
current wave. When the current exceeds a prescribed
hysterisis band, the upper switch in the half bridge is
turned off and the lower switch is turned on. The
output voltages charges from +0.5 V
d
to 0.5 V
d
and
the current starts to decay. As the current crosses the
lower band limit, the lower switch is turned off and
the upper switch is turned on. A lock out time is
Fig.15. Selected Harmonic Elimination Scheme
SG 7
provided at each transition to prevent short circuit.
The actual current in this forced to track the sine
reference within the hysterisis band by back and forth
(or bang-bang) switching of the upper and lower
switches. The inverter then essentially becomes a
current source with peak to peak current ripple,
which is controlled within the hysterisis band
irrespective of V
d
fluctuations.
When the upper switch is closed, positive slope of the
current is given as

L
t V V
dt
di
e cn d
sin 5 . 0
= .
Where 0.5 V
d
is the applied voltage, V
cn
sin
c
t is the
instantaneous value of the opposing load counter emf
and L is the effective load inductance.
When the lower switch is closed, negative slope of
the current is given as

L
t V V
dt
di
e cn d
sin 5 . 0
=
The peak to peak current ripple and switching
frequency are related to the width of the hysterisis
band. For example, a smaller band will increase
switching frequency and lower the ripple. An
optimum band that maintains a balance between the
harmonic ripple and inverter switching loss is
desirable. The bandwidth HB is given as
2 1
2
R R
R
V HB
+
= .
Where V is the comparator supply voltage. The
conditions for switching the devices are
Upper switch on: (i
*
- i) > HB.
Lower switch on (i
*
- i) < HB.
For a three phase inverter, a similar control circuit is
used in all phases.
8. Sigma-Delta Modulation
The principle of sigma delta modulation is given in
Fig.18. The modulator receives the concerned phase
voltage
*
ao
V at variable magnitude and frequency and
it is compared with the actual discrete phase voltage
pulses. The resulting error (delta operation) is
integrated (sigma operation) to generate the integral
error function e given as

= .
*
dt V dt V e
ao ao
The polarity of the error function is detected by a
bipolar compensator. The positive polarity of e
selects a positive voltage pulse whereas the polarity
selects a negative pulse.
9. Space Vector Modulation (SVM)
SVM is based on the space vector
representation of the voltages in the , , plane. They
are capable of producing the highest available
fundamental output voltage with low harmonic
distortion of the output current and are well suited for
digital implementation. Because of its superior
performance characteristics, if finds widespread
application in recent years. The SVM theory is based
on the concept of a rotating space vector. If a three
phase sinusoidal and balanced voltages are applied to
a three phase induction motor, it can be shown that
the space vector V with magnitude V
m
rotates in a
circular orbit at angular velocity . The direction of
Fig.16. Hysterisis band control scheme
Fig.17. Hysterisis band control scheme
Fig.18. Sigma Delta Modulation scheme
SG 8
rotation depends on the phase sequence of the
voltages. The composite PWM fabrication at the
inverter output should be such that the average
voltages follow the sinusoidal three phase command
voltages with a minimum amount of harmonic
distortion.
A 3 bridge inverter shown in Fig. 12 has
2
3
=8 permissible switching states. Following table
gives a summary of the switching states and the
corresponding phase to neutral voltages.
The inverter has 6 active states (1 6) when
voltage is impressed across the load and two zero
states (0 and 7) when the load terminals are shorted
through lower devices or upper devices respectively.
The vector V
1
(100) indicates the space vector for
switching state 1 and has a magnitude of
d
V
3
2
and
is aligned in the horizontal direction. In the same
way, all six active vectors and two zero vectors are
derived and plotted. The active vectors are /3 angle
apart and describe a hexagon boundary shown dotted.
Two zero vectors V
0
(000) and V
7
(111) are at the
origin. For three phase square wave operation of the
inverter, the vector sequence is V
1
, V
2
, V
3
, V
4
, V
5
, V
6
with each dwelling for an angle of /3 and there are
no zero vectors.
The space vectors are to be controlled to
generate harmonically optimum PWM voltage waves
at the output.
9.1 Linear or Undermodulation Region
In undermodulation region, the inverter transfer
characteristics are linear. The command voltages are
always sinusoidal and they constitute a rotating space
vector
*
V as shown in Fig. 19 . As an example, if
V
*
is located as in Fig. 19, then the convenient way
to generate the PWM output is to use the adjacent
vectors V
1
and V
2
of sector I on a part time basis to
satisfy the average output demand.
3
sin
3
sin

a
V V = |
.
|
\
|

3
sin sin

b
V V =
|
.
|
\
|
=
3
sin
3
2
*
V V
a
sin
3
2
*
V V
b
= .
where V
a
and V
b
are the components of V
*
aligned in
the directions of V
1
and V
2
respectively.
Consider a time period T
c
during which the average
output should match the command.
V
*
= V
a
+ V
b
= ( )
c
o
c
b
c
a
T
t
V or V
T
t
V
T
t
V
7 0 2 1
+ + .
or
V
*
T
c
= V
1
t
a
+ V
2
t
b
+ (V
0
or V
7
) t
0
.
Where
c
a
a
T
V
V
t
1
= ,
c
b
b
T
V
V
t
2
= , ) (
0 b a c
t t T t + =
Inverter devices are kept in the on state according to
space vector V
1
(100) for an internal t
a
and according
Fig.19. Space Vector Modulation scheme
Fig.20. Space Vector Modulation reference
phase voltage
SG 9
to V
2
(110) for an internal t
b
. Time to fills up the
remaining gap for T
c
with the zero or null vector.
Symmetrical pulse pattern for two consecutive T
c
internals is shown below. Here, T
s
= 2 T
c
= 1/f
s
(f
s
= switching frequency).
Null time has been conveniently distributed between
V
0
and V
7
vectors to describe the symmetrical pulse
widths. Symmetrical pulse patterns gives minimal
output harmonies.
In the under modulation region, the vector V
*
always
remains within the hexagon. The mode ends in the
upper limit when V
*
describes the inscribed circle of
the hexagon.
Modified modulation factor
ISW
V
V
m
*
1
=
Where
*
V - Peak value of reference

voltage
ISW
V
- Peak of the fundamental

component of the square wave =
d
V 2
.
m
1
varies from 0 to 1 at the square
wave output.
The maximum possible value of m
1
at the end of the
under modulation region is obtained as follows.
The radus of the inscribed circle is
. 577 . 0
6 3
2
*
d d m
V Cos V V = =

Therefore, m
1
for this condition is
. 907 . 0
3
2
577 . 0
*
1
= = =
d
d
ISW
m
V
V
V
V
m
This means that 90.7% of the fundamental at the
square wave is available in the linear region.
Compared to 78.55% in the sinusoidal PWM.
References
1. B K Bose, Modern Power Electronics and
AC Drives, Pearson Education, Inc, 2002.
2. N.Mohan, T M Undeland and WP Robbins,
Power Electronics, John Wiley, 1995
3. Dorin o Neacsu Space Vector Modulation
An Introduction, IECON01, 27
th
annual
Conference of the IEEE Industrial
Electronics Society, 2001.
Fig.19. Symmetrical pulse pattern for SVM
AUGMENTATION OF TRANSMISSION a review
S G MENON
Tata Consulting Engineers
Government Policy now encourages Independent
Power Producers & Large Scale Consumers
(Steel, Refinery, Fertiliser, Cement Plants etc.) to
generate Power for captive consumption and
feeding surplus power into connected grid This
helps in reducing burden on generation and T&D
allocation by Govt. But this requires system
discipline as the number and type of generating
agencies are higher
Steps in Expansion of T&D System
i) System Planning -- budget allocation for last
decade is less than 30% that of Generation
for T&D as against optimal of 100%
ii) Review Options:
a) New System or Strengthening/
Upgrading existing system (Physical
change)
b) Enhancing power system capability
(System Management)
Transmission System System Planning Criteria
1 Load forecast
(5yrs Short Term,10yrs Med Term,
15yrs Long Term)
2 Design redundancy (1
st
level)
3 Regional self sufficiency
(NREB,WREB,SREB,EREB, NREB)
(Tie lines exclusively for emergency
transfer) (Apply FACTS devices).
4 Voltage limits on EHV lines
( 5% Normal, 10% Emergency)
5 Equipment specifications (Line,
Transformer, CBs).
6 Requirement of series capacitors.
7 Optimal line loading (thermal limits)
if stability permits (Using FACTS devices)
8 System studies:
Anticipate system performance
(under normal and emergency condition)
Performance of AVRs, Governors,
Load shedding schemes, OLTC
9 Planning for network control and
management(for optimal usage of
system)
10 Reactive compensation (Voltage
improvement, through SVS)
a) Upgrading Existing T&D System-
Developing a New System demands-
Higher initial cost. Long gestation
period,Acquisition of land &Right of way
To overcome these issues,
Strengthening & Upgradation is an
attractive option
OPTIONS
Change of conductor size (managing current)
Upgrade Voltage on same line (managing
current)
Use of multi-circuit tower (managing ROW)
Use of insulated cross-arm (managing
ROW/Clearances)
Reduced span for reduced sag (managing in
crowded area)
Clearances to the minimum as per rules
Use of lighter but electrically superior
conductors (AAAC)
b) Enhancing Power System Capability by
modern Technology-Flexible AC Transmission
System
Types of FACTS Devices:
Static Var Compensator (SVC)
shunt connected Var generator for control
of capacitive/ inductive
reactive power. Large numbers are in
operation
Static Synchronous Compensator
(STATCOM)
Shunt connected GTO based convertor for
control of capacitive/ inductive reactive power.
Several are in operation in Japan and one in
the USA
Thyristor Controlled Series
Capacitor (TCSC)
For enhancing transient stability
limit of the line
Improved voltage regulation and reactive
power balance
SGM-1
Improved load sharing between parallel lines
Other benefits:
- Mitigation of SSR risks.
Damping of active power oscillations.
- Dynamic power flow control.
Significant no. of TCSC units are in
operation.
Raipur Rourkela 400 kV line recent order for
900 MVArUnified Power Flow Controller
(UPFC):
- Provides independent control of active and
reactive power.
- It is an ideal controller.
- Limited Experience
Case study
One case study was conducted wherein it was
required to limit the flow of reactive power
from one area to other in an interconnected
system. It was found that it is possible to limit
VAR flow within specified limits by use of
TCVR in the interconnected line.
It was also found that the combination of UPFC
and TCVR installed at two different ties
between interconnected systems will have
limited control over distribution of active
power flow and reactive power flow between
two systems.
Use of HVDC light to isolate systems e.g Large
industrial Generation
installing a 500 MW unit ( large size) in 3000
MW system (contingency of loss of biggest unit,
using suitably designed-and-positioned FACTS
device)
Captive generators are small compared to the
Grid. Hence, it requires special care to protect
these generators, in case of grid disturbances
.Isolation from Grid disturbances could also be
done by FACTS or HVDC. Currently Islanding
is one technique used.
The collapse of captive generation during grid
disturbances should be avoided
Hence, islanding schemes must be
incorporated in the system
After islanding, if there is excess load
compared to captive generation availability, load
shedding has to be initiated to save captive
system
Developement of FACTS
Power electronic controllers form the basis of a
Flexible AC Transmission System (FACTS),
which has been under development for nearly
twenty years and is now entering its third
generation.
The first generation of FACTS devices used
power electronics to control large transmission
circuit elements, such as capacitor banks, to
make them more responsive to changing system
conditions.
Second generation FACTS devices were able to
perform their functions, such as providing
voltage support to a long transmission line,
without the need for large, expensive external
circuit elements. Both first and second
generation FACTS controllers are currently
operating on utility transmission networks.
-Third generation FACTS called the Unified
Power Flow Controller (UPFC). The UPFC has a
unique ability to control simultaneously all three
parameters (voltage, phase angle, and
impedance) that govern power flow over
transmission lines. The first installation of a
UPFC has been completed at a substation of the
American Electric Power Company (AEP),
where it will increase power flow into a region of
rapid demand growth while also providing
voltage support for a neighboring industrial
region.
Limitations of FACTS
Stability issues can be managed more
economically at the generator end with advanced
stabilizer controls as stabilizer components need
only handle a fraction of the power they actually
control - the generator is like a big amplifier with
the signal conditioning being done at relatively
low power levels. By comparison, FACTS
technologies must handle the full power being
controlled.
However FACTS device can be deployed and
justified on the basis of other functions and to
provide other benefits, such as controlling power
flow in a corridor.
FACTS would have to be critically checked on a
case by case basis as our circuits are not
underutilised. Actually our main problem is
thermal limits on circuits.
Case Study will be presented and discussed in
detail
SGM -2
HVDC AND FACTS
P. Preetha
Lecturer
EED, NITC
Introduction.
The industrial growth of a nation requires
increased consumption of energy, particularly
electrical energy. This has lead to increase in the
generation and transmission facilities to meet the
increasing demand. Remote generation and system
interconnections lead to a search for efficient
power transmission at increasing power levels.
The problems of AC transmissions particularly in
long distance transmission have led to the
development of DC transmission. However as
generation and utilization of power remain at
alternating current, the DC transmission requires
conversion at two ends from AC to DC at the
sending end and back to AC at the receiving end.
This conversion is done at converter stations-
rectifier station at the sending end and inverter
station at the receiving end. The converters are
static- using high power thyristors connected in
series to give the required voltage ratings. The
physical process of conversion is so that the same
station can switch from rectifier to inverter by
simple control action, thus facilitating power
reversal.
With the developments of modern systems, it
becomes more and more important to control the
power flow along the transmission corridor. The
evolutionary process in the 1970s by introducing
power electronics based control for reactive power
and high voltage direct current (HVDC)
transmission has been greatly accelerated. Many
countries in Asian region are expanding their
electric power systems by augmentation or
construction of new high voltage (HV) or Extra
high voltage (EHV) power transmission systems,
interconnection of power systems within the
country and across country borders via HVDC or
EHV lines with flexible alternating current
transmission systems (FACTS) controllers.
At present, most high voltage transmission lines
are operating below thermal ratings due to
constraints such as voltage and transient stability
limits. Power electronics based technology
(HVDC & FACTS) can enhance transmission
system control and increase line loading in some
cases all the way to thermal limits without
compromising reliability. Based on these
capabilities, operational bottlenecks can be
eliminated, line capacity can be increased, and
reliability can be improved. These capabilities
allow transmission systems owners and operators
to maximize asset utilization and execute
additional bulk power transfers, with immediate
bottom-line benefits. Moreover, FACTS
controllers can also enable utilities to avoid or
minimize the time consuming, source-intensive
process of constructing new transmission facilities
and instead concentrate on maximizing
profitability of existing facilities as the market for
transmission service expands.
Comparison of AC and DC transmission:
The relatives merits of two modes of
transmission, which need to be considered by a
system planner, are based on the following factors.
Economics of transmission
Technical performance
Reliability
Economics of power transmission:
The cost of a transmission lines includes the
investment and operational cost. The investment
includes costs of Right of Way, Transmission
towers, conductors, insulators and terminal
Equipment. The operational cost includes mainly
the cost of losses.
Investment costs: Assuming same insulated
characteristics for AC and DC and based on peak
voltage: DC line (2 conductors+/- polarity w.r.t
ground) can carry as much current as AC (3
conductors of same size). For a given power level,
DC line requires less RoW, simpler and cheaper
towers and reduced conductor and insulator cost.
The terminal equipments (converters/ filter) are
costly and the break-even distance can vary from
500 to 800 Km in overhead lines. Figure (1) shows
the variation of costs of transmission with distance
for AC and DC transmission.
PP-1
Operational Cost: The corona effects tend to be
less significant on DC conductors than for AC.
Technical Performance:
DC: Power flow is controlled
(modulation for stability enhancement, fault
current limiting in DC lines is also possible)
Ground return possibility in DC due
to relatively low ground impedance for extended
periods. Buried metallic structures may pose
problems due to corrosion
Transformation of voltage level for
utilization is not possible without converter
station.
When two power systems are
connected through AC ties (synchronous
interconnection) the automatic generation control
of Both systems have to be coordinated using tie
line power and frequency signals. Even with
coordinated controls the operation of AC ties can
be problematic due to (i) The presence of large
power oscillation, which can lead to frequent
tripping (ii) Increase in fault level (iii)
Transmission of disturbances from one system to
the other. The controllability of power flow in DC
lines eliminates all the above problems
When the frequency of the two
systems is different the interconnection requires
the use of DC links.
Technical Aspects: Long distance AC
transmission
The power transfer in AC lines is dependent on the
angle difference between the voltage phases at the
two ends, for a given power level this angle
increases with distance. The maximum power
transfer is limited by the consideration of steady
state and transient stability. The power carrying
capability of AC/DC lines as a function of distance
is shown in Figure (2).
DC Line
P
SIL AC Line
distance
Figure 2 Power transfer capability vs distance
The line charging complicates the voltage control
in AC lines and inductive voltage drops. The
voltage profile in an AC line is relatively flat only
for a fixed level of power transfer corresponding to
surge impedance loading. (SIL). The voltage
profile varies with the line loading. Reactive
power generated or absorbed depends on deviation
from SIL. Therefore reactive power compensation
is necessary at various points and loading cannot
deviate much from SIL If voltage at both end is
maintained at 1, the voltage tend to sag as we
move towards the mid point if Ps > SIL. The line
absorbs reactive power. If Ps is < SIL voltage
swells and the line generates reactive power. AC
lines require shunt and series compensation in long
distance transmission, mainly to overcome the
problems of line charging and stability limitations.
Series capacitors and shunt inductors are used for
this purpose.
Although DC converter stations requires reactive
power related to the line loadings the line itself
does not require reactive power. HVDC find use in
the following situations
Long distance bulk power
transmission
Asynchronous Ties
Underwater cable transmission
Reliability
The reliability of DC transmission system is quite
good and comparable to that of AC systems. The
bipolar DC line can be as reliable as a double
circuit AC line with the same power capability.
This is because of the fact that the failure of one
pole does not affect the operation of the other pole
(with ground return).
Types of HVDC systems
Two terminal (with DC transmission line, one
rectifier terminal + one inverter terminal) Back-to-
Back (two terminal with no DC line used for
asynchronous tie) Multi-terminal (with DC lines
Distance
AC
DC
Cost
a
a-break even distance
Fig.1 Variation of cost with line length
PP-2
and several rectifier and/or inverter terminals
connected to more than 2 nodes of the AC
network).
Types of links
The DC links are classified into three types:
Mono polar link (figure 3.1) has
one conductor usually of negative polarity and
uses ground or sea return.
I
Fig 3.1 monopolar link
Bipolar link (figure 3.2) has two
conductors, one positive and other negative. Each
may be a double conductor in EHV lines. Each
terminal has two sets of converter of identical
ratings, in series on the DC side. The junction
between the two sets of converters is grounded at
one or both ends.
I
Homopolar link (figure3.3) has
two or more conductors all having the same
polarity, usually negative and always operated
with ground or metallic return.
I
2I
I
Fig 3.3 Homopolar link
Components of HVDC Transmission Systems
The major components of HVDC transmission
systems are converter stations. A typical converter
station with two 12-pulse converter units per pole
is shown in figure 4. The various components of a
converter station are converter unit, converter
transformer,
filter, reactive power source, smoothing reactor
and DC switchgear.
Converter Unit: this usually consists of two three-
phase converter bridges connected in series to
form a 12-pulse converter unit as shown in figure
5. The total number of valves in such a unit are 12.
The converter is fed by converter transformer
connected in star star and star-delta arrangements.
DC
Terminal
AC
Bus
Fig 5. A 12 pulse converter unit
Fig 3.2 Bipolar link
Pole 1
Fig 4 Schematic diagram of a typical
HVDC converter station
Tuned AC Filters
DC
Filters
Pole 2
Transformer
Smoothing reactor
12 Pulse
converter
PP-3
Filters: There are three types of filters used.
AC filters: These are passive
circuits used to provide low impedance, shunt
paths for AC harmonic currents.
DC Filters: These are similar to
AC filter and are used for the filtering of DC
harmonics.
High frequency filters: These
are connected between the converter transformer
and the station AC bus to suppress any high
frequency currents.
Reactive Power Source: Converter station
requires reactive power supply that is dependent
on the active power loading apart of this reactive
power requirement is provided by the AC filter in
addition shunt capacitors, synchronous condensers,
SVC and STATCOM are used depending on the
speed of control desired.
Smoothing Reactor: Sufficiently large series
reactor is used on DC side to smooth DC current.
HVDC and FACTS
HVDC systems are very useful for transmitting
energy between two asynchronous AC power
systems with high controllability. Conventional
HVDC transmission systems based on thyristor
converters have been widely applied where
flexibility and stability improvements are required.
However, thyristor based HVDC systems need
high support of local reactive power generation.
Moreover the active and reactive power cannot be
controlled independently from each other. New
HVDC system based on DC voltage links has been
considered feasible. Since they are based on force
commutated converters (also known as voltage
source converters VSC) they can provide
independent control of active (real) and reactive
(imaginary) power or even supply fully passive ac
loads.
The STATCOM is advanced power electronic
equipment for reactive power compensation. It is a
very fast acting, electronic equivalent of the
synchronous condenser. It is considered as a
flexible AC transmission systems controller
(FACTS). The STATCOM is a shunt compensator.
It can draw variable reactive current from the
system to control the voltage magnitude of a
selected bus (controlled AC bus). Thus HVDC
transmission system based on VSC technology is
an interesting alternative to conventional thyristor
based HVDC system in the fields of
Interconnecting week or isolated
AC systems
Interconnecting AC systems in
the lower and middle power range
Connecting remote isolated
loads like offshore oil and gas platforms.
Multi terminal HVDC systems
Ongoing development in the sector of power semi
conductors for high power applications is expected
to widen the range of commercial applications in
the near future.
REFERENCES
K.R Padiyar, HVDC Power
Transmission systems: Technology and system
Interactions, Wiley Eastern Ltd., New Delhi, 1990.
High voltage Direct Current
transmission systems Technology Review Paper
by Roberto Rudervall , Raghuveer Sharma.
HVDC Transmission Systems
using Voltage Sourced Converters- Design and
Application by F.Schettler, H Huang and N
Christl.
FACTS Option Permits The
Utilisation of The Full Thermal Capacity of AC
Transmission By D N Ewart, R J Koessler
Flexible AC Transmission
Controllers By Gautam Bajracharya
PP-1
PP-4
SK1 1
SINGLE-PHASE SHUNT ACTIVE POWER FILTER
Suresh Kuamr.K.S
Asst. Professor,Dept. of Elect. Engg.
N.I.T ,Calicut
1. Introduction
The increasing use of power electronics-based loads (adjustable speed drives, switch mode
power supplies, etc.) to improve system efficiency and controllability is increasing the concern for harmonic
distortion levels in end use facilities and on the overall power system. The application of passive tuned filters
creates new system resonances which are dependent on specific system conditions. In addition, passive filters
often need to be significantly overrated to account for possible harmonic absorption from the power system.
Passive filter ratings must be co-ordinated with reactive power requirements of the loads and it is often difficult
to design the filters to avoid leading power factor operation for some load conditions. Active filters have the
advantage of being able to compensate for harmonics without fundamental frequency reactive power concerns.
This means that the rating of the active power can be less than a comparable passive filter for the same non-
linear load and the active filter will not introduce system resonances that can move a harmonic problem from one
frequency to another.
The active filter concept uses power electronics to produce harmonic current components that
cancel the harmonic current components from the non-linear loads. The active filter uses power electronic
switching to generate harmonic currents that cancel the harmonic currents from a non-linear load. The active
filter configuration investigated in this lecture is based on a pulse-width modulated (PWM) voltage source
inverter that interfaces to the system through a system interface filter as shown in Figure 1. In this configuration,
the filter is connected in parallel with the load being compensated. Therefore, the configuration is often referred
to as an active parallel or shunt filter. Figure 1 illustrates the concept of the harmonic current cancellation so that
the current being supplied from the source is sinusoidal. The voltage source inverter used in the active filter
makes the harmonic control possible. This
inverter uses dc capacitors as the supply
and can switch at a high frequency to
generate a signal that will cancel the
harmonics from the non-linear load.
The active filter does not
need to provide any real power to cancel
harmonic currents from the load. The
harmonic currents to be cancelled show up
as reactive power. Reduction in the
harmonic voltage distortion occurs
because the harmonic currents flowing
through the source impedance are reduced.
Therefore, the dc capacitors and the filter
components must be rated based on the
reactive power associated with the
harmonics to be cancelled and on the
actual current waveform (rms and peak
current magnitude) that must be generated
to achieve the cancellation.
The current waveform for cancelling harmonics is achieved with the voltage source inverter in
the current controlled mode and an interfacing filter. The filter provides smoothing and isolation for high
frequency components. The desired current waveform is obtained by accurately controlling the switching of the
insulated gate bipolar transistors (IGBTs) in the inverter. Control of the current waveshape is limited by the
switching frequency of the inverter and by the available driving voltage across the interfacing inductance.
The driving voltage across the interfacing inductance determines the maximum di/dt that can
be achieved by the filter. This is important because relatively high values of di/dt may be needed to cancel higher
order harmonic components. Therefore, there is a trade-off involved in sizing the interface inductor. A larger
inductor is better for isolation from the power system and protection from transient disturbances. However, the
larger inductor limits the ability of the active filter to cancel higher order harmonics.
The Inverter (three-phase unit or single-phase unit as the case may be) in the Shunt Active
Power Filter is a bilateral converter and it is controlled in the Current Regulated mode i.e. the switching of the
Inverter is done in such a way that it delivers a current which is equal to the set value of current in the current
control loop. This mode of operation of a PWM-VSI has been covered in detail in an earlier lecture. Thus the
basic principle of Shunt Active Power Filter is that it generates a current equal and opposite in polarity to the
SK1 2
harmonic current drawn by the load and injects it to the point of coupling thereby forcing the source current to be
pure sinusoidal. This type of Shunt Active Power Filter is called the Current Injection Type APF.
2. A Single Phase Current Injection Type Active Power Filter
Single-Phase topology is assumed for purposes of explanation for the sake of simplicity.
Whatever is covered here will be equally applicable for three-phase systems also with minor modifications. A
simplified diagram of a single-phase APF is given in Fig.2 below.
The control system maintains the average voltage across the capacitor constant against
variations in line and filtering load on the APF.The Inverter is gated in such a way that the current I
L
follows a
reference current waveform set by the concerned control system. The voltage required at the terminals of Inverter
output will be automatically made suitable for maintaining the required current in the L
f
line,i.e. the Inverter is
controlled in the 'current regulated' mode. The current delivered by the source I
s
= I
o
- I
L
and it is desired that this
current be a pure sinusoidal wave even when the load draws a highly distorted current wave. This is
accomplished by making I
L
equal to the harmonic current required by the load. Thus,there has to be a harmonic
current calculator which will calculate the harmonic current to be generated by the Inverter in order to maintain
the source current harmonic free. Under a loss free situation, the Inverter does not need to draw any active
power. However,there will be losses in the resistances of inductor,switches etc. and switching losses when the
Inverter is generating current. Unless these losses are compensated , the capacitor voltage will come down
steadily. Hence the control of capacitor voltage involves drawing an in phase sinusoidal component of current
from the source along with the required harmonic currents, i.e. the reference current for I
L
should contain an
appropriate amount of 180
0
component to maintain the D.C voltage across the capacitor.
It is indeed possible to make the Inverter deliver the reactive current demanded by the load
along with its harmonic current requirement by providing suitable reference. In that case APF becomes an SVC -
cum-APF or an APF-cum-SVC.In fact,it should by now be clear that, whether it does reactive compensation or
not, the operation and control of this APF is almost the same as that of the SVC with Current Regulated Control.
The basic principles involved are the same. But, usually in an SVC harmonic filtering is not attempted along
with Fundamental frequency VAr compensation since the range of switching frequencies needed for APF action
is much higher than the frequency needed for SVC action. The kVAr rating of SVC for a load will be much
higher than the kVA rating needed for an APF.Hence it is better to use a small kVA rated Inverter with high
switching frequency(thereby demanding IGBTs/MOSFETs) for the APF function and a high power Inverter with
low switching frequency for ( thereby permitting the use of thyristors and GTOs) for SVC action. In fact , if the
two jobs are separated this way,it is possible to run the SVC at a still lower frequency with the APF helping to
cancel the harmonics generated by the low frequency switching of SVC partially. Such systems have been made
at subtransmission level. Notwithstanding the above, the continuous improvement in the voltage and current
ratings of IGBTs and MOSFET power modules has made it possible to combine both SVC and APF functions in
the same Inverter at distribution levels(i.e. at 440V,1.1kV,3.3kV,6.6kV and 11kV levels).
The control of a single-phase APF using hysterisis current control is given in Fig.3.The D.C
voltage across the capacitor is sensed,compared with reference and the error is processed in a PI controller. This
error multiplies a fixed amplitude sine wave which is pure and is in 180
0
phase with the source. The product
forms one component of the current reference of the Inverter.The harmonic current calculator receives the load
current signal from the CT in the load line and a pure sine wave template from the control system and calculates
the harmonic current component in the load in real time. The output of this calculator forms the second
SK1 3
component of reference current. These two components are added together and given as current reference into a
hysterisis current controller.
3. Current Control Schemes Suitable for APF
The block diagram above assumed hysteresis current control and hysteresis current control is
indeed suitable if only low order harmonics (like 3
rd
,5
th
,7
th
etc.) need be compensated. However,if harmonics
upto 25
th
or so are to be cancelled ,hysteresis control will require excessively high switching frequency. In
addition, the variation in switching frequency which is basic to hysteresis control makes it difficult to choose
filter components. Hence constant switching frequency,unipolar switching schemes are preferred for
implementing current control of Inverter in APF application as a rule.
In one constant switching frequency current control scheme,the filter inductor current is sensed
and compared directly with the reference current to form the current error. This error is amplified and used as the
modulating signal in the unipolar pulse width modulator which controls the gating of switches. This scheme
suffers from some disadvantages. First,the current sensed will have switching ripple in it and it will have to be
filtered before getting into the high gain error amplifier. This filtering introduces a time delay. Already the
system is of second order due to the L
f
and C
f
.This second order dynamics has sharp phase angle variation near
its resonance frequency due to its underdamped nature. In addition, the phase delay contributed by it depends
strongly on the operating condition. Now if a high gain stage with a first order filter is put in the feedback path ,
the system easily becomes unstable. Even if it is stable, its transient response will not be satisfactory. This will
call for reduction of gain in the error amplifier which will affect the ability of the APF to track the reference
current adversely. If a high gain has to be used then a high switching frequency becomes mandatory.
Secondly,the current that is being sensed is current in a switching system and will be corrupted by the inevitable
high frequency switching noise. The control loop usually gets thoroughly upset with this noisy feedback.
These limitations of feedback control scheme provided the motivation for the development of a
feed-forward control scheme for the control of current in the Inverters.The principle of this scheme follows.
Assuming the control is successful,the current that will flow through L
f
is known apriori and it
is equal to the reference current. Then,if the I
L
value is known before hand ,the voltage that the Inverter should
generate in order to make this current flow can be calculated and the calculation result(a voltage signal) can be
given as the modulating signal for the unipolar PWM generator. The voltage that the Inverter should generate is
given below by applying K.V.L.
V
inv
= V
ac
+ RI
ref
+ L
f
(dI
ref
/dt) where I
ref
is the current commanded by the control system,R is
the equivalent loss resistance(includes winding resistance,switch power loss etc.) , L
f
is the filter inductance and
SK1 4
V
ac
is the source voltage. A simple Opamp circuit can implement the above equation by accepting a stepped
down version of source voltage and the reference current signal as the inputs .The output of the circuit is given to
the unipolar PWM circuit after suitable scaling. Then the Inverter generates the right voltage and hence the
current in L
f
will have to be I
ref
.
However, this requires the knowledge of accurate values of R and L
f
.The value of R is
operating point dependent (through switch power losses) and can not be known accurately. If these values are
precisely known the current control would have been 'free of dynamics' i.e.,the bandwidth of current control loop
would have been infinite. But there are inaccuracies in the estimation of the parameters and inaccuracies in the
measurement of V
ac
.Also the differentiator operation has to be band limited in practise due to the well known
sensitivity of differentiator to noise and high frequency signals. These imperfections make the current control
logic deviate from the ideal and a small amount of actual current feedback will be needed along with the other
components to correct the minor deviations. However, now the role of current feedback is only to correct second
order effects and hence can be of low gain. Moreover, for the same reason no filtering is needed in the feedback
path. With this term added ,the Inverter voltage control equation becomes:
V
inv
= V
ac
+ RI
ref
+ L
f
(dI
ref
/dt) +K ( I
ref
- I
L
) where K is the feedback gain and is usually very
small. This scheme is capable of rise time of 50s -250 s and yields a high bandwidth current control loop
which is highly desirable in APF since APF is expected to track up to 25
th
harmonic and more.
K is the feedback gain,Kpwm is the gain of Inverter and Z
0
(s) is the equivalent load impedance
connected at the a.c source point.
4. The D.C Voltage Control Loop
The D.C voltage control loop in APF is similar to the D.C control loop of Active Line
Conditioners or PWM Rectifiers , Static VAr Compensators etc, and similar considerations apply.
The instantaneous power input into the inverter (due to harmonic currents, fundamental active
current needed to supply the inverter losses and fundamental reactive power if static Var compensation is also
being performed) from mains will get balanced by (i) the dissipation in the inverter and capacitor (ii) the rate of
change of stored energy in the inverter passive filter reactive elements and (iii) rate of change of stored energy in
the DC Side Capacitor. The inverter losses and the power that goes into changing the energy storage in the small
filter elements may be ignored in a first order qualitative analysis and we may say that to a good approximation
the instantaneous power that goes into the inverter reaches the DC Side capacitor. Fundamental current flow
(which will be a small active component if no shunt Var compensation is being done) will result in second
harmonic pulsations in the inverter input power and this should lead to second harmonic voltage components
appearing across DC side capacitor. Harmonic current flow into inverter similarly will give rise to higher
harmonic voltage ripples in the DC Side Capacitor.The second harmonic ripple in voltage across the DC Side
capacitor can cause some difficulty in the DC voltage control loop.The problem becomes significant if the
inverter is doing VAr control as well as harmonic control.
K
R/KsKpwm
(Lf/KsKpwm)d/dt
Kpwm
R
Ks 1/sLf
Zo(s) 1/Kpwm
+
+
+
+ +
Iref
+
+
+
- -
-
+
+
+
IL
Fig.4 Feedforward Current Control Scheme
+
+
SK1 5
When the DC Side voltage is sensed , compared with a set reference and the error is amplified
the second harmonic (and higher harmonics in capacitor voltage) get amplified and appear at the output of the
error amplifier.The second harmonic at the error amplifier output results in a third harmonic component
appearing in the reference current and this will lead to injection of third harmonic current in the line.The DC
Side voltage will have to be filtered to remove the second harmonic to prevent this.This filtering will invariably
slow down the DC voltage control loop which in turn will call for a higher value of DC side capacitance.
However, since the 50 Hz current in the Inverter line of an APF is small ,the DC side capacitor
will not have much second harmonic ripple and hence not much filtering is required on this voltage before it gets
into the control loop if the APF will never be required to do static VAr compensation too. By the same reason,
the D.C loop control can be faster in APF compared to APLC,SVC or Switched Mode Rectifier.
5. The Harmonic Current Calculator
This is the most important component in the control system. It accepts the load current and
sinusoidal templates from the PLL-Sine wave generator and returns the value of harmonic content of the load
current for further control purposes. The D.C side capacitor should not be asked to supply even a fraction of the
active power required by the load since it will run down rapidly if that happens. Hence, the Calculator must
ensure that neither under steady state nor under load transient conditions the calculated current will contain an
active fundamental component. However, it is not possible to ensure this under transient conditions strictly. Then
the Calculator must reduce the active component to zero as fast as possible. Any delay on the part of this
Calculator in removing the active power component in its output will be translated as higher and higher value for
the D.C side capacitor especially considering the unavoidable filtering in the DC voltage control loop.
The method for extracting the reactive fundamental component contained in a sinusoidal
current is based on extraction of orthogonal fundamental frequency components from the waveform. The sensed
load current is multiplied with unit amplitude sine and cosine waves (produced by PLL + EPROM method). The
products are integrated over one half cycle. The value of integrated outputs are sampled and held at the end of
the half cycle period and after sampling the integrators are reset briefly to start the next cycle of integration. The
sampled outputs will be the amplitude of active and reactive component respectively. The unit sine and cosine
templates are multiplied by these amplitudes to re-create the active and reactive fundamental components and
their sum is subtracted from the total load current. The result will be the instantaneous harmonic content in the
load current and this is sent to the output. Obviously, the maximum delay in the calculation is one half-cycle
time.This method of harmonic component calculation is insensitive to the presence of harmonics in supply
voltage.If the both the supply voltage and load current contain harmonics it is possible that some active power
transfer is taking place through harmonics.Then these active power components will be missed out by this
calculator ; but then the voltage control loop will handle this. However this method is sensitive to supply
frequency and component tolerances and can result in wrong estimates of harmonic components if frequency
varies over a wide range.
If the products of
load current and unit sine/cosine
templates are passed through low pass
filters of cutoff around 10Hz (to avoid
100Hz components in the products)
we can get the active and reactive
fundamental components of the load
current. Subtracting these components
from the total will lead us to the
harmonic content. And in order to
make the circuit rugged against
parameter inaccuracies and variations
the following closed loop system has
been suggested.(See A Simple
Frequency Independent Method for
Calculating the Reactive and
Harmonic Current in a Nonlinear
Load , J.Sebastian Tepper et.al, IEEE
Trans. On Industrial Electronics, Vol
43, No 6, Dec 1996, pp 647-654)
The low pass filter
in this scheme has to be of very low
bandwidth , otherwise the second
harmonic that comes through will
manifest as third harmonic in the line current.But then a low bandwidth in the LPF will make the circuit very
SK1 6
slow and when a sudden load change takes place all the load current will come through in name of harmonics
because of delayed response of LPF.This will lead to inverter trying to support the load active power for too long
- the result is too heavy a value for the DC Side Capacitor.
The two methods of harmonic extraction described above were compared by PSpice Simulation.The outputs
when a 1Volt amplitude 50 Hz pure sine wave was applied are shown below.The differences are clear.
6. Simulation of a Single Phase Active Power Filter
The Design Lab Simulation diagram for the simulation of a 0.5kVA Active Power Filter of
Current Injection type is given below.
The APF simulated uses a 230V,50Hz,500VA Single Phase Full Bridge Inverter using
IRFP450 MOSFETs as the power converter. An inductance of 1mH and a shunt connected capacitance of 2 uF
carry out the filtering of inverter output to remove the switching frequency components. The output of the
inverter is tied to the a.c supply and a non-linear load is supplied from the point of common coupling. The
SK1 7
Inverter uses unipolar PWM using triangular carrier of 20kHz.The inverter works in the current regulated mode
using feed forward method of current control.
There are two time dimensions involved in simulating a power electronic system of this kind
in Pspice. One is the period of switching in the inverter and the other is the characteristic time constants involved
in the rest of the control loops. These time constants could be in 10s or 100s of milliseconds. Simulating the
switching behaviour of an inverter in PSpice will require very small time steps due to the switching transients in
MOSFETs and IGBTs taking place in the nano second time range. Such a simulation long enough to cover at
least one full cycle of 50 Hz output in the case of a unipolar modulated inverter using 20kHz triangle carrier will
take 10s of minutes for completion. And long duration simulations at small time steps will usually encounter
convergence problems in Pspice. The outer control loop dynamics on the otherhand proceeds slowly compared to
the switching frequency. Thus simulation over many a.c cycles will be needed to catch dynamics of interest in
systems of the type described here. Obviously one cannot retain all the details of the inverter and simulate for
many a.c cycles.
The solution to this problem of excessively large simulation time and frequent convergence
problem lies in decoupling the two time dimensions. Two separate simulation models are to be derived for this.
In the first the inverter along with its gating control logic alone will be simulated with time step suitable for the
switching frequency. The simulation schematic will be same as the circuit diagram of the inverter with all
components and details. The simulation will be carried out for one or two cycles of a.c for different loading on
the inverter. The loading is arranged to represent the actual loading on the inverter when the inverter becomes
part of APF. The aim of this separate simulation of inverter in a stand alone mode is two fold. Primarily, the aim
is to verify the operation of electronic circuits and drivers (pulse transformer based , opto based as the case may
be) used in gating logic and to verify various critical issues like sufficiency of dead time designed into gating
logic etc. Secondly stand alone simulation of inverter is used to estimate the total losses taking place in the
inverter under various load conditions. Based on the loss data the equivalent loss resistance of the inverter can be
worked out. This value of equivalent inverter loss resistance is needed to simulate the dynamic behaviour of APF
and to design proper compensators in the APF control loops. Such a simulation was carried out and the loss
resistance was found to be 0.2 ohms. This value is used in the simulation diagram in Fig.4
The second simulation model is used to simulate the dynamics of the complete system. The
switching frequency domain is eliminated in this model by using an average model for the inverter. The time
constants involved in dynamics are usually lage compared to switching period in the inverter and hence nothing
much happens in the dynamics during one switching period. The dynamics responds to a sort of averaged effect
of the switching taking place in the inverter. In the present simulation the principle of Power Balance is used on
the inverter to arrive at an averaged model for the inverter. The a.c side power and d.c side power in the case of
an inverter will have to be equal within losses and changes in reactive energy storages. But the reactive
components in the inverter will be small value due to high frequency switching and the rate of change of their
energy storage can be ignored in a first order model. Then the a.c side power and d.c side power will be equal
within the loss in the inverter equivalent resistance.
In the simulation model shown in Fig.4,the inverter output is modelled as a voltage controlled
voltage source with saturation behaviour. The input side i.e, the d.c capacitor side modelled by implementing
power balance through an ABM block. The ABM block senses the inverter a.c side current, multiplies it by
inverter output voltage and divides the product by the d.c side capacitor voltage. Using power balance principle it
can be seen that the result of this calculation will be the capacitor current. ABM block output is a current and this
SK1 8
is fed into the capacitor node. The sensing points avoid the inverter loss resistance.
The load current is sensed and its harmonic content waveform is calculated by the harmonic
calculator block shown in Fig.5. This block implements the harmonic current calculation algorithm described
earlier.
The d.c capacitor voltage is compared with a set value and the error is processed in an opamp
based PI controller. The PI Controller output multiplied by unit amplitude sine wave becomes the active current
reference. The total current reference is formed by adding the harmonic calculator block output and the active
current component.
The reference current which comes out as a voltage signal in the simulation diagram is
converted into a current by the G device and the current is pushed into an impedance representing the net
impedance between the inverter and the a.c supply. The drop in the impedance added to the a.c supply voltage
will have to be the output voltage synthesised by inverter. Thus inverter control voltage is obtained by scaling
this voltage suitably.
The load circuits contain standard rectifies/thyristors to simulate a non-linear current load. Two
switches with controllable ON/OFF instants are included to simulate the load-switching transients on the APF.
7. Simulation Results
Case-1 Rectifier Load 300W with 330uF Capacitor Filter switched on at t=0 and switched off at t=100ms and
line at 230V r.m.s
Fig.6 shows the simulation waveforms in this case.
SK1 9
The source current is seen to be a good sine wave. The rectifier stops drawing load current at
t=100ms.However the effect of this will be felt in the current control loop since the feed back is based on a
sampling scheme. The information on how much active power and reactive power were drawn by the load in an
a.c cycle will be available only at the end of that cycle in the harmonic current calculator block. In other words
there is a maximum of one cycle delay between change in load current and change in the harmonic current
calculated by the harmonic current calculator. Hence the source current continues to be at the same old level for
one more cycle after the 100ms point. But, now since there is no load to absorb this power it will go into inverter
and charge up the d.c side capacitor. This is clearly seen in the capacitor voltage waveform. The set value of
capacitor voltage is 400V and as the capacitor approaches that level the source current tapers down to zero. Close
examination of the source voltage and source current waveforms reveal that there is a sudden phase change of
180 deg in source current at 120ms and that after that time point the power flow is into the source. It is as it
should be since the capacitor is overcharged now and the system has to pump energy back into the source in
order to bring the capacitor back to its set value.
Fig.7 shows the spectral analysis of the relevant currents when the 300W rectifier was drawing
power. The low frequency harmonics in source current are in the 10-50mA range indicating almost pure sine
wave current. Note that the inverter current and the rectifier current are harmonic rich.
The simulation model employed makes an assumption that whatever voltage is demanded of
the inverter by the current regulation loop can really be synthesised by the inverter. This is not true. The
maximum voltage that an inverter can synthesise is equal to the d.c side voltage theoretically. But there are
restrictions on minimum and maximum pulse widths that can be realised in an inverter practically. Due to these
restrictions the practical inverter can utilise only a maximum of 95% of d.c voltage. These practical limits are
ignored in this simulation and it is assumed that the inverter can utilise the d.c side voltage fully. This is why
there is a limiter set at 380V in the inverter model. This assumes that d.c side is maintained at 400V.But during
transients d.c voltage varies. Hence after simulation run is over the result should be checked to see that at no time
the inverter synthesised voltage was above the capacitor voltage. In case-1 the maximum inverter demand was
360V and the capacitor voltage never went below 382Volts.Hence the simulation results for case-1 will be
acceptable.
SK1 10
Case-2 Full Bridge Thyristor Converter Load 500W with negligible smoothing inductor on d.c side,line at 230V
r.m.s
Fig.8 shows the simulation output. The load waveform has sharp change at the firing instant
due to low level of smoothing inductance (the load circuit time constant was 20uS) in the d.c side. Inverter has to
absorb this sudden change in current if the supply current is to become pure sine. But if the inverter current
changes suddenly the filter inductance will demand a very high voltage. This high voltage can not be supplied by
the inverter due to limited value of d.c side voltage. Hence the inverter output goes to the maximum possible and
gets clamped there as evident in the form of narrow pulses in the waveform in fig.8. Thus the inductance gets
only a limited voltage (the difference between maximum inverter output and peak supply voltage) and hence its
current slews up only gradually. This results in the supply line taking the sudden changes in load current which is
clearly visible in the supply current waveform in Fig.8.Thyristor converter fed resistive load is the most
demanding load on an Active Power Filter and waveform improvement on supply side will be only partial as
illustrated in this case study.
In this case also the capacitor voltage was verified to be above the inverter output at all time
and hence simulation results are acceptable.
SK1 11
Case-3 Same as in case 2 but the load circuit time constant was changed to 200uS.
Fig.9 shows the relevant waveforms in this case. The source current is seen to be almost pure
sine wave in this case.
8. Shunt Active Filter for Reactive Compensation
It is possible to control the power factor at the load bus by varying the amount of reactive
power injection by the shunt active filter (within its capability range). A reactive power control loop which
calculates the amplitude of load reactive power, and controls the reactive current reference of the active filter to
be exactly the opposite of the load reactive power will be needed for this. Load reactive power is calculated by
product-integrate-sample every 10ms-reset strategy described earlier.
A PSpice simulation diagram for this scheme is given in Fig. 10 and PSpice simulation diagram for the Shunt
APF as a Reactive Compensator is given in Fig. 11.
SK1 12
The results of simulation for a RL load with APF enabled at 110ms (by using Gate block in
Fig. 11 ) is shown below.The rapid change in source current and its near unity power factor may be noted.The
power factor is not exactly upf because of the fundamental reactive power taken by the filter capacitor across the
inverter output which was not accounted for anywhere in the control loops.
SK2 1
HARMONIC VOLTAGE CANCELLATION & ISOLATION BY SERIES ACTIVE
POWER FILTERING (SPAF) IN DISTRIBUTION SYSTEMS
Suresh Kumar.K.S
Asst.Professor,Dept. of Elect. Engg.
N.I.T.,Calicut
1. Introduction
In Shunt Active Power Filtering ,the Inverter injects harmonic currents required for elimination
of harmonics in the source current and injects it at the node where the load is connected. The current drawn by
the Inverter is forced to contain a small in-phase sinusoidal component in order to draw enough active power
from source to supply losses in the APF and to maintain the D.C side capacitor voltage constant. Series APF is
the dual of Shunt APF.
In Series APF the Inverter injects a voltage in series with the line which feeds the polluting
load through a transformer. The injected voltage will be mostly harmonic with a small amount of sinusoidal
component which is in-phase with the current flowing in the line. The small sinusoidal in-phase (with line
current) component in the injected voltage results in the right amount of active power flow into the Inverter to
compensate for the losses within the Series APF and to maintain the D.C side capacitor voltage constant.
Obviously, the D.C voltage control loop will decide the amount of this in-phase component.
Depending upon the location of Series APF, nature of bus voltage and nature of load the
purpose of injecting harmonic voltage in series with the line can be one of the following.
(i) In this case the distribution bus (say 11 kV) is polluted and has non-negligible harmonic
content. It is required to clean up this voltage before it reaches sensitive loads. Essentially we want to
remove the harmonic content in the voltage at the distribution substation before it is fed into a feeder
supplying harmonic-sensitive loads. The bus voltage corruption may have been due to harmonic current
generating loads upstream. However, the Series APF is not aimed at that harmonic generation problem;
but is applied to protect other chosen loads from the already present harmonics in the source bus. In this
mode ,the Series APF senses the bus voltage and line currents and injects the right amount of harmonic
voltages in series with the line in such a way that the voltages after the filter will be harmonic free and
clean.Fig.1 shows the power circuit and control blocks of a Series APF working in this mode. This mode
of operation can be termed Harmonic Cancellation Mode since the Series APF in this mode cancels the
harmonics present in the source voltage before it gets to the load.
SK2 2
(ii) In the second context, a Series APF is used to help a shunt connected Passive Filter in diverting
the harmonic currents generated by a non-linear load. Tuned LC filters are supposed to have zero
impedance at the tuning frequency. However, they will have non-zero value due to losses in the
inductor. Hence, the tuned filter shares the harmonic current with the line and source impedance instead
of absorbing it entirely. Moreover, the filter is easily detuned with ageing of components and
degradation in capacitors. In addition, changes in system frequency make the filter detuned. If the filter
is detuned, the harmonic current generated by the non-linear load will flow in the source path partially
thereby reducing the filtering effectiveness of the Passive Filter.One way to increase the effectiveness of
the Passive Filter and make it absorb all the harmonic current is to insert a high impedance in series
with the line (source) before the load. Of course, this high impedance should be there only for harmonic
current flow and it should go to a zero value for fundamental current flow.
The Series APF in this mode of operation, senses the harmonic current flow in the line and
forces the Inverter to inject (through a transformer) a harmonic voltage proportional to this current in
series with the source in direction to oppose the current flow-in short the Series APF simulates a high
resistance in series with the line for harmonic currents alone. With this high resistance in the source
side, the Passive Filter is forced to absorb all the harmonic current generated by the load even if it has a
non zero impedance at the harmonic frequency due to detuning.
Of course, the load voltage will become distorted if the filter impedance is not zero. Moreover,
a single tuned LC filter will take care of only one harmonic component. It needs multiple LC filters to
handle all the major harmonics. All the LC sections will derive benefit from the same Series APF.If
there are harmonic components which the Passive Filters can not absorb without distorting load bus
voltage beyond acceptable levels, they will have to be permitted to flow into the source by Series APF
presenting a low or zero resistance those frequency components. The Series APF used in this mode of
operation is called Harmonic Isolator since it isolates the source bus at h frequencies from the polluting
load.
2. The Series APF in Harmonic Cancellation Mode
Fig.1 shows a Series APF in this mode. The source V
S
and inductance L
S
represent the
Thevenin's equivalent of the power system behind the distribution bus. V
sb
is the source bus voltage which
contains harmonics. Lline represents the line inductance of the feeder feeding the load bus.V
lb
is the load bus
voltage.The Series APF injects V
i
in series with the line as shown.Single-Phase topology is considered in the
interest of simplicity.
The line current I is sensed by a CT and converted to electronic level and is fed into a PLL-
Counter-EPROM-DAC type sine wave generator.This block generates unit amplitude pure Sine wave which is in
phase with the feeder line current.It also outputs a unit amplitude Cosine wave.The harmonic content of the
source bus voltage (and thereby the voltage that the APF must inject into line) can be found out by subtracting
the fundamental component of bus voltage from the total bus voltage.This requires the extraction of fundamental
component.
The sensed bus voltage is multiplied with unit Sine and Cosine respectively to extract the
fundamental orthogonal components of voltage.The products are integrated for a cycle duration and the value of
integrals is noted by a sample and hold mechanism at the end of cycle period.After sampling the integrators are
reset and allowed to perform the integration for the next period.The sampled values will give the amplitude of in-
phase and quadrature (with respect to line current) fundamental components of voltage.These amplitudes are
multiplied with appropriate sinusoidal templates and added to re-construct the net fundamental component of
voltage and then it subtracted from the total bus voltage to get the harmonic content.
The D.C side capacitor voltage will discharge down to zero unless sufficient power is drawn
from the line to meet the losses in the Inverter.This power is drawn by injecting a fundamental in-phase
component against the line current flow. The amount of this component is decided by a PI controller which
monitors the D.C bus voltage.
The Inverter in the Series APF carries the full line current (after transformation). But the
voltage generated at the output has only a small fundamental component and has mostly harmonic components
(usually 5
th
,7
th
,11
th
etc.).Therefore the a.c side power in the inverter will be at 4
th
,6
th
,8
th
harmonic etc. Thus, the
reactive power flow into the D.C. side capacitor is at those frequencies and the ripple across the capacitor can be
made small due to high frequency nature of these power components. Also, the kVA rating of Inverter and D.C
side capacitor will be decided by the harmonic content in the voltage and the maximum line current.
The control system design considerations for the D.C. voltage control loop has been described
already described in other contexts (SVC,Shunt APF,PWM Rectifier etc.) and need not be repeated here. The
SK2 3
crucial control block in this application is the harmonic content calculator. The calculator has to ensure that the
output from it does not contain any in-phase component. If it contains that the capacitor will either discharge fast
or overcharge and in order to limit the change in capacitor voltage before the voltage control loop can act ,it will
be necessary to use large valued capacitor. The calculator will ensure that there is no fundamental component in
its output under steady conditions. But under transient conditions (change in line current, changes in bus voltage
etc.), it may output fundamental component. The value of D.C side capacitor will be decided almost entirely by
the dynamic response of this Calculator block.
The most difficult thing about a Series APF is to protect it. Note that it is in series with the line
and has to carry all the load current (fundamental plus harmonic, if any) .Moreover,the fault currents also will
pass through it. It is not enough to shut down the Inverter based on fast over current sensing because if the
Inverter is shut down the transformer primary goes open and secondary imposes a large impedance in series with
the line. A Series APF is to be shorted to take it out of service i.e. it has to be taken out of line and a sort path has
to be put in its place. This can call for fast acting static transfer switches.
The Series APF effectively cancels the entire harmonic content of source bus voltage. Now
what if the load at the load bus is non-linear ? The harmonic currents drawn by the load via the line will flow
through the Thevenin's impedance of the source (L
s
) and produce further harmonic voltages at the source bus.
But these also will get cancelled by the Series APF.i.e. the Series APF makes the harmonic impedance to its left
side zero. Hence the harmonic impedance of the line plus source is reduced by Series APF and any shunt filter
put at the load bus will have to compete with a lower harmonic impedance in the harmonic current sharing
process. In particular ,if this Series APF is installed at the load bus i.e. after the line ,a passive shunt filter
(like capacitor or tuned LC etc.) is going to be completely useless and all the harmonic current will go into the
line,thereby corrupting the voltage received by other loads which are not protected by a Series APF.Of course
it is possible to install a Shunt Active Filter at the load bus to cancel the harmonic currents taken by load.
3. The Series APF as a Reactance Compensator
In the last section ,it was pointed out that the harmonic voltage calculator has the in-phase and
out-of-phase sine waves available to it in order to arrive at an estimate of net fundamental component in the
voltage. The injected voltage is harmonic plus a little in-phase fundamental component required to draw the loss
power. Now,if the injected voltage reference is made to have a sinusoidal component which is in quadrature with
line current , the Series APF will absorb or deliver fundamental frequency reactive power. It becomes a series
reactive power compensator or equivalently it becomes a reactance at fundamental frequency. Series APF in this
mode can provide series capacitor/inductor compensation to the line along with harmonic cancellation. The
required voltage reference can be obtained using the Cosine wave template already available in the control
system. Of course, the kVA rating of Inverter and other components will have to be suitably chosen.
This series compensation capability can be made use of in two ways. In one case, it can be
controlled in such a way that it injects a fundamental voltage in quadrature with the line current in proportion to
the current magnitude. In that case, the Series APF becomes a fixed reactance value at fundamental frequency -
usually capacitive. The application of series capacitors in the transmission lines to improve power transfer
capability,system stability and voltage regulation is well known. Series APF can implement this series capacitor
compensation as explained above.
A second way in which the fundamental Var compensation capability of Series APF can be
employed is by using it to regulate the voltage after the Series APF location at a pre-decided value. This can be
done by sensing the voltage magnitude downstream ,comparing it with a set value,processing the error in a PI
Controller and using the error to multiply Cos (t+180
0
) .The product is added along with the harmonic
reference coming from the Harmonic Content Calculator to form the net reference signal for the PWM
Inverter.Thereby the value of effective capacitive reactance at fundamental frequency simulated by the Series
APF is varied to maintain a constant amplitude a.c voltage at a point after the Series APF.
In both ways of implementing the Var compensation action,it is possible to derive additional
advantage from Series APF in the form of a fault current limiting reactance (provided the Series APF has high
overload capability for short duration).When the sensed line current indicates the occurrence of a fault(either by
p.f angle or by its magnitude) the Series APF fundamental reference can be shifted from -Cos t to +Cos t.
Then the Series APF will simulate an inductive reactance and thereby limit the fault current.Series APF is used
for this function too in practice.
SK2 4
4. The Series APF in Harmonic Isolation Mode
Fig.2 shows a Series APF in harmonic isolation mode where it serves to isolate the source from
the harmonic currents drawn by the load.it does this by simulating a high resistance in series with the line for
harmonic current flow. Only one tuned passive filter is shown at the load bus and it is assumed that the load
draws one harmonic component predominantly. Otherwise more tuned filters are needed at the load bus.
The source current I
s
is sensed and a pure sine wave is in phase with it is generated by the PLL
subsystem. The sine thus generated is used to extract the harmonic content in the source current using the
orthogonal decomposition method which has been described in the last section. The extracted harmonic
component of I
s
is multiplied by a gain K and that (along with the small fundamental component needed to
draw the loss power) is given as the reference to the PWM Voltage Source Inverter.Thus,the Inverter injects a
harmonic voltage which is proportional to the harmonic current into the line ,thereby simulating a resistance of
value K ohms in the line (only for harmonic current flows).
Now, the harmonic current drawn by the load has two parallel paths to choose-through the
filter and through the line which appears as a high resistance now. It chooses filter path predominantly even if
the filter is slightly detuned. Thus, the harmonic current into the source is reduced to very low levels.
Similar action takes place in the case of harmonic content in the source. The high resistance
simulated by the Series APF will absorb all the harmonic voltages (for which there are passive filter branches
at load end) present in the source bus and isolate the load from supply side harmonics. This is a welcome
feature since in the absence of Series APF, the tuned filter would have drawn large currents from source if
there were source side harmonics. This would have led to overloading of the filter and would have called for
parallel tuned LC section in series with the line to isolate the series tuned filter from supply side harmonics.
With a series tuned LC filter,there is always a chance of system resonances due to parallel
resonance between line/source inductance and filter components. The Series APF in the resistance emulation
mode will damp these resonances well and will avoid dangerous harmonic amplification.
It is possible to combine series capacitor compensation along with harmonic isolation in this
system by suitably modifying the reference signal to the PWM Inverter.
SK2 5
5. PSpice Simulation of a Series Active Filter in Harmonic Isolator Mode
(Also called Hybrid Active Filter)
The PSpice Simulation diagram (using Design Lab 8.0) for a Single Phase Series APF in
Harmonic Isolation mode is given below. The inverter was modelled as an ideal controlled voltage source. A
half-controlled thyristor converter is used as load.
The simulation run results for a pure sinusoidal source and thyristor load is shown below in
Fig. 4.The harmonic calculator takes one half cycle to calculate the harmonic content properly, till then it outputs
all the input as the harmonic content ; this explains why the inverter had to inject maximum (limited to 50V) in
the beginning.This will lead to a large active power outflow from the DC Side of Inverter and will require a
suitably sized capacitor to hold the voltage against such outflow (or inflow) of active power.The filter is seen to
take a large leading reactive power expected since passive filtering is practically possible only along with
passive capacitor reactive compensation.The value of inductor required for harmonic filtering alone (without
fundamental leading reactive power) will be impracticably high.The source current, though more or less
sinusoidal, shows high frequency content.This is so since the load current has high frequency content , but the
passive filter offers low impedance path only for a few harmonics.Thus the current sharing ratio between the
Series Inverter equivalent resistance (40 ohms in the simulation) and filter impedance is adversely affected at
high frequencies leading to more of high frequency currents flowing to source side and consequent appearance
of high frequency harmonic content at the load terminal voltage.
The simulation results for a distorted source containing 10% fifth harmonic is shown in Fig. 5.
Now the source current is distorted perceptibly since the inverter has to absorb all the source fifth harmonic
across it. However the load voltage is more or less sinusoidal with a little h.f content which is due to the h.f
content in load current as eaplained above.Thus it can be seen that the Series APF handles all those load current
harmonics and source voltage harmonics for which there are tuned passive filter structures at load bus well. And
it can not handle the harmonic components for which there is no low impedance path across load bus.The
distortion reported in this simulation will be on the optimistic side due to the neglecting of switching frequency
filter of the series inverter.
SK2 6
SK2 7
It may be better to introduce a high resistance in series with the line using Series Inverter only
for those harmonic components for which there is a tuned structure at the load bus. This will require a harmonic
calculator that can extract individual harmonics from the line current.
6. Differences in DC Side Control between Series APFs and Shunt APFs
Both Shunt and Series APFs with self-sustained DC bus (i.e a Capacitor holding DC Voltage
constant without any AC-DC Converter to help it to do so) control their DC Side voltage by drwaing a small
amount of active power from ac side to supply the losses in the inverter.In the Shunt APF this is done by a PI
Control loop on the DC Voltage injecting an active current component into the reference current of the APF.
Correspondingly a similar control loop will inject a sinusoidal voltage component which is in phase with the line
current to draw/supply the required adjustment power.In the Shunt APF case the loop gain of this control loop
will be directly proportional to the bus voltage magnitude and hence reasonably constant.But in the Series APF
case the loop gain of voltage control loop is directly proportional to the fundamental current amplitude in the line
i.e the load current and hence is widely variable with line loading level.This is a major problem with the design
of this control loop a loop which is well damped under low load conditions will either be unstable or will be
highly oscillatory under full load conditions.
If the function of Series APF is only harmonic cancellation or isolation (and not load voltage
regulation or series reactive compensation) an easy solution to this control problem will be to replace the DC
Side with a small rated single phase diode rectifier or a Battery with a Charger.In fact this is how such
installations are made in practice. The rating needed of such a converter will be very small and usually is about
3-5% of the line full load capacity.The rating of Series Inverter itself will be about 10-20% of the line capacity
depending on the amount of source and load side harmonics and on the extent of detuning and quality of the
passive filters.
Note :- The Series APF Systems described here can be applied in three phase systems too.Usually Series APFs in
three phase systems make use of three single phase inverters feeding a Y-Open Y transformer and in this case the
control strategy described here can strightwaway be applied on a phase by phase basis.Only that three PLL
systems are not needed. A single PLL locked onto first phase along with suitable EPROM storage can generate
the six required unit sinusoidal templates.Also, there are a variety of algorithms available for harmonic content
extraction which may have stndard implementations in DSP hardware.One of those can replace the harmonic
extraction procedure described here (but not with much advantage in performance !)
SK3 3
THREE PHASE SHUNT ACTIVE POWER FILTERS
PART I - INTRODUCTION
Suresh Kumar K.S
AP,EED,NIT Calicut
The use of modern electronic equipment has changed our lives (most would argue for the
better) but has also changed the load characteristic of modern facilities. Electronic loads have earned the name
"nonlinear load" to describe the way they draw power. The injected harmonics, reactive power burden,
unbalance, and excessive neutral currents cause low system efficiency and poor power factor. Harmonic
contamination has become a major concern for power system specialists due to its effects on sensitive loads and
on the power distribution system. Harmonic current components :
increase power system losses,
cause excessive heating in rotating machinery,
can create significant interference with communication circuits that share common right-of-ways with AC
power circuits,
and can generate noise on regulating and control circuits causing erroneous operation of such equipment.
The term nonlinear load is commonly used to describe the switch mode power supply found in
personal computers. In fact, this type of power supply is used commonly in a myriad of applications. Microwave
ovens, laser printers, medical instrumentation, stereos, televisions, and electronic lighting are among a few
devices using switch mode power supplies. Other types of nonlinear loads include light dimmers, 6-pulse
rectified supplies, 6-pulse phase-angle controlled loads, and 12-pulse rectified supplies. Variable speed drives
commonly use six-pulse rectified and phase-angle controlled power supplies.
Power electronic equipment can be designed to provide harmonics-free performance. But in
most applications, the economic incentives have not been sufficient to bring about design improvements. Power
system engineers have turned to regulation to force the use of lower-harmonic power supply design. Their
common objective is to preserve the sinusoidal nature of the power system voltage while protecting components
from added harmonic loading. The electrical utilities are quickly adopting the philosophy and constraints
proposed in IEEE 519-1992 [14], a Recommended Practice (one level short of a mandatory Standard), limiting
both utility voltage and end-user current distortions.
In order to maintain good power quality, various international agencies recommended limits
of harmonic current injection into the utility. According to IEEE-519 standards the limits on the magnitudes of
harmonic currents and harmonic voltage distortion at various harmonics frequencies are specified, as given in
Tables1 and 2.The amount of distortion in the voltage or current waveform is quantified by means of an index
called the total harmonic distortion(THD). The THD in current is defined as
Table 1. Harmonic Current Limits for non- - linear Loads
sc/I
1 <11 1 h 17 1< h< 23 3 h<35 HD
20 .5 .6
0-50 .5 .5
0-100 0 .5 .5 2
00-1000 2 .5 5
Isc is the maximum short circuit current at the point of common coupling (PCC) , I
1
is the maximum fundamental-frequency load current.
Table 2 Harmonic Voltage Limits for power producers
2.3 - 69 kV 69 - 138 kV
Max. for
individual harmonies
3.0 1.5
Total
harmonic distortion (THD)
5.0 2.5
=
1 n
2
s1
I
sn
I
100 %THD
SK3 4
The Table 2 lists the quality of the voltage that the power producer is required to furnish a
user. It is based on the voltage level at which the user is supplied.
1. PASSIVE FILTERS:
Conventionally, passive LC filters have been used to eliminate line current harmonics and to
increase the load power factor. However, in applications these passive second order filters present the following
disadvantages :
a) The source impedance strongly affects filtering characteristics.
b) As both the harmonic and the fundamental current components flow into the filter, the filter must be rated
by taking into account both currents.
c) When the harmonic current components increase, the filter can be overloaded.
d) Parallel resonance between the power system and the passive filter causes amplification of harmonic
currents on the source side at a specific frequency.
e) The passive filter may fall into series resonance with the power system so that voltage distortion produces
excessive harmonic currents flowing into the passive filter.
The increased severity of harmonic pollution in power networks has attracted the attention of
power electronics and power system engineers to develop dynamic and adjustable solutions to the power quality
problems. Such equipment, generally known as Active Filters (AF's), are also called Active Power Line
Conditioners (APLC's), Instantaneous Reactive Power Compensators (IRPC's), Active Power Filters (APF's),
and Active Power Quality Conditioners (APQC's).
2. ACTIVE POWER FILTERS
Parallel (or shunt) active filters have been recognized as a valid solution to current harmonic
and reactive power compensation of non-linear loads. The principle of operation of active filters is based on the
injection of the current harmonics required by the load. Thus the basic principle of Shunt Active Power filter is
that it generates a current equal and opposite in polarity to the harmonic current drawn by the load and injects it
to the point of coupling thereby forcing the source current to be pure sinusoidal. As a consequence, the
characteristics of the harmonic compensation are strongly dependent on the filtering algorithm employed for the
calculation of load current harmonics.
3. CLASSIFICATION OF ACTIVE POWER FILTERS
Active filters are basically categorized into three types, namely, two-wire (single phase), three-wire, and four-
wire three-phase configurations to meet the requirements of the three types of nonlinear loads on supply
systems[1].
AF's can be classified based on converter type, topology, and the number of phases. The converter type can be
either Current Source Inverter ( CSI ) or Voltage Source Inverter ( VSI ) bridge structure. The topology can be
Shunt, Series or a combination of both. The third classification is based on the number of phases, such as two-
wire (single phase) and three- or four-wire three phase systems.
Converter Based Classification
There are two types of converters used in the development of AF's. Fig.1a shows the current-
fed pulse width modulation (PWM) inverter bridge structure. It behaves as a nonsinusoidal current source to
meet the harmonic current requirment of the nonlinear load. A diode is used in series with the self commutating
device (IGBT) for reverse voltage blocking.
The other converter used as an AF is a voltage-fed PWM inverter structure, as shown in Fig.1b
It has a self - supporting dc voltage bus with a large dc capacitor. It has become more dominant, since it is
lighter, cheaper, and expandable to multistep versions, to enhance the performance with lower switching
frequencies . It is more popular in UPS-based applications, because in the presence of mains, the same inverter
bridge can be used as an AF to eliminate harmonics of critical nonlinear loads.
Topology -Based Classification
AF's can be classified based on the topology used as series or shunt filters, and unified power
quality conditioners use a combination of both. Combinations of active series and passive shunt filtering are
known as Hybrid filters. Fig.1b is an example of an active shunt filter, which is most widely used to eliminate
current harmonics, reactive power compensation and balancing unbalanced currents. It injects equal
compensating currents, opposite in phase, to cancel harmonics and /or reactive components at the point of
common coupling (PCC). It can also be used as a static VAR generator (STATCON) in the power system
network for stabilizing and improving the voltage profile.
Fig.1c shows the basic block of a stand-alone active series filter. It is connected before the
load in series with the mains, using a matching transformer, to eliminate voltage harmonics, and to balance and
regulate the terminal voltage of the load or line.
Fig.1d shows a unified power quality conditioner (also known as Universal AF), which is a
combination of active shunt and active series filters. The dc-link storage element (either inductor or capacitor) is
SK3 5
shared between two current- source or voltage-source bridges operating as active series and active shunt
compensators.
Fig.1e shows the hybrid filter, which is a combination of an active series filter and passive
shunt filter. It is quite popular because of the solid state devices used in the active series part can be of reduced
size and cost, and a major part of the hybrid filter is made of the passive shunt L-C filter used to eliminate lower
order harmonics.
Supply-System Based Configuration
This classification of AF's is based on the supply and/or the load system having single-phase
(two-wire) and three-phase (three wire or four wire) systems.
1) Two-wire AF's: Two wire (single phase) AF's are used in all three modes as active series, active shunt, and a
combination of both as unified line conditioners. Both converter configurations, current-source PWM bridge
with inductive energy storage element and voltage-source PWM bridge with capacitive dc-bus energy storage
elements are used to form two-wire AF circuits.
2) Three-wire AF's: Three-phase three-wire nonlinear loads, such as Adjustable Speed Drives (ASD's), are
major applications of solid-state power converters. All the configurations Figs 2.1-2.5 are developed, in three
wire AF's, with three wires on the ac side and two wires on the dc side. Active shunt AF's are also can be
designed with three single-phase AF's with isolation transformers for proper voltage matching, independent
phase control, and reliable compensation with unbalanced systems.
3) Four-wire AF's: A large number of single-phase loads may be supplied from three-phase mains with neutral
conductor. They cause excessive neutral current, harmonic and reactive power burden, and unbalance. To
reduce these problems, four-wire AF's have been developed
Compensated Variable Based Classification[2]
A) Harmonic compensation:
This is the most important system parameter requiring compensation in power systems and it
is subdivided into voltage- and current-harmonic compensation as follows.
Compensation of voltage harmonics: The subject of compensating voltage harmonics is not
widely addressed because power supplies usually have low impedance. The terminal voltage at the consumer
point of common coupling (PCC) is normally maintained within the standard limits for voltage sag and total
harmonic distortion and does not normally vary much with loading. Note that the compensation of voltage and
current harmonics is interrelated. The reduction of voltage harmonics at the PCC helps a great deal to reduce
current harmonics, especially for the particular cases of nonlinear loads with resonance at the harmonic
frequencies. However, the compensation of the voltage harmonics at the PCC does not eliminate the need for
current-harmonic compensation for the nonlinear loads.
Compensation of current harmonics: Compensation of current harmonics is very important in
low and medium-power applications. As mentioned above, the compensation of current harmonics reduces to a
great extent the amount of distortion in the voltage at the PCC. The imposition of harmonic standards[14] will
soon oblige factories and establishments to control the harmonics they inject into the power system.
B) Multiple compensation:
Different combinations of the above systems can be used to improve the effectiveness of
filters. The following are the most frequently used combinations.
Harmonic currents with Reactive power compensation: The most common and popular filters
are those which compensate for both the reactive power and the harmonic currents in order to maintain the
supply current completely free of harmonics and in phase with the supply voltage. The techniques employed for
this have several advantages over other alternatives, as only one filter is needed to compensate for everything,
which is much more attractive than using many different types of compensators. However, because of the limits
imposed by the ratings of power switches, one can only use this application for low powers. The resulting
switching frequency would need to be lower for higher-power applications, which restricts the filter under
consideration to small powers.
Harmonic voltages with Reactive power compensation: This combination, however rare, takes
place in certain configurations for controlling the voltage harmonics, which would normally affect indirectly
(using feedback) the reactive-power compensation. This compensation system is only suitable for low-power
applications.
Harmonic currents and voltages: The problem of addressing harmonic currents and voltages
simultaneously can only be treated by using the series/parallel combination of active-filter configurations. This,
ofcourse, is very important and very beneficial in making both the supply and the load free from harmonic
effects. However, this complex type is normally used only for very sensitive devices such as power-system-
protection equipment and superconducting magnetic-energy storage systems.
Harmonic currents and voltages with reactive-power compensation: This scheme is the
ultimate in sophistication since it controls harmonics and reactive power [2]. This technique requires the use of
SK3 6
the parallel/series active-filter combination. It is not employed very often because its control is rather difficult
and the information available on it in the literature is very limited.
SK3 7
4. THE THREE PHASE ACTIVE FILTERING SYSTEM
The active filtering system is based on a philosophy that addresses the load current distortion
from a time domain rather than a frequency domain approach. The most effective way to improve the distortive
power factor in a non-sinusoidal situation is to use a nonlinear active device that directly compensates for the
load current distortion.
The performance of these active filters is based on three basic design criteria.
1) The design of the power inverter ( semiconductor switches, inductances, capacitors, dc voltage)
2) PWM control method (hysteresis, triangular carrier, periodical sampling)
3) Method used to obtain the current reference or the control strategy used to generate the reference
template.
The active filter concept uses power electronics to produce harmonic current components that
cancel the harmonic current components from the non-linear loads[9]. The active filter configuration
investigated in this lecture is based on a
pulse-width modulated (PWM) voltage
source inverter that interfaces to the
system through a system interface filter as
shown in Figure 3.1. In this configuration,
the filter is connected in parallel with the
load being compensated. Therefore, the
configuration is often referred to as an
active parallel or shunt filter. Figure 1
illustrates the concept of the harmonic
current cancellation so that the current
being supplied from the source is
sinusoidal. The voltage source inverter
used in the active filter makes the
harmonic control possible. This inverter
uses dc capacitors as the supply and can
switch at a high frequency to generate a
signal that will cancel the harmonics from
the non-linear load.
The active filter does not need to provide any real power to cancel harmonic currents from the
load. The harmonic currents to be cancelled show up as reactive power. Reduction in the harmonic voltage
distortion occurs because the harmonic currents flowing through the source impedance are reduced. Therefore,
the dc capacitors and the filter components must be rated based on the reactive power associated with the
harmonics to be cancelled and on the actual current waveform (rms and peak current magnitude) that must be
generated to achieve the cancellation.
The current waveform for canceling harmonics is achieved with the voltage source inverter in
the current controlled mode and an interfacing filter. The filter provides smoothing and isolation for high
frequency components. The desired current waveform is obtained by accurately controlling the switching of the
insulated gate bipolar transistors (IGBTs) in the inverter. Control of the current waveshape is limited by the
switching frequency of the inverter and by the available driving voltage across the interfacing inductance.
The driving voltage across the interfacing inductance determines the maximum di/dt that can
be achieved by the filter[9]. This is important because relatively high values of di/dt may be needed to cancel
higher order harmonic components. Therefore, there is a trade-off involved in sizing the interface inductor. A
larger inductor is better for isolation from the power system and protection from transient disturbances.
However, the larger inductor limits the ability of the active filter to cancel higher order harmonics.
The Inverter (three-phase unit or single-phase unit as the case may be) in the Shunt Active
Power Filter is a bilateral converter and it is controlled in the Current Regulated mode i.e. the switching of the
Inverter is done in such a way that it delivers a current which is equal to the set value of current in the current
control loop. Thus the basic principle of Shunt Active Power Filter is that it generates a current equal and
opposite in polarity to the harmonic current drawn by the load and injects it to the point of coupling thereby
forcing the source current to be pure sinusoidal. This type of Shunt Active Power Filter is called the Current
Injection Type APF [9].
Configuration Of Three Phase Shunt Active Power Filter
The basic configuration of a three-phase three-wire active power filter is shown in fig 3.2. The
diode bridge rectifier is used as an ideal harmonic generator to study the performance of the Active filter. The
current-controlled voltage-source inverter (VSI) is shown connected at the load end. This PWM inverter consists
of six switches with antiparallel diode across each switch. The voltage which must be supported by one switch
is unipolar and limited by the DC voltage V
dc
. The peak value of the current which is bi-directional is imposed
by the active filter current. Thus the appropriate semiconductor device may be an IGBT with an antiparallel
SK3 8
diode and must be protected against overcurrent. The capacitor is designed in order to provide DC voltage with
acceptable ripples. In order to assure the filter current at any instant, the DC voltage V
dc
must be atleast equal to
3/2 of the peak value of the line AC mains voltage[11].
Fig.3 Configuration of the Three phase, Three wire Active Filtering system
SK4 18
PART II CONTROL STRATEGIES
Suresh Kumar K.S
AP,EED,NIT Calicut
1. Introduction To Control Strategies
Most conventional methods of harmonics/current reference can be classified either as time-
domain or frequency-domain. Other modern techniques do exist.
1.1 Time-domain approaches: The following seven subdivisions of time-domain approaches are mainly used
for three-phase systems except for the fictitious-power-compensation technique which can be adopted for
single- or three-phase systems[2].
(i) Instantaneous-reactive-power algorithm[3,4]: In this technique, suitable only for three-phase systems, the
instantaneous power of the load is calculated. It consists of a DC component and an oscillating component. The
oscillating component is separated over a certain interval of time (an integral number of cycles). The reference
signals are then calculated by distributing the total current equally to each of the three phases. This operation
takes place only under the assumption that the three-phase system is balanced and that the voltage waveforms
are purely sinusoidal.
(ii) Synchronous-detection algorithm[7]: This technique, which is very similar to the previous one, relies in the
fact that the three phase currents are balanced. The average power is calculated and divided equally between the
three phases. The signal is then synchronised relative to the mains voltage for each phase.
(iii) constant-active power algorithm[5]: The instantaneous and average powers of the load are calculated. The
active power component of the system is controlled to keep the instantaneous real power constant, while
maintaining the imaginary power to zero.
(iv) unity power factor algorithm [5]: This is another technique, which is very similar to that in (iii) above,
except the fact that it forces the instantaneous current signal to track the voltage reference waveform. This
implies that the power factor would be fixed to unity and the system would only be suitable for the combined
system of VAR and current-harmonic compensation.
(v) Fictitious-power-compensation algorithm: This technique relies on the principle of fictitious power
compensation. The system controller is designed to minimise the undesired component of power. In this aspect,
it is similar to the instantaneous-reactive-power algorithm but with a different definition of power. This
approach is suitable for both single- and three-phase systems. However it involves a large amount of
computation.
(vi) Synchronous-frame-based algorithm[6]: This algorithm relies on the Park transformations to transform the
three phase system from a stationary reference frame into synchronously rotating direct, quadrature and zero-
sequence components. These can easily be analysed since the fundamental-frequency component is transformed
into DC quantities. The active and reactive components of the system are represented by the direct and
quadrature components, respectively. The high-order harmonics still remain in the signal; however they are
modulated at different frequencies. These are the undesired components to be eliminated from the system and
they represent the reference harmonic current. The system is very stable since the controller deals mainly with
DC quantities. The computation is instantaneous but incurs time delays in filtering the DC quantities. This
method is applicable to only three-phase systems.
(vii) Synchronous-flux-detection algorithm: This technique is similar to that in (vi) above, in applying Park
transformations to transfer the system into synchronously rotating direct, quadrature and zero-sequence frames
of reference. However, it applies the transformation on the flux linkage of the filter inductance, which is then
controlled using the output voltages and currents in separate integral loops. The presence of these integral loops
incorporates time delays, which depend on the frequency response of the special feedforward and feedback
integrators.
1.2.Frequency-domain approaches[2]: Frequency-domain approaches are suitable for both single- and three-
phase systems. They mainly derived from the conventional Fourier analysis and include the following three
subdivisions.
(i) Conventional Fourier and FFT algorithms.
(ii) Sine-multiplication technique.
(iii) Modified-Fourier-series techniques.
1.3. Other algorithms: There are numerous optimization and estimation techniques, and all the utilities and
libraries for estimation can be used to perform this task. However some new methods arise, such as the Neural
network and adaptive-estimation techniques. Unfortunately, presently available control hardware is not suitable
for implementation of these techniques.
SK4 19
2.Control Strategies Covered in This Lecture
Control strategy is the heart of the AF and is implemented in three stages. In the first stage, the
essential voltage and current signals are sensed using potential transformers (PT's), CT's. In the second stage,
compensating commands in terms of current or voltage levels are derived based on control methods. In the third
stage of control, the gating signals for the solid-state devices of the AF are generated using Constant Frequency
PWM , hysteresis modulation or Space Vector Modulation techniques. In this lecture, the performance of the
four control methods for the three-phase three wire Active Power Filter control are considered. The control
strategies are discussed here.
2.1. Instantaneous Reactive Power Algorithm or Instantaneous Active and Reactive Power (p-q) method
As shown in fig.1, the control circuit of the active power filter consists of the current control
circuit for the PWM converter, the calculation circuit for the compensating current references within the block.
These circuits are designed on the basis of the instantaneous reactive power theory, which can be explained as
follows.
e
u ,
e
v ,
e
w
are the phase voltages of the three phase system,
i
Lu ,
i
Lv
,

i
Lw
are the load currents
i
Cu ,
i
Cv
,

i
Cw
are the compensating currents
The phase voltages e
u ,
e
v ,
e
w ,
and the load currents i
Lu ,
i
Lv
,

i
Lw
are transformed into the
orthogonal coordinates according to the following expressions, respectively:
From (1) and (2), the instantaneous real power p
L
and the instantaneous reactive power q
L
flowing into the load side are expressed by
Fig.1. Block diagram of the Instantaneous Reactive Power
algorithm
Calculation of
p* and q*
Current Control
Circuit
Calculation of
p
L
and q
L
Calculation of
i*
Cu
, i*
Cv,
and i*
Cw
Voltage
Control
i
Lu
i
Lv
i
Lw
e
u
e
v
e
w
p*+p
av
q*
q
L
p
L
Vdc
VRef
p* p
av
+
the inverter switching signals
( ) 1
e

2 / 3 - 2 / 3 0
1/2 - 1/2 - 1
3 / 2
u
(
(
(
=
(
w
v
e
e
e
e
( ) 2
i

2 / 3 - 2 / 3 0
1/2 - 1/2 - 1
3 / 2
Lu
(
(
(
=
(
Lw
Lv
L
L
i
i
i
i
( ) 3
i

e
e

L
(
(
(
=
(

L L
L
i e
e
q
p
SK4 20
The calculation circuit for the compensating current references (i*
Cu
,

i*
Cv
, i*
Cw
) performs
inversion of (3) and (2) to give
The calculation circuit for the compensating current references (i*
Cu
,

i*
Cv
, i*
Cw
) performs
inversion of (3) and (2) to give
Here, p
av
is the instantaneous real power necessary to adjust the voltage of the dc capacitor to
its reference value, and p* and q* are given by the calculation circuit for p* and q*, which should be the
harmonic components of p
L
and q
L
, i.e.,
Apart from the calculation circuit for p* and q* , and the control circuit for the dc capacitor
voltage, all the above-mentioned calculation circuits consists of analog multipliers, dividers and operational
amplifiers without any time-constant elements.
The calculation circuit for p* is composed of High-pass filters(HPF) to extract the harmonic
component in the load power p
L
(eq.7). This filtering technique is considered to be equivalent to differentiation,
which makes this technique vulnerable to noise [6]. In real filtering , a Butterworth type filter is chosen. This
particular filter type was chosen, in order to obtain magnitude and phase characteristics as close as possible to an
ideal filter since its magnitude response is maximally flat in the passband and is monotonic in both passband and
stopbands.
To minimize the influence of the HPFs phase responses, an alternative HPF (AHPF) is
obtained by mean of a Low-pass filter (LPF) of the same order and cutoff frequency, simply by the difference
between the input signal and the filtered one, which is equivalent to performing H
AHPF
(s) = 1-H
LPF
(s), which is
shown in Fig 2.
The transfer function, H(s), for an analog n-order Butterworth type HPF is
Fig.2. Alternative High Pass Filter ( AHPF-Butterworth)
The design of the low-pass filter is the most important in the control circuit, because various
compensation characteristics are obtained in accordance with the cutoff frequency and the order of the low pass
filter [3]. In this lecture a butterworth filter of fifth-order with cutoff frequency ,150Hz was chosen.
(8) e s ,
) s
s
w
(
1
HPF(s)
2n
1 2j
2
1
j
j
n
1 j
j
c
(

+
=
=
Low-Pass Filter
(Butterworth)
p
L
+
_
p*
so ly, respective p of component
harmonic the and source), the of hat lessthan t is p of frequency (the load of n fluctuatio
by the caused component frequency low component, dc the be p
~
and
,
p
,
p Let
L
L
L L L
(4) p
~
p p p
L L L L
+ + =
(5) q
~
q q q
L L L L
+ + =
(6)
* q
p * p

e e
e e

/2 3 - 1/2
/2 3 1/2 -
0 1
2/3
* i
* i
* i
av
1

Cw
Cv
Cu
(
+
(
(
(
(
(
=
(
(
(

(7) q q* , p
~
p*
L L
= =
SK4 21
Control circuit of the dc capacitor:
The dc capacitor voltage can be controlled by trimming the instantaneous real power p
av
,
which corresponds to the loss of the APF, while the instantaneous imaginary power q
*
does not have any effect
on the dc capacitor voltage. The control circuit has the negative feedback loop to trim p
av
automatically. Note
that the APF is considered as a harmonic generator rather than a harmonic suppressor when p
av
is fluctuating. In
fig.1, the average voltage across the dc capacitor is controlled so as to coincide with the reference voltage V
Ref
.
2.2. Synchronous Detection Algorithm(SDA):
In this algorithm [7], the three-phase mains currents are assumed to be balanced after
compensating. Thus ,
I
mu
= I
mv
=I
mw
(9)
Where I
mu
, I
mv
and I
mw
are the amplitudes of the three-phase mains currents after
compensating, respectively. The real power consumed by the load can be represented as
The real power p is sent to a lowpass filter to obtain its average value P
dc
. The real power is
then split into the three phases of the mains supply:
P
u
= (P
dc
E
u
)/E
tot
(11)
P
v
= (P
dc
E
v
)/E
tot
(12)
P
w
= (P
dc
E
w
)/E
tot
(13)
Where E
u
, E
v
and E
w
are the amplitude of the mains voltages, and E
tot
is the sum of E
u
, E
v
and E
w
. The desired mains currents can be calculated as
The reference compensation currents can then be calculated and represented as
i*
cu
= i
Lu
i
mu
(17)

i*
cv
= i
Lv
i
mv
(18)
i*
cw
= i
Lw
i
mw
(19)
[ ] (10)
i
i
i
e e e
Lw
Lv
Lu
w v u
(
(
(
= p
6) (1
E
P 2e
i
(15)
E
P 2e
i
(14)
E
P 2e
i
2
w
w w
mw
2
v
v v
mv
2
u
u u
mu
=
=
=
2e
w
/E
w
2
L.P.F
Power
distributor
e
u
e
v
e
w
i
Lu
i
Lv
i
Lw
i
Lu
i
Lv
i
Lw
i
cu
i
cv
i
cw
2e
v
/E
v
2
2e
u
/E
u
2
Fig.3 Block diagram for implementing synchronous detection algorithm
SK4 22
Control circuit of the dc capacitor:
The dc capacitor voltage regulation is achieved in the same manner as in the p-q method, the
instantaneous active power consumed in the power converter losses are compensated by an active component
drawn from the supply. Thus the dc voltage regulation of the capacitor is achieved. This is achieved in one cycle
of the supply voltage waveform.
2.3. An Instantaneous Active and Reactive Current Component i
d
-i
q
Method (D-Q Method):
In this method the currents i
ci
, are obtained from instantaneous active and reactive current
components i
ld
and i
lq
of the nonlinear load. The mains voltages and load currents are to be transformed into
coordinates as given by equations below.
The instantaneous active and reactive load powers are defined as
However, the dq load current components are derived from a synchronous reference frame
based on the Parks transformation, where represents the instantaneous voltage vector angle, given in eq.(4)
Under balanced and
sinusoidal mains voltage conditions
angle is a uniformly increasing
function of time. This transformation
angle is sensitive to voltage harmonics
and unbalance, therefore d/dt may
not be constant over a mains period.
With transformation (4) the direct voltage component is given by
d
q
i
lq
i
ld
u
0
2
2
dq d
e e | e | | e | e + = = =
(5)
i
i

e e
e e
e e
1
i
i
l
l

2
lq
ld
(
(
(
+
=
(
( ) 1
e

2 / 3 - 2 / 3 0
1/2 - 1/2 - 1
3 / 2
u
(
(
(
=
(
w
v
e
e
e
e
( ) 2
i

2 / 3 - 2 / 3 0
1/2 - 1/2 - 1
3 / 2
Lu
(
(
(
=
(
Lw
Lv
L
L
i
i
i
i
( ) 3
i

e
e

L
(
(
(
=
(

L L
L
i e
e
q
p
(4)
e
e
tan ,
i
i

cos sin -
sin cos

i
i
1 -
l
l
lq
ld
|
|
.
|
\
|
=
(
=
(
SK4 23
And the quadrature voltage component is always null, e
q
=0, so due to geometric relations (4)
becomes Instantaneous active and reactive load currents i
ld
and i
lq
can also be decomposed into oscillatory
and average terms.
The first harmonic current of positive sequence is transformed to dc quantities, il
+
dq1h
, i.e.,
this constitutes the average current components. All higher order current harmonics including the first harmonic
current of negative sequence, il
+-
dqnh
+il
-
dq1h
, are transformed to non-dc quantities and undergo a frequency shift
in the spectra, and so, constitute the oscillatory current components. These assumptions are valid under balanced
and sinusoidal mains voltage conditions. Eliminating the average current components by HPF's the currents that
should be compensated are obtained, i
cd
= -i
~
l
d
and i
cq
= -i
~
l
q .
Finally, the compensating currents can be calculated by the following equations
One of the characteristics of the Instantaneous Reactive Power algorithm and Instantaneous
Active and Reactive Current Component method [6]is that the compensating currents are calculated directly
from the mains voltages, enabling the methods to be frequency-independent. Avoiding the use of a PLL a large
frequency operating range can be achieved limited chiefly by the cutoff frequency of the current control system
(VSC and current controller ). Furthermore, under unbalanced and nonsinusoidal mains voltage conditions, a
large number of synchronization problems are avoided especially if a PLL is synthesized with a fast dynamic
response.
A butterworth filter is chosen for the filtering of harmonics. This particular filter type was
chosen, in order to obtain magnitude and phase characteristics as close as possible to an ideal filter since its
magnitude response is maximally flat in the passband and is monotonic in both passband and stopbands. The
filter here considered is a fourth-order filter with cutoff frequency f
c
= f/2 (f =50 hz) which assures the
elimination of dc components in the nonlinear load powers and currents.To minimize the influence of the HPF's
phase responses, an alternative HPF (AHPF) is obtained as shown in fig.2, by mean of a low-pass filter (LPF)
of the same order and cutoff frequency, simply by the difference between the input signal and the filtered one.
A) dc voltage regulation: A proportional-integral (PI) controller with anti-windup performs
the voltage regulation on the VSC dc side. Its input is the capacitor voltage error e*
dc
-e
dc
. Through regulation of
the first harmonic direct current of positive sequence i
+
d1h
it is possible to control the active power flow in the
VSC and thus the capacitor voltage e
dc
. The reactive power flow may be controlled by the first harmonic
quadrature current of positive sequence i
+
q1h
. However, considering that the primary end of the AF is simply the
lq
I
lq
i
~
lq
i and
ld,
I
ld
i
~
ld
i + = + =
(6)
i
i

e e
e - e

e e
1

i
i
cq
cd

2
c
c
(
(
(
+
=
(
(7)
i
i

/2 3 - /2 3 0
1/2 - 1/2 - 1
2/3
i
i
i
c
c
T
c3
c2
c1
(
=
(
(
(
il
q
il
d
LPF
LPF
PI e*dc
edc
i
d1h+
i
ldnh
il
d1h+
il
q1h+
i
lqnh
i*
cd
i*
cq
+
+
+
+
-
- -
-
i
q1h+
=0
Fig.5 dc voltage regulation and harmonic current generation system
+
-
SK4 24
elimination of current harmonics caused by nonlinear loads, the current i
+
q1h
is set to zero.
2.4 Modified Synchronous Detection Method[15]
The synchronous detection algorithm described in section 2.2 is an attempt to balance the line
currents after compensation and to make them sinusoidal.But the algorithm assumes a balanced source voltage
and uses the source voltage itself (possibly after a little filtering) as the reference templates.Thereby it avoids the
PLL based synchronisation hardware.And it calculates the total active power and redistributes this total power
among three phases in proportion to amplitudes of respective phase voltages.This will result in equal amplitude
currents in three phases and currents will be sinusoidal i.e the line currents will be at upf on a phase by phase
basis.This much will be true in the case of unbalanced mains too.But this implies that the currents in the mains
need not be balanced after compensation because the phase angles between voltages in an unbalanced system
need not be 120 degrees.Thus Synchronous Detection Algorithm produces equal amplitude currents which do
not necessarily make a balanced set after compensation.So it is either upf operation phase by phase or balanced
positive sequence currents after compensation and Synchronous Detection favours upf operation to positive
sequence currents in the case of supply voltage unbalance.The Modified Synchronous Detection Method
discussed here settles for positive sequence currents which are at upf with respect to positive sequence
component of supply voltage - after compensation. In this method too the total reactive power from mains will
be zero but individual phases may not operate at upf under unbalanced voltage conditions.
In this method all pass filters designed to contribute 90 degree phase shifts are used to extract
the amplitude of positive sequence component in the supply voltage.The diagram below makes this clear.
Using similar all pass filters and the calculated positive sequence amplitude a system of three
phase positive sequence unit voltages are synthesised.The total active power is calculated as in the case of
Synchronous Detection.The positive sequence voltage amplitude information is used to calculate the amplitude
of current for 1/3
rd
of this power and the positive sequence templates are used to convert this into desired mains
current reference.
SK5 18
PART III SIMULATION OF CONTROL STRATEGIES
Suresh Kumar K.S
AP,EED,NIT Calicut
All the four control strategies described in Part II had been converted into Matlab Simulink
Simulation files and these files are available in the CDROM accompanying this Course Notes.All those files
will run under Matlab 5.3 and up.Space limitation does not allow a detailed exposition on the simulation of all
the four strategies.One is chosen for detailed study in this lecture.All the control strategies perform more or less
the same under balanced sinusoidal supply voltage and balanced (but distorted) load current current
conditions.Differences emerge only when the load current is unbalanced and/or supply voltage is non-ideal (i.e
unbalanced and/or distorted). D-Q method is taken up for detailed discussion here and simulation results are
compared with those of Modified Synchronous Detection Method.
1. Simulink Simulation Diagram for D-Q Method
The top layer of Simulation Diagram for this method is shown in the next page.
The important subsystems are described below.
(a) General Three Phase Source is a masked subsystem which lets the user set the amplitude of positive and
negative sequence of the fundamental and two harmonic components (only one sequence) the 5
th
and 7
th
and
thereby create a balanced or unbalanced or unbalanced and distorted three phase source.
(b) Uvw to xy Block this block converts a set of three phase quantities into two phase quantities (zero
sequence component is not there since only three wire system is being considered)
(c) Sine Cos Template Block Generates unit vectors in the two phase coordinate system.
SK5 19
SK5 20
(d) Two Phase to Synchronously Rotating Reference Frame Transformation
(e) Filtering in d-q Extracts the dc component in d and q axis quantities and removes the dc from original
quantities in order to find out the reference signals for shunt Inverter in the d-q plane.
(f) d-q to two phase and two phase to three phase transformations
SK5 21
(g) VSI Inverter Subsystem
(h) Load Current Subsystem is a masked block giving a choice between 24kVA balanced Thyristor Load,
50kVA Balanced Rectifier Load, 50kVA Sinusoidal Load and 15kVA Unbalanced Rectifier Load.When the
Sinusoidal load is chosen the values entered in the frequency box and phase (in radians) box will be used.
2. Simulation Results and Discussion on D-Q Method
Four cases have been simulated to bring out the salient aspects of D-Q Method of Shunt Active Filter
Control.They are
(a) Balanced Three Phase Supply (360V amplitude phase voltage) with zero distortion feeding a load of
50kVA at 0.7 Lag.The load current waveform is balanced and sinusoidal.
(b) Same load (it is a sinusoidal current source load , not RL load) but the supply has 10% negative sequence.
(c) Same load , but supply has 5% each fifth and seventh harmonic and no negative sequence amplitude.
(d) Balanced , Undistorted supply with 24kVA balanced thyristor converter load (23.5% THD).
The important waveforms for these four cases appear in the pages at the end of this lecture note.
Analysis of Case (a) Waveforms
The waveforms of d-q components of load current are constants in steady state. This is expected since a
set of positive sequence three phase pure sinusoidal quantities will appear as dc quantities in the synchronously
revolving frame.However under transient conditions the 4
th
order butterworth low pass filter of 25Hz cutoff used
in the d-q filtering block will delay the rise of these dc quantities thereby forcing the APF to deliver or take
(deliver when load is switched on , take when the load is thrown off) active power from its DC Side
capacitor.This explains the dip in capacitor voltage.Increasing the bandwidth of the low pass filters will reduce
the dip , but will result in mains current distortion.
The inverter in the simulation is lossless and hence will not demand any active current flow into
it.However a large reactive current flows into it and this should have resulted in 2
nd
harmonic power pulsations
at the DC Capacitor node leading to second harmonic ripple in Capacitor Voltage.But then the reactive current
that goes into the inverter in this case is a balanced current and the power pulsations due to three phases cancel
out .Thus the Capacitor is virtually untouched in this case.
Thus as expected under steady state no harmonic components can appear at inverter reference currents
(they can appear only via d-q components of load current leaking through filters or from DC Side ripples) and
hence the line currents will remain pure sinusoidal as they should (after all load current in this case is pure
sinusoidal).
Analysis of Case (b) Waveforms
Here in this case the d-q components of load current show second harmonic component in addition to
the expected dc components.This is due to the fact that a set of negative sequence three phase quatities will
appear as second harmonic quantities when translated into a synchronously revoloving reference frame (they
will appear dc if the frame rotates in the opposite direction, but then a reference frame can not be rotating in
both directions at the same time !).This second harmonic shouldnt have come through the filter , but then the
low pass filter is not ideal, so a little will come through anyway.This second harmonic leaks into inverter current
reference in d-q plane and becomes third harmonic (and fundamental,creating unbalance in fundamental
frequency currents) when it is translated into three phase quantities.Unbalanced mains currents with balanced
load currents imply unbalanced inverter currents.Unbalanced inverter currents imply second harmonic ripple in
DC Side Capacitor and that in turn means further third harmonic current in the lines due to DC Voltage control
SK5 22
loop.The simulation results confirm that almost the entire THD of 8.3% reported for this case came from third
harmonic in the line currents.Obviously the third harmonic in the line currents are not co-phasal and the line
currents are not balanced.Thus d-q method succeeds in creating harmonics and unbalance in mains currents
when the load itself is pure balanced currents.The solution lies in sensing the dc values of load current d-q
components avoiding all other ripple components in them and generating unit templates from a PLL system
which locks on to the positive sequence component of voltage.
Analysis of Case (c) Waveforms
In this case the supply voltages have harmonic content and these voltages are used to generate the sine
and cos templates needed to move back and forth between static reference frame and rotating reference
frame.Obviously all the harmonics in the supply get carried into inverter current reference signals with no
attenuation whatsoever.Thus the line currents will get distorted.The ripples in the capacitor voltage adds to the
problem and this explains why the mains current has a THD of 7.4% which is more than the 7% THD of mains
voltage. No system which does not use a PLL based Synchronisation w.r.t to positive sequence component of
mains can be immune to supply voltage harmonics working its way into supply currents through an active shunt
filter.
Analysis of Case (d) Waveforms
This case returns a mains current with 6.1% THD when the load is a balanced thyristor converter load
of 24kVA and 23.5% THD with a balanced undistorted supply.An active filter should be able to do better than
this. Analysis of these waveforms reveal another problem with the d-q domain low pass filtering.The idea of the
filtering in d-q domain was to get the dc component of d-component of load current (and that of q-component if
no reactive compensation is desired) and subtract it from the total d-component to get the component to be
cancelled by the inverter.But the low pass filter used to get the dc component will also pass a little of 4
th
,6
th
etc.(5
th
and 7
th
harmonics in load current become 4
th
,6
th
and 8
th
in d-q domain).Thus after subtraction what
comes out is different (usually lesser than actual, but phase relations are also to be considered) from what is
expected.Thus it is not the inverters fault it is generating what it is being asked to , but it is not being asked
enough ! this results in incomplete cancellation of harmonic currents. And, harmonic currents flowing in
inverter results in ripple voltage in DC Side Capacitor which puts them back into the line through the DC
Voltage Control Loop.
3. Simulation Results and Discussion on Modified Synchronous Detection Method
Three cases were simulated with this method.They are
(e) 10% Negative Sequence in Supply and 50kVA Sinusoidal Load at 0.7 Lag
(f) 24kVA Balanaced Thyristor Load with Balanced Undistorted Supply
(g) 15kVA Unbalanced Rectifier Load with Balanced Undistorted Supply
The excellent immunity of this method against supply unbalance is evinced by 1.15% THD in the mains
currents in case (e).Case(f) returns a much better THD than the D-Q method for similar conditions.Finally the
unbalanced rectifier load case (g) is further proof for the excellent performance of this method.The negative
sequence component in line current is negligible.This method, like any method which does not use PLL based
synchronisation, will suffer from bad performance under distorted line conditions.A PLL based system locking
onto fundamental component of U Phase voltage and an EPROM table-readout to construct the template
waveform will improve this method in this respect.
SK5 23
SK5 24
SK5 25
SK5 26
SK5 27
SK5 28
SK5 29
SK5 30
REFERENCES
[1] Bhimsingh, Kamal Al-Haddad, and Ambrish Chandra, A Review of Active Filters for
Power Quality improvement, IEEE Trans.Ind.Electron., Vol.46, no.5, pp .960, 1999
[2] M.El-Habrouk, M.K.Darwish and P.Mehta, "Active power filters: A review", IEE Proc.-
Electr. Power Appl., Vol.147, no.5, pp.404, 2000
[3] H.Akagi, A. Nabae, and S. Atoh, Control strategy of active power filters using multiple
voltage-source PWM converters, IEEE Trans. Ind. Appl.,vol. IA-22, no.3, pp. 460, 1986.
[4] H.Akagi, F.Z. Peng, A.Nabae, A Study of active power filters using quad-series
Voltage-Source PWM Converters for Harmonic Compensation , IEEE Trans. Power
Electron., vol.5, no.1, pp.9, 1990.
[5] A.Cavallini, G.C.Carlo, Compensation Strategies for Shunt Active filter control, IEEE
Trans. Power Electron.,vol. 9, no. 6, pp. 587, 1994.
[6] Vasco Soares, P.Verdelho, and G.D.Marques, "An Instantaneous Active and Reactive
Current Component Method for Active Filters", IEEE Trans. Power Electron.,vol.15,no.4,
pp.660, 2000
[7] H.-L.Jou, Performance comparison of the three-phase active powerfilter algorithms,
IEE Proc.Gen. Trans. Distrib.,vol. 142, no.6,1995.
[8] S-J Huang, J-C wu, "A Control Algorithm for Three-Phase Three-wired Active Power
Filters Under Nonideal Mains Voltages", IEEE Trans. Power Electron.,vol.14, no.4, pp.753,
1999.
[9] Suresh Kumar.K.S., "Simulation of an Active Power Filter Using Microsim Design Lab
8.0", AICTE-ISTE Summer school on Recent trends in computer simulation of Electrical
machines and Control systems, pp.133, 2000.
[10] L.A.Moran, Juan W. Dixon, R.R.Wallace, "A Three-Phase Active Power Filter
Operating with Fixed Switching Frequency for Reactive Power and Current Harmonic
Compensation", IEEE Trans. Ind. Electron., vol.42, no.4, pp.402, 1995
[11] L.Benchatia, S.Saadate and A.Salem nia. "A Comparison of Voltage Source and Current
Source Shunt Active Filter by Simulation and Experimentation", IEEE Trans. Power
Systems, vol. 14, no. 2. pp.642 , 1999.
[12] Juan W.Dixon, J.J.Garcia, and Luis Moran, "Control System for Three-Phase Active
Power Filter Which Simultaneously Compensates Power Factor and Unbalanced Loads",
IEEE Trans.Ind. Electron.,vol.42, no.6, pp.636, 1995
[13] J.Sebastian Tepper, Juan W.Dixon, G.Venegas, and Luis Moran, "A Simple Frequency-
Independent Method for Calculating the Reactive and Harmonic Current in a Nonlinear
Load", IEEE Trans. Ind. Electron., vol.43.,no.6, 1996
[14] C.K.Duffey, Ray P. Stratford, "Update of Harmonic Standard IEEE-519: IEEE
Recommended Practices and Requirements for Harmonic Control in Electric Power
Systems", IEEE Trans. Ind.Appli.,vol.25, no.6,nov/dec., 1989
[15] M.Tarafdar Haque,T.Ise,S.H.Hosseini, A Novel Control Strategy for Unified Power
Quality Conditioner (UPQC), 2002,IEEE
SK6 1
DYNAMIC VOLTAGE RESTORERS (DVR) AND THEIR CONTROL
Suresh Kumar K.S
1. Introduction
Power quality has a significant influence on high-technology equipments related to communication,
advanced control, automation, precise manufacturing technique and on-line service. For example, voltage sag
can have a bad influence on the products of semiconductor fabrication with considerable financial losses. Power
quality problems include transients, sags, interruptions and other distortions to the sinusoidal waveform. One of
the most important power quality issues is voltage sag that is a sudden short duration reduction in voltage
magnitude between 10 and 90% compared to nominal voltage. Voltage sag is deemed as a momentary decrease
in the rms voltage, with duration ranging from half a cycle up to one minute. Deep voltage sags, even of
relatively short duration, can have significant costs because of the proliferation of voltage-sensitive computer-
based and variable speed drive loads. The fraction of load that is sensitive to low voltage is expected to grow
rapidly in the coming decades. Studies have shown that transmission faults, while relatively rare, can cause
widespread sags that may constitute a major source of process interruptions for very long distances from the
faulted point. Distribution faults are considerably more common but the resulting sags are more limited in
geographic extent. The majority of voltage sags are within 40%of the nominal voltage. Therefore, by designing
drives and other critical loads capable of riding through sags with magnitude of up to 40%, interruption of
processes can be reduced significantly. The DVR can correct sags resulting from faults in either the transmission
or the distribution system.
2. Basic Principle of DVR
To quantify voltage sag in radial distribution system, the voltage divider model, shown in Fig. 1, can be
used on the assumption that the fault current is much larger than the load current during faults. The point of
common coupling (PCC) is the point from which both the fault and the load are fed. Voltage sag is mostly
unbalanced and accompanied by phase angle jump.
From Fig. 1, the voltage at the PCC and phase angle jump can be obtained by
The DVR is able to compensate the voltage sag especially at sensitive loads by injecting an appropriate
voltage through an injection transformer. Figure 2 shows a block diagram of the DVR power circuit. When
examining the DVR it can be divided into four component blocks:
1) Energy storage device,
2) DC to DC power controller,
3) A three-phase voltage converter,
4) Three single-phase series injection transformers.
SK6 2
The design of the DVR allows real and reactive power to be either supplied or absorbed when
operating. If a small fault occurs on the protected system, then the DVR can correct it using only reactive power
generated internally. For correction of larger faults, the DVR may be required to develop real power. To enable
the development of real power an energy storage device must be used; currently the DVR design uses a
capacitor bank. Once the fault has been corrected and the supply is operating under normal conditions, the DVR
replenishes the energy expended from the healthy system. The rating (in terms of energy storage capabilities) of
the capacitor bank is dependent upon system factors such as the rating of the load that protects and the duration
and depth of anticipated sags. When correcting large sag (using real power), the power electronics are fed from
the capacitor bank via a DC-DC voltage conversion circuit.
The core element in DVR design is the three-phase voltage converter. This inverter utilizes solid-state
power electronics (insulated gate bipolar transistors, IGBTs) to convert DC to AC and back again during
operation. The DVR connects in series with the distribution line through an injection transformer, actually three
single-phase transformers. The primary side (connected into the line) must be sized to carry the full line
current.The primary voltage rating is the maximum voltage the DVR can inject into the line for a given
application.The DVR rating (per phase), is the maximum injection voltage times the primary current.The bridge
outputs on the secondary are filtered before being applied to the injection transformer. The bridges are
independently controllable to allow each phase to be compensated separately. The output voltage wave shapes
are generated by pulse-width modulated switching. When voltage sag reaches a value below the limit for
correction using zero energy, the energy storage system within the DVR has to be used to aid voltage correction.
The ideal restoration is to make load voltages unchanged. When DVR restores large voltage
disturbances, active power or energy should be injected from DVR to distribution system. If the capability of
energy storage of DVR were infinite, DVR could maintain load voltage unchanged ideally during any kind of
faults. However, the stored energy in DVR is limited practically by the limit of DC link capacity of DVR.
Namely, DVR cannot restore the load voltage constantly when the voltage across the DC link has gone down
and stored energy has run out eventually during deep voltage sag with long duration. Therefore, it is necessary
to minimize energy injection from DVR.
There are several methods how to inject DVR mitigating voltage to distribution system: pre-sag
compensation, in-phase compensation, and phase advance
3. Conventional DVR voltage injection methods
The possibility of compensating voltage sag can be limited by a number of factors including finite
DVR power rating, different load conditions, and different types of voltage sag. Some loads are very sensitive to
phase angle jump and others are tolerant to phase angle jump. Therefore, the control strategy depends on the
type of load character-istics . There are three distinguishing methods to inject DVR compensating voltage, that
is, pre-sag compensation method, in-phase compensation method, and phase advance method.
Pre-sag compensation methods is to track supply voltage continuously and compensate load voltage
during fault to pre-fault condition. Fig. 3 shows the single-phase vector diagram of the pre-sag compensation. In
SK6 3
this method, the load voltage can be restored ideally, but injected active power cannot be controlled and is
determined by external conditions such as the type of faults and load condition.
In in-phase compensation shown in Fig. 4, the injected DVR voltage is in phase with measured supply
voltage regardless of the load current and the pre-fault voltage. The advantage of this method is that magnitude
of injected DVR voltage is minimized for constant load voltage magnitude.
Pre-sag compensation and in-phase compensation must inject active power to loads almost all the time.
However, the amount of possible injection active power is confined to the stored energy in DC link, which is
one of the most expensive components in DVR. Due to the limit of energy storage capacity of DC link, the DVR
restoration time and performance are confined in these methods. For the sake of controlling injection energy,
phase advance method was proposed .
The injection active power is made zero by means of having the injection voltage phasor perpendicular
to the load current phasor. This method can reduce the consumption of energy stored in DC link by injecting
reactive power instead of active power. Reducing energy consumption means that ride-through ability is
increased when the energy storage capacity is fixed. On the other hand, the injection voltage magnitude of phase
advance method is larger than those of pre-sag or in-phase method and the voltage phase shift can cause voltage
waveform discontinuity, inaccurate zero crossing, and load power swing. Therefore, phase advance method
should be adjusted to the load that is tolerant to phase angle jump, or transition period should be taken while
phase angle is moved from pre-fault angle to advance angle:
4. A Three Phase DVR and its Control
A sample three phase DVR capable of maintaining the load voltage balanced and of constant amplitude
against flicker, harmonics, sags, swells and unbalance in supply and unbalance in load is discussed in the
remaining part of this lecture.
The three phase inverter is made by three single phase inverters connected to star connected primary of
interface transformer. The secondaries are connected in series in the lines.The three phase inverter rating is
10kVA and the transformer has a turns ratio of 1:5.This means that the inverter can inject upto 20% of rated
voltage in series with the supply.Inverter modulator will saturate after that and clip the injected voltage at
around 65V peak (assuming 320V peak phase voltage). The maximum load in the supply line is assumed to be
around 50kVA. The inverter uses sinusoidal PWM (unipolar switching) at 20kHz switching frequency. The
control strategy is explained with reference to the diagram that follows.
SK6 4
The load voltage is stepped down using PTs and a PLL is locked onto R phase.The pure sinewave
phase synchronised to R phase goes into a Positive Sequence Constructor circuit (all pass filter based) which
generates unit amplitude positive sequence waves.These templates are multiplied by the desired amplitude
(320V) to form the desired load voltage.The actual load voltage from the sensing circuit is subtracted from this
to form the reference signals into Inverter Modulator.The inverter injects the required voltage.The control
strategy is feed-forward and hence is fast, but suffers from the disadvantage of not having any feedback.The Dc
Side is assumed to be a power source like a battery or a AC-DC converter running from same bus.Correction
strategy is inphase and hence active power flow is involved.
The Simulink Simulation diagram for this system is given in the next page.
SK6 5
SK6 6
The saturation block in this subsystem is set at 65 Volts to reflect the overmodulation limit of inverter. The
simulation results are not included here due to space limitations. However the following comments are in order.
i. Three simulation files (Simulink files) are included in the accompanying CDROM for this DVR. They are
dvr_simple.mdl, dvr_filt.mdl and dvr_full.mdl. The first one models the inverter as an ideal voltage
controlled voltage source and can be used only to illustrate the concepts involved. The second one models
the inverter as an ideal voltage controlled voltage source but includes the filter at the output of the
inverter.The third one includes the PWM switching also , but does not take care of the inverter losses.
ii. The first model will give very optimistic results under dynamic conditions for example it will show that
the output voltage is not even aware of a sudden phase change at input. This will not be true in practice. The
various unmodelled delays along with the inverter filter response time will really pass the sudden changes
in the input voltages at least partially to the output side.
iii. The first model will yield a performance, which simply does not depend on the load current, since this
model has no impedance anywhere. But in practice the output voltage will get affected by load harmonics
due to two reasons the inverter output filter will call for harmonic drops when harmonic load currents
flow through it and in the absence of feedback control the system does not correct anything to the right of
inverter. Secondly the finite bandwidth of inverter (due to a finite switching frequency) will make it fail in
generating high frequency content produced at the source bus by high frequency component of load
currents flowing in source impedance (which is taken as zero in the first simulink model).
iv. When the amount of sag, swell or flicker or harmonic content is excessive the inverter will saturate and clip
its output. This will lead to distortion in output voltage. But simulation runs reveal that this distortion
remains under 10% even for sags which take source voltage to 100V peak. All three models include this
clipping effect.
v. The control of DVR is not a very complex problem and in fact field experience justifies feedforward
control. However providing a suitable DC Side energy source to handle long periods of sag or swell or
flicker throughout the day (like arc furnace) will be a problem. If it is a Battery it requires a charger. Some
researchers have proposed drawing charging power from the line using the same inverter during periods
which sag or swell is little and can be handled by 90-degree voltage injection. But that makes the control
pretty complex. If it is a AC-DC Diode Rectifier the DVR can handle only sags and not swells since during
swells the inverter will absorb power (in the inphase injection strategy considered here) and dump it on
the DC Side.So, then it has to be a Bilaterlal Converter based AC-DC Converter and then we get very close
to what they call a Unified Power Quality Conditioner then it is no more a DVR alone, but can easily
become a UPQC.
SK7 1
SIMULATION OF A SINGLE-PHASE ACTIVE POWER LINE CONDITIONER
USING MICROSIM DESIGN LAB 8.0
Suresh Kumar.K.S.,
Asst.Prof.,Dept. of Elect. Engg.,
N.I.T.,Calicut
1. Introduction
Deterioration of Power Quality due to the connection of a large number of non-linear loads in
the power system network has become a major concern world over in the recent years. Whenever a large load is
switched into or switched off from the network, a sag or swell of the supply voltage for 2 to 5 cycles is very
common. Also, a sustained dip or rise in voltage level around 230V is common. To protect the voltage sensitive
devices from this kind of hazards, a voltage stabilizer is required which will not let the variation in supply
voltage to affect the device by keeping the voltage across the device fixed.
The other way to look at the use of power quality conditioner is that due to increasing use of
electronic devices, the quality of power is getting corrupted. This is because harmonics are injected into the
supply by the electronic/industrial electronic loads which are mostly non-linear in nature.
A single phase PWM Inverter based Active Power Quality Conditioner (APQC, sometimes
called Active Power Line Conditioner too) which can deliver clean, stable and regulated AC voltage to a critical
load working from an AC line which suffers from poor power quality including sags, swells, transients and
harmonics is discussed in this lecture. This device takes care of the sags, swells as well as sustained voltage
dip/rise in the supply. It also takes care of the power quality of the system by preventing the harmonics produced
by the loads being injected into the supply and isolates the load from voltage harmonics that may be present in
the line.
2. Synchronous Link in Active Power Quality Conditioners (APQC)
2.1 Basic Principle Of a Synchronous Link
A PQC is essentially a synchronous link. Various topologies differ only in control strategies.
Consider two synchronous AC sources connected through a reactor i.e., a synchronous link.
Fig. 2.1 Synchronous Link
Assuming the reactor to be lossless, the active and reactive power equations can be found out as follows:
( )
( )
( )

= +

=
= +
jX
1
V 0
2
V
1
V jQ P
*
jX
1
V 0
2
V
*
I But,
*
I
1
V jQ P
SK7 2
Separating into real and imaginary parts,
The following factors can be observed from this :
1) Real power flow P takes place from the leading bus to the lagging bus. It is proportional to sin and it does
not depend much on the voltage difference |V
1
V
2
|.
2) Reactive power flow takes place from the bus with higher voltage to the bus with lower voltage. It is
proportional to |V
1
V
2
| and does not depend much on .
Fig. 2.2 Block diagram of the APQC
Thus, the inverter output voltage can be made constant even for varying source voltages by
controlling the reactive power flow through the link reactor. This is the basic principle of the proposed PQC.
When the supply voltage is low, a leading reactive power is drawn from the supply by the inverter in order to
make the inverter output voltage 230V. Similarly, when supply voltage is high, a lagging reactive power is
drawn.
The link reactor serves another purpose also. When any harmonic current is required for the
load, most of it comes from the inverter side because the link reactor presents high impedance to harmonics. The
supply current remains essentially sinusoidal even for non-linear loads.
Fig. 2.3 Equivalent circuit for current harmonics
In steady state, when the supply is present, the inverter supplies only reactive power. However,
during the transient period (i.e., when load is switched on), the active power must also come from the inverter. If
the PQC is without backup, this drawing of active power will result in an appreciable dip in the capacitor voltage
that should be corrected immediately by drawing more active power from the source. So, the control of the PQC
without backup should be very fast.
( )
. small for
X
2
V
1
V
1
V
cos
X
2
V
1
V
X
2
1
V
Q
sin
X
2
V
1
V
P

= =
=
SK7 3
But if the PQC is having a backup, the DC side voltage will not dip even if the active power is
taken from the inverter. This eases the control strategy. Even if the control is a bit slow, the buffering action of
the battery will prevent the system from going haywire.
The PQC without backup can function only when the supply is present because it needs to
draw active power from the supply to maintain its DC side voltage. But the PQC with backup can function even
when the supply is absent.
3. A Single Phase APQC without Battery Backup
3.1 Basic principle of Power Quality Conditioner
The Active Power Quality Conditioner is expected to provide a constant amplitude sinusoidal
voltage to the load against a varying line input; all the while drawing a sinusoidal current even when the load is
non-linear. The principle of synchronous link power flow is used in the system.
Active power flows from leading bus to lagging bus in a synchronous link and it is
proportional to lead angle (in radians) for small variations of current. Reactive power flows from higher voltage
magnitude bus to lower voltage magnitude bus and is roughly proportional to difference in voltage magnitudes.
In the APQC without Battery backup, one of the two AC sources is the AC mains voltage
whereas the other one is the output of the PWM sine wave inverter running from a DC voltage assumed to be
available from a charged DC side capacitor. A link inductance L links them up and the load is connected across
inverter output.
Fig. 3.1 Basic system
The line voltage (or its fundamental component if it is a distorted one) is the reference wave in
the system. The output synthesized by the inverter is adjustable in phase with respect to this reference wave by
proper inverter gating control. Thus the power flow from mains to the load plus inverter combination can be
controlled by making the phase angle of the inverter output lagging with respect to line by varying amounts to
suit the requirement. Also, by suitable control of gating, it is possible to control the amplitude of the inverter
output (and hence the load voltage). The reactive power flow in the link will adjust according to the line voltage
conditions. For example, if the line has a low voltage and inverter output is maintained at a lower value, the
inverter will automatically deliver the required amount of lagging reactive power to the line as per the
synchronous link power flow equation.
If the inverter is a loss-free one, the active power flow from the line into the inverter will get
translated as an even increasing voltage in the DC side capacitor. Similarly, an active power flow out of the
inverter will eventually take the DC side to zero voltage condition. It is necessary that the DC side capacitor
voltage be maintained at a fixed value (at least within a band around the nominal value) in order to synthesize a
rated amplitude sinusoidal output at the inverter for all load conditions. Practical constraints on the maximum
modulation index achievable in a Sinusoidal pulse Width Modulated (SPWM) inverter will put the desired DC
bus voltage in the range of 350 V to 370 V DC. Thus, in a loss-free inverter, the active power flow from the line
must be exactly equal to the active power required by the load and no active power must flow into or out of the
inverter under steady state and the inverter must be able to draw/deliver active power when the DC side capacitor
voltage is to be corrected. This calls for a continuous adjustment of phase angle of inverter output conditioned
upon the value of the DC side capacitor.
Usually the switches in the inverter will have diodes connected across them. At the time of
startup, the DC side capacitor will charge up to the line voltage peak through the line inductor and these diodes
like in any ordinary rectifier circuit. After that the active power flow control will maintain the DC side voltage at
the desired value. If the inverter has losses, the active power flow control will maintain the power flow into the
inverter at the right value such that the losses are met and there is no extra power left to upset the capacitor
voltage.
SK7 4
A non-linear load draws a non-sinusoidal current. This current can come from two paths
from inverter and from line. The active fundamental component will come from line side as per the above logic.
The reactive component may come from line or inverter or both depending upon the line voltage conditions. And
the harmonic components of the load current will come from both line and inverter. If the inverter output
impedance had been zero all the harmonic currents would have come from the inverter and hence line current
would have been a pure sine wave. But the inverter output impedance will not be zero; hence part of the
harmonic current flows in the mains line too and this will result in line current distortion as well as output
voltage distortion. However, inverter impedance is small compared to link impedance and hence only a very
small portion of total harmonic current generated by the load will flow through the line. It is possible to bring
down the distortion in both the line current and output voltage to less than 5% by proper control of inverter
output filter impedance.
3.2 Control of PQC
Essentially three types of control strategies are applicable to a PQC.
The first is the phase angle control scheme. Here the controlled variable is DC side capacitor
voltage and the variable used for control is phase lag of inverter output with respect to line. A synchronous but
phase shifted sine wave is synthesized from line and given as the reference input for inverter. Inverter is gated as
per sinusoidal PWM logic or delta modulating logic to produce a constant amplitude sine wave output. The
phase of this output is controlled in such a way that DC side voltage is maintained constant. A PI control system
is used for this purpose and a voltage to phase angle converter implements the control finally. A secondary
control loop that senses the amplitude of inverter output and adjusts the amplitude against load variations may be
needed if tight control of regulation is required. But if regulation within 5% is sufficient, such a loop can be
dispensed with. The most important disadvantage of this control scheme is its slow response and prominent
overshoots and undershoots in the DC side voltage and corresponding swells and sags in line current during
transient conditions.
The second control strategy is direct current control of inverter i.e. it converts the voltage
source inverter into a current regulated PWM inverter. Two sinusoidal templates one sinusoidal and in phase
with a.c. line and second sinusoidal and 90
0
leading w.r.t a.c. line i.e cosine are generated from the a.c. line
using a PLL based system. DC side voltage is sensed and compared with a set reference value. The resultant
error is used to amplitude modulate the sine wave template and the result will be the desired active component of
current that the inverter has to draw from the line. Similarly, the inverter output voltage amplitude is sensed and
compared with a set reference value. The resultant error is used to amplitude modulate the cosine template. The
result is the desired reactive current that the inverter has to draw. These two current references are added to form
the reference current for the inverter. The actual current in the inverter is fed back into a current control loop and
the inverter switches are gated in order to bridge the gap between the reference and the actual current by
hysteresis control or unipolar switching scheme.
Considerable improvement in speed and accuracy results in this control scheme. However, the
current control loop can be difficult to compensate due to sharp changes in phase lag of inverter filter at about its
resonance frequency. Also this kind of feedback current control tends to be sensitive to noise pickup in the
current sensing process.
An indirect current control is used in the third control scheme. Assume that all impedances
between the AC line and DC side capacitor are precisely known. These include link inductance value, its
resistance, inverter filter impedance and inverter equivalent resistance. The reference current i.e., the current that
the inverter must draw in order to maintain the DC side voltage and output voltage constant is calculated in the
same way as in the case of the second control scheme described above. If all impedances are known and the line
side voltage is known, the inverter internal output voltage required to make this current flow in the link can be
calculated by adding the impedance drop to the line voltage. This calculation is done in real time in analog
OpAmp circuits and the inverter voltage reference is created thereby. If all impedances are accurately known, the
actual current will be equal to the reference current. However, due to error in parameter measurement/estimation,
a current feedback loop will be needed in practice in this scheme too. But this feedback loop needs to have only a
small gain and need not be compensated at all. Also, if PI control is employed on capacitor voltage and output
voltage, this minor current loop can be removed. Even if only proportional control is used everywhere, the
allowed tolerances in regulation will make the current feedback unnecessary. Similarly, if link impedance is the
dominant impedance, other impedances may be ignored in calculation at the expense of slight degradation of
output voltage regulation. This is the control scheme that is considered further in the sections that follow.
With the fundamental component of current flow in the AC side of the inverter, the DC side
capacitor will have second harmonic current flow and resulting second harmonic ripple in the voltage across it.
Size of this capacitor is selected to reduce this ripple. But when this capacitor voltage is sensed and compared
with a set value, considerable filtering will be needed to avoid injection of third harmonic into the active current
reference. Such filtering makes a system sluggish and gain/phase margins also come down resulting in
impermissible overshoots and undershoots in the capacitor voltage. Hence, a sampling scheme with sampling
period of 10ms is generally used to derive the capacitor voltage signal needed for control purpose. A similar
SK7 5
sampling scheme senses the AC source voltage at peak and avoids filtering in that sensing path too. These two
sampling processes make it possible to implement corrections in one half cycle, thereby permitting the use of a
lower value of capacitor than what would have been necessary otherwise. Further, the control scheme
compensation is simpler with this sampling scheme.
3.2.1 Indirect Current Control Based APQC Control
From the block diagram (Fig. 3.2), it can be seen that, Inverter output voltage = AC supply voltage +
Inductor drop =
dt
di
L
ac
V +
where, i consists of active and reactive components.
To realize this, the supply voltage is peak sampled and compared with 230V reference. This
error is multiplied by the cosine template to give the reactive current reference. Likewise, the capacitor voltage is
sampled and compared with 350V reference. This error is multiplied by sine template through an analog
multiplier to give the active current reference. Adding these two currents, the current reference is obtained. This
current is differentiated with a gain of L so that L( di/dt) is obtained. This is added to the supply voltage to get
the output voltage.
In this scheme, there arises the need for DC offset control. The input AC source will not
contain any DC component but the synthesized AC provided by the inverter may contain DC. This may be due to
the fact that the switches are not identical and switching times are not similar. This DC will appear as a 50 Hz
current on the capacitor side. This 50 Hz current should ideally create a cosine ripple in the capacitor voltage that
will give only a second harmonic in the inverter output. But because of the non linear relationship between
voltage and energy ( E = CV
2
), an upper excursion of voltage of voltage ripple will be of lower magnitude
than the lower excursion. This will result in a 50 Hz sine content in capacitor voltage. The fundamental cosine
content in capacitor voltage results in pure second harmonic in the output. But fundamental sine content in
capacitor voltage results in further generation of DC content at the inverter output which will eventually be
limited only by the total resistance present on the AC side. The DC current can be eliminated by giving a DC
offset to the inverter control voltage. The offset given is controlled by the magnitude of the DC current present in
the AC side. A low pass filter on the sensed inverter current measures this magnitude.
The inverter control voltage is obtained by adding this offset control voltage to the inverter
output voltage. This control voltage is compared with the high frequency triangular wave to be used in SPWM
scheme to provide gating signal to the MOSFETs/IGBTs.
SK7 6
3.3 Simulation Model Of The Scheme
3.3.1 Simulation of Control Dynamics
The model used for simulating the scheme is shown in the Fig.3.3. The supply line is
represented by a 230V, 50Hz sine wave source. On the other side of the link inductor (which is represented by L
and its related resistance R), the inverter is represented using an ABM block. The various hierarchical blocks and
other elements used in the model are explained below
.
(a) Reactive Current Control Block
This hierarchical block is used to obtain the reactive current reference from the supply voltage.
In this block, the scaled down supply voltage is peak sampled using a transistor that is switched at 10ms intervals
by a square wave generator (VPULSE) of 10us pulse width. This signal is held by a capacitor, inverted and
added with a 1V-amplitude reference voltage (which represents the 230V supply). The error is multiplied by the
inductor impedance using an E-device. This is passed through a limiter and multiplied with the cosine template.
The output of the multiplier is the required reactive current reference.
(b) Active Current Control Block

This hierarchical block is used to obtain the active current reference from the scaled down DC
capacitor voltage. The conversion scheme followed is same as in the previous case. However, the reference
voltage is 1.0937V (representing 350V DC). Also, after the limiter, the error signal is multiplied with the sine
template. The resultant signal is the active current reference.
SK7 7
Fig. 3.4 Reactive Current Control Block
Fig. 3.5 Active Current Control Block
(c) Inverter Control Voltage Block
This hierarchical block is used to obtain the inverter modulation voltage from the active and
reactive current references and the supply voltage. Here, the current references are added together and
differentiated in a differentiator. This is added to the scaled down supply voltage and passed through a limiter.
The output obtained is the inverter modulation voltage.
(d) PWM-Converter Model
This hierarchical block is used to calculate the output voltage of the inverter after filtering as
well as the capacitor current. The DC offset control is also calculated in this block and is added to the inverter
control voltage. The top ABM block is used to calculate the inverter output voltage. Here, the inverter control
voltage is multiplied with the DC capacitor voltage (referred to a 320V scale). The output is the required voltage.
The bottom ABM block is used to calculate the DC side capacitor current. In this, the inverter output voltage
(obtained from the first ABM block) is multiplied with the inverter output current (obtained from the H-device)
and this is divided with the capacitor voltage. The resulting current is the capacitor current. The implied principle
is one of instantaneous power balance between DC side power and output side power in the inverter, neglecting
the losses in the inverter and changes in energy storage in the inverter output filter components.
SK7 8
Fig.3.6 Inverter Control Voltage Block
Fig.3.7 PWM Converter Model
(e) Load
A non-linear load consisting of a rectifier and an R-L load connected in parallel is contained in
this hierarchical block. Either the R-L load or the rectifier load was made active at various instants for different
simulation runs using switch models available in PSpice.
(f) Perturbation AC
The perturbations in the supply are introduced by multiplying two voltage sources (VSIN) and
adding this to the original source voltage. Such an arrangement can produce different source disturbances
including an amplitude-modulated wave.
SK7 9
Fig.3.8 Load Circuit Model
Fig. 3.9 Perturbation AC
3.4 Analysis Of Waveforms Obtained From Simulation
A PQC based on the above models was simulated using Microsim Pspice (Design Lab 8.0)
package. The results of simulation studies are included in the sections that follow. The system simulated had the
following parameters.
Rating - 500VA, Input Single Phase 170 t0 270 V, Output 230 5% V
Inverter Loss Resistance 3 ohms , Inverter Output Filter Inductance 4mH
Output Filter Capacitances 1uF in parallel with series combination of 1uF & 100 ohms
Link Inductor 96mH with 2 ohms resistance
Inverter Details Single Phase Full Bridge MOSFET Inverter using IRFP450 MOSFETs
Inverter Modulation Scheme Unipolar Sinusoidal Modulation at 20kHz
SK7 10
3.4.1 Simulation of control dynamics for various load conditions
Case 1 : Rms. line voltage 230V with 500VA R-L load of 0.6 p.f switched on at 100 ms
Figure 3.4.1 show the source voltage, output voltage, source current, load current, inverter
current and capacitor voltage. Before the load is switched on, a very small source current is drawn in order to
supply the inverter losses. The load gets switched on immediately after the sampling of the capacitor voltage has
been done. So for the next 10ms, the active current reference cannot change. The capacitor has to supply the
power during this time. This explains the dip in capacitor voltage at 100ms. At 110ms, the capacitor voltage is
sampled and the active current reference changes accordingly. This change in active current reference causes
phase shift in the inverter output voltage resulting in current flowing through the link inductor.
At the time of sensing (110ms), the capacitor voltage was at the lowest point. So active current
reference is made somewhat larger resulting in a high source current than required. The next cycle of load
current will be then somewhat lower. These oscillations in source current and capacitor voltage will be damped
out in a few cycles.
The capacitor voltage has a 100 Hz ripple that occurs because of the 100 Hz ripple in the
power on the AC side. A steady state error in the capacitor voltage can also be seen. This happens because only
proportional control has been used.
In steady state, the inverter is supplying all the reactive power. This is evident from the fact
that the inverter output voltage and output current are at a phase shift of 90 degrees.
Fig. 3.4.1 Waveforms for Case 1
Case 2 : Rms line voltage changes from 230 V to 170 V at 200ms with R-L load switched on at 40ms.
Figure 3.4.2 shows the source voltage, output voltage, source current, load current and inverter
current. The waveforms similar behaviour as in the previous case when the load is switched on. Source voltage
decreases to 170V at 200ms. But this dip in source voltage is not recognized instantaneously by the reactive
current reference block because the next sampling of source voltage will take place only at 205ms. So the
reactive current will continue to be the same resulting in the inverter output voltage following the source. At
205ms, the reactive current reference will change which results in a sudden rise in the inverter output voltage.
This sudden rise will appear as a step input to the LC filter resulting in some oscillations in the output.
The link inductor current will change at 205ms reflecting the change in the reactive current
reference.
The inverter output current, after 205ms, shows that the inverter is supplying both the lagging
reactive power needed by the load and the lagging reactive power required for making the output voltage
constant. For power balance, as voltage decreases, the inverter and link current increase.
SK7 11
Case 3 : Rms line voltage changes from 230V to 270V at 200ms with R-L load switched on at 40ms.
Figure 3.4.3 shows the source voltage, output voltage, source current, load current and inverter current.
This is similar to the previous case except in the inverter current after 205ms. The leading reactive power
requirement for making the output voltage constant cancels out the lagging reactive power requirement of the
load. Hence the inverter output current is almost zero.
SK7 12
The source current after 205ms is leading the inverter output voltage keeping the output
voltage at 230V.
Case 4 : Rms line voltage = 230V with 300W rectifier load switched on at 40ms.
Figure 3.4.4 shows the output voltage, link current, the load current and the inverter current.
The waveforms are shown from 100ms to 160ms. Output voltage shows clipping at its peak because at this
moment, the diodes conduct and the output voltage is the same as the capacitor voltage which cannot change
instantaneously. Small filter oscillations can be observed in the output waveform when the diodes of the
rectifier stop conducting. For damping the oscillations, a coupling capacitor with a resistor is used.
The input current waveform remains appreciably sinusoidal even with the load current being of
pulse nature. The THD of the input current was calculated and it was found to be well within the accepted limit
of 5%. See Table 1
Table. 1
Harmonic Analysis of Currents and Voltages Case 4
50 Hz 150 Hz 250 Hz 350 Hz 450 Hz THD(%)
Source
Current(A) 1.71 .0471 -
- -
2.75
Load
Current(A) 1.6 1.39 0.986 0.586 0.240 113.6
Inverter
Current(A) 0.17 1.36 0.983 0.576 0.237 1068.6
Output
Voltage(V) 312.6 3.0 2.9 -
-
1.3
The inverter supplies both the reactive power and the current harmonics. This is
manifested in the output current waveform of the inverter. The small oscillations seen are filter oscillations.
Case 5 : Rms line voltage changes from 230V to 170V at 200ms with rectifier load switched on at 40ms.
Figure 3.4.5 shows source voltage, output voltage, link current, load current and inverter
current. After 40ms, the output voltage shows some clipping at the peak which was already explained. When the
line voltage changes at 200ms, the corresponding adjustment in the output voltage takes place only at 205ms as
was previously explained.
SK7 13
Till 40ms, the inverter output current was almost zero. From 40ms to 50ms, the inverter
supplies the active power to the load. From 50ms to 205ms the inverter supplies the harmonic current as well as
the reactive power required by the load. From 205ms onwards, the decrease in the source voltage causes the
inverter to supply the extra reactive power required to make the output voltage 230V.This explains the inverter
current waveform.
The source current waveform remains more or less sinusoidal in this case also. The THD has
been calculated and was found to be less than 5% (Table 2). The capacitor voltage waveform shows the fact that
the reactive and harmonic currents are supplied from the inverter.
Fig. 3.4.5 Waveforms for Case 5 and the details in the figure below
Table. 2
Harmonic Analysis of Voltages and Currents Case 5
50 Hz 150 Hz 250 Hz 350 Hz THD(%)
Source
Current(A) 2.0 0.036 0.0325 - 2.43
Load
Current(A) 1.56 1.29 0.88 0.489 104.89
SK7 14
Inverter
Current(A) 1.03 1.24 .897 0.483 155.81
Output
Voltage(V) 320 2.53
- -
0.79
Case 6 : Rms line voltage changes from 230V to 270V at 200ms with rectifier load switched on at 40ms.
Figure 3.4.6 shows the source voltage, output voltage, and link current, load current and the
inverter current. Up to 200ms, the waveforms are similar to those in case 5. After 200ms, the inverter will
supply leading reactive power in order to make the output voltage 230V. This explains the source current and
inverter current waveforms. An expanded view of the above waveforms after the change in voltage is shown in
Figure 3.4.6 (Details).
Table. 3
Harmonic Analysis of Voltages and Currents Case 6
50 Hz 150 Hz 250 Hz 350 Hz THD(%)
Source
Current 1.6 0.05
- -
3.125
Load
Current 1.47 1.24 0.844 0.489 107.32
Inverter
Current 0.617 1.24 0.84 0.483 255.05
Output
Voltage 320.0 3.86
- -
1.2
SK7 15
Fig. 3.4.6(Details)
Case 7 : Rms line voltage changes from 170Vto 270V continuously (Amplitude Modulated wave) with R-L load.
Figure 3.4.7 shows the source voltage, output voltage and link current. Link current is lagging
when source voltage is high and leading when the source voltage is low.
One interesting observation is made here. The maximum value of the inverter output voltage
occurs when the supply voltage is minimum. Similarly, the minimum value of the inverter output voltage occurs
when the source voltage is maximum. In other words, the system is over-compensated. This over-compensation
comes from the DC offset control mechanism. The low pass filter used to extract the DC current will pass some
amount of the 50 Hz component also (around 2%). This will result in the inverter control voltage being
somewhat over-compensated.

===============
SDP 1
VARIABLE IMPEDANCE TYPE STATIC SERIES COMPENSATORS
Subha D. Puthankattil
Lecturer, EED
NITC
SERIES COMPENSATION
At a particular transmission voltage, the
transmission of power is determined by the series line
impedance and the angle between the end voltages of
line i.e., power flow is limited by the series reactive
impedance of the line. To increase the transmittable
power, series capacitive compensation was introduced
to cancel a portion of the reactive line impedance. But
with the upcoming of FACTS, it is seen that variable
series compensation is effective in controlling the
power flow in the line and improving the stability.
Hence controllable series line compensation helps in
controlling the power flow in the lines, prevent the
loop flows and also minimises the effect of system
disturbances. The effect of series compensation on
voltage stability, transient stability power oscillation
damping and sub synchronous oscillation damping is
being analysed.
Series Capacitive Compensation
Series capacitive compensation is provided
to decrease the overall effective series transmission
impedance from the sending end to the receiving end.
Consider a simple two-machine model with a series
capacitor compensated line, assumed to be composed
of two identical segments.
Refer fig.1
The magnitude of the total voltage across the series
line inductance is increased by the magnitude of the
opposite voltage, V
c
developed across the series
capacitor.
The effective transmission impedance X
eff
with the
series capacitive compensation is given by
X
eff
= X - X
c
X
eff
= (1-k) X
Where k is the degree of series compensation,
i.e., K = X
c
/X 0 k < 1
Assuming Vs = Vr = V, the current in the
compensated line and the corresponding real power
transmitted is,

( ) 2
sin
1
2
X k
V
I
=
sin
) 1 (
2
X k
V
VmI P
= =
The reactive power supplied by the series capacitor is,
( )
( ) cos 1
1
2
2
2
2
= =
k
k
X
V
X I Qc
c
Refer fig. 2.
It is observed that the transmittable power rapidly
increases with the degree of series compensation k.
Similarly, reactive power supplied by the series
capacitor also increases sharply with k and varies
with angle in a similar manner as the line reactive
power.
Voltage stability
Series capacitive compensation can be used
to reduce the series reactive impedance to minimise
the receiving-end voltage variation and the possibility
of voltage collapse. A simple radial system with
feeder line reactance X, series compensating
reactance Xc and load impedance Z is shown.
Refer Fig. 3
The normalised terminal voltage V
r
versus power P
plots with unity power factor load at 0, 50, 75% series
capacitive compensation are shown.
Refer Fig.4
Both shunt and series capacitive compensation can
effectively increase the voltage stability limit. Shunt
compensation does it by supplying the reactive load
demand and regulating the terminal voltage. Series
capacitive compensation does it by cancelling a
portion of the line reactance. For increasing the
voltage stability limit of overhead transmission, series
SDP 2
compensation is much more effective than shunt
compensation.
Improvement of transient stability
Series line compensation can be utilized
more effectively to increase the transient stability
limit and to provide power oscillation damping.
Consider the system with the series
compensated line in Fig 1 for the analysis. The pre
fault and post fault systems are assumed to be the
same for the series compensated case. It transmits the
same power with and without series compensation.
Assume that both the uncompensated and the series
compensated systems are subjected to the same fault
for the same period of time. Prior to the fault both of
then transmit power P
m
at angles
1
and
s1
respectively.
Refer Fig.5
During the fault, the transmitted electric power
becomes zero while the mechanical input power to
the generators remains constant, P
m
. Therefore, the
sending-end generator accelerates from the steady
state angle
1
and
s1
to angles
2
and
s2
respectively,
when the fault clears. The accelerating energies are
represented by areas A
1
and A
s1
. After fault clearing,
the transmitted electric power exceeds the mechanical
input power and therefore the sending-end machine
decelerates. However, the accumulated kinetic
energy further increases until a balance between the
accelerating and decelerating energies, represented by
areas A
1
, A
s1
, and A
2
, A
s2
, respectively, is reached at
the maximum angular swings,
3
and
s3
,
respectively. The areas between the P versus curve
and the constant P
m
line over the intervals defined by
angles
3
and
crit
, and
s3
and
scrit
, respectively,
determine the margin of transient stability,
margin
and A
smargin
. The increase
of transient stability margin is proportional to the
degree of series compensation.
Power oscillation damping
Controlled series compensation can be applied
effectively to damp power oscillations. It is
necessary to vary the applied compensation for power
oscillation damping so as to counteract the
accelerating and decelerating swings of the disturbed
machines. That is, when the rotationally oscillating
generator accelerates and angle increases
> 0
dt
d
, the electric power transmitted must be
increased to compensate for the excess mechanical
input power. Conversely, when the generator
decelerates and angle decreases
< 0
dt
d
, the
electric power must be decreased to balance the
insufficient mechanical input power.
Subsynchronous Oscillation Damping
The interactions between a series capacitor
compensated transmission line oscillating at the
natural resonant frequency, and the mechanical
system of a turbine-generator set in torsional
mechanical oscillation results in negative damping
with the consequent mutual reinforcement of the
electrical and mechanical oscillations. A capacitor in
series with the total circuit inductance of the
transmission line forms a series resonant circuit with
the natural frequency of
X
X
f
LC
f
c
c
= =
2
1
Where X
c
is the reactance of the series capacitor and
X is the total reactance of the line at the fundamental
power system frequency f. Since the degree of series
compensation
X
Xc
k = is usually in the 25 to 75 %
range, the electrical resonant frequency f
e
is less than
the power frequency f. If the electrical circuit is
brought into oscillation then the subharmonic
component of the line current results in a
corresponding subharmonic field in the machine
which, as it rotates backwards relative to the main
field (since f
e
< f), produces an alternating torque on
the rotor at the difference frequency of f f
c
. If
this difference frequency coincides with one of the
torsional resonances of the turbine generator sets,
mechanical torsional oscillation is excited, which,
inturn, further excites the electrical resonance. Large
generators with multistage steam turbines, which
have multiple torsional modes with frequencies below
the power frequency, are more susceptible to
subsynchronous resonance with series capacitor
compensated transmission lines.
Hence it is seen that the series compensator is mainly
required to solve the power flow problems. The
problems may be either due to the electric length of
the line or the structure of the transmission network.
The power transmission requirements due to the
electric length of the line can be solved by fixed
SDP 3
compensation of the line. Network structure related
problems as well as parallel and loop power flows
resulting in power flow unbalance require controlled
series compensation. Both fixed and controlled series
capacitive compensation can be used to minimize the
end voltage variation of radial lines and prevent
voltage collapse. Series compensation also helps in
improving transient stability for post fault systems
and is also highly effective in power oscillation
damping. The functional requirement to be met by
controlled series compensation can be achieved by
both thyristor controlled impedance type and
converter based voltage source type compensators.
Different Approaches To Controllable
Series Compensation
The series compensator is a reciprocal of the shunt
compensator. The basic reference parameter in shunt
compensation is the transmission voltage and it is the
line current in case of series compensation. The
shunt compensator is functionally a controlled
reactive current source which is connected in parallel
with the transmission line to control its voltage. The
series compensator is functionally a controlled
voltage source which is connected in series with the
transmission line to control its current. The series
compensator can be implemented either as a variable
reactive impedance or as a controlled voltage source
in series with the line.
Variable Impedance Type Series
Compensators
The two schemes involved are
1. Thyristor-switched / controlled-
capacitors
2. Thyristor-controlled reactors with fixed
capacitors
They are
1. GTO Thyristor-Controlled Series
Capacitor (GCSC)
2. Thyristor-Switched Series Capacitor
(TSSC)
3. Thyristor-Controlled Series Capacitor
(TCSC)
1. GTO Thyristor Controlled Series
Capacitor (GCSC)
An elementary GTO Thyristor-Controlled Series
Capacitor consists of a fixed capacitor in parallel with
a GTO Thyristor Valve that has the capability to turn
on and off upon command.
Refer Fig. 6
The objective of the GCSC scheme is to control the
ac voltage v
c
across the capacitor at a given line
current i. When the GTO valve, sw, is closed, the
voltage across the capacitor = o, and when the valve
is opened, it is maximum. For controlling the
capacitor voltage, the closing and opening of the
valve is carried out in each half cycle in synchronism
with the ac system frequency. The GTO valve is
stipulated to lose automatically whenever the
capacitor voltage crosses zero. However, the turn-off
instant of the valve in each half cycle is controlled by
a delay angle (0 / 2), with respect to the peak
of the line current.
Refer Figure 7
When the valve sw is opened at the crest of the line
current, the resultant capacitor voltage v
c
will be the
same is that obtained in steady state with a
permanently open switch. When the opening of the
valve is delayed by the angle with respect to the
crest of the line current, the capacitor voltage can be
expressed with the defined line current, i(t) = I cos t,
as follows:
) sin (sin ) (
1
) (
= =
t
C
I
dt t i
C
t v
t
c
Since the valve opens at and stipulated to close at
the first voltage 0, is valid for the integral t -
. For subsequent positive half cycle intervals the
same expressions remains valid. For subsequent
negative half cycle intervals, the sign of the
terms in the above equations becomes
opposite.
It is evident that the magnitude of the capacitor
voltage can be varied continuously by the method of
turn off delay angle control from maximum ( = 0) to
0
=
2
. The adjustment of the capacitor

voltage is discrete and can take place only
once in each half cycle.
Refer Fig. 8
The GCSC is stipulated to close at voltage zero. The
GCSC is controlled by a turnoff delay with respect to
the peak of the line current, which defines the
SDP 4
blocking interval of the valve. The GCSC controls
the voltage developed by a constant current source
across a fixed capacitor, thereby presenting a variable
reactive impedance to the source. The amplitude V
CF
() of the fundamental capacitor voltage v
CF
() can be
expressed as a function of angle .

2 sin
1 2
1
1
) (
C
V
CF
where I is the amplitude of the line current, c is the
capacitance of the GTO Thyristor Controlled
Capacitor and is the angular frequency of the ac
system.
The variation of the amplitude V
CF
() normalized to
the maximum voltage is shown plotted against delay
angle .
Refer Fig. 9
On the basis of the figure, varying the fundamental
capacitor voltage at a fixed line current, could be
considered as a variable capacitive impedance. An
effective capacitive impedance X
c
can be found for a
given value of angle . That is,

2 sin
1 2
1
1
) (
C
X
c
The admittance X
c
() varies with in the same
manner as the fundamental capacitor voltage V
CF
().
In practical application the GCSC can be operated
either to control the compensating voltage, V
CF
(), or
the compensating reactance, X
c
().
The turn-off delay angle control of the GCSC
generates harmonics. For identical positive and
negative voltage half cycles, only odd harmonics are
generated. The magnitudes of the harmonics
generated by GCSC can be attenuated effectively by
the complementary application of the method of
sequential control. It requires the use of m-series
connected GCSCs each with 1/m of the total rating
required. All but one of m capacitors are sequentially
controlled to be inserted or bypassed.
Refer Fig. 10
2. Thyristor-Switched Series
Capacitor (TSSC)
TSSC consists of a number of capacitors each
shunted by an appropriately rated bypass valve
composed of a string of reverse parallel connected
thyristors in series.
Refer Fig. 11
The degree of series compensation in TSSC is
controlled in a step like manner by increasing or
decreasing the number of series capacitors inserted.
A capacitor is inserted by turning of and it is
bypassed by turning on the corresponding thyristor
valve.
A thyristor valve commutates naturally. A capacitor
can be inserted into the line by the thyristor valve
only at the zero crossings of the line current. Since
the insertion takes place at line current zero, a full
half cycle of the line current will charge the capacitor
from zero to maximum and the successive, opposite
polarity half cycle of the line current will discharge it
from this maximum to zero.
Refer Fig. 12
The capacitor insertion at line current zero results in a
dc offset voltage which is equal to the amplitude of
the ac capacitor voltage. In order to minimize the
initial surge current in the valve, and the
corresponding circuit transient, the thyristor valve
should be turned on for by pass only when the
capacitor voltage is zero. With the prevailing dc
offset, this requirement can cause a delay of upto one
full cycle, which would set the theoretical limit for
the response time of the TSSC. The TSSC can
control the degree of series compensation by either
inserting or bypassing series capacitors but it cannot
change the natural characteristic of the classical series
capacitor compensated line. That is a sufficiently
high degree of TSSC compensation could cause
subsynchronous resonance just as well as an ordinary
capacitor. In principle the TSSC switching could be
modulated to counteracts subsynchronous
oscillations. The TSSC could be applied for power
flow control and for damping power oscillation where
the required speed of response is moderate.
3. Thyristor-Controlled Series
Capacitor (TCSC)
TCSC consists of the series compensating capacitor
shunted by a thyristor controlled reactor.
Refer Fig. 13
In a practical TCSC implementation several such
basic compensators may be connected in series to
obtain the desired voltage rating and operating
characteristics. The TCSC scheme provides a
SDP 5
continuously variable capacitor by means of partially
canceling the effective compensating capacitance by
the TCR. The steady state impedance of the TCSC is
that of the parallel LC circuit, consisting of a fixed
capacitive impedance, X
c
, and variable inductive
impedance X
L
(), that is,
C L
L C
TCSC
X X
X X
X
=
) (
) (
) (
where from
. ) ( ,
sin 2
) (

=

L L L L
X X X X
X
L
= L and is the delay angle measured from the
crest of the capacitor voltage.
The TCSC, with partial conduction of the TCR,
injects harmonic voltages into the line. These
harmonic voltages are caused by the TCR harmonic
currents which circulate through the series
compensating capacitor. The harmonic voltages
corresponding to these currents in a TCSC circuit are
clearly dependent on the impedence ratio of the TCR
reactor to the series capacitor, X
L
/X
C
.
Subsynchronous Characteristics
Series capacitive line compensation can cause
subsynchronous resonance when the series capacitor
resonates with the total circuit inductance of the
transmission line at a subsynchronous frequency, f
e
=
f f
m
. An effective method for the damping of
subsynchronous oscillations lead to NGH Damper.
The NGH Damper is basically a thyristor controlled
discharge resistor operated synchronously with the
power system frequency in the region near the end of
the half cycle on the capacitor voltage.
Refer Fig. 14
The basic principle of the NGH Damper is to force
the voltage of the series capacitor to zero at the end of
each half period if it exceeds the value associated
with the fundamental voltage component of the
synchronous power frequency. The
similarity between the NGH Damper and the
TCSC circuit is, the former being composed of a
thyristor controlled resistor and the latter of a
thyristor controlled reactor both in parallel with the
series compensating capacitor. The TCSC circuit
exhibits the impedance characteristic of an inductor at
subsynchronous frequencies whereas the NGH
Damper with actual energy dissipation establishes
resistive characteristic for the series capacitor. TCSC
is substantially neutral to subsynchronous resonance
and would not aggregate subsynhronous oscillations.
Basic operating control schemes for
GCSC TSSC and TCSC
The function of the operating or internal control of
the variable impedance type compensator is to
provide appropriate gate drive for the thyristor valve
to produce the compensating voltage or impedance
defined by a reference. The internal control operates
the power circuits of the series compensator, enabling
it to function in a self sufficient manner as a variable
reactive impedance. Thus the power circuit of the
series compensator together with the internal control
can be viewed as an impedance amplifier, the output
of which can be varied from the input with a low
power reference signal. The reference to the internal
control is provided by the external or system control
whose function is to operate the controllable reactive
impedance. The external control receives a line
impedance, current, power or angle reference and,
within measured system variables, derives the
operating reference for the internal control.
Structurally the internal controls for the three variable
impedance type compensators (GCSC, TCSC, TSSC)
could be similar. Their function is simply to define
the conduction and / or the blocking intervals of the
valve in relation to the fundamental frequency
component of the line current. This requires the
execution of three basic functions: synchronization to
the line current, turn-on or turn-off delay angle
computation and gate signal generation. Three
possible internal control schemes are discussed: one
for the GCSC and the other two for the TCSC power
circuit arrangements.
An internal control scheme for the GTO controlled
series capacitor scheme is shown.
Refer Fig. 15
It has four basic functions.
The first function is synchronous timing provided by
a face-locked loop circuit that runs in synchronism
with the line current. The second function is the
reactive voltage or impedance to turn-off delay angle
conversion. The third function is the determination of
the instant of valve turn-on when the capacitor
voltage becomes zero. The fourth function is the
generation of suitable turn-off and turn-on pulses for
the GTO valve.
SDP 6
The operation of the GCSC power circuit
and internal control is illustrated by the following
wave forms.
Refer Fig. 16
The main consideration for the structure of
the internal control operating the power circuit of the
TCSC is to ensure immunity to subsynchronous
resonance. It follows two basic control philosophies.
One is to operate the basic phase-locked-loop (PLL)
from the fundamental component of the line-current.
In order to achieve this it is necessary to provide
substantial filtering to remove the super and the
subsynchronous components from the line current
and at the same time maintain correct phase
relationship for proper synchronization. The internal
control scheme of this type is shown below.
Refer Fig. 17
In this arrangement the conventional
technique of converting the demanded TCR current
into the corresponding delay angle, which is
measured from the peak of the fundamental line
current, is used. The reference for the demanded
TCR current is usually provided by regulation loop of
the external control, which compares the actual
capacitive impedance or compensating voltage to the
reference given for the desired system operation.
The second approach also employs a PLL,
synchronize to the line current for the generation of
the basic timing reference. In this method, the actual
zero crossing of the capacitor voltage is estimated
from the prevailing capacitor voltage and line current
by an angle correction circuit. The delay angle is
then determined from the desired angle and the
estimated correction angle so as to make the TCR
conduction symmetrical with respect to the expected
zero crossing as shown below.
Refer Fig. 18
The desired delay angle in this scheme can
be adjusted by a closed loop control phase shift of the
basic time reference provided by the PLL circuit. The
delay angle of the TCR and the compensating
capacitive voltage is controlled over all by a
regulation loop of the external control in order to
meet system operating requirements. The second
approach is theoretically more likely to provide faster
response.
SDP 7
Fig. 1
Two Machine power system with series capacitive compensation (a) Corresponding phasor diagram (b)
Fig. 2
Real power and series capacitor reactive power vs. angle characteristics
SDP 8
Fig. 3
Transmittable power and voltage stability limit of a radial transmission line as function of series capacitive
compensation
Fig. 4
SDP 9
Fig. 5
Equal area criterion to illustrate the transient margin for a simple two-machine system (a) without compensation and
(b) with a series capacitor
Fig. 6
Basic GTO -Controlled Series Capacitor
SDP 10
Fig. 7
Principle of turn-off delay angle control
Fig. 8
Attainable compensating voltage waveform
SDP 11
Fig. 9
Fundamental component of the series capacitor voltage Vs the turn off delay angle
Fig. 10
Wave illustrating method of controlling four series -connected GCSC banks "sequentially "to achieve harmonic
reduction
SDP 12
Fig. 11
Basic Thyristor -Switched Series Capacitor scheme
Fig. 12
Illustration of capacitor offset voltage resulting from the restriction of inserting at zero line current.
Fig. 13
Basic Thyristor- Controlled Series Capacitor scheme
SDP 13
Fig. 14
Basic NGH SSR Damper
Fig. 15
Functional internal control scheme for the GCSC
Fig. 16
Associated waveforms illustrating the basic operating principle
SDP 14
Fig. 17
A functional internal control scheme for the TCSC based on the synchronization
to the fundamental component of the line current
Fig.18
A functional internal control scheme for the TCSC based on the
prediction of the capacitor voltage zero crossings
EPC2 1
Variable Impedance Type Static Shunt Var Compensators
Elizabeth P Cheriyan
Lecturer, EED
NITC
Objectives Of Shunt Compensation
The ultimate objective of applying reactive shunt
compensation in a transmission system is to increase
the transmittable power. This may be required to
improve the steady-state transmission characteristics as
well as the stability of the system. It has long been
recognized that the steady-state transmittable power can
be increased and the voltage profile along the line
controlled by appropriate reactive shunt compensation.
The purpose of this reactive compensation is to
change the natural electrical characteristics of the
transmission line to make it more compatible with the
prevailing load demand. Thus, shunt connected, fixed
or mechanically switched reactors are applied to
minimize line over voltage under light load conditions,
and shunt connected, fixed or mechanically switched
capacitors are applied to maintain voltage levels under
heavy load conditions. Var compensation is thus used
for the following objectives:
Midpoint Voltage Regulation for Line
Segmentation
End of Line Voltage Support to Prevent Voltage
Instability
Improvement of Transient Stability
Power Oscillation Damping
Controllable Var Generation
By definition, capacitors generate and reactors
(inductors) absorb reactive power when connected to an
ac power source. Using appropriate switch control, the
var output can be controlled continuously from
maximum capacitive to maximum inductive output at
a given bus voltage. More recently gate turn-off
thyristors and other power semiconductors with internal
turn-off capability have been used in switching
converter circuits to generate and absorb reactive
power without the use of ac capacitors or reactors.
These perform as ideal synchronous compensators
(condensers), in which the magnitude of the internally
generated ac voltage is varied to control the var output. All
of the different semiconductor power circuits, with their
internal control enabling them to produce var output
proportional to an input reference, are collectively
termed static var generators (SVG). Thus, a static var
compensator (SVC) is a static var generator whose
output is varied so as to maintain or control specific
parameters (e.g., voltage, frequency) of the electric power
system. a static var generator becomes a static var
compensator when it is equipped with special external
(or system) controls which derive the necessary
reference for its input, from the operating
requirements and prevailing variables of the power
system, to execute the desired compensation of the
transmission line.
Modern static var generators are based on high-
power semiconductor switching circuits. These switching
circuits inherently determine some of the important
operating characteristics, such as the applied voltage
versus obtainable reactive output current, harmonic
generation, loss versus var output, and attainable
response time, setting limits for the achievable
performance of the var generator and, independent of
the external controls used, ultimately also that of the
static var compensator. The two types of static var
generator presently used are: (i) those which employ
thyristor-controlled reactors with fixed and/or thyristor-
switched capacitors to realize variable reactive impedance
and (ii) those, which employ a switching, power converter
to realize a controllable synchronous voltage source.
Here we will see the first case ie. Variable Impedance
Type Static Var Generators. The performance and operating
characteristics of the impedance type var generators are
determined by their major thyristor-controlled
constituents: the thyristor-controlled reactor and the
thyristor-switched capacitor. Based on this five such
devices are discussed here.
The Thyristor-Controlled and Thyristor-Switched
Reactor (TCR and TSR)
An elementary single-phase thyristor-controlled
reactor (TCR) is shown in Figure 1(a). It consists of a
fixed (usually air-core) reactor of inductance L, and a
bi-directional thyristor valve (or switch) sw. In a
practical valve many thyristor (typically 10 to 20) are
connected in series to meet the required blocking voltage
levels at a given power rating. A thyristor valve can be
brought into conduction by simultaneous application
of a gate pulse to all thyristors of the same polarity.
The valve will automatically block immediately after
the ac current crosses zero, unless the gate signal is
reapplied.
The current in the reactor can be controlled
from maximum (thyristor valve closed) to zero
(thyristor valve open) by the method of firing delay
angle control. That is, the closure of the thyristor
valve is delayed with respect to the peak of the
applied voltage in each half-cycle, and thus the
duration of the current conduction intervals is
controlled.
EPC2 2
Fig 1 (a) Basic thyristor -controlled reactor
(b) Firing Delay angle Control (c) Operating wave
forms.
This method of current control is illustrated
separately for the positive and negative current half-
cycles in Figure 1(b), where the applied voltage v and
the reactor current i
L
(), at zero delay angle (switch
fully closed) and at an arbitrary delay angle, are
shown. When the gating of the valve is delayed by an
angle /2) (0 with respect to the crest of the
voltage, the current in the reactor can be expressed with
v (t) = V cos t as follows:
Since the valve automatically turns off at the
instant of current zero crossing (which, for a lossless
reactor, is symmetrical on the time axis to the instant of
turn-on with respect to the peak of the current), this
process actually controls the conduction interval (or angle)
of the thyristor valve. That is, the delay angle defines the
prevailing conduction angle : = 2. Thus, as the
delay angle a increases, the correspondingly increasing
offset results in the reduction of the conduction angle a of
the valve, and the consequent reduction of the reactor
current. At the maximum delay of = /2, the offset
also reaches its maximum of V/L, at which both the
conduction angle and the reactor current become zero. It is
evident that the magnitude of the current in the
reactor can be varied continuously by this method of
delay angle control from maximum ( = 0) to zero ( =
/2), as illustrated in Figure 1(c), where the reactor
current i
L
(), together with its fundamental component
I
LF
(), are shown at various delay angles, .
The amplitude I
LF
() of the fundamental
reactorcurrent i
LF
()can be expressed as a function of
angle :
:
where V is the amplitude of the applied ac
voltage, L is the inductance of the thyristor-controlled
reactor, and is the angular frequency of the applied
voltage. The variation of the amplitude I
Lf
(), normalized
to the maximum current I
LFmax
, (I
LFmax
=
V/L), is shown
plotted against delay angle a in Figure 2.
Fig 2
It is clear from Figure 2 that the TCR can
control the fundamental current continuously from zero
(valve open) to a maximum (valve closed) as if it was a
variable reactive admittance. Thus, an effective reactive
admittance, B
L
(), for the TCR can be defined. This
admittance, as a function of angle a, can be written
directly from (2), i.e.,
Evidently, the admittance B
L
() varies with
in the same manner as the fundamental current I
LF
().
The meaning of (3) is that at each delay angle an
effective admittance B
L
() can be denned which
determines the magnitude of the fundamental current,
I
LF
(), in the TCR at a given applied voltage V.
If the TCR switching is restricted to a fixed
delay angle, usually = 0, then it becomes a thyristor-
switched reactor (TSR). The TSR provides a fixed
inductive admittance and thus, when connected to the
ac system, the reactive current in it will be proportional
to the applied voltage. Several TSRs can provide a
reactive admittance controllable in a step-like
manner. If the TSRs are operated at = 0, the
resultant steady-state current will be sinusoidal.
Inspection of Figure 1(b) shows that the conduction angle
control, characterizing the operation of the TCR,
results in a non-sinusoidal current waveform in the
reactor. In other words, the thyristor-controlled
reactor, in addition to the wanted fundamental
current, also generates harmonics.For identical positive
EPC2 3
and negative current half-cycles, only odd harmonics
are generated. The amplitudes of these are a function of
angle , as expressed by the following equation:
---(4)
Where n = 2k + 1, k = 1, 2, 3...
The amplitude variation of the harmonics,
expressed as percent of the maximum fundamental
current, is shown plotted against in Figure 3.
Fig 3
In a three-phase system, three single-phase
thyristor-controlled reactors are used, usually in delta
connection. Under balanced conditions, the triple-n
harmonic currents (3rd, 9th, 15th, etc.) circulate in the
delta connected TCRs and do not enter the power
system. The magnitudes of the other harmonics
generated by the thyristor-controlled reactors can be
reduced by various methods.
The Thyristor-Switched Capacitor (TSC).
Fig 4 (a) Basic thyristor switched capacitor () and
associated waveform
A single-phase thyristor-switched
capacitor (TSC) is shown in Figure 4(a). It
consists of a capacitor, a bidirectional
thyristor valve, and a relatively small surge
current limiting reactor. This reactor is needed
primarily to limit the surge current in the
thyristor valve under abnormal operating
conditions. It may also be used to avoid
resonances with the ac system impedance at
particular frequencies.
Under steady-state conditions, when the thyristor
valve is closed and the TSC branch is connected to a
sinusoidal ac voltage source, v = V sin t the current in
the branch is given by
XL
Xc
LC w
n
t C
n
n
V t i
= =
=
2
1
cos
1
) (
2
2

----(5)
The amplitude of the voltage across the capacitor is
V
n
n
Vc
1
2
2
= ----(6)
The TSC branch can be disconnected ("switched out") at
any current zero by prior removal of the gate drive to the
thyristor valve. At the current zero crossing, the
capacitor voltage is at its peak value, v
C,I=0 =
Vn
2
/(n
2
-1).
The disconnected capacitor stays charged to this voltage
and, consequently, the voltage across the non-conducting
thyristor valve varies between zero and the peak-to-peak
value of the applied ac voltage, as illustrated in Figure 4.
If the voltage across the disconnected capacitor
remained unchanged, the TSC bank could be switched in
again, without any transient, at the appropriate peak of
the applied ac voltage, as illustrated for a positively and
negatively charged capacitor in Figure 5(a) and (b),
respectively. Normally, the capacitor bank is discharged
after disconnection. Thus, the recormection of the capacitor
may have to be executed at some residual capacitor voltage
between zero and Vn
2
/(n
2
1). This can be accomplished
with the minimum possible transient disturbance if the
thyristor valve is turned on at those instants at which the
capacitor residual voltage and the applied ac voltage are
equal, that is, when the voltage across the thyristor valve is
zero.
EPC2 4
Fig . 5
The conditions for "transient-free" switching of a
capacitor are summarized in Figure 6. As seen, two
simple rules cover all possible cases: (1) if the residual
capacitor voltage is lower than the peak ac voltage (V
c
<
V), then the correct instant of switching is when the
instantaneous ac voltage becomes equal to the capacitor
voltage; and (2) if the residual capacitor voltage is equal
to or higher than the peak ac voltage (V
c
>= V), then the
correct switching is at the peak of the ac voltage at
which the thyristor valve voltage is minimum.
Fig. 6
From the above, it follows that the maximum
possible delay in switching in a capacitor bank is one full
cycle of the applied ac voltage, that is, the interval from one
positive (negative) peak to the next positive (negative) peak. It
also follows that firing delay angle control is not applicable to
capacitors; the capacitor switching must take place at that
specific instant in each cycle at which the conditions for
minimum transients are satisfied, that is, when the voltage
across the thyristor valve is zero or minimum. For this reason,
a TSC branch can provide only a step-like change in the
reactive current it draws (maximum or zero). In other words,
the TSC branch represents a single capacitive admittance,
which is either connected to, or disconnected from the ac
system. The current in the TSC branch varies linearly with the
applied voltage according to the admittance of the capacitor.
To approximate continuous current variation, several TSC
branches in parallel (which would increase in a step-like
manner the capacitive admittance) may be employed.
Fixed Capacitor, Thyristor-Controlled Reactor Type Var
Generator
A basic var generator arrangement using a fixed
(permanently connected) capacitor with a thyristor-controlled
reactor (FC-TCR) is shown functionally in Figure7. The
current in the reactor is varied by the previously discussed
method of firing delay angle control. The fixed capacitor,
thyristor-controlled reactor type var generator may be
considered essentially to consist of a variable reactor
(controlled by delay angle a) and a fixed capacitor.
Fig.7
The control of the thyristor-controlled reactor in the
FC-TCR type var generator needs to provide four basic
functions, as shown in Figure 8 .One function is synchronous
timing. This function is usually provided by a phase-locked
loop circuit that runs in synchronism with the ac system
voltage and generates appropriate timing pulses with respect
to the peak of that voltage.
Fig .8 (a) Functional control scheme for the FC-
TCR type static var generator (b) and associated waveform
illustrating the basic operating principles.
The second function is the reactive current (or
admittance) to firing angle conversion.. This can be provided
by a real time circuit implementation of the mathematical
relationship between the amplitude of the fundamental TCR
current I
LF
() and the delay angle given by (2). Several
circuit approaches are possible. One is an analog function
EPC2 5
generator producing in each half-cycle a scaled electrical
signal that represents the I
LF
()versus relationship. [This
approach is illustrated in Figure8 (b)].
Thyristor-Switched Capacitor, Thyristor-Controlled
Reactor Type Var Generator
The thyristor-switched capacitor, thyristor-
controlled reactor (TSC- TCR) type compensator was
developed primarily for dynamic compensation of power
transmission systems with the intention of minimizing
standby losses and providing increased operating flexibility.
A basic single-phase TSC-TCR arrangement is shown in
Figure 9. For a given capacitive output range, it typically
consists of n TSC branches and one TCR. The number of
branches, n, is determined by practical considerations that
include the operating voltage level, maximum var output,
current rating of the thyristor valves, bus work and installation
cost, etc. Of course, the inductive range also can be expanded
to any maximum rating by employing additional TCR
branches.
Fig.9 (a) Basic TSC-TCR type static var generator
(b) var demand versus var output characteristic.
The operation of the basic TSC-TCR var generator
shown in Figure 9 (a) can be described as follows:
The total capacitive output range is divided into n
intervals. In the first interval, the output of the var generator is
controllable in the zero to Q
cmax
/n range, where Q
cmax
is the
total rating provided by all TSC branches. In this interval, one
capacitor bank is switched in (by firing, for example, thyristor
valve SW
1
,) and, simultaneously, the current in the TCR is set
by the appropriate firing delay angle so that the sum of the var
output of the TSC (negative) and that of the TCR (positive)
equals the capacitive output required.
In the second, third,..., and nth intervals, the output
is controllable in the Q
cmax
/n to 2Q
cmax
/n, 2 Q
cmax
/n to 3
Q
cmax
/n,..., and (n - l) Q
cmax
/n to Q
cmax
/n range by switching in
the second, third, ..., and nth capacitor bank and using the
TCR to absorb the surplus capacitive vars. By being able to
switch the capacitor banks in and out within one cycle of the
applied ac voltage, the maximum surplus capacitive var in the
total output range can be restricted to that produced by one
capacitor bank, and thus, theoretically, the TCR should have
the same var rating as the TSC. However, to ensure that the
switching conditions at the endpoints of the intervals are not
indeterminate, the var rating of the TCR has to be somewhat
larger in practice than that of one TSC in order to provide
enough overlap (hysteresis) between the "switching in" and
"switching out" var levels.
The var demand versus var output characteristic
of the TSC-TCR type var generator is shown in Figure 9(b).
.A functional control scheme for the TSC-TCR type var
generator is shown in Figure10. It provides three major
functions:
1. Determines the number of TSC branches needed to be
switched in to approxi-mate the required capacitive output
current (with a positive surplus), and computes the amplitude
of the inductive current needed to cancel the surplus
capacitive current.
2. Controls the switching of the TSC branches in a "transient-
free" manner.
3. Varies the current in the TCR by firing delay angle control.
Fig . 10
The first function is relatively simple. The input
current reference I
QRef
representing the magnitude of the
requested output current is divided by the (scaled) amplitude
Ic of the current that a TSC branch would draw at the given
amplitude V of the ac voltage. The result, rounded to the next
higher integer, gives the number of capacitor banks needed.
The difference in magnitude between the sum of the activated
capacitor currents, I
Cn
, and the reference current, I
QRef
, gives
the amplitude, I
LF
, of the fundamental reactor current required.
The basic logic for the second function (switching of
the TSC branches) is detailed in Figure 11.This follows the
two simple rules for "transient-free" switching summarized in
Figure 6. That is, either switches the capacitor bank when the
voltage across the thyristor valve becomes zero or when the
thyristor valve voltage is at a minimum. The actual firing
pulse generation for the thyristors in the TSC valve is similar
to that used for the TCR with the exception that a continuous
gate drive is usually provided to maintain continuity in
conduction when the current is transferred from one thyristor
string carrying current of one polarity (e.g., positive) to the
other string carrying current of opposite polarity (e.g.,
negative).The third function (TCR firing delay angle control)
is identical to that used in the fixed-capacitor, thyristor-
EPC2 6
Fig. 11
controlled reactor scheme (refer to Figure 8(a)).
The TSC-TCR type var generator , similarly to its
FC-TCR counterpart, can be considered as a controllable
reactive admittance, which, when connected to the ac system,
faithfully follows an arbitrary input reference (reactive
admittance or current) signal. An external observer
monitoring the output current generally would not be able to
detect (when the conditions for transient-free switching are
satisfied) the internal capacitor switching; indeed, would not
be able to tell whether the var generator employs fixed or
thyristor-switched capacitors.
SK9 1
STATIC SYNCHRONOUS COMPENSATORS (STATCOM)
AT DISTRIBUTION AND TRANSMISSION LEVELS
Surersh Kumar.K.S
Asst.Professor,Dept. of Elect.Engg
N.I.T,Calicut
1. Introduction
Shunt Connected Controllers at distribution and transmission levels usually fall under two
catogories - Static Synchronous Generators (SSG) and Static VAr Compensators (SVC).
A Static Synchronous Generator (SSG) is defined by IEEE as a self-commutated switching
power converter supplied from from an appropriate electric energy source and operated to produce a set of
adjustable multiphase voltages , which may be coupled to an ac power system for the purpose of exchanging
independently controllable real and reactive power. When the active energy source (usually battery bank,
Superconducting Magnetic Energy Storage etc) is dispensed with and replaced by a DC Capacitor which can not
absorb or deliver real power except for short durations the SVG becomes a Static Synchronous Compensator
(STATCOM) . STATCOM has no long term energy support in the DC Side and can not exchange real power
with the ac system ; however it can exchange reactive power. Also , in principle, it can exchange harmonic
power too. But when a STATCOM is designed to handle reactive power and harmonic currents together it gets a
new name Shunt Active Power Filter. So a STATCOM handles only fundamental reactive power exchange
with the ac system.
STATCOMs are employed at distribution and transmission levels though for different
purposes. When a STATCOM is employed at the distribution level or at the load end for power factor
improvement and voltage regulation alone it is called DSTATCOM. When it is used to do harmonic filtering in
addition or exclusively it is called Active Power Filter. In the transmission system STATCOMs handle only
fundamental reactive power and provide voltage support to buses. In addition STATCOMs in transmission
system are also used to modulate bus voltages duting transient and dynamic disturbances in order to improve
transient stability margins and to damp dynamic oscillations.
IEEE defines the second kind of Shunt Connected Controller called Static VAr Compensator
(SVC) as a shunt connected static var generator or absorber whose output is adjusted to exchange capacitive or
inductive current so as to maintain or control specific parameters of the electrical power system (typically bus
voltage).Thyristor-switched or thyristor-controlled capacitors/inductors and combinations of such equipment
with fixed capacitors and inductors come under this.This has been covered in an earlier lecture and this lecture
focusses on STACOMs at distribution and transmission levels.
PWM Voltage Source Inverter based Static VAr Compensators (referred to as SVC here
onwards) began to be considered a viable alternative to the existing passive shunt compensators and Thyristor
Controlled Reactor (TCR ) based compensators from mid-eighties onwards. The disadvantages of
capacitor/inductor compensation are well known. TCRs could overcome many of the disadvantages of passive
compensators. However they suffered from two major disadvantages ;namely slow response to a VAr command
and injection of considerable amount of harmonic currents into the power system which had to be cancelled by
special transformers and filtered by heavy passive filters.
It became clear in the early eighties that apart from the mundane job of pumping
lagging/leading VArs into the power system at chosen points ,VAr generators can assist in enhancing stability of
the power system during large signal and small signal disturbances if only they were faster in the time domain.
Also ,they can provide reactive support against a fluctuating load to maintain the bus voltage regulation and to
reduce flicker problems,provide reactive support to control bus voltages against sag and swell conditions and
provide reactive support to correct the voltage unbalance in the source if only they were fast enough. PWM
STATCOMs covered in this lecture are capable of delivering lagging/leading VArs to a load or to a bus in the
power system in a rapidly controlled manner.
High Power STATCOMs of this type essentially consist of a three phase PWM Inverter using
GTOs,Thyristors or IGBTs, a D.C. side capacitor which provides the D.C. voltage required by the inverter,filter
components to filter out the high frequency components of inverter output voltage,a link inductor which links the
inverter output to the a.c supply side,interface magnetics (if required) and the related control blocks. The Inverter
generates a three-phase voltage, which is synchronized with the a.c supply ,from the D.C. side capacitor and the
link inductance links up this voltage to the a.c source. The current drawn by the Inverter from the a.c supply is
controlled to be mainly reactive(leading or lagging as per requirement) with a small active component needed to
supply the losses in the Inverter and Link Inductor (and in the magnetics,if any).The D.C. side capacitor voltage
is maintained constant( or allowed to vary with a definite relationship maintained between its value and the
reactive power to be delivered by the Inverter) by controlling this small active current component. The currents
are controlled indirectly by controlling the phase angle of Inverter output Voltage with respect to the a.c side
source voltage in the "Synchronous Link Based Control Scheme" whereas they are controlled directly by current
SK9 2
feedback in the case of "Current Controlled Scheme".In the latter case the Inverter will be a Current Regulated
one ,i.e. its switches are controlled in such a way that the Inverter delivers a commanded current at its output
rather than a commanded voltage (the voltage required to see that the commanded current flows out of Inverter
will automatically be synthesized by the Inverter).Current Control Scheme results in a very fast STATCOM
which can adjust its reactive output within tens of microseconds of a sudden change in the reactive demand.
However,current control schemes will require high frequency switching in the Inverter
switching frequencies which are so high that low frequency devices like thyristors and GTOs are ruled out.
Hence they have to be based on MOSFETS or IGBTS.The latter seems to be the current choice with its high
voltage and high current rating availability with low conduction losses. However, at present, they are limited to
applications in the low voltage systems (400V,1.1kV etc) and at distribution power level rather than transmission
and sub-transmission power levels. This is because of the limited maximum voltage/current ratings available in a
single device/module. Thus DSTATCOMs use IGBTs and they usually employ the standard two-level 3 limb ,
three phase inverter with voltage and current levels adjusted by ratio of transformation in the coupling
transformer At the most they may use series-parallel device structures to increase voltage and current rating of
the switches.However multi-pulse or multi-level or cascaded inverters are rarely required in Distribution
STATCOMs. High frequency switching is possible due to the device being IGBT and Current Regulated Mode
of Operation is employed to force the inverter to deliver set values of currents into the ac system.
When it comes to transmission/sub-transmission level GTOs are the preferred devices and they
can take switching frequencies below 1-3 kHz. Hence, at these levels, STATCOMs are made with the
Synchronous Link Control Scheme which gates the Inverter to deliver a voltage output (rather than a regulated
current).This kind of Inverter operation makes it possible to implement one of the many specialized PWM
switching schemes aimed at minimizing the switching frequency while keeping acceptable level of harmonic
content in the Inverter output.The device used i.e GTO dictates a low switching frequency.But the inverter
should not inject harmonics into the ac system. And the voltages and currents to be handled are large.These three
factors together make two-level three-limb three-phase inverter under SPWM impossible in STATCOM. The
solution usually lies in Multi-Pulse Inverters , Muti-Level Inverters or Multi-Level Cascaded Inverters. These
types are better controlled as voltage sources than current sources.Thus Synchronous Link Phase Angle Control
Scheme or Predictive Indirect Current Control are the control choices.
Summing up, STATCOMs are fast responding generators of reactive power with leading
VAr/lagging VAr capability which can provide steady state reactive compensation as well as dynamic
compensation during power system transients,sags, swells,flicker etc. Thereby they can contribute significantly
to enhancement of Power Quality. High Power STATCOMs in the transmission system are usually made with
devices of low switching frequency capability (GTOs) and hence need special PWM patterns to optimize
switching behaviour. Such STATCOMs use Synchronous Link principle in the control blocks. DSTATCOMs
use high speed switching levels, simple inverter structures and high frequency PWM or Hysteresis Control to
function as Current Regulated Sources whereas transmission system STATCOMs use multi-pulse or multi-level
inverters using GTOs and function as controlled voltage sources with controllable phase and use Synchronous
Link Control principle.
2. The Basic Principle of Synchronous Link Based STATCOM
In a synchronous link where two a.c sources of same frequency are connected together by
means of a link inductor, active power flows from the leading bus to the lagging one and reactive power flows
from the source with higher voltage magnitude to the one with lower voltage magnitude. The active power flow
is almost entirely decided by the lead angle whereas the reactive flow is almost entirely decided by the difference
in voltage magnitudes provided the inductor is loss free ,the lead angle is small (less than 15 degrees) and the
voltage magnitude difference is small(less than 0.1 p.u) . The situation changes slightly if the link contains
resistance. If two sources V1 with a phase angle of and V2 with a phase angle of 0 are connected together by
means of an inductive link of impedance (R+jX) ohms and if the active power flowing into the source V2 is
constrained to be zero (because this represents the STATCOM situation) the power delivered by the source V1
(which will not be zero and it will be equal to the power absorbed by the resistance in the link ) and the reactive
power delivered to the link by the source V2 will be given by the following relations (after a little algebra along
with the assumptions that is small and R << X ).
Active Power Delivered by V1,P = (V1
2
/R)
2
Watts ---------- (1)
Reactive Power Delivered by V2,Q = (V1V2/R) VArs --------- (2)
Also , Q = V2(V2-V1)/X VArs
where the powers are for a phase and voltages have phase values. These relations can be used upto about 20
degrees for .Active Power drawn from the source V1 is independent of sign of phase angle (only V1 can
supply losses in R because of the zero active power constraint at V2) whereas the reactive power delivered by
V2 is directly proportional to the phase angle. In the STATCOM context, the source V1 is the power system
voltage at the bus where the STATCOM is connected,V2 is the a.c voltage generated by the Inverter in the
STATCOM, R is the total loss resistance in the link comprising the winding losses in the link inductor,interface
SK9 3
magnetics and the inverter switches and snubbers etc. It is also possible to derive the following useful
relationships in this context.
The Phase Angle of V1 w.r.t V2 , = (R/X) (V2-V1)/V1 --------- (3)
This shows that the relative phase angle is linearly related to the voltage magnitude difference (for small
differences) and hence the reactive power delivered by V2 is proportional to the voltage magnitude difference.
Thus Q is proportional to or equivalently to (V2-V1). Both points of view will be useful later to understand the
two different ways in which this STATCOM can be controlled.
In the STATCOM, the required a.c voltage source V2 is generated by inverting the D.C. voltage, which is
assumed available across the capacitor in the D.C. side. But if the active power which goes into the inverter from
the mains is kept zero, the initially charged capacitor will soon discharge down to zero due to active power
losses in the Inverter which the D.C. side will have to supply. The D.C. side voltage will remain constant (or at
least controlled) if the power drawn from mains is just enough to supply all the losses which take place
everywhere due to the flow of demanded reactive current. The following relation may be derived for the D.C.
side ca voltage under this condition.
The D.C. side voltage ,Vd = (V1/k)(1-(X/R) ) volts --------- (4)
Where V1 is the rms phase voltage of a.c mains,k is a constant, which also absorbs the modulation index of
PWM process in the Inverter.
From the relations cited above two control strategies emerge for the control of a Synchronous
Link Based STATCOM.They are described below. The reference signal to the controller is assumed to be the
desired reactive power flow from the STATCOM.
1. Keep the D.C. side voltage constant by controlling the value of .And control the reactive power from
the inverter by directly changing (V2-V1) by controlling the modulation depth (i.e. the multiplication
factor that comes between the D.C. voltage and the amplitude of a.c output in the Inverter).It should be
obvious from the equations 1 to 4 that this strategy will result in an interacting control system.
2. Let the D.C. side voltage vary according to equation(4) and use control to control the reactive power
delivered by the STATCOM.There is only one control variable and that is .The modulation index of
the Inverter is kept constant and D.C. voltage is allowed to vary. The D.C. voltage increases when the
STATCOM delivers increasing lagging VAr and it decreases when STATCOM delivers leading
VArs.Here the control of VAr is indirect. When the reactive power reference changes, it causes a
change in value. The residual voltage across link inductor changes resulting in more active power
flow into/out of the Inverter.Increased active power flow into/out of the Inverter results in
increase/decrease in the energy storage in the D.C. side capacitor resulting in an increase/decrease in the
D.C. side voltage. With a fixed modulation index ,the increase/decrease in the D.C. voltage is straight
away passed on to Inverter output voltage V2.Change in the Inverter output voltage results in the
desired reactive power change. Obviously the response time is decided by the link inductor and D.C.
side capacitor and will be relatively slow.
In the constant D.C. voltage scheme, the D.C. voltage dynamics is going to be slow since the
same mechanism described above will be responsible for maintaining the D.C. voltage. However,the
reactive power flow is controlled by controlling V2 directly by changing the modulation index of the
Inverter and this dynamics can be fast. The components which decide the dynamics will be the loss
resistance,link inductor value,Inverter filter components and the feed back system parameters.
3. The Inverter and Programmed Harmonic Elimination PWM
A Three-Phase Inverter
using IGBTs is shown in Fig.1.In certain
cases the neutral wire may not be present and
the D.C. side capacitor may be a single one.
However, for the purpose of explanation, a
neutral point may always be imagined. With
this the three phase Inverter becomes three
separate single-phase half bridge Inverters
sharing the same D.C. source. Bipolar and
unipolar PWM schemes using a triangular
carrier frequency was discussed in another
lecture (page 70-72) in the context of single-
phase full bridge converters. Much of the
same is applicable here too except that only
bipolar PWM is possible for a half bridge
topology since no combination of switching
patterns for the upper and lower switches of a
half bridge can apply zero potential at the load point. Bipolar PWM using a triangular carrier and sinusoidal
SK9 4
modulating voltage can be applied here with the modulating waves of the three half bridge sections forming a
balanced three phase signal set.
However,the switching frequency required in Sinusoidal Pulse Width Modulation using
triangular Carrier to achieve reduction in output harmonics is usually excessive as far as high power devices like
GTOs are concerned. Hence, programmed harmonic elimination techniques is preferred at high power levels.
Like in any other PWM scheme, +Vd/2 and Vd/2 pulses are applied across the load in the
programmed harmonic elimination technique also. But in this scheme the position and duration of these pulses
are pre-calculated off-line in such a way that (i) certain chosen harmonics are completely eliminated completely
in the output and (ii) the fundamental component of the output has a desired value. By a general formulation of
Fourier series coefficients of a pulse wave it is possible to derive a set of equations involving angle positions of
the positive and negative pulses to satisfy the conditions on elimination of chosen harmonics and on the
fundamental amplitude. The maximum possible amplitude will be available when the output is a full square
wave(i.e. no harmonics are eliminated) and will be 1.275(Vd/2).But when harmonics are to be eliminated it is
not possible to reach this value of fundamental voltage. For every selection of harmonics to be eliminated there
exists a maximum value the fundamental component can have and it will be less than 1.275(Vd/2).For example
,it is 1.188(Vd/2) for a scheme where fifth and seventh harmonics are eliminated.Fig.2 shows the normalized
pulse pattern which appears at A phase output when fifth and seventh harmonics are sought to be eliminated. The
switching frequency of each
will be 350Hz with this
pattern.
The equations which
yield the angular positions for
a chosen elimination format
and fundamental amplitude is
transcendental algebraic in
nature and require numerical
techniques for solution.
Moreover for the same
harmonic elimination format
the switching angles will vary
with the fundamental
amplitude desired;and the
variation can be highly
nonlinear. See Fig.3.The
nature of equations make an
on-line implementation of
pattern generation very
difficult. In addition, the
nonlinear angular position
variation with changes in the desired fundamental component makes it difficult to generate the PWM pattern in
real time by analog/digital logic. However, it is possible to implement this scheme using micro
processors/controllers and EPROMs.
A sinusoidal reference wave at frequency equal to the desired output frequency of the Inverter
is frequency multiplied in a PLL system. The square wave from VCO of PLL is used to clock a UP/DOWN
counter. The counter output is used as address bytes of an EPROM which has the required switching pattern at
that instant written in it(by off-line
computation and EPROM programming).The
EPROM has patterns
stored for various quantised values of
fundamental amplitude. The control signal
which sets the fundamental amplitude is A/D
converted and the code is used to decide the
range of EPROM memory locations to be read
out by the counter output. Once in a
fundamental cycle the counter is forcibly reset
(at zero crossing of reference sine wave
usually), to avoid subharmonic components in
the output due to jitter in the PLL and other
similar errors everywhere. Note that it is
possible to shift the phase of the fundamental
component of Inverter output with respect to
reference sine by shifting the counter reset
point with respect to the zero crossing point of
SK9 5
reference sine. A three-phase pattern can be similarly generated. However, large memory may be required for
fine control of output voltage fundamental value.
4. Phase Angle Control of STATCOM
Fig.4. shows a DSTATCOM configured to keep the reactive power delivered by the Source at
a zero value as long as the reactive demand from the load is within the DSTATCOM rating. Thus, the p.f of the
Source will be maintained at unity under steady state conditions by the DSTATCOM.The control of
DSTATCOM reactive power is by pure control and the D.C. bus voltage is allowed to vary. This scheme,
though somewhat slow, results in simplified control hardware.
The source side voltages and currents are sensed and the reactive power is calculated by
analog/pulse circuitry. This calculated value is compared with the desired value (usually zero) and the error is
processed in a proportional-integral controller. The error output decides the phase shift needed in the inverter
output in order to develop the required D.C. bus voltage such that the inverter output voltage magnitude will be
sufficient to make the Inverter deliver the VArs required by the load. The Inverter is gated by a fixed PWM
pattern optimised for eliminating chosen harmonics (usually fifth, seventh, eleventh etc; triplen harmonics need
not be eliminated since they do not result in current flows in a three wire system). The needed PWM pattern is
stored in an EPROM and is read out using the scheme described in the last section. This is by far the most
popular scheme used in high power STATCOMs.
The open loop dynamics of the STATCOM features a third order transfer function (for small
signals) between and Qc, the reactive power delivered by the Inverter.The transfer function has a pair of
complex zeros, a real pole and a pair complex poles. Various research workers have derived the following
transfer function for the STATCOM.
Q
c
(s)/(s) = N(s)/D(s) where N(s)=(Vs
2
/L){s
2
+(R/L)s+(k
2
/2LC)} and
D(s)=s
3
+(2R/L)s
2
+{(R/L)
2
+(k
2
/2LC)+
2
}s+(k
2
R/2L
2
C) where all the parameters have the already defined
meaning and is the system frequency.The step response usually features a rise time ranging from 3-7 cycles of
a.c.It is possible to employ a PI controller with suitable gain characteristics to compensate the closed loop system
and to obtain a step response rise/fall time between 1 to 3 a.c cycles.
It is not necessary to sense the reactive power in all three phases of the source in the case of
balanced operation.However if the source or load is unbalanced all the three phases will have to be monitored to
calculate the total source reactive power.But the STATCOM will be configured to deliver this total demand by
dividing it equally among three phases to ensure current balance in STATCOM.If exact cancellation of reactive
power in all the three phases is required under unbalanced conditions a three phase STATCOM made of three
single phase units with entirely independent control will yield better results (i.e easier control ; it is possible to
do the job using a three phase inverter too).
5. STATCOM with Constant D.C Bus Voltage
The above scheme suffers from the disadvantage of variable D.C. voltage across the Inverter
input and sluggish response to changes in reactive demand.The solution is to control the D.C. voltage by phase
SK9 6
angle control and to control the reactive power flow by control of modulation index control.Two separate control
loops (which interact with each other ) are involved here.But by separating the time scale of dynamics it is
possible to decouple the interaction to a satisfactory degree.
Control of modulation index i.e. control of fundamental component of inverter output voltage
with a constant value of D.C. voltage can not be easily achieved without complex hardware with a large memory
requirement as explained before.Hence this scheme of control is better suited for STATCOMs with Sinusoidal
Pulse Width Modulation (SPWM) in the Inverter.While it is true that programmed harmonic elimination is better
than SPWM in terms of switching frequency minimisation for a given level of harmonic reduction,SPWM with a
synchronised triangle wave carrier at around 2 to 3kHz can be a viable alternative; especially when the
fundamental amplitude is to be controlled.This is true even for GTO based inverters using state of the art GTOs.
Only bipolar PWM is possible for a three phase Inverter.Hence SPWM in bipolar format using
a triangular carrier in the frequency range of 1 to 3 kHz is assumed in this section.The carrier wave has to be
synchronised to the modulating signal (i.e. sine wave) to eliminate subharmonic components in the output.The
process of SPWM produces a fundamental component equal to (Vd/2)(V
sm
/V
t
) at the inverter output terminals
where V
sm
is the amplitude of the modulating signal and V
t
is the amplitude of the triangle wave.The harmonics
are sufficiently shifted in frequency by the PWM process to allow easy filtering.Now the inverter output voltage
can be controlled by controlling the amplitude of modulating signal .
Fig.5 shows the block diagram of the STATCOM with D.C. voltage control.The D.C. voltage
is sensed,compared with reference level and the error is processed in a PI controller.The output of the PI
controller is converted into a time marker pulse which is time shifted from zero crossing of phase voltage by an
amount proportional to the output voltage of PI controller.This time marker pulse will reset the counter in the
phase locked sine wave generator and thereby effect phase shift in the Inverter modulating signal .The VAr in
the line is calculated in the VAr calculator and this forms the actuating voltage on an analog multiplier which
scales up or down the fixed amplitude sine wave generated by PLL-Counter-EPROM-DAC system.The phase
shifted and amplitude adjusted sine wave becomes the modulating signal for a SPWM block and the Inverter
reproduces the signal at its output after amplification by Vd/2.
The VAr control loop here is essentially of first order due to link inductor and system losses. A
high gain PI controller will accelerate the step response of this loop to a level where VAr commands are
followed in less than a cycle. The slower voltage control loop will carry out the slow adjustment of phase angle
needed to maintain the D.C. voltage constant. A combination of large valued capacitor, low valued inductor, fast
VAr control loop and slow D.C. voltage control loop will ensure rapid VAr control with much reduced current
amplitude oscillations in the link inductor. This scheme can very effectively provide reactive support during the
power system transient conditions and can compensate a highly fluctuating load like an arc furnace.
SK9 7
6. The Reactive Demand Calculator
The speed of response of the STATCOM is decided by two time delays the rise time of
STATCOM when a step change is applied to its reactive power command input and the rise time behavior of the
reactive demand calculator when the actual reactive flow in the source line changes suddenly. Hence, the
Reactive Power Calculator has to extract the reactive component of the source current rapidly.The reactive
command was shown as a VAr flow till now. However, the reactive component of the line current is enough for
control purposes. A simple method to extract the reactive content in the current is explained here. Let the source
current in one phase be i(t) = I
0
+I
1
Sin (t+
1
) +I
5
Sin (5t+
5
) + I
7
Sin (7t+
7
)+....... This covers the
possibility of a non-linear load which draws harmonic currents and D.C. offsets too. Form the product of this
current with unit amplitude cosine wave which is at 90 degrees in phase with that phase voltage. This product
signal is called p(t).
P(t) = I
0
Cost+I
1
Cost

Sin (t+
1
) +I
5
Cost Sin (5t+
5
) + I
7
Cost Sin (7t+
7
)+......
The integral of this product over integral number of fundamental periods will have content only from
(I
1
Sin
1
)/2 since all other products have zero average over fundamental period.Thus, the strategy is to form this
product,integrate it for one period,sample the integrator output and hold the sample,reset the integrator after
sampling and allow it integrate the product for the next period.The sampled integrator output will be a quantity
proportional to the reactive component of the current.This output can be used as the reactive power signal in the
STATCOM control block.The sampling and integrator reset are performed at zero crossing of sine wave and the
product current is taken with the cosine wave.The cosine wave has to be pure,without harmonics.The required
sinusoidal templates are obtained by PLL-Counter-EPROM-DAC technique already described.
7. STATCOMs at Transmission Level
The STATCOMs discussed until now were configured for compensating the reactive power
taken by a load and for maintaining the utility power factor at unity. Even in this configuration STATCOM
results in PQ enhancement since it can respond rapidly to a rapidly varying load like arc furnace; large hammer
mills, stone crushers, ball mills etc; large motors with frequent starts/stops etc. These are potentially troublesome
loads from Power Quality point of view. They can cause flicker and sag. Fast responding STATCOM renders
support to bus voltage against these loads.
However, at transmission/subtransmission level the issue of providing voltage support at buses
is addressed more directly and STATCOMs are connected to deliver/take as much reactive power to/from the
bus as required to maintain the bus voltage within pre-decided limits. STATCOM does not try to maintain the
power factor at the bus at unity anymore. Rather, it tries to maintain the bus voltage by injecting leading or
lagging VArs into the system. In this case there will be an outer control loop which senses the bus voltage,
compares it with a set value and processes the error in a PI Controller and sets the reactive reference for the inner
control loop. The effectiveness of a given STATCOM with a specified rating in providing voltage support at a
particular bus will depend on the short circuit capacity at that bus. Low value of S.C. capacity implies that the
Thevenin's impedance behind the bus voltage is large. In addition, the STATCOM there will be more effective
than similarly rated STATCOM at another bus with a higher short circuit capacity. But then, a bus with a higher
value of short circuit capacity will have better immunity against sags/flickers/swells due to problems elsewhere
and hence probably does not need a STATCOM at all.
In many transmission applications the STATCOM is not used as a perfect voltage regulator ,
but rather the terminal voltage is allowed to vary in proportion with the compensating current.The useful linear
range of the equipment is extended if this kind of droop regulation is used.Moreover droop regulation allows
automatic load sharing between various static compensators.
The control system block diagram is given in Figure 6. The terminal voltage is sensed and a
PLL system is locked on to it. This is needed for controlling the inverter.The amplitude information is extracted
from the sensed voltage and it is compared with the set reference value. The error decided the magnitude and
polarity of the reactive current to be drawn by the STATCOM inverter from the ac system.A PI controller is used
to speed up the response and reduce steady state error.The inner current loop on the sensed reactive current
magnitude is used to pull down (in the case of capacitive compensation) the voltage reference value thereby
effecting a droop characteristiv in the voltage regulation. X represents the system impedance at the point of
connection.Auxiliary inputs refer to the additional inputs into the control loop to make the STATCOM
contribute to improvement of transient and dynamic stability.
The loop gain of the control system is a strong function of system impedance X. Increasing the
droop gain value reduces loop gain and increasing system impedance at the point of connection increases the
loop gain.Hence the maximum system imedance condition must be identified and control system compensation
must be done for that condition.
SK9 8
SK10 1
STATIC SYNCHRONOUS SERIES COMPENSATOR (SSSC) AND ITS CONTROL
Suresh Kumar K.S
1. Introduction
A Static Synchronous Series Compensator (SSSC) is a Power Electronic Switched Converter operating
as a Voltage Source Inverter connected in series with a transmission line through interfacing transformers and
controlled in such a way as to inject capacitive or inductive voltage drop in series with the line with the effective
value of reactance settable and controllable. Typically SSSC can inject voltages in quadrature and can not
handle real power exchange with the line for extended periods.
SSSC can be controlled to maintain a preset value of capacitive (or inductive) reactance in series with
the line thereby effecting the traditional series capacitor compensation (but the capacitive reactance value is
controllable unlike in the fixed capacitor systems). It is also possible to control the SSSC such that it always
injects a preset value of voltage in quadrature with current , but independent of current.In both modes of control
, it is possible to put an outer control loop which can be designed to maintain the real power flow in the line at a
preset value against bus voltage variations or bus angle variations.Similarly it is also possible to employ an outer
loop to maintain the bus voltage to the right of SSSC constant.Also , by suitably modulating the reference
setting (whatever that be) according to some relevant information it is possible to make use of SSSC to
introduce damping in the system to improve dynamic stability and subsynchronous behaviour.Finally it is also
possible to modulate the reference setting in such a way that the transient stability margins can be improved
when the system undergoes large disturbances.
There has to be a DC Source for a converter to produce ac this DC Source in a SSSC is a large DC
Capacitor. The Capacitor maintains a large enough voltage for the inverter to generate a 3 phase system of
voltages as per the compensation requirements.The inverter ,as stated already, injects only quadrature voltage
into the line.This means that the real power flow into or out of inverter is zero.Well, not exactly. When the
entire line current flows through the interface transformer and inverter passive and active components there will
be losses everywhere. If inverter has no real power coming in from line , then the DC Side Capacitor has to
deliver these losses and soon it will discharge down to a level at which the SSSC has to trip. Hence there has to
be a control loop on the DC Side voltage , maintaining it constant by drawing or delivering active power
suitably.Of course, since this active power essentially takes care of losses in the system it can be expected to be
small.Thus the voltage injected by SSSC has to have a small component which is in phase with the line current.
The application is a transmission level application (otherwise , if it is distribution level, it will be called
active series filter ; at transmission levels only fundamental reactive compensation is usually attempted) and
assumption of balanced system voltages and negligible harmonics will be permitted. And it is unlikely that
SSSC will be expected to work when the system voltage (one or more phases) go down to such low levels where
PLLs will lose lock.In fact under severe fault conditions SSSCs are bypassed by fast acting static bypass
switches. Thus we have balanced, relatively distortion free voltage of sufficient amplitude at the bus to the left
of SSSC installation and it is possible to loack a PLL system with sufficient ease at this point.Moreover with a
balanced , distortion free system the best way to control a three phase system is to jump over to Synchronously
Revolving Reference Frame or the so called d-q plane. This lectures deals with such a control strategy.
The voltage level is high and even with interface transformer, the voltage levels and current levels will
usually be beyond the capability of IGBTs (though they are catching up rapidly) and GTOs and other similar
devices rule. And when GTOs rule, switching frequency can only be low and that brings in multi-pulse or
multi-level or cascade inverters. Typically multi-pulse inverter is used in one installation a 48 Pulse three
phase inverter comprising 8 three phase inverters of 6 pulse two-level type. The construction of 48 pulse
waveform was done in transformer magnetics in this case.
2. Control Strategy
The d-q domain control strategy for an SSSC is explained with respect to the following system.
The d-q domain equations of the system are given below.
SK10 2
(V
1d
V
2d
) = Ri
d
+ X
C
I
q
- X i
q
(V
1q
V
2q
) = Ri
q
- X
C
Id

- X i
d
Now , the line currents are sensed and transformed into d-q plane by using unit sine and cosine
template waveforms.These template waveforms are generated by a digital PLL system locking on to the system
voltage at the left side bus. The purpose of control is to maintain X
C
ohms of compensating reactance in the line.
For this purpose the required d and q component voltages can be calculated i.e X
C
I
q
and - X
C
Id can be
calculated from the set value for X
C
and calculated values of I
d
and I
q
.These values are reconverted into three
phase quantities and given as reference signal to PWM Gating Syatem of Inverter. However, this is not enough
because a small inphase voltage injection will be needed to meet the inverter losses. This is done with the help
of a PI Controller on DC Side Voltage.When the DC Side Voltage goes down the PI Controller output increases
and this error output is used to inject kI
d
volts in the d-axis and kI
q
volts in the q-axis where k is the error output.
Essentially we are putting a resistance (fictitious) in series with X
C
of value k. The power which goes into that
resistance is the power that meets the losses in the SSSC.
A Simulink simulation diagram to illustrate these concepts is given in the next page. The values for V1
and V2 were 320 Volt peak Phase-Neutral. The line reactance was 3 ohms and line resistance was set at zero for
simulation runs.
The d-q method will calculate the current components instantaneously and there is no need for a filter
in d-q domain on sensed currents if currents are balanced and distortion free. However in the presence of such
corruptions d-q components will have high frequency contents like 100Hz and above and these should not be
sent into the inverter reference.Hence a 25Hz low pass filter is used in the d-q lines in the current sensing part.
The Simulink Diagram essentially solves the following two equations for I
d
and I
q
.
(V
1d
V
2d
) = Ri
d
+ X
C
I
q
+ (vc) i
d
- X i
q
(V
1q
V
2q
) = Ri
q
- X
C
Id

+ (vc) i
q
- X i
d
where (vc) is the output of PI Controller in the DC Side Voltage Controller Loop. The ac side of inverter is
modelled as an ideal voltage source which generates the commanded voltages without any distortion and delay
and with zero output impedance.The DC side is modelled by using power balance to calculate the capacitor
voltage. The PLL system is not modelled.In fact exact phase lock is not so important.The PLL output has to be
in synchronism with the system voltage, but it need not have same phase that of mains.
Typical simulation results for sudden switching on of X
C
value, sudden change of phase angle between
the buses, etc are given. The results given in figure 4 reveal the DC Voltage regulation dynamics.This dynamics
comes into picture whenever the phase relation between the injected voltage and line current undergo sudden
changes as in the case when the angle of one or both bus voltages change instantaneously (due to a fault in the
system elsewhere etc.).This dynamics is dependent on the loading level in the line at the instant of
disturbance.This is so since the loop gain of DC Voltage control loop is proportional to the line current.
SK10 3
SK10 4
SK10 5
IMPROVEMENT OF POWER SYSTEM STABILITY
USING STATIC VAR COMPENSATORS
Dr. R. Sreeram Kumar
National Institute of Technology, Calicut
1. Introduction
This notes gives an overview of the
application of static VAR compensators (SVCs) for
the improvement of power system stability. The term
stability means essentially that the synchronous
machines in the system tend to run in synchronism.
Stability considerations usually determine the
transmittable power in a given system. SVCs can be
applied very effectively to improve the transient and
dynamic stability of power systems.
2. Transient Stability
The term transient stability means that a power
system can recover normal operation following a
major disturbance (fault, loss of generation, etc.).
The transient stability improvement attainable by a
static VAR compensator is due to the fact that the
power transfer capability of a transmission system
can be increased by controlled reactive shunt
compensation that maintains the voltage at specific
points of the transmission line. Considering the
simple model of a generator being linked to an
infinite bus by a reactive line (Fig. 1a), the
transmitted power P is given by the following well
known equation:
sin
2
X
V
P = (1)
where V is the magnitude of the generator and
infinite bus voltage, X is the total interconnective
reactance, and is the power angle between the
sending end machine internal voltage and the infinite
bus voltage. The relationship between the power P
and angle is shown in Fig. 1b.
The theoretical maximum transmittable power
defining the steady-state stability limit is obtained at
2 / = :
X
V
P
2
max
= (2)
If an ideal synchronous condenser is connected at the
midpoint of the transmission line (as shown in Fig.
2a) and its excitation is controlled to keep the
magnitude of the voltage at that point the same as that
at the sending and receiving ends, then equation (1)
can be applied for each half of the line, that is,
2
sin
2
2
X
V
P = (3)
The power transmission relationship expressed by
equation (3) is illustrated in Fig. 2b where power P is
plotted against angle . Evidently, the maximum
transmittable power obtained at / 2 is 2 V
2
/X twice
the steady state limit of the uncompensated case in
general, the transmission reactance X can be divide
into n equal sections with a perfect synchronous
condenser at the joining points of he sections. In this
case, the power transmission is characterized
theoretically by the following equation:
n
sin
2
n
X
V
P = (4)
This equation indicates that the maximum
transmittable power as nV
2
/X, that is, n times the
steady-state power limit of the uncompensated case.
In the line compensation by sectioning the power is
sent from the generator to the first synchronous
condenser via the first line section X/n, the first
synchronous condenser sends the same power to the
second one via the second line section, and so on,
until the power gets from the (n-1) synchronous
condenser to the receiving end bus via the nth line
section. The total real power sent from the sending
end is consumed at the receiving end. The
synchronous condensers have no real power
exchange; they regulate the magnitude of the voltage
at each section of transmission line by providing the
necessary reactive power.
The improvement in transient stability
achievable with controlled shunt compensation is
simply due to the significant increase in the steady-
state stability limit obtained. A greatly simplified
example is used here to illustrate the basic concepts
and help to establish the control requirements for the
static VAR compensator. Consider the simple power
system models shown in Figures 1a and 2a. Suppose
that in both the compensated and uncompensated
systems the transmitted power is the same. Assume
that both systems are subjected to the same fault for
the same period of time. The dynamic behaviour of
Srk-A1
the two systems is illustrated in Fig 3a and
3b. Prior to the fault, each system transmits power
P
M
at angles and
c1
, respectively (subscript c stands
for compensated). During the fault, the transmitted
electric power to the generators remains constant
(P
M
). therefore, the generators accelerate from the
steady-state angles
1
and
c1
to angles
2
and
c2
, at
which the fault clears. The accelerating energies in
the two systems are represented by areas A
1
and A
c1
.
After fault clearing, the transmitted electric power
exceeds the mechanical input power and the
machines decelerate, but their angle further increases
due to the kinetic energies accumulated in the rotors.
The maximum rotor angles
3
and
c3
are reached
when the decelerating energies defined by areas A
2
and A
c2
are equal to the accelerating energies defined
by areas A
1
and A
c1
, respectively.
If for a given power level and post-fault
system the maximum rotor angle (
3
or
c3
) reached is
below the critical rotor angle (
crit
or
ccrit
), the system
will remain transiently stable. The critical rotor angle
represents the rotor angular swing and the critical
angle determines the margin of transient stability, that
is, the unused and still available decelerating
energy represented by areas A
margin
and A
cmargin
in Fig.
3a and 3b.
Comparison of Fig. 3a and 3b clearly shows the
substantial increase in transient stability margin the
(ideal) shunt compensation can provide.
Alternatively, if the uncompensated system has
sufficient transient stability margin, shunt
compensation can increase significantly the
transmittable power.
In the above stability considerations, the
shunt compensator is assumed to be an ideal
synchronous condenser. The adjective ideal here
would mean that the amplitude of the midpoint
voltage remains constant all the time, except possible
during the fault, and its phase angle would follow the
generator (rotor) angle swings so that the
synchronous condenser would not be involved in real
power exchange. The basic characteristics of the
ideal synchronous condenser indicate that a static
VAR compensator regulating the midpoint terminal
voltage could fulfill the same function provided that
(i) it can stay in synchronism with the terminal
voltage in face of major disturbances and (ii) it is able
to regulate the terminal voltage.
The requirement of staying in synchronism
with the ac terminal voltage is basic for all solid-state
static VAR generators, and it can be met even under
the most severe disturbances by using modern phase-
locked loop techniques. The requirement to regulate
the terminal voltage effectively requires fast response
for the voltage control loop and, of course, sufficient
VAR rating for the compensator. Presently used
static VAR compensators have a worst-case response
time of 30 to 50 ms (2 to 3 cycles) for regulating the
terminal voltage in a closed-loop manner.
The ideal synchronous condenser in the
previous elementary stability consideration is
assumed to act essentially as a synchronized voltage
source providing reactive power as needed without
limitation. In the simple midpoint compensating
scheme shown in Fig. 2a, the reactive power demand
at constant midpoint voltage increases rapidly with
increasing power transmission, reaching a maximum
value equal to 4 P
max
at the maximum steady-state
power transmission limit of 2 P
max
(P
max
is the
maximum transmittable power of the uncompensated
system). The relationships between real power P,
midpoint reactive power Q, and angle is illustrated
in Fig. 4. In most practical applications, for
economic reasons, the rating of the static
compensator is lower than that required for maximum
attainable power transfer. For this reason, a practical
static VAR compensator approximates an ideal
synchronized voltage source only as long as the
(midpoint) VAR demand does not exceed its
(capacitive) rating. If a static VAR compensator with
limited capacity is operated above its rating, it acts as
a constant shunt susceptance (capacitive admittance),
which means that the midpoint voltage can no longer
be kept at the constant end point voltage level,, V. In
this region, the power system behaves in the same
way as if the compensation at the midpoint were
provided by a fixed capacitor, as illustrated in Fig. 5.
3. Dynamic Stability
The term dynamic stability means that a power
system can recover normal operation following a
specified minor disturbance. In other words, a
dynamically stable power system has positive
damping. Under some conditions, a power system
may have very small positive or even negative
damping, which could result in sustained voltage and
power swings and even in eventual loss of
synchronism between the main power generators.
Since static VAR compensators can control the
voltage at given terminal of the transmission system,
and thereby alter its power transmission
characteristic, it is expected that with appropriate
controls they can provide damping for power
oscillation.
Consider the simple power system with an
ideal compensator, controlling the magnitude of the
midpoint voltage v
m
, shown in Figure 5. The
mechanical power applied to the generator is P
M
and
the electrical power transmitted to the infinite bus at
the receiving end is P
E
. if the mechanical angular
momentum is M and is the rotor angular position
(with respect to a synchronously rotating axis), the
Srk A2
dynamic behaviour of the system can be described by
the so-called swing equation:
E M
P P
dt
d
M =
2
2
(5)
where the difference P
M
P
E
is the accelerating
power.
For dynamic stability, it is enough to consider small
perturbations. Thus,
( )
E M
P P
dt
d
M =
2
2
(6)
Since the mechanical power P
M
is constant,
P
M
= 0 (7)
since the electrical power, as per equation (3), is
2
sin
2
X
VV
P
m
E
= (8)
the change in the electrical power can be expressed in
the following form:
=
E
m
m
E E
E
P
V
V
P
V
V
P
P (9)
In equation (9) V = 0, since the amplitude of the
sending end voltage is constant. Therefore, the
substitution of equations (7) and (8) with V = 0, into
equation (6), results in the following expression:
0
) (
2
2
=
E
m
m
E
P
V
V
P
dt
d
M (10)
In equation (10), the middle term
m m E
V V P ) / ( represents the effect of the
midpoint compensator on the dynamic behaviour of
the system. Recall that the function of the
compensator is to control the midpoint voltage (by
supplying appropriate amount of VARs). Consider
first that the amplitude of the midpoint voltage is kept
constant, that is, the compensator is operated as a
voltage regulator in the same way as is discussed in
connection with voltage support and transient
stability improvement. Then, with V
m
= const and
V
m
= 0, equation (10) becomes,
0
) (
2
2
=
E
P
dt
d
M (11)
The corresponding characteristic equation
0
1
2
=
+
o
E
P
M
s
(12)
indicates an undamped oscillation of angle (the
roots being on the imaginary axis of the s-plane) with
an angular frequency of
o
E
o
P
M
w

=
1
(13)
This means that, in general, a compensator
maintaining constant (midpoint) terminal voltage is
not effective in damping power oscillations.
In order to make the power oscillations damped, the
midpoint voltage in the system of Fig. 5 must be
varied as a function of d ()/dt, that is
dt
d
K V
M
) (
= (14)
where K is a constant.
With equation (14), equation (10) becomes
0
) ( ) (
2
2
=

o
E
o
m
E
P
dt
d
K
V
P
dt
d
M
(15)
which yields the following characteristic equation
0 2
2
0
2
= + + w s s (16)
where
o
m
E
V
P
M
K
= 2 (17)
and w
o
is given by equation (13).
The characteristic equation (16) clearly represents a
positively damped system (the roots being on the left
hand side of the s-plane) meaning that the oscillation
of angle decays with time.
The conclusion therefore can be made that,
in contrast to the previous cases of compensation
(voltage support and transient stability improvement),
which required terminal voltage regulation in order to
obtain oscillation damping, the VAR output of the
compensator must be controlled so as to vary the
terminal voltage in proportion to the rate of change of
the rotor angle or, since
f
dt
d

) (
(18)
according to the variation of the power system
frequency.
4. Subsynchronous Resonance Damping
When series capacitors are used to compensate the
series inductance of long transmission lines, a
phenomenon known as subsynchronous resonance
(SSR) can occur. The phenomenon occurs when the
series capacitors resonate with the equivalent
inductance of the generator and transmission line at a
frequency lower than the system nominal frequency.
Under such resonance conditions, the mechanical
impedance of the generator shaft system may exhibit
negative damping for a particular torsional mode. As
a result, torsional oscillation will spontaneously arise
and continue to increase in amplitude until the
generator shaft system is destroyed. The application
of an SVC for damping sunsynchronous resonance by
incorporating suitable controls is illustrated in Fig. 6.
Srk A3
Srk A3
References
1. IEEE Special Stability Working Group, Static
VAR Compensator Models for Power Flow and
Dynamic Performance Simulation, IEEE Trans. On
Power Systems, Vol.9, No.1, pp.229-240, Feb.1994.
2. P.Kundur, Power System Stability and
Control, The EPRI Power System Engineering
Series, Mc.Graw-Hill, Inc., New York, 1994.
Srk A4
Optimal location of multifunctional FACTS devices for power transit control
Elizabeth P Cheriyan
Lecturer, EED
NITC
Abstract Load flow control with multifunctional
FACT devices can maintain the reliable system
operation in the event of additionally demanded
power transits. The problem of placing FACTS
devices in a power system has received renewed
attention in recent years. The problem here is to
determine the optimal locations and sizes of FACTs
devices so as to facilitate greater control of power,
such that it flows on the prescribed transmission
routes and secure loading of transmission lines to
levels nearer their thermal limits is possible.
Genetic Algorithms have been used to solve the
above problem. The Optimisations are performed
on the location of the devices, their types and their
values. The system loadability is applied as the
measure of power system performance. The
simulation results show the difference of efficiency
of three devices used in this context. It is also
observed that the simultaneous use of several kinds
of controllers is the most efficient solution to
increase the loadability of the power system.
Introduction
The present day trend of deregulation is getting
translated into separation of generation and
transmission. Every consumer will be able to buy
his own electricity from any source desired. (Third
party access). On the technical side, we may
observe an increase of unplanned power exchange
due to the competition among utilities and to
contracts concluded directly between producers and
consumers. Problems could appear with the power
flow, which obey Kirchoffs laws. If the exchanges
were not controlled, some lines located on
particular paths may become overloaded, leading to
power congestion and thus the full capacity of
transmission inter connections could not be
utilized. Parallel to deregulation, electrical load
goes on increasing. Even though this growth has
been practically stabilized in developed nations,
some transmission lines are already close to their
thermal limits. Political and environmental
constraints make the building of new lines difficult
and lead electrical utilities to a better use of the
existing network. Therefore it is attractive for
electrical utilities to have a way of permitting a
more efficient use of the transmission lines by
controlling the power flows. Until a year ago the
only means of carrying out this function were
electromechanical devices such as switched
inductors or switched capacitor banks and phase
shifting transformers. However, specific problems
related to these devices make them not very
efficient in some situations. They are not only
relatively slow, but they also cannot be switched
frequently, because they tend to wear out quickly.
Appearance of FACS devices linked to the
improvements in semiconductor technology
permitted to suppress these drawbacks. It opens up
up new opportunities for controlling power and
enhancing the usable capacity of existing
transmission lines. Studies and realization have
their capabilities in steady state or dynamic
stability. With their ability to change the apparent
impedance of a transmission line, FACTS devices
may be used for active power control, as well as
reactive power or voltage control. For a meshed
network, an optimal location of FACTS devices
allows to control its power flows and thus to
increase the system loadability. Among the above-
quoted benefits, only some of them can be provided
by a given kind of FACTS device and it is
important to choose the suitable type(s) of devices
in order to reach a defined goal.
In this paper a case study is made on the
the optimal location of multitype FACTS devices.
Four different devices, with specific characteristics,
have been selected and modelled for steady-state
analysis. They are used in order to maximize the
power transmitted by the network by controlling
the power flows. The optimal location of a given
number of FACTS is a problem of combinatorial
analysis. To solve such kind of problem, heuristic
methods can be used. Among them, genetic
algorithms (GA) is chosen.
FACTS devices in general
In a power system, FACTS devices may be used to
achieve different goals. In steady state, for a
meshed network, they permit to operate the
transmission lines close to the thermal limits and
reduce the loop flows. They achieve these by
supplying or absorbing reactive power, increasing
or reducing voltage, and controlling series
impedance or phase angle. Their high-speed
operation gives them several qualities in dynamic
stability. In particular, they are capable of
increasing the synchronizing torque, damp
oscillations at various frequencies below the rated
frequency (.2 to1.5Hz), support dynamic voltage or
power flow control. Moreover, FACTS devices
may have benefits in case of short circuits, by
limiting short circuit current. Different types of
FACTS devices have been developed and one way
to classify them is on the basis of the type of
compensation. Accordingly, three categories of
FACTS controllers are distinguished: (i) series
controllers (ii) shunt controllers (iii) combined
series-shunt controllers. Within a category, several
FACTS devices exist and each one has its own
properties and may be used in specific contexts.
The choice of the appropriate device is important
since it depends on the goal to be reached.
Selection of FACTS devices
In an interconnected electrical network, power
flows obey Kirchoffs laws. Usually, the value of
the transverse conductance is zero and for most
transmission lines, the resistance is small compared
to reactance. By neglecting the transverse
capacitance, active and reactive power transmitted
by a line between two buses 1 and 2 may be
approximated by the following relationships:
, sin
12
12
2 1
12

X
V V
P = (1)
, ) cos (
1
12 2 1
2
1
12
12
V V V
X
Q = (2)
Where
V
1
and V
2
:voltages at buses 1 and 2 ;
X
12
:reactance of the line ;
12
:angle between V
1
and V
2
(underlines
variable denotes a phasor).
Under normal operating conditions for
high voltage lines V
1
V
2
and
12
is typically small.
In that case there is a decoupling between the
controls of the flows of active versus reactive
power. Active power flow is coupled with
12
and
reactive power flow is linked to the difference V
1
-
V
2
.The control of the value of X
12
acts on both and
modify active and reactive power.
Four different types of devices have been
chosen to be optimally located in order to control
power flows (fig. 1). Each of them is able to
change only one of the above-mentioned
parameters. The first one is the TCSC (Thyristor
controlled series capacitor), which permits to
modify the reactance of the line X
12
. To control the
phase-angle
12
, the TCPST (thyristor- Controlled
Phase Shifting Transformer) has been selected. The
TCVR (Thyristor- Controlled Voltage Regulator) is
picked up to act principally on V
1
-V
2.
Finally
,
the
SVC (static Var Compensator) is used to absorb or
inject reactive power at the midpoint of the line.
Fig.1
Modelling of FACTS Devices
The models of the FACTS devices are developed to
be suitably for steady state. Each device may take a
fixed number of discrete values.The TCSC may
have one of the two possible characteristics:
capacitive or inductive, respectively to decrease or
increase the reactance of the line X
L
. It is modelled
with three ideal switched elements in parallel: a
capacitance, an inductance and a simple wire,
which permits the TCSC to have the value zero.
The capacitance and the inductance are variable
and their values are functions of the reactance of
the line in which the device is located. In order to
avoid resonance, only one of the three elements can
be switched at a time. Moreover, to not
overcompensate the line, the maximum value of the
capacitance is fixed at 0.8X
L
.For the inductance,
the maximum is 0.2X
L
.The
TCPST acts by adding a quadrature component to
the prevailing bus device
voltage in order to increase or decrease its angle.
The model used for this is an ideal phase shifter
with series impedance equal to zero. It is inserted
in series and may take values of angles comprised
in the range of 5 deg to +5deg. Zero is also a
possible value for the TCPST.
The TCVR operates by inserting an in-
phase voltage to the main bus voltage so as to
change its magnitude. An ideal tap changer
transformer without series impedance is used to
model for this controller. The value of the turns
ratio is given by the ratio V
1
/V
2.
It determines the
additional transformation and its values range from
0.9 to 1.1 (1.0 corresponds to no additional
transformation).
The SVC may have two characters:
inductive or capacitive. In the first case it absorbs
reactive power while in the second one the reactive
power is injected. The SVC is modelled with two
ideal switched elements in parallel: a capacitance
and inductance. It may take values characterized by
the reactive power injected or absorbed at the
voltage of 1 p. u.The values are between 100Mvar
and 100 Mvar.
A graphical representation of the above-
described model is shown in Fig. 2.Only one
FACTS device per line may be allowed. For the
TCSC, TCPST, and TCVR, the devices are directly
integrated to the model of the line. They are
inserted in series with reactance and the reactance
of the line. For the SVC, the line is split into two
equal parts and the device is inserted in the middle.
Fig.2
Optimisation Algorithm
Heuristic methods may be used to solve
combinatorial optimisation problems. These
methods are called intelligent, because the move
from one place to another is done using rules close
to the human reasoning. The heuristic algorithms
search for a solution inside a subspace of the total
search space. Thus they are able to give a good
solution of a certain problem in a reasonable
computation time but they do not assure to reach
the global optimum. The most important advantage
of heuristic methods lies in the fact that they are
not limited by restrictive assumptions about the
search space like continuity, existence of derivative
of objective function, etc.
In this case study, Genetic
algorithms are chosen as the optimisation tool.
Genetic algorithms are based on the mechanisms of
natural selection. They always produce high quality
solutions because they are independent of the
choice of initial configurations. Moreover, they are
computationally simple and easy to implement.
One of the drawbacks is their possibility to
converge prematurely to a suboptimal solution.
The optimal solution is sought after from a
population of solutions using random process. A
new generation is created by applying to the
current population the three following operators:
reproduction, crossover and mutation. The
reproduction is a process dependant of an objective
function to maximise or minimize according to the
cases.
Description of the Used Genetic Algorithm
The goal of the optimisation is to find the
best location of a given number of FACTS devices
in accordance with a defined criterion. A
configuration of n
f
Facts devices is defined with
three parameters: the location of the devices, their
types and their values. In order to take into account
the three aforementioned parameters in the
optimisation, a particular coding is developed. An
individual is represented with three strings of
length n
F
, where n
F
is the number of the devices to
locate optimally.
The first string corresponds to the location
of the devices. It contains the numbers of the lines
where the FACTS are to be located. Each line
could appear at maximum once in the string. The
order of the lines in the string is not important for a
given configuration, but could have its importance
when applying the operator of crossover. Note that
the number of the lines is related with the order of
the branches in the description file of the power
system. The second string is related to the types of
the devices. A value is assigned to each type of
modelled FACTS device: 1 for TCSC; 2 for
TCPST; 3 for TCVR, and 4 for SVC at the mid
point of the line. By this way other new types of
FACTS may be easily added.
The last string of the individual represents
the value of the devices. It can take n
v
discrete
values contained between 0 and1; 0 corresponding
to the minimum value that the device can take and
1 to the maximum. According to the model of the
FACTS, the real value of the device v
realF
is
calculated with relation:
v
realF
= v
minF
+ (v
maxF
v
minF)
v
F,
where v
minF
and v
maxF
are respectively the
minimum and the maximum setting value of the
device, and v
F
is the its normalised value.
Fig. 3 gives an example of configuration
of five FACTS devices on a 7- bus, 11-branch
network and the corresponding three coded strings.
A TCSC is located on branch 1. Its value is a
capacitance of 0.5X
L1,
where X
L
is the reactance
of the line. A TCPST, producing a phase shifting of
4
0
on the voltage, is present on branch 5. Two
TCVR are located on lines 6 and 8. Their voltage
transformations are respectively 1.0 and 1.1.
Finally, a SVC is situated in the middle of the line
number 10. It is inductive and absorbs a reactive
power of 20 Mvar at V=1.0 p.u.
Fig.3
For a given power system of n
b
branches, the
initial population is generated from the following
parameters:
n
f
the number of FACTS devices to be
located optimally
The different types of devices to be
located
n
v
the number of possible discrete settings
for aq device
n
i
the number of individuals of the
population.
The creation of an individual is done in three
stages. First, a set of n
f
branches of the network are
randomly drawn and is put in the first string. As
previously mentioned, the order of the branches is
not important and different individuals may
represent the same configuration of FACTS
devices .After drawing the branches where the
FACTS devices will be located, the next two steps
consists in the attribution of of the characteristics
of the devices. The second string, referred to the
types of the devices, is obtained by randomly
drawing numbers among the selected device. Thus
if it is decided to optimally locate only one type of
device, this string will contain the same character.
Setting values of the devices are finally randomly
drawn among the n
v
possible. To obtain the entire
initial population, these operations are repeated n
i
times.
Then, the objective function is computed
for every individuals of the population. It
represents a mathematical, translation of the
optimisation to realise and does not have to be
continuous or derivable. It has to be elaborated so
as to favour the reproduction of interesting others.
In our case, the objective function is defined in
order to quantify the impact of the FACTS devices
on the state of the power system. The move to a
new generation is done from the results obtained
for the old generation. A biased roulette wheel is
created from the obtained values of the objective
function of the current population as represented in
Fig. 4. After that, the operators of reproduction,
crossover and mutation are applied successively to
generate the offspring.
In turn, two individuals are randomly
drawn from the population and reproduced. The
probability of drawing an individual is proportional
to its part on the biased roulette wheel. Fig.5 shows
the process of reproduction.
Fig 4
Fig.5
The crossover may occur with a
probability p
c
; generally close to 1. A double
crosser is applied. Two crossing sites are picked up
uniformly at random along the individuals.
Elements outside these two points are kept to be
part of the offspring. Then, from the first position
of the crossover to the second one, elements of the
three strings of both parents are exchanged. As
previously mentioned, only one FACTS device per
branch is authorized. Therefore, if the crossover
leads to place a second device on a branch, a
correction has to be applied. In the case where an
element of the first string already occupies a
position in the kept part of the parent, it is replaced
by the element corresponding to the same position
in the other parent. This algorithm is repeated until
an element not already present in the string is
reached. Fig. 6 illustrates a crossover between two
individuals. A correction has to be applied on the
second offspring. The element 8 is already present
at the fourth position of the string. Therefore, the
element 8 at the third position is replaced by the
fourth element of the first parent, which
corresponds to the element 5.
Fig.6
Mutations are possible independently on all
elements of the three strings of an individual. A
specific probability is applied for each string: p
m
L
for the first string, p
m
T for the second and P
m
V for
the last. These probabilities change with the
generations. When a mutation occurs on the first
string, the one related to the location, a new line
among the set of branches having no FACTS
israndomly drawn. In the case of mutation on the
two other strings, a new value is drawn among the
set of possible ones. Examples of mutations are
shown in Fig. 7.
Fig.7
Operations of selection, crossover and
mutation are repeated until the number of desired
offsprings is created. The objective function is then
calculated for every offsprings and the n
i
best
individuals among the entire pool, comprising
parents and their offsprings, are kept to constitute
the new generation. By this way, the objective
function of the best individual of the new
generation will be the same or higher than the
objective function of the best individual of the
previous generation. Similarly, the average fitness
of the population will be the same or higher than
the average fitness of the previous generation.
Thus the fitness of the entire population and the
fitness of the best individual are increasing for each
generation.
Objectives of the optimization
The goal of the optimization is to perform a best
utilization of the existing transmission lines. In this
respect, the FACTS devices are located in order to
maximize the system load ability while observing
thermal and voltage constraints. In other words, it
is looked for increasing as much as possible the
power transmitted by the network to the
consumers, keeping the power system in a secure
state in terms of branch loading and voltage
levels.The objective function is built in order to
penalize the configurations of FACTS leading to
overloaded transmission lines and over- or under-
voltages at buses. Only the technical benefits of the
FACTS controllers, in terms of loadability, are
taken into account. Other criteria such as costs of
installing and maintaining devices are not taken
into consideration presently.
As commonly done for multi-criteria
constrained optimization, the problem is
transformed into a single objective optimization
problem. The objective function is defined as a
sum of two terms with individual criteria. The first
one is related to the branch loading and penalizes
overloads in the lines. This term, called O
V
l , is
computed for every line of the network. While the
branch loading is less than 100%, its value is equal
to 1; then it decreases exponentially with the
overload. To accelerate the convergence, the
product of all objective function is taken. The
second part of the objective function concerns
voltage levels. It favours buses voltages close to 1
p.u. The function is calculated for all buses of the
power system. For voltage levels comprised
between 0.95 p.u. and 1.05 p.u., the value of the
objective function Vtg is equal to 1. Outside this
range, the value decreases exponentially with the
voltage deviation. Therefore, for a configuration of
FACTS devices, the objective function Cfg is given
by:

+ =
bus
bus
line
line
Vtg Ovl g f C , (4)
where functions Ovl and Vtg are
represented in Fig. 8.
Ovl
and
Vtg
are respectively
two coefficients used to adjust the slope of the
exponentials.
Fig .8-(a)
Fig. 8-(b)
Optimizations are carried out with a tool
developed in Matlab language. Power flows are
solved with a modified version of the free Matlab
power simulation package Matpower 2.0.
Simulations are performed on a 118-bus, 187 lines
test power system. Generators are modelled as PV-
node and loads as PQ-node. The line is modeled
using the classical -scheme, valid for electrically
short lines.
Optimization Strategy
As explained previously, the aim is to find the
maximum amount of power that the power system
is able to supply without overloaded line and with
an acceptable voltage level. We look for locating a
given number of FACTS devices to increase as
much as possible the capacity of the network. For
several number of FACTS devices, the best
location with the best values of the most
appropriate controllers is sought. When the
number of devices is increased, the results obtained
previously are not taken into account. In others
words, FACTS devices may disappear from
specific lines to reappear on others when their
number is increased.
For a given number of devices, the strategy consists
of adding to the power supplied as long as a
configuration of FACTS permits to keep the power
system in a secure state. Starting from an initial
load, the GA described in previous section is
applied recursively. The stop criterion is either the
maximum number of generations or a solution with
an objective function equal to 1. In the first case the
algorithm is stopped, otherwise the load is raised
and a new optimization starts again. All loads are
increased in the same proportion and real power of
generators as well. Additional losses due to the
increasing of the power transmitted are shared out
among all the generators proportionally to their
power. The whole optimization strategy is
summarized in Fig. 9. To compare the benefit of
multi-type FACTS devices, simulations are also
performed only for a single-type of device, namely
TCSC, TCPST, TCVR and SVC.
Fig .9
Observed Results from the case study
For all the types of FACTS devices, the optimal
location allows to increase the system loadability.
There are a maximum number of devices beyond
which the efficiency of the network cannot be
further improved. According to the used
optimization criterion and for the considered power
system, the results show that the limit is about 30
devices.
For a single-type optimization, the
simulations show that the TCSC are the most
efficient, before TCPST and TCVR. SVC permit to
increase the system loadability too, but less than
with the other devices as expected. Simultaneous
use of all the types of devices is the most efficient.
In this case, each type of device is located to satisfy
specific purpose. Until 5 devices the difference of
benefit is not valuable, then it increases to reach a
limit of 5% with 30 devices.
The obtained results are shown in Fig. 10.
Values are related to the maximum power that can
be supplied without FACTS devices while keeping
the power system in secure state. It corresponds to
an active power of 3651(MW) and a reactive power
of 1438(MVar).
Fig.10.
Conclusion
A case study has been done on the application of
genetic algorithm to optimally locate multi-type
FACTS devices in a power system. Four types of
controllers were chosen and modeled for steady-
state studies. Optimizations were performed on
three parameters: the locations of the devices, their
types, and their values. The system loadability was
employed as measure of power system
performance. A difference of efficiency on the
loadability of the used devices has been quantified.
Moreover, results have shown that the
simultaneous use of several kinds of FACTS was
the most efficient solution to increase the system
loadability. For all the types of device, even with
multi-type devices, it is observed that there is a
maximum number of FACTS devices beyond
which this loadability cannot be improved.
REFERENCES
[1]Stphane Gerbex,Rachid Cherkaoui, and Alain
J. Germond,Optimal Location of Multi-Type
FACTS Devices in a Power System by Means of
Genetic Algorithms,IEEE Transactions On Power
Systems, Vol. 16, No. 3, August 2001.
[2] N. G. Hingorani and L. Gyugyi, Understanding
FACTS Concepts and
Technology of Flexible AC Transmission Systems.
Piscataway: IEEE Press, 1999
[3] F. D. Galiana, K. Almeida, M. Toussaint, J.
Griffin, and D. Atanackovic,Assessment and
control of the impact of FACTS devices on power
system performance, IEEE Trans. Power Systems,
vol. 11, no. 4, Nov.1996.
[4] D. E. Goldberg, Genetic Algorithms in Search
Optimization and Machine Learning: Addison-
Wesley Publishing Company, Inc., 1989
[5] S.Gerbes R.Cherkaoui and A.J Germond
"Optimal location of FACTS devices in a power
system using genetic algorithms", In proceedings
of the 13 power systems computation
conference,1999, pp 1252-1259
APPLICATION OF STATCOM AND TCSC FOR IMPROVEMENT OF
SYSTEM DYNAMIC PERFORMANCE
Dr R. Sreeram Kumar
National Institute Technology, Calicut
1. Application of STATCOM for Transient
Stability Improvement
The ability of the STATCOM to maintain
full capacitive output current at low system voltage
also makes it more effective than the SVC in
improving the transient (first swing) stability. The
effectiveness of the STATCOM in increasing the
transmittable power is illustrated in Figure 1, where
the transmitted power P is shown against the
transmission angle for the usual two-machine
model at various capacitive ratings defined by the
maximum capacitive output current I
Cmax
. For
comparison, an equivalent P versus relationship is
shown for an SVC, behaves like an ideal midpoint
shunt compensator with P versus relationship
defined by P = (2 V
2
/X) sin (/2) until the
maximum capacitive output current I
Cmax
is reached.
From this point, the STATCOM keeps providing this
maximum capacitive output current (instead of a
fixed capacitive admittance like the SVC),
independent of the further increasing angle and the
consequent variation of the midpoint voltage. As a
result, the sharp decrease of transmitted power P in
the < < 2 / region, characterizing the power
transmission of an SVC supported system, is avoided
and the obtainable
Pd area representing the

improvement in stability margin is significantly
increased. That the transmittable power can be
increased if the shunt compensation is provided by a
STATCOM rather than by an SVC, or, for the same
stability margin, the rating of the STATCOM can be
decreased below that of the SVC.
2. Application of TCSC for Stability
Improvement
2.1 Improvement of Transient Stability
As discussed in the previous notes, transient
stability improvement by controlled shunt
compensation is achieved by increasing the power
transmission via increasing (or maintaining) the
(midpoint) transmission line voltage during the
accelerating swing of the disturbed machine(s). The
powerful capability of series line compensation to
control the transmitted power can be utilized much
more effectively to increase the transient stability
limit and to provide power oscillation damping.
Consider the simple system with the series
compensated line shown in Figure 2a. Suppose that
this system with and without series capacitive
compensation, transmits the same power P
m
. Assume
that both the uncompensated and the series
compensated systems are subjected to the same fault
for the same period of time. The dynamic behaviour
of these systems is illustrated in Figures 3 (a) and (b).
As seen, prior to the fault both of them transmit
power P
m
at angles
1
and
s1
, respectively. During
the fault, the transmitted electric power becomes zero
while the mechanical input power to the generators
remains constant, P
m
. Therefore, the sending-end
generator accelerates from the steady-state angles
1
and
s1
to angles
2
and
s2
, respectively, when the
fault clears. The accelerating energies are
1
and A
s1
. After fault clearing,
the transmitted electric power exceeds the mechanical
input power and therefore the sending-end machine
decelerates. However, the accumulated kinetic
energy further increases until a balance between the
accelerating and decelerating energies, represented by
areas A
1
, A
s1
, and A
s2
, respectively, is reached at the
maximum angular swings,
3
and
s3
, respectively.
The areas between the P versus curve and the
constant P
m
line over the intervals defined by angles
3
and
crit
, and
s3
and
scrit,
respectively, determine
the margin of transient stability, represented by areas
A
margin
and A
smargin
.
Comparison of Figures 3 (a) and (b) clearly
shows a substantial increase in the transient stability
margin the series capacitive compensation can
provide by partial cancellation of the series
impedance of the transmission line. The increase of
transient stability margin is proportional to the degree
of series compensation. Theoretically this increase
becomes unlimited for an ideal reactive line as the
compensation approaches 100%. However, practical
series capacitive compensation does not usually
exceed 75% for a number of reasons, including load
balancing with parallel paths, high fault current, and
the possible difficulties of power flow control. Often
the compensation is limited to less than 30% due to
subsynchronous concerns.
It is emphasized here again that under
practical fault scenarios the pre-fault and post-fault
systems are generally different. From the standpoint
of transient stability, and of overall system security,
the post-fault system is the one that matters. That is,
power systems are normally designed to be
transiently stable, with defined pre-fault contingency
scenarios and post-fault system degradation, when
subjected to a major disturbance. For this reason, in
most practical systems, the actual capacity of
SRK-C1
transmission networks is considerably higher than
that at which they are normally used. The powerful
capability of series compensation, with sufficiently
fast controls, to handle dynamic disturbances and
increase the transmission capability of post fault or
otherwise degraded systems, can be effectively used
to reduce the by-design underutilization of many
power systems.
2.2 Power Oscillation Damping
Controlled series compensation can be
applied effectively to damp power oscillations. For
power oscillation damping it is necessary to vary the
applied compensation so as to counteract the
accelerating and decelerating swings of the disturbed
machine(s). That is, when the rotationally oscillating
generator accelerates and angle increases (d/dt>0),
the electric power transmitted must be increased to
compensate for the excess mechanical input power.
Conversely, when the generator decelerates and angle
decreases (d/dt<0), the electric power must be
decreased to balance the insufficient mechanical
input power.
The required variation of the degree of series
compensation, together with the corresponding
variation of the transmission angle and transmitted
power P versus time of an under-damped oscillating
system are shown for an illustrative hypothetical case
in Figure 4. Waveforms in Figure 4(a) show the
undamped and damped oscillations of angle around
the steady-state value
0
. Waveforms in Figure 4(b)
show the corresponding undamped and damped
oscillations of the electric power P around the steady-
state value P
0
, following an assumed fault (sudden
drop in P) that initiated the oscillation. Waveform c
shows the applied variation of the degree of series
capacitive compensation, k, applied. As seen, k is
maximum when d/dt>0, and it is zero when d/dt<0.
With maximum k, the effective line impedance is
minimum (or, alternatively, the voltage across the
actual line impedance is maximum) and
consequently, the electric power transmitted over the
line is maximum. When k is zero, the effective line
impedance is maximum (or, alternatively, the voltage
across the actual line impedance is minimum) and the
power transmitted is minimum.
2.3 Subsynchronous Oscillation Damping
Large generators with multistage steam
turbines, which have multiple torsional modes with
frequencies below the power frequency, are most
susceptible to subsynchronous resonance with series
capacitor compensated transmission lines. In order to
be able to fully exploit the functional capabilities of
controlled series capacitive compensation for power
flow control, transient stability improvement and
power oscillation damping, it is imperative that the
series compensator, as a minimal requirement,
remains passive (nonparticipating) to, or, preferably,
actively mitigates subsynchronous resonance. Power
electronics-based series compensators can meet this
requirement either by their non-capacitive
characteristic in the subharmonic frequency range of
interest or by active, control-initiated damping action.
Reference
N.Hingorani, Flexible AC Transmission Systems,
(Book)
SRK-C2
SK11 5
UNIFIED POWER FLOW CONTROLLER (UPFC) AN INTRODUCTION
Suresh Kumar K.S
AP,EED,NIT Calicut
1. Introduction
Gyugyi proposed the Unified Power Flow Controller (UPFC) concept in 1991[3]. The UPFC
was devised for the real time control and dynamic compensation of ac transmission systems,
providing multifunctional flexibility required to solve many of the problems facing the delivery
industry[1-3] . Within the framework of traditional power transmission concepts, the UPFC is able
to control, simultaneously or selectively, all the parameters affecting power flow in the transmission
line (i.e., voltage, impedance and phase angle), and this unique capability is signified by the
adjective unified in its name. Alternatively, it can independently control both the real and reactive
power flows in the line.
2. Circuit Arrangement:
In the presently used practical implementation, the UPFC consists of two switching
converters, which in the implementations considered are voltage source inverters using gate turn-
off (GTO) thyristor valves, as illustrated in the Fig 2.1.These back to back converters labeled
Inverter 1 and Inverter 2 in the figure, are operated from a common dc link provided by a dc
storage capacitor. This arrangement functions as an ac to ac power converter in which the real
power can freely flow in either direction between the ac terminals of the two inverters and each
inverter can independently generate (or absorb) reactive power at its own ac output terminal.
Fig 2.1. Basic circuit arrangement of unified power flow controller
3. Operation of UPFC
Inverter 2 provides the main function of the UPFC by injecting an ac voltage Vpq with
controllable magnitude V
pq
(0 V
pq
V
pqmax
) and phase angle (0 360), at the power
frequency, in series with the line via an insertion transformer. The injected voltage is considered
essentially as a synchronous voltage source. The transmission line current flows through this
voltage source resulting in real and reactive power exchange between it and the ac system. The
real power exchanged at the ac terminal (i.e.,at the terminal of insertion transformer) is converted
by the inverter into dc power that appears at the dc link as positive or negative real power
demanded. The reactive power exchanged at the ac terminal is generated internally by the
inverter.
The basic function of Inverter 1 is to supply or absorb the real power demanded by Inverter
2 at the common dc link. This dc link power is converted back to ac and coupled to the
transmission line via a shunt-connected transformer. Inverter 1 can also generate or absorb
controllable reactive power, if it is desired, and there by it can provide independent shunt reactive
compensation for the line. It is important to note that where as there is a closed direct path for
the real power negotiated by the action of series voltage injection through Inverters 1 and 2 back to
the line, the corresponding reactive power exchanged is supplied or absorbed locally by inverter 2
and therefore it does not flow through the line. Thus, inverter 1 can be operated at a unity power
SK11 6
factor or be controlled to have a reactive power exchange with the line independently of the
reactive power exchanged by the by the Inverter 2. This means there is no continuous reactive
power flow through UPFC.
4. Basic Control Functions
Operation of the UPFC from the standpoint of conventional power transmission based on
reactive shunt compensation, series compensation, and phase shifting, the UPFC can fulfill these
functions and thereby meet multiple control objectives by adding the injected voltage Vpq, with
appropriate amplitude
and phase angle, to the terminal voltage V
o
. Using phasor representation, the basic UPFC power
flow control functions are illustrated in Fig. 2.
Terminal Voltage Regulation, similar to that obtainable with a transformer tap- changer
having infinitely small steps, as shown at (a) where V
pq
=V (boldface letters represent phasors) is
injected in-phase (or anti-phase) with V
o
.
Series Capacitor Compensation is shown at (b) where V
pq
=V
c
is in quadrature with the
line current I.
Transmission Angle Regulation (phase shifting) is shown at (c) where V
pq
=V
o
is injected
with angular relationship with respect to V
o
that achieves the desired s phase shift (advance or
retard) with out any change in magnitude.
Vo
Vo+Vo
Vc
Vo+Vc
Vo
(a) voltage regulation
(c) Phase angle
Regulation
V
Vo+V
Vo

Fig. 2 - Basic UPFC control functions:
(a) Voltage regulation, (b) Series compensation, (c) Angle
regulation, and (d) Multifunction power flow control
Vpq Vo
Vc
Vc
(d) Multi-function
Power flow control
Vo
V
o
+V
0
+V
c
+V
(b) series compensation
SK11 7
Multifunctional Power Flow Control, executed by simultaneous terminal voltage
regulation, series capacitive compensation, and phase shifting, is shown at (d) where V
pq
=V
+V
c
+V
o
5. Basic Principles of P and Q Control [1,3]
Consider Fig 3. At (a) a simple two machine (or two bus ac inter-tie) system with sending
end voltage Vs, receiving-end voltage Vr, and line (or tie) impedance X (assumed, for simplicity,
inductive) is shown. At (b) the voltages of the system in the form of a phasor diagram are shown
with transmission angle and |Vs|=|Vr|=V. At (c) the transmitted power P (P=V
2
/X sin) and the
reactive power Q=Qs=Qr (Q= V
2
/X (1-cos)) supplied at the ends of the line are shown plotted
against angle . At (d) the reactive power Q=Qs=Qr is shown plotted against the transmitted power
P corresponding to stable values of (i.e., 090).
The basic power system of Fig 3 with the well known transmission characteristics is
introduced for the purpose of providing a vehicle to establish the capability of the UPFC to control
the transmitted real power P and the reactive power demands, Qs and Qr, at the sending end,
respectively, the receiving end of the line.
Consider Fig 4.The simple power system of Fig 2.3 is expanded to include the UPFC. The
UPFC is represented by a controllable voltage source in series with the line which, as explained in
the previous section, can generate or absorb reactive power that it negotiates with the line, but the
real power it exchanges must be supplied to it, or absorbed from it, bye the sending end generator.
The UPFC in series with the line is represented by the phasor V
pq
having magnitude V
pq
(0 V
pq

Fig 3. -Simple two machine system (a), related voltage phasors (b), real
and reactive power verses transmission angle (c), and sending-end/
receiving- end reactive power verses transmitted real power(d).
X
Vs V
Qs
Q
P
(a
|Vs|=|Vr|
Vs
Vx
Vr
P=V
2
/X sin
2
(b)
Qs
Qr
(d)
0
P 1
1
Qs
Qr
P
Qs,Qr
P
90
2
2
0
(c)
=90
SK11 8
V
pqmax
) and angle (0 360) measured from the given phase position of phasor Vs, as
illustrated in the figure. The line current represented by the phasor I, flows through the series
voltage source, V
pq,
and generally results in both reactive and real power exchanges.
In order to represent UPFC properly, the series voltage source is stipulated to generate
only the reactive power Q
pq
it exchanges with the line. Thus the real power P
pq
it negotiates with
the line is assumed to be transferred to the sending-end generators if a perfect coupling for real
power flow between it and the sending-end generator excited. This is in arrangement with the
UPFC circuit structure in which the dc link between the two constituent inverters establishes a bi-
directional coupling for real power flow between the injected series voltage source and the sending
end bus.
As Fig 4 implies, in the present discussion it is further assumed for clarity that the shunt
reactive compensation capability of the UPFC not utilized. This is the UPFC shunt inverter is
assumed to be operated at unity power factor, its sole function being to transfer the real power
demand of the series inverter to the sending-end generator. With these assumptions, the series
voltage source, together with the real power coupling to the sending end generator as shown in fig
4, is an accurate representation of the basic UPFC.
It can be readily observed in Fig 4 shows that the transmission line sees V
s
+V
pq
as the
effective sending end voltage. Thus it is clear that the UPFC effects the voltage (both its magnitude
and angle) across the transmission line and therefore it is reasonable to expect that it is able to
control, by varying the magnitude and angle of V
pq
, the transmittable real power as well as the
reactive power demand of the line at any given transmission angle between the sending-end and
receiving-end voltages.
6. Independent Real And Reactive Power Flow Control
In Fig 5(a) through 5(d) the reactive power Qs supplied by the
sending end generator, and Q
r
supplied by the receiving-end generator, are shown plotted
separately against the transmitted power P as a function of the magnitude V
pq
and angle of the
injected voltage phasor V
pq
at four transmission lines: =0, 30, 60, and 90. At V
pq=0,
each of these
plots becomes a discrete point on the basic Q-P curve as shown in Fig 3 (d), which is included in
each of the above figures for reference. The curves showing the relationships between Qs and P,
and Q
r
and P, for the transmission angle range of 090, when the UPFC is operated to provide
the maximum transmittable power with no reactive power control (V
pq
=V
pqmax
and =
P=Pmax
), are
Vr Vs
Vpq
Vx
Vr
Ppq
Vs
P
Vx
Qs
Qr
Vpq
Fig 4.Two machine system with the unified power flow controller
SK11 9
also shown by a broken-line with the label P()=MAX at the sending end and, respectively ,
receiving-end plots of the figures.
Fig 5(a)&5(b). Attainable sending-end reactive power vs.transmitted power
(left hand side plots)and receiving-end reactive power Vs
transmitted power(right hand side plots) values with the
UPFC at =0 and =30.
SK11 10
Fig 5(c)&5(d). Attainable sending-end reactive power vs.transmitted
power (left-hand side plots) and receiving-end
reactive power Vs transmitted power (right hand
side plots) values with the UPFC at =60and =90.
Consider the first Fig. 5(a), which illustrates the case when the transmission angle is zero
(=0). With V
pq
=0, P, Q
s
, and Q
r
are all zero, i.e., the system is standstill at the origins of the Qs, P,
and Q
r
, P coordinates. The circles around the origin of the {Qs, P} and {Q
r
, P} planes show the
variation of Qs and P, and Q
r
and P, respectively. As the voltage phasor V
pq
, with its maximum
magnitude V
pqmax
is rotated a full revolution (0360). The area with in these circles define all P
and Q values obtainable by controlling the magnitude V
pq
and of the phasor V
pq
.
In other words, the circle in the {Qs, P} and {Qr, p} planes define all P and Qs and,
respectively, P and Qr values attainable with the UPFC of a given rating. It can be observed, for
example, that the UPFC with the stipulated voltage rating of 0.5 p.u. is able to establish 0.5 p.u
power flow, in either direction, without imposing any reactive power demand on either the sending-
end or the receiving-end generator. Of course, the UPFC, as seen, can force the generator at one
end to supply reactive power for the generator at the other end. (In case of intertie, one system can
be forced to supply reactive power of the line.)
In general at any given transmission angle , the transmitted real power P, and the reactive
power demands at the transmission line ends, Q
s
and Q
r
, can be controlled freely by the UPFC
SK11 11
within the boundaries obtained in the {Q
s
, P} and {Q
r,
P} planes by rotating the injected voltage
phasor V
pq
with its maximum magnitude a full revolution. The boundary in each plane is centered
around the point defined by the transmission angle on the Q verses P curve that characterizes the
basic power transmission at V
pq
=0.
Consider the next case of =30(Fig. 5(b)), it is seen that the receiving-end control region
boundary in the {Q
s
, P} plane become an ellipse. As the transmission angle is further increased,
for example, to 60 (Fig.5(c)), the ellipse defining the control region for P and Q
s
in the {Q
s
, P}
plane becomes narrower and finally 90 (Fig.5 (d)) it degenerates into a straight line. By contrast,
the control region boundary for p and Q
r
in the {Q
r
, P) plane remains a circle at all transmission
angles.
7. Summary
In summary, the UPFC, with its unique capability to control independently the real and
reactive power flow at any transmission angle provides a powerful new tool for transmission
system control.
8. References
[1]L.Gyugyi, C.D. Schauder, S.L. Williams, T.R.Rietman, D.R.Torgerson, A.Edris,The Unified Power Flow
Controller: A New Approach to Powe Transmission Control, IEEE Trans .on Power Delivery, Vol.10, No.2
April 1995,pp.1085- 1097.
[2]L.Gyugyi, Unified Power Flow Concept for Flexible Ac Transmission Systems
IEEE Proc-C, Vol.139, No.4, July1992, pp.323-332.
[3] Narian G.Hingorani, Laszio Gyugyi Understanding FACTS Concepts and Technology of Flexible AC
Transmission Systems , First edition 2001, IEEE press.
SK12 18
CONTROL OF A UNIFIED POWER FLOW CONDITIONER
Suresh Kumar K.S
AP,EED,NIT Calicut
1. Vector Representation of Instantaneous Three Phase Quantities:
The notion of the real and reactive power is well known in the phasor sense. However, to
study and control the dynamics of the UPFC within subcycle frame and subject to line distortions,
disturbances and unbalance, we need a broader definition of reactive power which is valid on an
instantaneous basis [4].
The instantaneous real power at a point on the line is given by P=V
a
I
a
+V
b
I
b
+V
c
I
c.
We can
define instantaneous reactive voltages conceptually as a part of the three-phase voltage set that
could be eliminated at any instant without altering p. The definition of instantaneous reactive
voltage is obtained by vector interpretation of the instantaneous values of the circuit variables.
A set of three instantaneous phase variables that sum to zero can be uniquely
represented by a single point in a plane, as illustrated in Fig.1. By definition, the vector drawn
from the origin to this point has a vertical projection onto each of the three symmetrically
disposed phase axis, which corresponds to the instantaneous value of the associated phase
variable. This transformation of phase variables to instantaneous vectors can be applied to
voltages as well as currents. As the values of phase variables change, the associated vector
moves around the plane describing various trajectories. The vector contains all the information on
the three-phase set, including steady-state unbalance, harmonic waveform distortions, and
transient components.
2. Three Phase to D-Q Transformation
In Fig 2, the vector representation is extended by introducing an orthogonal co-ordinate
system in which each vector is described by means of its ds- and qs- components. The
transformation of phase variables to ds and qs co-ordinates is as follows.
Fig.1 Vector representation of instantaneous three-phase variables
V
a
(+)
I
b
(-)
I
c
(+)
+A-phase
axis
+C-phase
axis
+B-phase
axis
I
SK12 19
If V
a,
V
b,
V
c
are balnced set of voltages V
a
= 2 V
rms
sint,
Vb= 2 V
rms
sin(t-120), V
c
= 2 V
rms
sin(t-240)
then by using the above trasformation matrix, the ds and qs axis coordinates are given by
V
ds
= V
rms
cost
V
qs
= -V
rms
sint (2)
The per unit values represent rms qunatities.The constants are derived based on power
invarience principle =>V
a
I
a
+ V
b
I
b
+ V
c
I
c
=V
ds
I
ds
+V
qs
I
qs
The inverse trasformation matrix is given by V
old
= C
1
V
new
+qs-axis
+ds-axis
Fig.3.2 Definition of orthogonal co-ordinates
(A-axis)
(C-axis)
MMF
direction
[ ] ) 1 (
2
1
2
1
2
1
2 2
1
2
3
2
3
0
2 3
2
1
1
1 1
C
SK12 20
Single phase per-unit system is used and the per-unit values represent rms quantities.
Fig.3 shows how further manipulation of vector coordinate frame leads to a useful
separation of variables for power control purposes. The d-axis voltage component V
d,
accounts
for real component and q-axis voltage V
q
, is the instantaneous reactive component. The d and q
axes are not stationary in the plane. They follow the trajectory of the voltage vector, and the d
and q co-ordinates within this synchronously reference frame are given by the following time-
varying transformation:
The transformation matrix in synchronously revolving reference frame is given by
For balanced set of phase voltages Va= 2 V
rms
sin(t-) V
b
= 2 V
rms
sin(t-120-) Vc= 2
V
rms
sin(t-240-) and =t. the d and q axis components are given by
V
d
= V
rms
cos
Vq

= -V
rms
sin
Under balanced steady-state conditions, the co-ordinates of the voltage and current
vectors in synchronous reference frame are constant quantities. The inverse transformation in
synchronous reference frame is [C]
-1
=[C]
t
The d-q axis real power component is P= V
d
I
d
+ V
q
I
q
and the reactive power is given by
Q= -V
q
I
d
+ V
d
I
q
. These represent power in single-phase quantities. This can be summarized this
way, defining complex vectors in d-q plane is
[ ] ) 4 (
cos sin
sin cos
2
=

C
[ ] ) 3 (
2
1 1
2
3
2
1
2
2
3
2
1
1 0
2
1
2
1
= C
d-axis
q-axis
qs-axis
ds-axis
Fig. 3 Transformation in rotating reference frame

SK12 21
V

= V
d
+ j V
q
, I
= I
d
+j I
q
P + jQ = V I
*
= ( V
d
I
d
+ V
q
I
q
)+ j (V
q
I
d
V
d
I
q
)
3. Transformation of Impedance Matrix [5]
The transformation is explained by considering a simple three-phase
system as shown in Fig 4
The balanced three-phase system can be transformed into a synchronously rotating
orthogonal system.
Z
new
= C
1t
Z
old
C
in the ds- qs plane the impedance matrix transformed into
Now in the synchronously revolving reference frame ( d-q transformation) the impedance
matrix is transformed into
Where P= d/dt , the voltage equations after d-q transformation is given by
the above equation can be written as
V
1a
V
1b
V
1c
V
2a
V
2b
V
2c
L
a
L
b
L
c
R
a
R
c
R
b
Fig 4 Simple balanced system
I
a
) 5 (
0 0
0 0
0 0
2 1
2 1
2 1
+
+
+
=
i
i
i
V V
V V
V V
c
b
a
c c
b b
a a
PL R
PL R
PL R
) 6 (
0
0
PL R
PL R
Znew
+
+
=
) 7 (
'
PL R L
L PL R
Znew
+
+
=
) 8 (
1 1
2 1
+
+
=
i
i
V V
V V
d
d
q q
d d
PL R L
L PL R
) 9 (
2 1
L L
R
dt
d
V V
i i
i d d
q d
d

+ + =
) 10 (
2 1
L L
R
dt
d
V V
i i
i q q
d q
q

+ =
SK12 22
per-unit system is adopted according to the following definitions:
by using the per unit system the above equations rewritten as
Where
b
= base frequency
= synchronously rotating system frequency
The significance of the transformation summarized as follows:
1. The physical significance of the phase transformation C
1
is therefore to replace the actual three
phase system by an equivalent two phase system.
2. The original circuit produced in Fig 4 gave rise to an impedance matrix Z with
nine non-zero terms. The transformed impedance matrix Z has only four terms.
4. Controller Design [6-8]
A control strategy, in general, should preferably have the following attributes:
1. Steady state objectives (i.e. real and reactive power flows) should be readily
achievable by setting the references of the controllers.
2. Dynamic and transient stability improvement by appropriate modulation of
controller references.
To simplify the design procedure we carry out the design of the series and shunt branches
separately. In each case, the external system is represented by a simple equivalent. The design
has to be validated when the various sub systems are integrated.
The design tasks are listed below:
1. Series injected voltage control:
a. Power flow control by series voltage injection.
b. UPFC port 2-voltage control by series voltage injection.
2. Shunt converter voltage control
a. Closed loop current (real and reactive) control
b. UPFC port 1 voltage control using reactive current injection
c. Capacitor voltage regulation using real current injection.
The basic design considerations are illustrated using simplified system models. The
performance of all the controllers is subsequently evaluated using detailed simulations for a case
study.
) 11 (
) (
'
2 1
'
'
x x
R
dt
d
V V
i i
i d d b
q d
b d

+ + =

) 12 (
) (
'
2 1
'
'
x x
R
dt
d
V V
i i
i q q b
d q
b
q

+ =

c b a x
R
L
e
z
R
z
x
i
v
z
v
e
v
v
v
i
i
i
B B
B
B
x
x
B
x
x
B
x
x
B
x
x
, ,
; ;
; ;
' ' '
'
'
'
=
= = =
= = =
SK12 23
5. Series Injected Voltage Controller
5.1 Power Flow Control
In this section we consider the control of real power using series voltage injection.
We carry out analysis on the simplified system shown below in Fig.3.5. The differential equations
for the current at port 2 in the D-Q (synchronously rotating at system frequency
0
) frame of
reference are given by:
The subscripts D and Q denote the variables in D-Q reference frame.
Power at the receiving end bus P
R
is approximately equal to that at port 2 ( P
u2
) of the
UPFC in the study state ; therefore we control the power at port 2 since the feed back signal is
readily available.
2 port UPFC at the voltages of components Q D ,
1 port UPFC at the voltages of components Q D ,
bus end receiving at the voltages of components Q D ,
bus end sending at the voltages of components Q D ,
2 2
1 1
=
=
=
=
v v
v v
v v
v v
Q D
Q D
RQ RD
SQ SD
) 13 ( ) (
2 v v
x
i i
x
r i
RD D
se
b
Qse Dse
se
b se Dse
dt
d
+ + =

e v v
e v
v
Qse Q Q
Dse D
D
+ =
+ =
1 2
1
2
where,
) 14 ( ) (
2 v v
x
i i
x
r
i
RQ Q
se
b
Dse Qse
se
b se
r
Qse
dt
d
+ =

+
Port 2
X
se
R
se
V
R
V
S
Fig.5 Simplified system UPFC
e
se
) 15 (
2 2 2 i v i v P Qse Q Dse D
+ =
SK12 24
Power delivered by the series converter is
From the above equations we will get the actual D-Q currents flowing in the line.
References for D-Q currents is set by the required real power flow and the port 2 voltage.
Advanced Control Scheme [8]:-
The reference voltage vector for the series device e
*
se
is generalized as follows:
From the above differential equations we can calculate the K
r
, K
p
, K
q
values. The values
are given by K
p
= K
q
= -X
se
and K
r
acts as the damping resistor
Note that the control scheme comprehends both phase angle and cross coupling control
schemes, so that it can be considered a generalized control scheme for UPFC. This scheme has
two additional terms with identical gain K
r
. A voltage vector produced by the two terms is in phase
with a current phasor vector of i*-i , paying attention to the polarity of the e
se.
The above mentioned control strategy assumes that all quantities are referred to the
synchronously revolving reference frame at bus 1. Hence the actual d-q currents (referred to
receiving end bus) are transformed based on V
1
reference as above before they are used in the
above control equation.Similarly the control references are transformed back into the
synchronously revolving reference frame at receiving end bus..
The assumption here for transient analysis is : the series device is assumed to be an ideal
and instantaneously controllable voltage source. Therefore, the output voltage vector e
se
is equal
to its reference e*
se
.
5.2 Port 2 Voltage Control
The voltage at port 2 of the UPFC is algebraically related to that at port 1 and the series
voltage injected for power flow control. (For simplicity the series transformer reactance is clubbed
with the line impedance). Since all the quantities are locally available, we can easily calculate the
series voltage to be injected to obtain desired magnitude of V
2
.
The series injected controller diagram in d-q axis referred to bus 1 is given by:
) 16 (
i e i e
p
se
Q
se
Q
se
D
se
D
se
+ =
) 18 (
*
*
*
*
i i
i i
K K
K K
e
e
Qse Q
Dse D
r p
q r
qse
dse
) 17 (
3
1
3
1
1
Re 2
*
1
Re 2
*
V
Q
i
V
P
i
f
Qse
f
Dse
= =
sin cos
'
i i X Qse Dse D
+ =
) 19 ( ) ( tan
cos sin
1
1 1
'
V
V
i i X
D
Q
qse Dse Q
=
+ =

( ) ( )
( ) ( ) ) 20 (
2
1
2
1
2
2
2
2 2
e V e V
V V V
Qse Q Dse D
Q D
+ + + =
+ =
SK12 25
6 Shunt Current Control
The shunt current is controlled by varying the magnitude and angle of the shunt converter
voltage. The dynamic equations in the D-Q frame are given by,
Where,
r
sh
, x
sh
= shunt transformer resistance and leakage reactance respectively
e
Dsh
,e
Qsh
= converter output voltage components
V
1D
,V
1Q
= voltage components at the bus into which current injected (port 1 of UPFC)
) 22 ( ) (
) 21 ( ) (
1
1
v e
x
i i
x
r
i
v e
x
i i
x
r i
Q Qsh
sh
b
Dsh Qsh
sh
b sh
Qsh
D Dsh
sh
b
Qsh Dsh
sh
b sh Dsh
dt
d
dt
d
+ =
+ + =
I
q
I
d
V
1
I
r
I
p
Fig 7 Vector representation of real and reactive currents
PI
+
P
REF
P
U2
Fig.6 Series injected voltage controller

V
u1
I*
D
X
D
PI

V
u2REF
V
u2
V
u1
Q* I*
Q
X
Q
Series
Voltage
Calcula
tor
e
Qse
e
Dse
SK12 26
The reactive and real currents are defined as
where,
The real and reactive voltages of the shunt converter is given by

In
shunt current control block we are calculating the shunt converter output voltages through
the drop calculator block by using I
dref
and I
qref.
The differential equations used in drop calculator are
) 24 ( ) ( ) (
1
) ( tan
2
1
2
1
1
1 1
v v
v
v
v
Q D
Q
D
+ =
=

) 25 ( ) cos( ) sin(
) sin( ) cos(

e e e
e e e
Qsh Dsh psh
s
Qsh Dsh Rsh
+ =
=
) 27 (
) 26 (
1
1
V i X
i
x
i R e
V i X
i
x
i R e
q dshref sh
qshref
b
sh
qshref sh psh
d qshref sh
dshref
b
sh
dshref sh Rsh
dt
d
dt
d
+ =
+ + =
) 23 ( ) ( cos ) sin(
) ( sin ) ( cos

i i i
i i i
Qsh Dsh Psh
Qsh Dsh Rsh
+ =
=
+
V
1REF PI
V
DCREF
PI
V
1
V
DC
Shunt
current
controls
e
Pshord
e
Rshord
Figure. 8. Shunt current controller
+
I
Rref
I
Pref
SK12 27
Port 1 voltages are calculated by adding shunt and series currents and from the given
sending end voltage. The differential equations for port 1 voltage calculation is
The dynamical equation for the capacitor is given by
Any real power drawn / supplied by the series branch or by shunt branch (due to real
current injection I
psh
) manifests as DC side currents I
DC
ser
and I
DC
sh
respectively. Since we allow
variable series voltage injection, and due to losses, the capacitor voltage tends change. To
compensate this by I
DC
sh
, we set the real current reference (I
Pshref
) as the output of a PI type
capacitor voltage regulator.
REFERENCES
[1]L.Gyugyi, C.D. Schauder, S.L. Williams, T.R.Rietman, D.R.Torgerson, A.Edris,The Unified Power Flow
Controller: A New Approach to Powe Transmission Control, IEEE Trans .on Power Delivery, Vol.10, No.2
April 1995,pp.1085- 1097.
[2]L.Gyugyi, Unified Power Flow Concept for Flexible Ac Transmission Systems
IEEE Proc-C, Vol.139, No.4, July1992, pp.323-332.
[3]Sanbao Zheng And Yoke Lin Tan Dynamic Character Study of UPFC Based on
Detailed Simulation Model IEEE Power Conference 2000.
[4]C.Schauder and H.Metha, Vector Analysis and Control of Advanced Static Var
Compensator , IEE Proc-C , Vol. 140, No.4, July 1993., pp. 299-306.
[5]H.Fujita,Y.Watanabe, H. Akagi., Control and Analysis of a Unified Power Flow
Controller IEEE Trans.on Power electronics Vol.14 No.6.Nov 1999.
[6]I.Papic, P.Zunko, D.Povh, M.Weinhold, Basic Control Of Unified Power Flow
Controller IEEE Transactions On Power Systems, Vol.12, No.4.November 1997.
[7]K.R.Padiyar, K.Uma Rao Modeling and Control Of Unified Power Flow Controller for Transient Stability
A Journal on Electrical Power and Energy Systems Vol.No.21 (1999) 1-11.
[8]Padiyar, K.R., Kulakarni, A.M., Control Design And Simulation Of Unified Power Flow Controller IEEE
Tans. on Power Delivery, Vol.13, No.4, October 1998, pp.1348-1354.
) 30 ( ) (
i i
b
V
b
g
V
dse dsh
cap
b
DC
cap
b
cap
DC
dt
d
+ =

Drop
caliculator
I
dshref
I
qshref
V
1q
V
1d
e
dsh
e
dsh
Fig. 9 Converter voltage calculator
) 29 (
) 28 (
1
1
V i X
i
x
i R V
V i X
i x
i R V
SQ dL se
qL
b
se
qL se Q
SD ql se
dL
b
se
dL se D
dt
d
dt
d
+ =
+ + =
SK13 1
SIMULATION OF UPFC USING MATLAB SIMULINK
Suresh Kumar K.S
AP,EED,NIT Calicut
The test system taken for simulation study of UPFC as shown below:
Specifications of the system
taken for testing the simulation study are:
X
se
= 0.075 R
se
= 0.0075
X
sh
= 0.15 R
sh
= 0.01 V
DCRef
=3.4 p.u
g
cap
= 0.02 b
cap
= 2
V
r
= 10, Laod 3 p.u with power factor 0.8 (lag).
All the above quantities are on the UPFC MVA base (33.33 MVA), which is assumed to be 1/3
rd
of
the transmission line MVA base.
Notations used to represent simulated waveforms are:
E
se
= Series inverter output voltage.
E
sh
= Shunt inverter output voltage.
E
shrms
= RMS value of series converter output voltage
E
serms
= RMS value of series converter output voltage
P1= Real power flow from sending end to port1 measured at port1.
Q1=Reactive power flow from sending end to port1 measured at port1
P2= Real power flow from port2 to receiving end bus measured at port2
Q2=Reactive power flow from port2 to receiving end measured at port2
P
sh
= Real power flow from port1 to shunt converter measured at port1
Q
sh
= Reactive power flow from port1 to shunt converter measured at port1
P
L
=Real power flow from port1 to load measured at port1
Q
L
=Reactive power flow from port1 to load measured at port1.
P
se
= Real power flow from series converter to port2 measured at port2.
Q
se
=Reactive power flow from series converter to port2 measured at port2.
V
DC
= Voltage across DC capacitor
V1-A=Port1phase-A voltage.
V2-A= Port 2 phase-A voltage.
V
1rms
= RMS value of port 1 voltage
V
2rms
= RMS value of port2 voltage.
In all the plots below X-axis represents time in seconds.
VSI
VSI
R
se
R
s
e
X
se X
se
Substation
bus(port1)
UPFC o/p
bus
(port2)
Local
load
V
s
P
1
+ jQ
1 P
2
+jQ
2
P
s
h
+
j
Q
s
h
P
L
+
j
Q
L
Fig. 5.1.Test system
SK13 2
1. Modeling 3ph To D-Q Transformation Block:
The transformation subsystem block transforms the three phase quantities to
D-Q quantities in the synchronous reference frame. This transformation has been done in two
phases.
1. Transforming the three phase quantities to single phase quantities by using the
transformation matrix [C
1
] in the stationary reference frame.
2. Transforming the stationary reference frame quantities into synchronously rotating
at System frequency (
o
) quantities by using transformation matrix [C
2
].
Supply Modeling:
The three phase voltages are modeled using sine wave block in the source
library of SIMULINK. The parameters for amplitude set between 0.95-1.05pu and frequency set as
315 rad/sec. The phase angle parameter is set according to three phase supply, 0, 2.0944, -2.0944
rad for the, b and c phases. Accordingly parameters for lead, lag and unbalanced voltages are set.
Modeling Of Transformation Matrices: The transformation matrices are modelled by using gain
and sum blocks available in the linear library.
Fig.1.Transformation block in stationary reference frame
SK13 3
2. Modeling of UPFC
The control system described in the previous chapter was derived by
assuming that the series and parallel converters are treated as ideal controllable voltage sources,
that the values of the fundamental components of the line currents are locally available.
The UPFC is modeled by combining the shunt and series branches coupled
by the DC voltage control branch. Local load is added at port 1 of the UPFC.
Fig.2.Transformation block in synchronously revolving reference frame
SHUNT
CONVERTER
CONTROL
BLOCK
TRANSMIS-
SION LINE 1
MODEL
TRANSMISS
ION LINE-
2 MODEL
INVERTER
DC SIDE
MODEL
LOAD
MODEL
SERIES
INVERTER
CONTROL
MODEL
Fig 3. Organization of UPFC modeling blocks
SK13 4

F
i
g

4
.
.

U
n
i
f
i
e
d

P
o
w
e
r

F
l
o
w

C
o
n
t
r
o
l
l
e
r
SK13 5
UPFC was modeled by combining various blocks as shown above.
2.1Shunt Converter Control Model:
Shunt converter was modeled to inject currents into the port1. Inputs for the shunt
converter block are V
u1Ref
, V
dcRef
. In these two PI control blocks are used. The PI parameters are
tuned accordingly to get required output.
The PI values used in port1 voltage control loop are K
P
= 3, K
I
=3000. Large value of
integrator gain parameter was set to obtain rapid attainment of steady state without unacceptable
oscillations.
The PI values used in DC control loop are K
P
= 3, K
I
=0. Normally integral gain in the
capacitor loop set zero to avoid very low frequency oscillations in voltage across capacitor which
take a long time to die down.
Rate limiters are used in I
dsh
and I
qsh
loops. The reason is only limited voltage available
from the inverter to drive current through L
sh
of inverter. The limits used are [+2000, -2000].
2.2 Transmission Line 1 Model:
The transmission line 1 model was used to calculate the port1 voltage and the real and
reactive power flows (P1 and Q1) from the sending end at port1. Inputs to this block are sending
end voltages (d-q quantities).
In port1 voltage calculator block imperfect differentiators are used to represent line
reactances because transmission line are generally made up of aluminium conductor steel
reinforced (A.S.C.R) . So the eddy current losses are taken into account and hence the h.f gain is
limited.
Sensing delays are used to sense d-q components of the port1 voltage. Normally voltages
are sensed by potential transformers, it has delay in measurement. The delay time constant set at
a representative value of 1ms.These delays also serve to break the Simulink algebraic loops
Small value (0.00001) is used as a input to the sum block in calculating V
1rms
to avoid
division by zero or NaN in simulation .
SK13 6

F
i
g
.
5

S
h
u
n
t

c
o
n
v
e
r
t
e
r

c
o
n
t
r
o
l

b
l
o
c
k
SK13 7

F
i
g
.
6

.

T
r
a
n
s
m
i
s
s
i
o
n

l
i
n
e

1

m
o
d
e
l
SK13 8
2.3 Transmission Line 2 Model:
Transmission line 2 was modeled to calculate the series current flowing in the line from port
2 to the receiving end bus. D-Q power calculator block calculates the real and reactive power flow
from port2 to receiving end. Inputs to this block are receiving end voltages ( d-q quantities).
Fig.7 Transmission Line 2 Model
2.4 Inverter DC Side Control Model
The capacitor voltage is sensed using the power balance theory , according to which the
power at the AC side of the inverter is equal to the power at the DC capacitor side of the inverter,
when the switching losses in the inverter switches are neglected.
Inverter dc side control model was used to find the shunt converter output voltages and its
RMS value. Power calculator block is used to calculate real and reactive shunt powers.
SK13 9
2.5 Load Modeling
Load was connected at the port1 of the UPFC. The real and reactive
currents drawn by the load are transformed to calculate the its d-q components. The inputs to the
load model are real and reactive power references.
SK13 10
Fig.9. Load modeling
Currents in load will be delayed in practice by reactive energy storage elements. A delay
time constant of 10ms is employed to take this into account.
4.3.5 Series Inverter Control modeling:
To achieve real power and port 2 control we need to inject series voltage of
appropriate magnitude and angle. The blocks are modeled using the product, trigonometric and
mathematical functions available from nonlinear library.
SK13 11
VSI Inverter Modeling: The PWM-voltage source inverter was assumed to be
instantaneous and infinitely fast to track the voltage reference template set by the control strategy,
so it was implemented as a voltage amplifier with unity gain.

F
i
g
.

1
0
.

S
e
r
i
e
s

i
n
v
e
r
t
e
r

c
o
n
t
r
o
l
SK13 12
Inputs to this block are P
Ref
and V
u2Ref.
In these two PI controllers was used to get the real
and reactive power references at the port1. PI parameters used in real power reference loop are
K
p
= 1,K
I
=500, K
D
=0.001.Derivative control used to limit the initial peak overshoot. PI parameters
used in voltage control loop are K
p
= 20, K
I
=7500.
Parameters of saturation blocks are set to [+0.5, -0.5] otherwise the output of the inverter
goes to high values.
Power calculator Block:
Fig.11. Power calculator block
Results of a sample simulation run using the model developed follow.
SK13 13
Study Case : V
s
= 1 0,load 3p.u with lagging power factor 0.8, initially shunt control is OFF, shunt
control ON at T=0.04sec, P
Ref=
0, load switch on at t=0.08sec, at t=0.25 sec load throw and
subsequently shunt control OFF.
The simulation results are:
Fig. 12. Simulation results are (a) V
1rms,
V
1d ,
V
2q
(b) V
1rms
(expanded at T=0.08s) (c) V
1rms
(expanded at T=0.25s)
SK13 14
Fig. 13. Simulation results are (d) V
2rms
, V
2d
, V
2q
(e)V
2rms
(expanded at T=0.08s) (f) V
2rms
(expanded
at T=0.25s) (g) E
shrms,
E
serms
SK13 15
Fig .14 Simulation results are (h)V
1ang,
V
2ang
(i) V
1ph-A,
V
2ph-A
(j) I
dse,
I
qse
(k) P
2,
Q
2.
SK13 16
Fig . 15 Simulation results are (l) P
2
(expanded at T=0.08s) (m) P
2
(expanded at T=0.3s) (n) P
1,
Q
1
(o) P
sh
, Q
sh
SK13 17
Fig 5.6 Simulation results are (p)

P
INV
, Q
INV
(q) P
L
, Q
L
(r) V
dc.
By analyzing the above results for a step change in load at t=0.08sec, sudden change in q-
component of the voltage observed. At that time shunt converter RMS voltage rises to inject reactive power
into the bus. Reactive power shown as negative i.e. shunt converter delivering lagging reactive power to the
bus to keep the bus voltage constant.
When the load is switched on at T=0.08sec reactive power flow in the line (Q2) increases. So the
series converter voltage changes accordingly to supply the reactive power. In the above plots the real power
consumed by the shunt converter is not equal to the real power delivered by the series converter. The
reason is we are measuring the shunt converter real power at port1. So, we have to subtract the real power
dissipated in the resistance in the shunt converter path from the shunt real power.
The rise and fall times observed when sudden load change occurred at T=0.08sec and at T=0.25sec
in port1 voltage are given by T
r
=0.025sec, T
f
= 0.02sec.The load powers given in the figure is that of the
commanded powers and are different from the actual power drawn from the bus by the time constant of
1ms.This accounts for the higher rise time observed. The parameters of the controllers at different locations
are tuned to get satisfactory gain when sudden changes in load.
Initially there is no power flows from sending end to the receiving end because load angle is zero.
When load changes the port1 voltage angle changes with respect to the receiving end, so there is a real
power flow from port1 to receiving end and from sending end to the port1.
The rise and fall times observed in real power flow when load suddenly switched on are T
r
=
0.004sec and T
f
= 0.0001sec. The rise and fall times observed when load suddenly switched off at
T=0.25sec areT
r
=0.0001sec,T
f
=0.0075sec.

FACTS Controllers

Hochgeladen von

Dokumentinformationen

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

FACTS Controllers

Hochgeladen von

Copyright:

Verfügbare Formate

FACTS

Controllers and Applications

environment. MATLAB/Simulink platform is being extensively used in industries also to

automatically generates C code directly from Simulink block

l current phase per

i current phase per

Co- factor matrix =

can be resolved along the d- and q-axes, giving the relationship,

is the peak amplitude of the control

is the peak of the triangular carrier

to avoid short circuiting. This

The equation contains K number of variables like

V - Peak value of reference

- Peak of the fundamental

. The adjustment of the capacitor

Pd area representing the

Fig. 3 Transformation in rotating reference frame

Das könnte Ihnen auch gefallen